Updated: mars 2, 2017

Welcome to the NIOS II Xenomai Project
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| Motivations | Hardware Requirements | Software Requirements | Hardware Links | Software Links | Howtos | Guides | Latency measurement | NIOS II boards running Xenomai | Downloads |

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g_green_anim.gif (878 octets) Motivations

This page collects all informations on how to use Xenomai realtime extension with the Altera NIOS II softcore processor. With Philippe Gerum, maintainer of the Xenomai project, we have made an effort to propose this new port. With codesign, a new difficulty appears with flexibility during codesign generation. This page proposes to give important informations specially to this important part. Our wish is that your experience on Xenomai for NIOS II will be successful!

This work has been done for the RTEL4I project with help of the System@TIC ICT cluster.

g_green_anim.gif (878 octets) Hardware Requirements

You need a board with an Altera FPGA circuit and a system (JTAG) for programming it. We suggest to use:

g_green_anim.gif (878 octets) Software Requirements

g_green_anim.gif (878 octets) Hardware Links

g_green_anim.gif (878 octets) Software Links

Main links:

Other links:

g_green_anim.gif (878 octets) Howtos

Hardware requirements:

You must in your SoPC builder design add extra timers for Xenomai support.

You must have finally 3timers:

Please respect the name of the timers...

Software requirements:

Ready to use:

g_green_anim.gif (878 octets) Guides

g_green_anim.gif (878 octets) Latency measurement

Latency can be measured with tools provided by Xenomai through cross compilation. The principe is to generate a periodic thread and measures difference between the effectiv period and the theorical period that defines latency.

For stressing the system, we have used:

g_green_anim.gif (878 octets) NIOS II Boards tested and in use with Xenomai

For measuring latencies, boards are stressed by stress tool (# stress -c 10 -i 10 &) and ping flooding (# ping -f @IP).

Board µClinux kernel version Xenomai version Max latency (1) Max latency (2) Max latency (3) Max latency (4) NIOS II Frequency Contact Comments Xenomai Design
Altera Stratix 1S10 board 2.6.30 2.5.2   107 µs     50 MHz Patrice Kadionik 04/06/2010 trace From Altera standard reference design
Altera DE2-70 board 2.6.30 2.5.2   56 µs     100 MHz Huan Fang 03/30/2010 trace ?
Altera Cyclone III 3C25 board 2.6.30 2.5.2   60 µs     100 MHz Patrice Kadionik 04/06/2010 trace From Altera standard_neek_80 reference design
Altera Cyclone III 3C120 board 2.6.30 2.5.2   67 µs     100 MHz Patrice Kadionik

04/12/2010 trace

04/12/2010 trace

From Altera cycloneIII_3c120_niosII_video reference design

From Altera cycloneIII_3c120_niosII_standard reference design

Altera Cyclone III 3C25 board 2.6.30 2.5.2   42 µs     100 MHz Chtourou Sonda 04/07/2010 trace ?


g_green_anim.gif (878 octets) Downloads

The following Altera SoPC designs for Xenomai are given as an example without any guaranty and AS IS. You must purchase Altera tools for regenerating files for programming your Altera FPGA of your board.

th visitor since 04/01/2010