Table of Contents |
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Legal Notice |
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Copyright (C) 1991-2006 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details.
Analysis & Synthesis Summary |
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Analysis & Synthesis Status | Successful - Fri Apr 21 02:59:19 2006 |
Quartus II Version | 6.0 Build 176 04/19/2006 SJ Full Version |
Revision Name | standard |
Top-level Entity Name | standard |
Family | Stratix |
Total logic elements | 4,556 |
Total pins | 179 |
Total virtual pins | 0 |
Total memory bits | 571,136 |
DSP block 9-bit elements | 8 |
Total PLLs | 1 |
Total DLLs | 0 |
Analysis & Synthesis Settings |
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Option | Setting | Default Value |
---|---|---|
Device | EP1S10F780C6 | |
Top-level entity name | standard | standard |
Family name | Stratix | Stratix |
Restructure Multiplexers | Off | Auto |
Optimization Technique -- Stratix/Stratix GX | Speed | Balanced |
Use smart compilation | Off | Off |
Create Debugging Nodes for IP Cores | Off | Off |
Preserve fewer node names | On | On |
Disable OpenCore Plus hardware evaluation | Off | Off |
Verilog Version | Verilog_2001 | Verilog_2001 |
VHDL Version | VHDL93 | VHDL93 |
State Machine Processing | Auto | Auto |
Extract Verilog State Machines | On | On |
Extract VHDL State Machines | On | On |
Add Pass-Through Logic to Inferred RAMs | On | On |
DSP Block Balancing | Auto | Auto |
Maximum DSP Block Usage | Unlimited | Unlimited |
NOT Gate Push-Back | On | On |
Power-Up Don't Care | On | On |
Remove Redundant Logic Cells | Off | Off |
Remove Duplicate Registers | On | On |
Ignore CARRY Buffers | Off | Off |
Ignore CASCADE Buffers | Off | Off |
Ignore GLOBAL Buffers | Off | Off |
Ignore ROW GLOBAL Buffers | Off | Off |
Ignore LCELL Buffers | Off | Off |
Ignore SOFT Buffers | On | On |
Limit AHDL Integers to 32 Bits | Off | Off |
Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II | 70 | 70 |
Auto Carry Chains | On | On |
Auto Open-Drain Pins | On | On |
Remove Duplicate Logic | On | On |
Perform WYSIWYG Primitive Resynthesis | Off | Off |
Perform gate-level register retiming | Off | Off |
Allow register retiming to trade off Tsu/Tco with Fmax | On | On |
Auto ROM Replacement | On | On |
Auto RAM Replacement | On | On |
Auto DSP Block Replacement | On | On |
Auto Shift Register Replacement | On | On |
Auto Clock Enable Replacement | On | On |
Allow Synchronous Control Signals | On | On |
Force Use of Synchronous Clear Signals | Off | Off |
Auto RAM Block Balancing | On | On |
Auto Resource Sharing | Off | Off |
Allow Any RAM Size For Recognition | Off | Off |
Allow Any ROM Size For Recognition | Off | Off |
Allow Any Shift Register Size For Recognition | Off | Off |
Maximum Number of M512 Memory Blocks | Unlimited | Unlimited |
Maximum Number of M4K Memory Blocks | Unlimited | Unlimited |
Maximum Number of M-RAM Memory Blocks | Unlimited | Unlimited |
Ignore translate_off and translate_on Synthesis Directives | Off | Off |
Show Parameter Settings Tables in Synthesis Report | On | On |
Ignore Maximum Fan-Out Assignments | Off | Off |
Retiming Meta-Stability Register Sequence Length | 2 | 2 |
PowerPlay Power Optimization | Normal compilation | Normal compilation |
HDL message level | Level2 | Level2 |
Analysis & Synthesis Source Files Read |
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File Name with User-Entered Path | Used in Netlist | File Type | File Name with Absolute Path |
---|---|---|---|
standard.bdf | yes | User Block Diagram/Schematic File | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/standard.bdf |
std_1s10.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/std_1s10.vhd |
button_pio.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/button_pio.vhd |
clock_0.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/clock_0.vhd |
cpu.vhd | yes | Encrypted File | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/cpu.vhd |
cpu_test_bench.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/cpu_test_bench.vhd |
altsyncram.tdf | yes | Megafunction | /tools/quartus/6.0/176/libraries/megafunctions/altsyncram.tdf |
stratix_ram_block.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/stratix_ram_block.inc |
lpm_mux.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/lpm_mux.inc |
lpm_decode.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/lpm_decode.inc |
aglobal60.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/aglobal60.inc |
altsyncram.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/altsyncram.inc |
a_rdenreg.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/a_rdenreg.inc |
altrom.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/altrom.inc |
altram.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/altram.inc |
altdpram.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/altdpram.inc |
altqpram.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/altqpram.inc |
db/altsyncram_nnb1.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/altsyncram_nnb1.tdf |
db/altsyncram_t9e1.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/altsyncram_t9e1.tdf |
db/altsyncram_00e1.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/altsyncram_00e1.tdf |
db/altsyncram_10e1.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/altsyncram_10e1.tdf |
cpu_mult_cell.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/cpu_mult_cell.vhd |
altmult_add.tdf | yes | Megafunction | /tools/quartus/6.0/176/libraries/megafunctions/altmult_add.tdf |
stratix_mac_mult.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/stratix_mac_mult.inc |
stratix_mac_out.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/stratix_mac_out.inc |
db/mult_add_1f72.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/mult_add_1f72.tdf |
db/altsyncram_8q62.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/altsyncram_8q62.tdf |
db/altsyncram_puv1.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/altsyncram_puv1.tdf |
cpu_jtag_debug_module_wrapper.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/cpu_jtag_debug_module_wrapper.vhd |
cpu_jtag_debug_module.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/cpu_jtag_debug_module.vhd |
high_res_timer.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/high_res_timer.vhd |
jtag_uart.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/jtag_uart.vhd |
scfifo.tdf | yes | Megafunction | /tools/quartus/6.0/176/libraries/megafunctions/scfifo.tdf |
a_regfifo.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/a_regfifo.inc |
a_dpfifo.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/a_dpfifo.inc |
a_i2fifo.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/a_i2fifo.inc |
a_fffifo.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/a_fffifo.inc |
a_f2fifo.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/a_f2fifo.inc |
db/scfifo_gg21.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/scfifo_gg21.tdf |
db/a_dpfifo_jm21.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/a_dpfifo_jm21.tdf |
db/a_fefifo_7cf.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/a_fefifo_7cf.tdf |
db/cntr_bd7.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/cntr_bd7.tdf |
db/dpram_ga21.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/dpram_ga21.tdf |
db/altsyncram_kml1.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/altsyncram_kml1.tdf |
db/cntr_te8.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/cntr_te8.tdf |
alt_jtag_atlantic.v | yes | Encrypted Megafunction | /tools/quartus/6.0/176/libraries/megafunctions/alt_jtag_atlantic.v |
lcd_display.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/lcd_display.vhd |
led_pio.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/led_pio.vhd |
onchip_ram_64_kbytes.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/onchip_ram_64_kbytes.vhd |
db/altsyncram_7b71.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/altsyncram_7b71.tdf |
pll.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/pll.vhd |
altpllpll.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/altpllpll.vhd |
altpll.tdf | yes | Megafunction | /tools/quartus/6.0/176/libraries/megafunctions/altpll.tdf |
stratix_pll.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/stratix_pll.inc |
stratixii_pll.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/stratixii_pll.inc |
cycloneii_pll.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/cycloneii_pll.inc |
reconfig_request_pio.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/reconfig_request_pio.vhd |
sdram.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/sdram.vhd |
seven_seg_pio.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/seven_seg_pio.vhd |
sys_clk_timer.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/sys_clk_timer.vhd |
sysid.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/sysid.vhd |
uart1.vhd | yes | Other | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/uart1.vhd |
sld_hub.vhd | yes | Encrypted Megafunction | /tools/quartus/6.0/176/libraries/megafunctions/sld_hub.vhd |
lpm_shiftreg.tdf | yes | Megafunction | /tools/quartus/6.0/176/libraries/megafunctions/lpm_shiftreg.tdf |
lpm_constant.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/lpm_constant.inc |
dffeea.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/dffeea.inc |
lpm_decode.tdf | yes | Megafunction | /tools/quartus/6.0/176/libraries/megafunctions/lpm_decode.tdf |
declut.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/declut.inc |
altshift.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/altshift.inc |
lpm_compare.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/lpm_compare.inc |
db/decode_lhi.tdf | yes | Auto-Generated Megafunction | /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/db/decode_lhi.tdf |
sld_dffex.vhd | yes | Encrypted Megafunction | /tools/quartus/6.0/176/libraries/megafunctions/sld_dffex.vhd |
sld_rom_sr.vhd | yes | Encrypted Megafunction | /tools/quartus/6.0/176/libraries/megafunctions/sld_rom_sr.vhd |
lpm_add_sub.tdf | yes | Megafunction | /tools/quartus/6.0/176/libraries/megafunctions/lpm_add_sub.tdf |
addcore.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/addcore.inc |
look_add.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/look_add.inc |
bypassff.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/bypassff.inc |
alt_stratix_add_sub.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/alt_stratix_add_sub.inc |
alt_mercury_add_sub.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/alt_mercury_add_sub.inc |
alt_stratix_add_sub.tdf | yes | Megafunction | /tools/quartus/6.0/176/libraries/megafunctions/alt_stratix_add_sub.tdf |
stratix_lcell.inc | yes | Other | /tools/quartus/6.0/176/libraries/megafunctions/stratix_lcell.inc |
Analysis & Synthesis Resource Usage Summary |
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Resource | Usage |
---|---|
Total logic elements | 4556 |
-- Combinational with no register | 2378 |
-- Register only | 829 |
-- Combinational with a register | 1349 |
Logic element usage by number of LUT inputs | |
-- 4 input functions | 2109 |
-- 3 input functions | 1056 |
-- 2 input functions | 469 |
-- 1 input functions | 85 |
-- 0 input functions | 8 |
-- Combinational cells for routing | 0 |
Logic elements by mode | |
-- normal mode | 4275 |
-- arithmetic mode | 281 |
-- qfbk mode | 0 |
-- register cascade mode | 0 |
-- synchronous clear/load mode | 334 |
-- asynchronous clear/load mode | 1903 |
Total registers | 2178 |
Total logic cells in carry chains | 305 |
I/O pins | 179 |
Total memory bits | 571136 |
DSP block 9-bit elements | 8 |
Total PLLs | 1 |
Maximum fan-out node | std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0 |
Maximum fan-out | 2062 |
Total fan-out | 22400 |
Average fan-out | 4.59 |
Analysis & Synthesis Resource Utilization by Entity |
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Compilation Hierarchy Node | Logic Cells | LC Registers | Memory Bits | M512s | M4Ks | M-RAMs | DSP Elements | DSP 9x9 | DSP 18x18 | DSP 36x36 | Pins | Virtual Pins | LUT-Only LCs | Register-Only LCs | LUT/Register LCs | Carry Chain LCs | Packed LCs | Full Hierarchy Name |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|standard | 4556 (2) | 2178 | 571136 | 0 | 0 | 4 | 8 | 0 | 0 | 1 | 179 | 0 | 2378 (2) | 829 (0) | 1349 (0) | 305 (0) | 0 (0) | |standard |
|sld_hub:sld_hub_inst| | 108 (28) | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 40 (21) | 11 (0) | 57 (7) | 5 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst |
|lpm_decode:instruction_decoder| | 5 (0) | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 5 (0) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder |
|decode_lhi:auto_generated| | 5 (5) | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 5 (5) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated |
|lpm_shiftreg:jtag_ir_register| | 10 (10) | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 9 (9) | 1 (1) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register |
|sld_dffex:BROADCAST| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:BROADCAST |
|sld_dffex:IRF_ENA_0| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0 |
|sld_dffex:IRF_ENA| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 2 (2) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA |
|sld_dffex:IRSR| | 9 (9) | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 (2) | 0 (0) | 7 (7) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:IRSR |
|sld_dffex:RESET| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:RESET |
|sld_dffex:\GEN_IRF:1:IRF| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 2 (2) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF |
|sld_dffex:\GEN_IRF:2:IRF| | 2 (2) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 (1) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF |
|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 2 (2) | 0 (0) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF |
|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF |
|sld_jtag_state_machine:jtag_state_machine| | 20 (20) | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 (1) | 0 (0) | 19 (19) | 0 (0) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine |
|sld_rom_sr:HUB_INFO_REG| | 24 (24) | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 (15) | 0 (0) | 9 (9) | 5 (5) | 0 (0) | |standard|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG |
|std_1s10:inst| | 4446 (1) | 2110 | 571136 | 0 | 0 | 4 | 8 | 0 | 0 | 1 | 0 | 0 | 2336 (1) | 818 (0) | 1292 (0) | 300 (0) | 0 (0) | |standard|std_1s10:inst |
|button_pio:the_button_pio| | 27 (27) | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7 (7) | 12 (12) | 8 (8) | 0 (0) | 0 (0) | |standard|std_1s10:inst|button_pio:the_button_pio |
|button_pio_s1_arbitrator:the_button_pio_s1| | 1 (1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 (1) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|button_pio_s1_arbitrator:the_button_pio_s1 |
|clock_0:the_clock_0| | 107 (71) | 92 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 (1) | 66 (54) | 26 (16) | 0 (0) | 0 (0) | |standard|std_1s10:inst|clock_0:the_clock_0 |
|clock_0_edge_to_pulse:read_done_edge_to_pulse| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse |
|clock_0_edge_to_pulse:read_request_edge_to_pulse| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_request_edge_to_pulse |
|clock_0_edge_to_pulse:write_done_edge_to_pulse| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_done_edge_to_pulse |
|clock_0_edge_to_pulse:write_request_edge_to_pulse| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_request_edge_to_pulse |
|clock_0_master_FSM:master_FSM| | 11 (11) | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 (6) | 0 (0) | 5 (5) | 0 (0) | 0 (0) | |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM |
|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 2 (2) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync |
|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 2 (2) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync |
|clock_0_slave_FSM:slave_FSM| | 13 (13) | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 (8) | 0 (0) | 5 (5) | 0 (0) | 0 (0) | |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM |
|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 2 (2) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync |
|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 2 (2) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync |
|clock_0_in_arbitrator:the_clock_0_in| | 3 (3) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 (3) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|clock_0_in_arbitrator:the_clock_0_in |
|cpu:the_cpu| | 1787 (1365) | 882 | 45824 | 0 | 0 | 0 | 8 | 0 | 0 | 1 | 0 | 0 | 905 (663) | 275 (228) | 607 (474) | 125 (50) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu |
|cpu_ic_data_module:cpu_ic_data| | 0 (0) | 0 | 32768 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data |
|altsyncram:the_altsyncram| | 0 (0) | 0 | 32768 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram |
|altsyncram_nnb1:auto_generated| | 0 (0) | 0 | 32768 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated |
|cpu_ic_tag_module:cpu_ic_tag| | 0 (0) | 0 | 2816 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag |
|altsyncram:the_altsyncram| | 0 (0) | 0 | 2816 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram |
|altsyncram_t9e1:auto_generated| | 0 (0) | 0 | 2816 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated |
|cpu_mult_cell:the_cpu_mult_cell| | 2 (0) | 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 1 | 0 | 0 | 2 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell |
|altmult_add:the_altmult_add| | 2 (0) | 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 1 | 0 | 0 | 2 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add |
|mult_add_1f72:auto_generated| | 2 (2) | 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 1 | 0 | 0 | 2 (2) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated |
|cpu_nios2_oci:the_cpu_nios2_oci| | 354 (35) | 180 | 8192 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 174 (35) | 47 (0) | 133 (0) | 9 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci |
|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper| | 188 (0) | 90 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 98 (0) | 45 (0) | 45 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper |
|cpu_jtag_debug_module:the_cpu_jtag_debug_module1| | 188 (188) | 90 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 98 (98) | 45 (45) | 45 (45) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1 |
|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg| | 12 (12) | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 (5) | 0 (0) | 7 (7) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg |
|cpu_nios2_oci_break:the_cpu_nios2_oci_break| | 32 (32) | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 32 (32) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break |
|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug| | 12 (12) | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 (5) | 1 (1) | 6 (6) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug |
|cpu_nios2_ocimem:the_cpu_nios2_ocimem| | 75 (75) | 44 | 8192 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 31 (31) | 1 (1) | 43 (43) | 9 (9) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem |
|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component| | 0 (0) | 0 | 8192 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component |
|altsyncram:the_altsyncram| | 0 (0) | 0 | 8192 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram |
|altsyncram_8q62:auto_generated| | 0 (0) | 0 | 8192 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated |
|cpu_register_bank_a_module:cpu_register_bank_a| | 0 (0) | 0 | 1024 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a |
|altsyncram:the_altsyncram| | 0 (0) | 0 | 1024 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram |
|altsyncram_00e1:auto_generated| | 0 (0) | 0 | 1024 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated |
|cpu_register_bank_b_module:cpu_register_bank_b| | 0 (0) | 0 | 1024 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b |
|altsyncram:the_altsyncram| | 0 (0) | 0 | 1024 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram |
|altsyncram_10e1:auto_generated| | 0 (0) | 0 | 1024 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated |
|cpu_test_bench:the_cpu_test_bench| | 33 (33) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 33 (33) | 0 (0) | 0 (0) | 33 (33) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench |
|lpm_add_sub:Add8| | 33 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 33 (0) | 0 (0) | 0 (0) | 33 (0) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8 |
|alt_stratix_add_sub:stratix_adder| | 33 (33) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 33 (33) | 0 (0) | 0 (0) | 33 (33) | 0 (0) | |standard|std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder |
|cpu_data_master_arbitrator:the_cpu_data_master| | 342 (342) | 60 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 282 (282) | 24 (24) | 36 (36) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master |
|cpu_instruction_master_arbitrator:the_cpu_instruction_master| | 157 (157) | 31 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 126 (126) | 24 (24) | 7 (7) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master |
|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module| | 37 (37) | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 33 (33) | 2 (2) | 2 (2) | 0 (0) | 0 (0) | |standard|std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module |
|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave| | 269 (269) | 148 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 121 (121) | 49 (49) | 99 (99) | 12 (12) | 0 (0) | |standard|std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave |
|high_res_timer:the_high_res_timer| | 173 (173) | 120 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 53 (53) | 50 (50) | 70 (70) | 32 (32) | 0 (0) | |standard|std_1s10:inst|high_res_timer:the_high_res_timer |
|high_res_timer_s1_arbitrator:the_high_res_timer_s1| | 2 (2) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 (2) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|high_res_timer_s1_arbitrator:the_high_res_timer_s1 |
|jtag_uart:the_jtag_uart| | 180 (51) | 106 | 1024 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 74 (38) | 28 (6) | 78 (7) | 51 (15) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart |
|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic| | 78 (78) | 53 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 25 (25) | 22 (22) | 31 (31) | 0 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic |
|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r| | 26 (0) | 20 | 512 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r |
|scfifo:rfifo| | 26 (0) | 20 | 512 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo |
|scfifo_gg21:auto_generated| | 26 (0) | 20 | 512 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated |
|a_dpfifo_jm21:dpfifo| | 26 (0) | 20 | 512 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo |
|a_fefifo_7cf:fifo_state| | 14 (8) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 (6) | 0 (0) | 8 (2) | 6 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state |
|cntr_bd7:count_usedw| | 6 (6) | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 6 (6) | 6 (6) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw |
|cntr_te8:rd_ptr_count| | 6 (6) | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 6 (6) | 6 (6) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count |
|cntr_te8:wr_ptr| | 6 (6) | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 6 (6) | 6 (6) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr |
|dpram_ga21:FIFOram| | 0 (0) | 0 | 512 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram |
|altsyncram_kml1:altsyncram1| | 0 (0) | 0 | 512 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1 |
|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w| | 25 (0) | 20 | 512 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w |
|scfifo:wfifo| | 25 (0) | 20 | 512 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo |
|scfifo_gg21:auto_generated| | 25 (0) | 20 | 512 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated |
|a_dpfifo_jm21:dpfifo| | 25 (0) | 20 | 512 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 (0) | 0 (0) | 20 (0) | 18 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo |
|a_fefifo_7cf:fifo_state| | 13 (7) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 (5) | 0 (0) | 8 (2) | 6 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state |
|cntr_bd7:count_usedw| | 6 (6) | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 6 (6) | 6 (6) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw |
|cntr_te8:rd_ptr_count| | 6 (6) | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 6 (6) | 6 (6) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count |
|cntr_te8:wr_ptr| | 6 (6) | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 6 (6) | 6 (6) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr |
|dpram_ga21:FIFOram| | 0 (0) | 0 | 512 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram |
|altsyncram_kml1:altsyncram1| | 0 (0) | 0 | 512 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1 |
|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave| | 2 (2) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 (2) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave |
|lcd_display:the_lcd_display| | 5 (5) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 (5) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|lcd_display:the_lcd_display |
|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave| | 24 (24) | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 (17) | 0 (0) | 7 (7) | 6 (6) | 0 (0) | |standard|std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave |
|led_pio:the_led_pio| | 12 (12) | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 (4) | 8 (8) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|led_pio:the_led_pio |
|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes| | 1 (1) | 0 | 524288 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 1 (1) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes |
|altsyncram:the_altsyncram| | 0 (0) | 0 | 524288 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram |
|altsyncram_7b71:auto_generated| | 0 (0) | 0 | 524288 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated |
|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1| | 36 (36) | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 33 (33) | 1 (1) | 2 (2) | 0 (0) | 0 (0) | |standard|std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1 |
|pll:the_pll| | 26 (26) | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 (2) | 15 (15) | 9 (9) | 5 (5) | 0 (0) | |standard|std_1s10:inst|pll:the_pll |
|altpllpll:the_pll| | 0 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|pll:the_pll|altpllpll:the_pll |
|altpll:altpll_component| | 0 (0) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component |
|pll_s1_arbitrator:the_pll_s1| | 1 (1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1s10:inst|pll_s1_arbitrator:the_pll_s1 |
|reconfig_request_pio:the_reconfig_request_pio| | 4 (4) | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 (1) | 0 (0) | 3 (3) | 0 (0) | 0 (0) | |standard|std_1s10:inst|reconfig_request_pio:the_reconfig_request_pio |
|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1| | 4 (4) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 (4) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1 |
|sdram:the_sdram| | 750 (577) | 323 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 427 (376) | 153 (37) | 170 (164) | 13 (13) | 0 (0) | |standard|std_1s10:inst|sdram:the_sdram |
|sdram_input_efifo_module:the_sdram_input_efifo_module| | 173 (173) | 122 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 51 (51) | 116 (116) | 6 (6) | 0 (0) | 0 (0) | |standard|std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module |
|sdram_s1_arbitrator:the_sdram_s1| | 133 (77) | 45 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 88 (63) | 16 (6) | 29 (8) | 6 (6) | 0 (0) | |standard|std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1 |
|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1| | 21 (21) | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 (9) | 5 (5) | 7 (7) | 0 (0) | 0 (0) | |standard|std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1 |
|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1| | 35 (35) | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 16 (16) | 5 (5) | 14 (14) | 0 (0) | 0 (0) | |standard|std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1 |
|seven_seg_pio:the_seven_seg_pio| | 17 (17) | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 (1) | 16 (16) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|seven_seg_pio:the_seven_seg_pio |
|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1s10:inst|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch |
|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch| | 2 (2) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 (0) | 1 (1) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1s10:inst|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch |
|sys_clk_timer:the_sys_clk_timer| | 174 (174) | 120 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 54 (54) | 46 (46) | 74 (74) | 32 (32) | 0 (0) | |standard|std_1s10:inst|sys_clk_timer:the_sys_clk_timer |
|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1| | 3 (3) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 (3) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1 |
|sysid_control_slave_arbitrator:the_sysid_control_slave| | 4 (4) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 (4) | 0 (0) | 0 (0) | 0 (0) | 0 (0) | |standard|std_1s10:inst|sysid_control_slave_arbitrator:the_sysid_control_slave |
|uart1:the_uart1| | 156 (0) | 92 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 64 (0) | 31 (0) | 61 (0) | 18 (0) | 0 (0) | |standard|std_1s10:inst|uart1:the_uart1 |
|uart1_regs:the_uart1_regs| | 61 (61) | 29 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 32 (32) | 18 (18) | 11 (11) | 0 (0) | 0 (0) | |standard|std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs |
|uart1_rx:the_uart1_rx| | 60 (60) | 37 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 23 (23) | 12 (12) | 25 (25) | 9 (9) | 0 (0) | |standard|std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx |
|uart1_tx:the_uart1_tx| | 35 (35) | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 (9) | 1 (1) | 25 (25) | 9 (9) | 0 (0) | |standard|std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx |
|uart1_s1_arbitrator:the_uart1_s1| | 4 (4) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 (3) | 0 (0) | 1 (1) | 0 (0) | 0 (0) | |standard|std_1s10:inst|uart1_s1_arbitrator:the_uart1_s1 |
Analysis & Synthesis RAM Summary |
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Name | Type | Mode | Port A Depth | Port A Width | Port B Depth | Port B Width | Size | MIF |
---|---|---|---|---|---|---|---|---|
std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|ALTSYNCRAM | AUTO | Simple Dual Port | 1024 | 32 | 1024 | 32 | 32768 | None |
std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|ALTSYNCRAM | AUTO | Simple Dual Port | 128 | 22 | 128 | 22 | 2816 | cpu_ic_tag_ram.mif |
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|ALTSYNCRAM | AUTO | True Dual Port | 256 | 32 | 256 | 32 | 8192 | cpu_ociram_default_contents.mif |
std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|ALTSYNCRAM | AUTO | Simple Dual Port | 32 | 32 | 32 | 32 | 1024 | cpu_rf_ram_a.mif |
std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|ALTSYNCRAM | AUTO | Simple Dual Port | 32 | 32 | 32 | 32 | 1024 | cpu_rf_ram_b.mif |
std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|ALTSYNCRAM | AUTO | Simple Dual Port | 64 | 8 | 64 | 8 | 512 | None |
std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|ALTSYNCRAM | AUTO | Simple Dual Port | 64 | 8 | 64 | 8 | 512 | None |
std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|ALTSYNCRAM | M-RAM | Single Port | 16384 | 32 | -- | -- | 524288 | None |
Analysis & Synthesis DSP Block Usage Summary |
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Statistic | Number Used |
---|---|
Simple Multipliers (9-bit) | 0 |
Simple Multipliers (18-bit) | 0 |
Simple Multipliers (36-bit) | 1 |
Multiply Accumulators (18-bit) | 0 |
Two-Multipliers Adders (9-bit) | 0 |
Two-Multipliers Adders (18-bit) | 0 |
Four-Multipliers Adders (9-bit) | 0 |
Four-Multipliers Adders (18-bit) | 0 |
DSP Blocks | -- |
DSP Block 9-bit Elements | 8 |
Signed Multipliers | 1 |
Unsigned Multipliers | 0 |
Mixed Sign Multipliers | 0 |
Variable Sign Multipliers | 0 |
Dedicated Shift Register Chains | 0 |
Registers Protected by Synthesis |
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Register Name | Protected by Synthesis Attribute or Preserve Register Assignment | Not to be Touched by Netlist Optimizations |
---|---|---|
std_1s10:inst|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch|data_out | yes | yes |
std_1s10:inst|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch|data_in_d1 | yes | yes |
std_1s10:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_out | yes | yes |
std_1s10:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync|data_out | yes | yes |
std_1s10:inst|pll:the_pll|not_areset | yes | yes |
std_1s10:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_in_d1 | yes | yes |
std_1s10:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync|data_in_d1 | yes | yes |
std_1s10:inst|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch|data_out | yes | yes |
std_1s10:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_out | yes | yes |
std_1s10:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_out | yes | yes |
std_1s10:inst|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch|data_in_d1 | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_nativeaddress[0] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_in_d1 | yes | yes |
std_1s10:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_in_d1 | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_nativeaddress_d1[0] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[2] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_nativeaddress[1] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_nativeaddress[2] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[3] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[5] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[4] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[15] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[7] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[14] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[13] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[12] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[11] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[10] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[9] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[8] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[6] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[2] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_nativeaddress_d1[1] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_nativeaddress_d1[2] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[3] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[5] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[4] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[15] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[7] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[14] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[13] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[12] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[11] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[10] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[9] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[8] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[6] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[1] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|master_writedata[0] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[1] | yes | yes |
std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[0] | yes | yes |
General Register Statistics |
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Statistic | Value |
---|---|
Total registers | 2178 |
Number of registers using Synchronous Clear | 47 |
Number of registers using Synchronous Load | 320 |
Number of registers using Asynchronous Clear | 1898 |
Number of registers using Asynchronous Load | 5 |
Number of registers using Clock Enable | 1329 |
Number of registers using Preset | 0 |
Inverted Register Statistics |
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Inverted Register | Fan out |
---|---|
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ior_n_to_the_lan91c111 | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_flash | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|iow_n_to_the_lan91c111 | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_flash | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_local | 3 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_mask | 1 |
std_1s10:inst|sdram:the_sdram|m_cmd[1] | 2 |
std_1s10:inst|sdram:the_sdram|m_cmd[3] | 1 |
std_1s10:inst|sdram:the_sdram|m_cmd[2] | 2 |
std_1s10:inst|sdram:the_sdram|m_cmd[0] | 2 |
std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|txd | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_flash | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[3] | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[2] | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[1] | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[0] | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[3] | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[2] | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[1] | 1 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[0] | 1 |
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n | 4 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer | 9 |
std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest | 17 |
std_1s10:inst|sdram:the_sdram|m_state[0] | 58 |
std_1s10:inst|sdram:the_sdram|i_cmd[1] | 1 |
std_1s10:inst|sdram:the_sdram|i_cmd[3] | 1 |
std_1s10:inst|sdram:the_sdram|m_next[0] | 5 |
std_1s10:inst|sdram:the_sdram|i_cmd[2] | 1 |
std_1s10:inst|sdram:the_sdram|i_cmd[0] | 1 |
std_1s10:inst|cpu:the_cpu|M_pipe_flush | 32 |
std_1s10:inst|cpu:the_cpu|hbreak_enabled | 40 |
std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd | 2 |
std_1s10:inst|sdram:the_sdram|i_addr[0] | 10 |
sld_hub:sld_hub_inst|hub_tdo | 2 |
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n | 2 |
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[0] | 6 |
std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0] | 6 |
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0] | 1 |
std_1s10:inst|jtag_uart:the_jtag_uart|internal_av_waitrequest | 1 |
std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[0] | 6 |
std_1s10:inst|sdram:the_sdram|refresh_counter[3] | 2 |
std_1s10:inst|sdram:the_sdram|refresh_counter[7] | 2 |
std_1s10:inst|sdram:the_sdram|refresh_counter[12] | 2 |
std_1s10:inst|sdram:the_sdram|refresh_counter[8] | 2 |
std_1s10:inst|sdram:the_sdram|refresh_counter[9] | 2 |
std_1s10:inst|cpu:the_cpu|M_wr_dst_reg | 67 |
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[2] | 2 |
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[3] | 2 |
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[4] | 2 |
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[5] | 2 |
std_1s10:inst|cpu:the_cpu|reset_d1 | 9 |
std_1s10:inst|jtag_uart:the_jtag_uart|t_dav | 3 |
std_1s10:inst|cpu:the_cpu|ic_tag_clr_valid_bits | 1 |
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[1] | 2 |
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[0] | 2 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[2] | 2 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[2] | 2 |
std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[2] | 2 |
std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_shift_empty | 2 |
std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|internal_tx_ready | 6 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[3] | 2 |
std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[3] | 2 |
std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[0] | 3 |
std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[1] | 3 |
std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[2] | 3 |
std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[3] | 3 |
std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[6] | 3 |
std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[8] | 3 |
std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[9] | 3 |
std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[14] | 3 |
std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[15] | 3 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[4] | 2 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[15] | 2 |
std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[15] | 2 |
std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[14] | 2 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[13] | 2 |
std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[9] | 2 |
std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[8] | 2 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[8] | 2 |
std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[6] | 2 |
std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[0] | 6 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[0] | 3 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[1] | 3 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[2] | 3 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[3] | 3 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[4] | 3 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[8] | 3 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[13] | 3 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[15] | 3 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[16] | 3 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[17] | 3 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[18] | 3 |
std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[0] | 2 |
std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[1] | 2 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[0] | 2 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[0] | 2 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[1] | 2 |
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[1] | 2 |
Total number of inverted registers = 100 |
Multiplexer Restructuring Statistics (No Restructuring Performed) |
Top |
Multiplexer Inputs | Bus Width | Baseline Area | Area if Restructured | Saving if Restructured | Registered | Example Multiplexer Output |
---|---|---|---|---|---|---|
3:1 | 2 bits | 4 LEs | 4 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0] |
3:1 | 32 bits | 64 LEs | 64 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|E_src2_prelim[20] |
3:1 | 16 bits | 32 LEs | 16 LEs | 16 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|E_src2_imm[5] |
3:1 | 32 bits | 64 LEs | 64 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|E_src1_prelim[1] |
3:1 | 8 bits | 16 LEs | 16 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[4] |
3:1 | 6 bits | 12 LEs | 12 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[4] |
3:1 | 12 bits | 24 LEs | 24 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|D_iw[3] |
3:1 | 20 bits | 40 LEs | 40 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|D_iw[27] |
3:1 | 8 bits | 16 LEs | 8 LEs | 8 LEs | Yes | |standard|std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] |
3:1 | 8 bits | 16 LEs | 8 LEs | 8 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|M_st_data[21] |
3:1 | 8 bits | 16 LEs | 16 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|M_st_data[29] |
3:1 | 10 bits | 20 LEs | 10 LEs | 10 LEs | Yes | |standard|std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] |
3:1 | 4 bits | 8 LEs | 4 LEs | 4 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|ic_fill_ap_cnt[2] |
3:1 | 3 bits | 6 LEs | 3 LEs | 3 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|ic_fill_ap_offset[2] |
3:1 | 5 bits | 10 LEs | 10 LEs | 0 LEs | Yes | |standard|std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4] |
5:1 | 2 bits | 6 LEs | 2 LEs | 4 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entries[1] |
4:1 | 20 bits | 40 LEs | 40 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[25] |
4:1 | 10 bits | 20 LEs | 20 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[27] |
4:1 | 9 bits | 18 LEs | 9 LEs | 9 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[8] |
8:1 | 3 bits | 15 LEs | 3 LEs | 12 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|i_refs[2] |
4:1 | 32 bits | 64 LEs | 64 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[5] |
4:1 | 15 bits | 30 LEs | 30 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|E_src2_imm[22] |
8:1 | 5 bits | 25 LEs | 10 LEs | 15 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[5] |
4:1 | 3 bits | 6 LEs | 3 LEs | 3 LEs | Yes | |standard|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] |
4:1 | 14 bits | 28 LEs | 28 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|F_pc[21] |
4:1 | 3 bits | 6 LEs | 6 LEs | 0 LEs | Yes | |standard|std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[4] |
4:1 | 3 bits | 6 LEs | 6 LEs | 0 LEs | Yes | |standard|std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[5] |
4:1 | 3 bits | 6 LEs | 6 LEs | 0 LEs | Yes | |standard|std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[0] |
4:1 | 2 bits | 4 LEs | 4 LEs | 0 LEs | Yes | |standard|std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[3] |
4:1 | 2 bits | 4 LEs | 2 LEs | 2 LEs | Yes | |standard|std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[2] |
5:1 | 2 bits | 6 LEs | 6 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|M_mem_byte_en[2] |
5:1 | 32 bits | 96 LEs | 32 LEs | 64 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[28] |
5:1 | 5 bits | 15 LEs | 5 LEs | 10 LEs | Yes | |standard|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[2] |
9:1 | 3 bits | 18 LEs | 6 LEs | 12 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|i_count[2] |
6:1 | 2 bits | 8 LEs | 4 LEs | 4 LEs | Yes | |standard|std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[0] |
6:1 | 21 bits | 84 LEs | 21 LEs | 63 LEs | Yes | |standard|std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[5] |
6:1 | 2 bits | 8 LEs | 6 LEs | 2 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[18] |
10:1 | 3 bits | 18 LEs | 12 LEs | 6 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|i_state[0] |
6:1 | 24 bits | 96 LEs | 96 LEs | 0 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[12] |
9:1 | 6 bits | 36 LEs | 24 LEs | 12 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|M_alu_result[31] |
9:1 | 20 bits | 120 LEs | 100 LEs | 20 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|M_alu_result[15] |
28:1 | 4 bits | 72 LEs | 48 LEs | 24 LEs | Yes | |standard|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] |
513:1 | 4 bits | 1368 LEs | 8 LEs | 1360 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|m_addr[11] |
512:1 | 6 bits | 2046 LEs | 6 LEs | 2040 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|m_bank[1] |
513:1 | 2 bits | 684 LEs | 6 LEs | 678 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|m_addr[4] |
513:1 | 6 bits | 2052 LEs | 18 LEs | 2034 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|m_addr[6] |
516:1 | 2 bits | 688 LEs | 2 LEs | 686 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|m_next[4] |
517:1 | 2 bits | 688 LEs | 26 LEs | 662 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|m_state[8] |
519:1 | 59 bits | 20414 LEs | 0 LEs | 20414 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|active_data[3] |
518:1 | 2 bits | 690 LEs | 54 LEs | 636 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|m_state[6] |
521:1 | 2 bits | 694 LEs | 12 LEs | 682 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|m_state[4] |
3:1 | 24 bits | 48 LEs | 24 LEs | 24 LEs | Yes | |standard|std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[22] |
8:1 | 4 bits | 20 LEs | 12 LEs | 8 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|i_cmd[0] |
6:1 | 8 bits | 32 LEs | 16 LEs | 16 LEs | Yes | |standard|std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[4] |
513:1 | 32 bits | 10944 LEs | 64 LEs | 10880 LEs | Yes | |standard|std_1s10:inst|sdram:the_sdram|m_data[3] |
3:1 | 32 bits | 64 LEs | 64 LEs | 0 LEs | No | |standard|std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[0] |
3:1 | 4 bits | 8 LEs | 4 LEs | 4 LEs | No | |standard|std_1s10:inst|sdram:the_sdram|module_input1[34] |
3:1 | 3 bits | 6 LEs | 6 LEs | 0 LEs | No | |standard|std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter_next_value[2] |
3:1 | 3 bits | 6 LEs | 3 LEs | 3 LEs | No | |standard|std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_share_counter_next_value[1] |
3:1 | 6 bits | 12 LEs | 12 LEs | 0 LEs | No | |standard|std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[1] |
3:1 | 3 bits | 6 LEs | 3 LEs | 3 LEs | No | |standard|std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_arb_share_counter_next_value[0] |
4:1 | 2 bits | 4 LEs | 2 LEs | 2 LEs | No | |standard|std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_set_values[0] |
4:1 | 3 bits | 6 LEs | 6 LEs | 0 LEs | No | |standard|std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~10 |
4:1 | 5 bits | 10 LEs | 10 LEs | 0 LEs | No | |standard|std_1s10:inst|cpu:the_cpu|D_dst_regnum[3] |
4:1 | 3 bits | 6 LEs | 6 LEs | 0 LEs | No | |standard|std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~8 |
4:1 | 2 bits | 4 LEs | 4 LEs | 0 LEs | No | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[4] |
4:1 | 4 bits | 8 LEs | 8 LEs | 0 LEs | No | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[1] |
4:1 | 10 bits | 20 LEs | 20 LEs | 0 LEs | No | |standard|std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[0] |
16:1 | 2 bits | 20 LEs | 8 LEs | 12 LEs | No | |standard|std_1s10:inst|cpu:the_cpu|E_sh_cnt_col[1] |
16:1 | 2 bits | 20 LEs | 12 LEs | 8 LEs | No | |standard|std_1s10:inst|cpu:the_cpu|E_sh_cnt_row[1] |
9:1 | 4 bits | 24 LEs | 24 LEs | 0 LEs | No | |standard|std_1s10:inst|cpu:the_cpu|E_alu_result[2] |
6:1 | 2 bits | 8 LEs | 4 LEs | 4 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[36] |
6:1 | 6 bits | 24 LEs | 18 LEs | 6 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[10] |
6:1 | 18 bits | 72 LEs | 36 LEs | 36 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[28] |
6:1 | 7 bits | 28 LEs | 21 LEs | 7 LEs | Yes | |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[1] |
3:1 | 10 bits | 20 LEs | 10 LEs | 10 LEs | Yes | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[1] |
4:1 | 2 bits | 4 LEs | 4 LEs | 0 LEs | Yes | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9] |
5:1 | 3 bits | 9 LEs | 6 LEs | 3 LEs | Yes | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[7] |
5:1 | 4 bits | 12 LEs | 8 LEs | 4 LEs | Yes | |standard|std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[1] |
Source assignments for std_1s10:inst|clock_0:the_clock_0 |
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Assignment | Value | From | To |
---|---|---|---|
PRESERVE_REGISTER | ON | - | master_address[3] |
PRESERVE_REGISTER | ON | - | master_address[2] |
PRESERVE_REGISTER | ON | - | master_address[1] |
PRESERVE_REGISTER | ON | - | master_address[0] |
PRESERVE_REGISTER | ON | - | master_byteenable[1] |
PRESERVE_REGISTER | ON | - | master_byteenable[0] |
PRESERVE_REGISTER | ON | - | master_nativeaddress[2] |
PRESERVE_REGISTER | ON | - | master_nativeaddress[1] |
PRESERVE_REGISTER | ON | - | master_nativeaddress[0] |
PRESERVE_REGISTER | ON | - | master_writedata[15] |
PRESERVE_REGISTER | ON | - | master_writedata[14] |
PRESERVE_REGISTER | ON | - | master_writedata[13] |
PRESERVE_REGISTER | ON | - | master_writedata[12] |
PRESERVE_REGISTER | ON | - | master_writedata[11] |
PRESERVE_REGISTER | ON | - | master_writedata[10] |
PRESERVE_REGISTER | ON | - | master_writedata[9] |
PRESERVE_REGISTER | ON | - | master_writedata[8] |
PRESERVE_REGISTER | ON | - | master_writedata[7] |
PRESERVE_REGISTER | ON | - | master_writedata[6] |
PRESERVE_REGISTER | ON | - | master_writedata[5] |
PRESERVE_REGISTER | ON | - | master_writedata[4] |
PRESERVE_REGISTER | ON | - | master_writedata[3] |
PRESERVE_REGISTER | ON | - | master_writedata[2] |
PRESERVE_REGISTER | ON | - | master_writedata[1] |
PRESERVE_REGISTER | ON | - | master_writedata[0] |
CUT | ON | * | slave_readdata[15] |
CUT | ON | * | slave_readdata[14] |
CUT | ON | * | slave_readdata[13] |
CUT | ON | * | slave_readdata[12] |
CUT | ON | * | slave_readdata[11] |
CUT | ON | * | slave_readdata[10] |
CUT | ON | * | slave_readdata[9] |
CUT | ON | * | slave_readdata[8] |
CUT | ON | * | slave_readdata[7] |
CUT | ON | * | slave_readdata[6] |
CUT | ON | * | slave_readdata[5] |
CUT | ON | * | slave_readdata[4] |
CUT | ON | * | slave_readdata[3] |
CUT | ON | * | slave_readdata[2] |
CUT | ON | * | slave_readdata[1] |
CUT | ON | * | slave_readdata[0] |
PRESERVE_REGISTER | ON | - | master_byteenable[0]~reg0 |
PRESERVE_REGISTER | ON | - | master_byteenable[1]~reg0 |
CUT | ON | slave_byteenable_d1[0] | * |
PRESERVE_REGISTER | ON | - | slave_byteenable_d1[0] |
CUT | ON | slave_byteenable_d1[1] | * |
PRESERVE_REGISTER | ON | - | slave_byteenable_d1[1] |
PRESERVE_REGISTER | ON | - | master_nativeaddress[0]~reg0 |
PRESERVE_REGISTER | ON | - | master_nativeaddress[1]~reg0 |
PRESERVE_REGISTER | ON | - | master_nativeaddress[2]~reg0 |
CUT | ON | slave_nativeaddress_d1[0] | * |
PRESERVE_REGISTER | ON | - | slave_nativeaddress_d1[0] |
CUT | ON | slave_nativeaddress_d1[1] | * |
PRESERVE_REGISTER | ON | - | slave_nativeaddress_d1[1] |
CUT | ON | slave_nativeaddress_d1[2] | * |
PRESERVE_REGISTER | ON | - | slave_nativeaddress_d1[2] |
PRESERVE_REGISTER | ON | - | master_address[0]~reg0 |
PRESERVE_REGISTER | ON | - | master_address[1]~reg0 |
PRESERVE_REGISTER | ON | - | master_address[2]~reg0 |
PRESERVE_REGISTER | ON | - | master_address[3]~reg0 |
CUT | ON | slave_address_d1[0] | * |
PRESERVE_REGISTER | ON | - | slave_address_d1[0] |
CUT | ON | slave_address_d1[1] | * |
PRESERVE_REGISTER | ON | - | slave_address_d1[1] |
CUT | ON | slave_address_d1[2] | * |
PRESERVE_REGISTER | ON | - | slave_address_d1[2] |
CUT | ON | slave_address_d1[3] | * |
PRESERVE_REGISTER | ON | - | slave_address_d1[3] |
PRESERVE_REGISTER | ON | - | master_writedata[0]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[1]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[2]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[3]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[4]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[5]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[6]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[7]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[8]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[9]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[10]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[11]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[12]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[13]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[14]~reg0 |
PRESERVE_REGISTER | ON | - | master_writedata[15]~reg0 |
CUT | ON | slave_writedata_d1[0] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[0] |
CUT | ON | slave_writedata_d1[1] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[1] |
CUT | ON | slave_writedata_d1[2] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[2] |
CUT | ON | slave_writedata_d1[3] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[3] |
CUT | ON | slave_writedata_d1[4] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[4] |
CUT | ON | slave_writedata_d1[5] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[5] |
CUT | ON | slave_writedata_d1[6] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[6] |
CUT | ON | slave_writedata_d1[7] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[7] |
CUT | ON | slave_writedata_d1[8] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[8] |
CUT | ON | slave_writedata_d1[9] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[9] |
CUT | ON | slave_writedata_d1[10] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[10] |
CUT | ON | slave_writedata_d1[11] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[11] |
CUT | ON | slave_writedata_d1[12] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[12] |
CUT | ON | slave_writedata_d1[13] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[13] |
CUT | ON | slave_writedata_d1[14] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[14] |
CUT | ON | slave_writedata_d1[15] | * |
PRESERVE_REGISTER | ON | - | slave_writedata_d1[15] |
CUT | ON | * | slave_readdata[0]~reg0 |
CUT | ON | * | slave_readdata[1]~reg0 |
CUT | ON | * | slave_readdata[2]~reg0 |
CUT | ON | * | slave_readdata[3]~reg0 |
CUT | ON | * | slave_readdata[4]~reg0 |
CUT | ON | * | slave_readdata[5]~reg0 |
CUT | ON | * | slave_readdata[6]~reg0 |
CUT | ON | * | slave_readdata[7]~reg0 |
CUT | ON | * | slave_readdata[8]~reg0 |
CUT | ON | * | slave_readdata[9]~reg0 |
CUT | ON | * | slave_readdata[10]~reg0 |
CUT | ON | * | slave_readdata[11]~reg0 |
CUT | ON | * | slave_readdata[12]~reg0 |
CUT | ON | * | slave_readdata[13]~reg0 |
CUT | ON | * | slave_readdata[14]~reg0 |
CUT | ON | * | slave_readdata[15]~reg0 |
Source assignments for std_1s10:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync |
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Assignment | Value | From | To |
---|---|---|---|
PRESERVE_REGISTER | ON | - | data_out |
PRESERVE_REGISTER | ON | - | data_out~reg0 |
MAX_DELAY | 100ns | - | data_in_d1 |
PRESERVE_REGISTER | ON | - | data_in_d1 |
Source assignments for std_1s10:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync |
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Assignment | Value | From | To |
---|---|---|---|
PRESERVE_REGISTER | ON | - | data_out |
PRESERVE_REGISTER | ON | - | data_out~reg0 |
MAX_DELAY | 100ns | - | data_in_d1 |
PRESERVE_REGISTER | ON | - | data_in_d1 |
Source assignments for std_1s10:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync |
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Assignment | Value | From | To |
---|---|---|---|
PRESERVE_REGISTER | ON | - | data_out |
PRESERVE_REGISTER | ON | - | data_out~reg0 |
MAX_DELAY | 100ns | - | data_in_d1 |
PRESERVE_REGISTER | ON | - | data_in_d1 |
Source assignments for std_1s10:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync |
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Assignment | Value | From | To |
---|---|---|---|
PRESERVE_REGISTER | ON | - | data_out |
PRESERVE_REGISTER | ON | - | data_out~reg0 |
MAX_DELAY | 100ns | - | data_in_d1 |
PRESERVE_REGISTER | ON | - | data_in_d1 |
Source assignments for std_1s10:inst|clock_0:the_clock_0|clock_0_bit_pipe:endofpacket_bit_pipe |
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Assignment | Value | From | To |
---|---|---|---|
PRESERVE_REGISTER | ON | - | data_out |
PRESERVE_REGISTER | ON | - | data_out~reg0 |
CUT | ON | data_in_d1 | * |
PRESERVE_REGISTER | ON | - | data_in_d1 |
Source assignments for std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated |
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Assignment | Value | From | To |
---|---|---|---|
OPTIMIZE_POWER_DURING_SYNTHESIS | NORMAL_COMPILATION | - | - |
Source assignments for std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated |
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Assignment | Value | From | To |
---|---|---|---|
OPTIMIZE_POWER_DURING_SYNTHESIS | NORMAL_COMPILATION | - | - |
Source assignments for std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated |
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Assignment | Value | From | To |
---|---|---|---|
OPTIMIZE_POWER_DURING_SYNTHESIS | NORMAL_COMPILATION | - | - |
Source assignments for std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated |
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Assignment | Value | From | To |
---|---|---|---|
OPTIMIZE_POWER_DURING_SYNTHESIS | NORMAL_COMPILATION | - | - |
Source assignments for std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated |
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Assignment | Value | From | To |
---|---|---|---|
OPTIMIZE_POWER_DURING_SYNTHESIS | NORMAL_COMPILATION | - | - |
Source assignments for std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated |
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Assignment | Value | From | To |
---|---|---|---|
OPTIMIZE_POWER_DURING_SYNTHESIS | NORMAL_COMPILATION | - | - |
Source assignments for std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave |
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Assignment | Value | From | To |
---|---|---|---|
FAST_OUTPUT_REGISTER | ON | - | be_n_to_the_ext_ram[3] |
FAST_OUTPUT_REGISTER | ON | - | be_n_to_the_ext_ram[2] |
FAST_OUTPUT_REGISTER | ON | - | be_n_to_the_ext_ram[1] |
FAST_OUTPUT_REGISTER | ON | - | be_n_to_the_ext_ram[0] |
FAST_OUTPUT_REGISTER | ON | - | byteenablen_to_the_lan91c111[3] |
FAST_OUTPUT_REGISTER | ON | - | byteenablen_to_the_lan91c111[2] |
FAST_OUTPUT_REGISTER | ON | - | byteenablen_to_the_lan91c111[1] |
FAST_OUTPUT_REGISTER | ON | - | byteenablen_to_the_lan91c111[0] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[22] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[21] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[20] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[19] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[18] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[17] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[16] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[15] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[14] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[13] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[12] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[11] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[10] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[9] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[8] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[7] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[6] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[5] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[4] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[3] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[2] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[1] |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[0] |
FAST_OUTPUT_REGISTER | ON | - | ior_n_to_the_lan91c111 |
FAST_OUTPUT_REGISTER | ON | - | iow_n_to_the_lan91c111 |
FAST_OUTPUT_REGISTER | ON | - | read_n_to_the_ext_flash |
FAST_OUTPUT_REGISTER | ON | - | read_n_to_the_ext_ram |
FAST_OUTPUT_REGISTER | ON | - | reset_to_the_lan91c111 |
FAST_OUTPUT_REGISTER | ON | - | select_n_to_the_ext_flash |
FAST_OUTPUT_REGISTER | ON | - | select_n_to_the_ext_ram |
FAST_OUTPUT_REGISTER | ON | - | write_n_to_the_ext_flash |
FAST_OUTPUT_REGISTER | ON | - | reset_to_the_lan91c111~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ior_n_to_the_lan91c111~reg0 |
FAST_OUTPUT_REGISTER | ON | - | iow_n_to_the_lan91c111~reg0 |
FAST_OUTPUT_REGISTER | ON | - | byteenablen_to_the_lan91c111[3]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | byteenablen_to_the_lan91c111[2]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | byteenablen_to_the_lan91c111[1]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | byteenablen_to_the_lan91c111[0]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[22]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[21]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[20]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[19]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[18]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[17]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[16]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[15]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[14]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[13]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[12]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[11]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[10]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[9]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[8]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[7]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[6]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[5]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[4]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[3]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[2]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[1]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | ext_ram_bus_address[0]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | read_n_to_the_ext_flash~reg0 |
FAST_OUTPUT_REGISTER | ON | - | write_n_to_the_ext_flash~reg0 |
FAST_OUTPUT_REGISTER | ON | - | read_n_to_the_ext_ram~reg0 |
FAST_OUTPUT_REGISTER | ON | - | be_n_to_the_ext_ram[3]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | be_n_to_the_ext_ram[2]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | be_n_to_the_ext_ram[1]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | be_n_to_the_ext_ram[0]~reg0 |
FAST_OUTPUT_ENABLE_REGISTER | ON | - | d1_in_a_write_cycle |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[0] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[1] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[2] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[3] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[4] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[5] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[6] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[7] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[8] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[9] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[10] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[11] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[12] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[13] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[14] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[15] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[16] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[17] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[18] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[19] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[20] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[21] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[22] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[23] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[24] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[25] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[26] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[27] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[28] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[29] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[30] |
FAST_OUTPUT_REGISTER | ON | - | d1_outgoing_ext_ram_bus_data[31] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[0] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[1] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[2] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[3] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[4] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[5] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[6] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[7] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[8] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[9] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[10] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[11] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[12] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[13] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[14] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[15] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[16] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[17] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[18] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[19] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[20] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[21] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[22] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[23] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[24] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[25] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[26] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[27] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[28] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[29] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[30] |
FAST_INPUT_REGISTER | ON | - | internal_incoming_ext_ram_bus_data[31] |
FAST_OUTPUT_REGISTER | ON | - | select_n_to_the_ext_ram~reg0 |
FAST_OUTPUT_REGISTER | ON | - | select_n_to_the_ext_flash~reg0 |
Source assignments for std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1 |
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Assignment | Value | From | To |
---|---|---|---|
OPTIMIZE_POWER_DURING_SYNTHESIS | NORMAL_COMPILATION | - | - |
Source assignments for std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1 |
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Assignment | Value | From | To |
---|---|---|---|
OPTIMIZE_POWER_DURING_SYNTHESIS | NORMAL_COMPILATION | - | - |
Source assignments for std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated |
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Assignment | Value | From | To |
---|---|---|---|
OPTIMIZE_POWER_DURING_SYNTHESIS | NORMAL_COMPILATION | - | - |
Source assignments for std_1s10:inst|pll:the_pll |
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Assignment | Value | From | To |
---|---|---|---|
PRESERVE_REGISTER | ON | - | not_areset |
Source assignments for std_1s10:inst|sdram:the_sdram |
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Assignment | Value | From | To |
---|---|---|---|
FAST_INPUT_REGISTER | ON | - | za_data[31] |
FAST_INPUT_REGISTER | ON | - | za_data[30] |
FAST_INPUT_REGISTER | ON | - | za_data[29] |
FAST_INPUT_REGISTER | ON | - | za_data[28] |
FAST_INPUT_REGISTER | ON | - | za_data[27] |
FAST_INPUT_REGISTER | ON | - | za_data[26] |
FAST_INPUT_REGISTER | ON | - | za_data[25] |
FAST_INPUT_REGISTER | ON | - | za_data[24] |
FAST_INPUT_REGISTER | ON | - | za_data[23] |
FAST_INPUT_REGISTER | ON | - | za_data[22] |
FAST_INPUT_REGISTER | ON | - | za_data[21] |
FAST_INPUT_REGISTER | ON | - | za_data[20] |
FAST_INPUT_REGISTER | ON | - | za_data[19] |
FAST_INPUT_REGISTER | ON | - | za_data[18] |
FAST_INPUT_REGISTER | ON | - | za_data[17] |
FAST_INPUT_REGISTER | ON | - | za_data[16] |
FAST_INPUT_REGISTER | ON | - | za_data[15] |
FAST_INPUT_REGISTER | ON | - | za_data[14] |
FAST_INPUT_REGISTER | ON | - | za_data[13] |
FAST_INPUT_REGISTER | ON | - | za_data[12] |
FAST_INPUT_REGISTER | ON | - | za_data[11] |
FAST_INPUT_REGISTER | ON | - | za_data[10] |
FAST_INPUT_REGISTER | ON | - | za_data[9] |
FAST_INPUT_REGISTER | ON | - | za_data[8] |
FAST_INPUT_REGISTER | ON | - | za_data[7] |
FAST_INPUT_REGISTER | ON | - | za_data[6] |
FAST_INPUT_REGISTER | ON | - | za_data[5] |
FAST_INPUT_REGISTER | ON | - | za_data[4] |
FAST_INPUT_REGISTER | ON | - | za_data[3] |
FAST_INPUT_REGISTER | ON | - | za_data[2] |
FAST_INPUT_REGISTER | ON | - | za_data[1] |
FAST_INPUT_REGISTER | ON | - | za_data[0] |
FAST_INPUT_REGISTER | ON | - | za_data[6]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[5]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[4]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[3]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[2]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[1]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[0]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[7]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[8]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[9]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[10]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[11]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[12]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[13]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[14]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[15]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[16]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[17]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[18]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[19]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[20]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[21]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[22]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[23]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[24]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[25]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[26]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[27]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[28]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[29]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[30]~reg0 |
FAST_INPUT_REGISTER | ON | - | za_data[31]~reg0 |
FAST_OUTPUT_REGISTER | ON | - | m_dqm[0] |
FAST_OUTPUT_REGISTER | ON | - | m_dqm[1] |
FAST_OUTPUT_REGISTER | ON | - | m_dqm[2] |
FAST_OUTPUT_REGISTER | ON | - | m_dqm[3] |
FAST_OUTPUT_REGISTER | ON | - | m_data[0] |
FAST_OUTPUT_REGISTER | ON | - | m_data[1] |
FAST_OUTPUT_REGISTER | ON | - | m_data[2] |
FAST_OUTPUT_REGISTER | ON | - | m_data[3] |
FAST_OUTPUT_REGISTER | ON | - | m_data[4] |
FAST_OUTPUT_REGISTER | ON | - | m_data[5] |
FAST_OUTPUT_REGISTER | ON | - | m_data[6] |
FAST_OUTPUT_REGISTER | ON | - | m_data[7] |
FAST_OUTPUT_REGISTER | ON | - | m_data[8] |
FAST_OUTPUT_REGISTER | ON | - | m_data[9] |
FAST_OUTPUT_REGISTER | ON | - | m_data[10] |
FAST_OUTPUT_REGISTER | ON | - | m_data[11] |
FAST_OUTPUT_REGISTER | ON | - | m_data[12] |
FAST_OUTPUT_REGISTER | ON | - | m_data[13] |
FAST_OUTPUT_REGISTER | ON | - | m_data[14] |
FAST_OUTPUT_REGISTER | ON | - | m_data[15] |
FAST_OUTPUT_REGISTER | ON | - | m_data[16] |
FAST_OUTPUT_REGISTER | ON | - | m_data[17] |
FAST_OUTPUT_REGISTER | ON | - | m_data[18] |
FAST_OUTPUT_REGISTER | ON | - | m_data[19] |
FAST_OUTPUT_REGISTER | ON | - | m_data[20] |
FAST_OUTPUT_REGISTER | ON | - | m_data[21] |
FAST_OUTPUT_REGISTER | ON | - | m_data[22] |
FAST_OUTPUT_REGISTER | ON | - | m_data[23] |
FAST_OUTPUT_REGISTER | ON | - | m_data[24] |
FAST_OUTPUT_REGISTER | ON | - | m_data[25] |
FAST_OUTPUT_REGISTER | ON | - | m_data[26] |
FAST_OUTPUT_REGISTER | ON | - | m_data[27] |
FAST_OUTPUT_REGISTER | ON | - | m_data[28] |
FAST_OUTPUT_REGISTER | ON | - | m_data[29] |
FAST_OUTPUT_REGISTER | ON | - | m_data[30] |
FAST_OUTPUT_REGISTER | ON | - | m_data[31] |
FAST_OUTPUT_REGISTER | ON | - | m_addr[0] |
FAST_OUTPUT_REGISTER | ON | - | m_addr[1] |
FAST_OUTPUT_REGISTER | ON | - | m_addr[2] |
FAST_OUTPUT_REGISTER | ON | - | m_addr[3] |
FAST_OUTPUT_REGISTER | ON | - | m_addr[4] |
FAST_OUTPUT_REGISTER | ON | - | m_addr[5] |
FAST_OUTPUT_REGISTER | ON | - | m_addr[6] |
FAST_OUTPUT_REGISTER | ON | - | m_addr[7] |
FAST_OUTPUT_REGISTER | ON | - | m_addr[8] |
FAST_OUTPUT_REGISTER | ON | - | m_addr[9] |
FAST_OUTPUT_REGISTER | ON | - | m_addr[10] |
FAST_OUTPUT_REGISTER | ON | - | m_addr[11] |
FAST_OUTPUT_REGISTER | ON | - | m_bank[0] |
FAST_OUTPUT_REGISTER | ON | - | m_bank[1] |
FAST_OUTPUT_REGISTER | ON | - | m_cmd[0] |
FAST_OUTPUT_REGISTER | ON | - | m_cmd[1] |
FAST_OUTPUT_REGISTER | ON | - | m_cmd[2] |
FAST_OUTPUT_REGISTER | ON | - | m_cmd[3] |
Source assignments for std_1s10:inst|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch |
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Assignment | Value | From | To |
---|---|---|---|
PRESERVE_REGISTER | ON | - | data_out |
PRESERVE_REGISTER | ON | - | data_out~reg0 |
MAX_DELAY | 100ns | - | data_in_d1 |
PRESERVE_REGISTER | ON | - | data_in_d1 |
Source assignments for std_1s10:inst|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch |
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Assignment | Value | From | To |
---|---|---|---|
PRESERVE_REGISTER | ON | - | data_out |
PRESERVE_REGISTER | ON | - | data_out~reg0 |
MAX_DELAY | 100ns | - | data_in_d1 |
PRESERVE_REGISTER | ON | - | data_in_d1 |
Source assignments for sld_hub:sld_hub_inst |
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Assignment | Value | From | To |
---|---|---|---|
IGNORE_LCELL_BUFFERS | OFF | - | - |
REMOVE_REDUNDANT_LOGIC_CELLS | OFF | - | - |
NOT_GATE_PUSH_BACK | OFF | - | CLR_SIGNAL |
POWER_UP_LEVEL | LOW | - | CLR_SIGNAL |
Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine |
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Assignment | Value | From | To |
---|---|---|---|
POWER_UP_LEVEL | Low | - | state[0] |
POWER_UP_LEVEL | Low | - | state[1] |
POWER_UP_LEVEL | Low | - | state[2] |
POWER_UP_LEVEL | Low | - | state[3] |
POWER_UP_LEVEL | Low | - | state[4] |
POWER_UP_LEVEL | Low | - | state[5] |
POWER_UP_LEVEL | Low | - | state[6] |
POWER_UP_LEVEL | Low | - | state[7] |
POWER_UP_LEVEL | Low | - | state[8] |
POWER_UP_LEVEL | Low | - | state[9] |
POWER_UP_LEVEL | Low | - | state[10] |
POWER_UP_LEVEL | Low | - | state[11] |
POWER_UP_LEVEL | Low | - | state[12] |
POWER_UP_LEVEL | Low | - | state[13] |
POWER_UP_LEVEL | Low | - | state[14] |
POWER_UP_LEVEL | Low | - | state[15] |
Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG |
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Assignment | Value | From | To |
---|---|---|---|
AUTO_ROM_RECOGNITION | OFF | - | - |
POWER_UP_LEVEL | Low | - | word_counter[0] |
POWER_UP_LEVEL | Low | - | word_counter[1] |
POWER_UP_LEVEL | Low | - | word_counter[2] |
POWER_UP_LEVEL | Low | - | word_counter[3] |
POWER_UP_LEVEL | Low | - | word_counter[4] |
Parameter Settings for User Entity Instance: std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data |
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Parameter Name | Value | Type |
---|---|---|
lpm_file | String |
Parameter Settings for User Entity Instance: std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram |
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Parameter Name | Value | Type |
---|---|---|
BYTE_SIZE_BLOCK | 8 | Untyped |
AUTO_CARRY_CHAINS | ON | AUTO_CARRY |
IGNORE_CARRY_BUFFERS | OFF | IGNORE_CARRY |
AUTO_CASCADE_CHAINS | ON | AUTO_CASCADE |
IGNORE_CASCADE_BUFFERS | OFF | IGNORE_CASCADE |
OPERATION_MODE | DUAL_PORT | Untyped |
WIDTH_A | 32 | Integer |
WIDTHAD_A | 10 | Integer |
NUMWORDS_A | 1024 | Integer |
OUTDATA_REG_A | UNREGISTERED | Untyped |
ADDRESS_ACLR_A | NONE | Untyped |
OUTDATA_ACLR_A | NONE | Untyped |
WRCONTROL_ACLR_A | NONE | Untyped |
INDATA_ACLR_A | NONE | Untyped |
BYTEENA_ACLR_A | NONE | Untyped |
WIDTH_B | 32 | Integer |
WIDTHAD_B | 10 | Integer |
NUMWORDS_B | 1024 | Integer |
INDATA_REG_B | CLOCK1 | Untyped |
WRCONTROL_WRADDRESS_REG_B | CLOCK1 | Untyped |
RDCONTROL_REG_B | CLOCK1 | Untyped |
ADDRESS_REG_B | CLOCK1 | Untyped |
OUTDATA_REG_B | UNREGISTERED | Untyped |
BYTEENA_REG_B | CLOCK1 | Untyped |
INDATA_ACLR_B | NONE | Untyped |
WRCONTROL_ACLR_B | NONE | Untyped |
ADDRESS_ACLR_B | NONE | Untyped |
OUTDATA_ACLR_B | NONE | Untyped |
RDCONTROL_ACLR_B | NONE | Untyped |
BYTEENA_ACLR_B | NONE | Untyped |
WIDTH_BYTEENA_A | 1 | Untyped |
WIDTH_BYTEENA_B | 1 | Untyped |
RAM_BLOCK_TYPE | AUTO | Untyped |
BYTE_SIZE | 8 | Untyped |
READ_DURING_WRITE_MODE_MIXED_PORTS | DONT_CARE | Untyped |
INIT_FILE | UNUSED | Untyped |
INIT_FILE_LAYOUT | PORT_A | Untyped |
MAXIMUM_DEPTH | 0 | Integer |
CLOCK_ENABLE_INPUT_A | NORMAL | Untyped |
CLOCK_ENABLE_INPUT_B | NORMAL | Untyped |
CLOCK_ENABLE_OUTPUT_A | NORMAL | Untyped |
CLOCK_ENABLE_OUTPUT_B | NORMAL | Untyped |
DEVICE_FAMILY | Stratix | Untyped |
CBXI_PARAMETER | altsyncram_nnb1 | Untyped |
Parameter Settings for User Entity Instance: std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag |
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Parameter Name | Value | Type |
---|---|---|
lpm_file | cpu_ic_tag_ram.mif | String |
Parameter Settings for User Entity Instance: std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram |
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Parameter Name | Value | Type |
---|---|---|
BYTE_SIZE_BLOCK | 8 | Untyped |
AUTO_CARRY_CHAINS | ON | AUTO_CARRY |
IGNORE_CARRY_BUFFERS | OFF | IGNORE_CARRY |
AUTO_CASCADE_CHAINS | ON | AUTO_CASCADE |
IGNORE_CASCADE_BUFFERS | OFF | IGNORE_CASCADE |
OPERATION_MODE | DUAL_PORT | Untyped |
WIDTH_A | 22 | Integer |
WIDTHAD_A | 7 | Integer |
NUMWORDS_A | 128 | Integer |
OUTDATA_REG_A | UNREGISTERED | Untyped |
ADDRESS_ACLR_A | NONE | Untyped |
OUTDATA_ACLR_A | NONE | Untyped |
WRCONTROL_ACLR_A | NONE | Untyped |
INDATA_ACLR_A | NONE | Untyped |
BYTEENA_ACLR_A | NONE | Untyped |
WIDTH_B | 22 | Integer |
WIDTHAD_B | 7 | Integer |
NUMWORDS_B | 128 | Integer |
INDATA_REG_B | CLOCK1 | Untyped |
WRCONTROL_WRADDRESS_REG_B | CLOCK1 | Untyped |
RDCONTROL_REG_B | CLOCK1 | Untyped |
ADDRESS_REG_B | CLOCK1 | Untyped |
OUTDATA_REG_B | UNREGISTERED | Untyped |
BYTEENA_REG_B | CLOCK1 | Untyped |
INDATA_ACLR_B | NONE | Untyped |
WRCONTROL_ACLR_B | NONE | Untyped |
ADDRESS_ACLR_B | NONE | Untyped |
OUTDATA_ACLR_B | NONE | Untyped |
RDCONTROL_ACLR_B | NONE | Untyped |
BYTEENA_ACLR_B | NONE | Untyped |
WIDTH_BYTEENA_A | 1 | Untyped |
WIDTH_BYTEENA_B | 1 | Untyped |
RAM_BLOCK_TYPE | AUTO | Untyped |
BYTE_SIZE | 8 | Untyped |
READ_DURING_WRITE_MODE_MIXED_PORTS | OLD_DATA | Untyped |
INIT_FILE | cpu_ic_tag_ram.mif | Untyped |
INIT_FILE_LAYOUT | PORT_A | Untyped |
MAXIMUM_DEPTH | 0 | Integer |
CLOCK_ENABLE_INPUT_A | NORMAL | Untyped |
CLOCK_ENABLE_INPUT_B | NORMAL | Untyped |
CLOCK_ENABLE_OUTPUT_A | NORMAL | Untyped |
CLOCK_ENABLE_OUTPUT_B | NORMAL | Untyped |
DEVICE_FAMILY | Stratix | Untyped |
CBXI_PARAMETER | altsyncram_t9e1 | Untyped |
Parameter Settings for User Entity Instance: std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a |
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Parameter Name | Value | Type |
---|---|---|
lpm_file | cpu_rf_ram_a.mif | String |
Parameter Settings for User Entity Instance: std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram |
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Parameter Name | Value | Type |
---|---|---|
BYTE_SIZE_BLOCK | 8 | Untyped |
AUTO_CARRY_CHAINS | ON | AUTO_CARRY |
IGNORE_CARRY_BUFFERS | OFF | IGNORE_CARRY |
AUTO_CASCADE_CHAINS | ON | AUTO_CASCADE |
IGNORE_CASCADE_BUFFERS | OFF | IGNORE_CASCADE |
OPERATION_MODE | DUAL_PORT | Untyped |
WIDTH_A | 32 | Integer |
WIDTHAD_A | 5 | Integer |
NUMWORDS_A | 32 | Integer |
OUTDATA_REG_A | UNREGISTERED | Untyped |
ADDRESS_ACLR_A | NONE | Untyped |
OUTDATA_ACLR_A | NONE | Untyped |
WRCONTROL_ACLR_A | NONE | Untyped |
INDATA_ACLR_A | NONE | Untyped |
BYTEENA_ACLR_A | NONE | Untyped |
WIDTH_B | 32 | Integer |
WIDTHAD_B | 5 | Integer |
NUMWORDS_B | 32 | Integer |
INDATA_REG_B | CLOCK1 | Untyped |
WRCONTROL_WRADDRESS_REG_B | CLOCK1 | Untyped |
RDCONTROL_REG_B | CLOCK1 | Untyped |
ADDRESS_REG_B | CLOCK1 | Untyped |
OUTDATA_REG_B | UNREGISTERED | Untyped |
BYTEENA_REG_B | CLOCK1 | Untyped |
INDATA_ACLR_B | NONE | Untyped |
WRCONTROL_ACLR_B | NONE | Untyped |
ADDRESS_ACLR_B | NONE | Untyped |
OUTDATA_ACLR_B | NONE | Untyped |
RDCONTROL_ACLR_B | NONE | Untyped |
BYTEENA_ACLR_B | NONE | Untyped |
WIDTH_BYTEENA_A | 1 | Untyped |
WIDTH_BYTEENA_B | 1 | Untyped |
RAM_BLOCK_TYPE | AUTO | Untyped |
BYTE_SIZE | 8 | Untyped |
READ_DURING_WRITE_MODE_MIXED_PORTS | OLD_DATA | Untyped |
INIT_FILE | cpu_rf_ram_a.mif | Untyped |
INIT_FILE_LAYOUT | PORT_A | Untyped |
MAXIMUM_DEPTH | 0 | Integer |
CLOCK_ENABLE_INPUT_A | NORMAL | Untyped |
CLOCK_ENABLE_INPUT_B | NORMAL | Untyped |
CLOCK_ENABLE_OUTPUT_A | NORMAL | Untyped |
CLOCK_ENABLE_OUTPUT_B | NORMAL | Untyped |
DEVICE_FAMILY | Stratix | Untyped |
CBXI_PARAMETER | altsyncram_00e1 | Untyped |
Parameter Settings for User Entity Instance: std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b |
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Parameter Name | Value | Type |
---|---|---|
lpm_file | cpu_rf_ram_b.mif | String |
Parameter Settings for User Entity Instance: std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram |
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Parameter Name | Value | Type |
---|---|---|
BYTE_SIZE_BLOCK | 8 | Untyped |
AUTO_CARRY_CHAINS | ON | AUTO_CARRY |
IGNORE_CARRY_BUFFERS | OFF | IGNORE_CARRY |
AUTO_CASCADE_CHAINS | ON | AUTO_CASCADE |
IGNORE_CASCADE_BUFFERS | OFF | IGNORE_CASCADE |
OPERATION_MODE | DUAL_PORT | Untyped |
WIDTH_A | 32 | Integer |
WIDTHAD_A | 5 | Integer |
NUMWORDS_A | 32 | Integer |
OUTDATA_REG_A | UNREGISTERED | Untyped |
ADDRESS_ACLR_A | NONE | Untyped |
OUTDATA_ACLR_A | NONE | Untyped |
WRCONTROL_ACLR_A | NONE | Untyped |
INDATA_ACLR_A | NONE | Untyped |
BYTEENA_ACLR_A | NONE | Untyped |
WIDTH_B | 32 | Integer |
WIDTHAD_B | 5 | Integer |
NUMWORDS_B | 32 | Integer |
INDATA_REG_B | CLOCK1 | Untyped |
WRCONTROL_WRADDRESS_REG_B | CLOCK1 | Untyped |
RDCONTROL_REG_B | CLOCK1 | Untyped |
ADDRESS_REG_B | CLOCK1 | Untyped |
OUTDATA_REG_B | UNREGISTERED | Untyped |
BYTEENA_REG_B | CLOCK1 | Untyped |
INDATA_ACLR_B | NONE | Untyped |
WRCONTROL_ACLR_B | NONE | Untyped |
ADDRESS_ACLR_B | NONE | Untyped |
OUTDATA_ACLR_B | NONE | Untyped |
RDCONTROL_ACLR_B | NONE | Untyped |
BYTEENA_ACLR_B | NONE | Untyped |
WIDTH_BYTEENA_A | 1 | Untyped |
WIDTH_BYTEENA_B | 1 | Untyped |
RAM_BLOCK_TYPE | AUTO | Untyped |
BYTE_SIZE | 8 | Untyped |
READ_DURING_WRITE_MODE_MIXED_PORTS | OLD_DATA | Untyped |
INIT_FILE | cpu_rf_ram_b.mif | Untyped |
INIT_FILE_LAYOUT | PORT_A | Untyped |
MAXIMUM_DEPTH | 0 | Integer |
CLOCK_ENABLE_INPUT_A | NORMAL | Untyped |
CLOCK_ENABLE_INPUT_B | NORMAL | Untyped |
CLOCK_ENABLE_OUTPUT_A | NORMAL | Untyped |
CLOCK_ENABLE_OUTPUT_B | NORMAL | Untyped |
DEVICE_FAMILY | Stratix | Untyped |
CBXI_PARAMETER | altsyncram_10e1 | Untyped |
Parameter Settings for User Entity Instance: std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add |
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Parameter Name | Value | Type |
---|---|---|
AUTO_CARRY_CHAINS | ON | AUTO_CARRY |
IGNORE_CARRY_BUFFERS | OFF | IGNORE_CARRY |
AUTO_CASCADE_CHAINS | ON | AUTO_CASCADE |
IGNORE_CASCADE_BUFFERS | OFF | IGNORE_CASCADE |
NUMBER_OF_MULTIPLIERS | 1 | Integer |
WIDTH_A | 32 | Integer |
WIDTH_B | 32 | Integer |
WIDTH_RESULT | 64 | Integer |
INPUT_REGISTER_A0 | CLOCK0 | Untyped |
INPUT_ACLR_A0 | ACLR0 | Untyped |
INPUT_SOURCE_A0 | DATAA | Untyped |
INPUT_REGISTER_A1 | CLOCK0 | Untyped |
INPUT_ACLR_A1 | ACLR3 | Untyped |
INPUT_SOURCE_A1 | DATAA | Untyped |
INPUT_REGISTER_A2 | CLOCK0 | Untyped |
INPUT_ACLR_A2 | ACLR3 | Untyped |
INPUT_SOURCE_A2 | DATAA | Untyped |
INPUT_REGISTER_A3 | CLOCK0 | Untyped |
INPUT_ACLR_A3 | ACLR3 | Untyped |
INPUT_SOURCE_A3 | DATAA | Untyped |
REPRESENTATION_A | UNUSED | Untyped |
SIGNED_REGISTER_A | CLOCK0 | Untyped |
SIGNED_ACLR_A | ACLR0 | Untyped |
SIGNED_PIPELINE_REGISTER_A | UNREGISTERED | Untyped |
SIGNED_PIPELINE_ACLR_A | ACLR3 | Untyped |
INPUT_REGISTER_B0 | CLOCK0 | Untyped |
INPUT_ACLR_B0 | ACLR0 | Untyped |
INPUT_SOURCE_B0 | DATAB | Untyped |
INPUT_REGISTER_B1 | CLOCK0 | Untyped |
INPUT_ACLR_B1 | ACLR3 | Untyped |
INPUT_SOURCE_B1 | DATAB | Untyped |
INPUT_REGISTER_B2 | CLOCK0 | Untyped |
INPUT_ACLR_B2 | ACLR3 | Untyped |
INPUT_SOURCE_B2 | DATAB | Untyped |
INPUT_REGISTER_B3 | CLOCK0 | Untyped |
INPUT_ACLR_B3 | ACLR3 | Untyped |
INPUT_SOURCE_B3 | DATAB | Untyped |
REPRESENTATION_B | UNUSED | Untyped |
SIGNED_REGISTER_B | CLOCK0 | Untyped |
SIGNED_ACLR_B | ACLR0 | Untyped |
SIGNED_PIPELINE_REGISTER_B | UNREGISTERED | Untyped |
SIGNED_PIPELINE_ACLR_B | ACLR3 | Untyped |
MULTIPLIER_REGISTER0 | UNREGISTERED | Untyped |
MULTIPLIER_ACLR0 | ACLR3 | Untyped |
MULTIPLIER_REGISTER1 | CLOCK0 | Untyped |
MULTIPLIER_ACLR1 | ACLR3 | Untyped |
MULTIPLIER1_DIRECTION | ADD | Untyped |
ADDNSUB_MULTIPLIER_REGISTER1 | CLOCK0 | Untyped |
ADDNSUB_MULTIPLIER_ACLR1 | ACLR3 | Untyped |
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 | CLOCK0 | Untyped |
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 | ACLR3 | Untyped |
MULTIPLIER_REGISTER2 | CLOCK0 | Untyped |
MULTIPLIER_ACLR2 | ACLR3 | Untyped |
MULTIPLIER_REGISTER3 | CLOCK0 | Untyped |
MULTIPLIER_ACLR3 | ACLR3 | Untyped |
MULTIPLIER3_DIRECTION | UNUSED | Untyped |
ADDNSUB_MULTIPLIER_REGISTER3 | CLOCK0 | Untyped |
ADDNSUB_MULTIPLIER_ACLR3 | ACLR3 | Untyped |
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 | CLOCK0 | Untyped |
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 | ACLR3 | Untyped |
MULTIPLIER01_ROUNDING | NO | Untyped |
MULTIPLIER01_SATURATION | NO | Untyped |
MULTIPLIER23_ROUNDING | NO | Untyped |
MULTIPLIER23_SATURATION | NO | Untyped |
ADDER1_ROUNDING | NO | Untyped |
ADDER3_ROUNDING | NO | Untyped |
PORT_MULT0_IS_SATURATED | UNUSED | Untyped |
PORT_MULT1_IS_SATURATED | UNUSED | Untyped |
PORT_MULT2_IS_SATURATED | UNUSED | Untyped |
PORT_MULT3_IS_SATURATED | UNUSED | Untyped |
MULT01_ROUND_REGISTER | CLOCK0 | Untyped |
MULT01_ROUND_ACLR | ACLR3 | Untyped |
MULT23_ROUND_REGISTER | CLOCK0 | Untyped |
MULT23_ROUND_ACLR | ACLR3 | Untyped |
MULT01_SATURATION_REGISTER | CLOCK0 | Untyped |
MULT01_SATURATION_ACLR | ACLR3 | Untyped |
MULT23_SATURATION_REGISTER | CLOCK0 | Untyped |
MULT23_SATURATION_ACLR | ACLR3 | Untyped |
ADDNSUB1_ROUND_REGISTER | CLOCK0 | Untyped |
ADDNSUB1_ROUND_ACLR | ACLR3 | Untyped |
ADDNSUB1_ROUND_PIPELINE_REGISTER | CLOCK0 | Untyped |
ADDNSUB1_ROUND_PIPELINE_ACLR | ACLR3 | Untyped |
ADDNSUB3_ROUND_REGISTER | CLOCK0 | Untyped |
ADDNSUB3_ROUND_ACLR | ACLR3 | Untyped |
ADDNSUB3_ROUND_PIPELINE_REGISTER | CLOCK0 | Untyped |
ADDNSUB3_ROUND_PIPELINE_ACLR | ACLR3 | Untyped |
PORT_SIGNA | PORT_CONNECTIVITY | Untyped |
PORT_SIGNB | PORT_CONNECTIVITY | Untyped |
OUTPUT_REGISTER | CLOCK1 | Untyped |
OUTPUT_ACLR | ACLR1 | Untyped |
EXTRA_LATENCY | 0 | Untyped |
DEDICATED_MULTIPLIER_CIRCUITRY | YES | Untyped |
DSP_BLOCK_BALANCING | AUTO | Untyped |
CBXI_PARAMETER | mult_add_1f72 | Untyped |
DEVICE_FAMILY | Stratix | Untyped |
Parameter Settings for User Entity Instance: std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component |
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Parameter Name | Value | Type |
---|---|---|
lpm_file | cpu_ociram_default_contents.mif | String |
Parameter Settings for User Entity Instance: std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram |
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Parameter Name | Value | Type |
---|---|---|
BYTE_SIZE_BLOCK | 8 | Untyped |
AUTO_CARRY_CHAINS | ON | AUTO_CARRY |
IGNORE_CARRY_BUFFERS | OFF | IGNORE_CARRY |
AUTO_CASCADE_CHAINS | ON | AUTO_CASCADE |
IGNORE_CASCADE_BUFFERS | OFF | IGNORE_CASCADE |
OPERATION_MODE | BIDIR_DUAL_PORT | Untyped |
WIDTH_A | 32 | Integer |
WIDTHAD_A | 8 | Integer |
NUMWORDS_A | 256 | Integer |
OUTDATA_REG_A | UNREGISTERED | Untyped |
ADDRESS_ACLR_A | NONE | Untyped |
OUTDATA_ACLR_A | NONE | Untyped |
WRCONTROL_ACLR_A | NONE | Untyped |
INDATA_ACLR_A | NONE | Untyped |
BYTEENA_ACLR_A | NONE | Untyped |
WIDTH_B | 32 | Integer |
WIDTHAD_B | 8 | Integer |
NUMWORDS_B | 256 | Integer |
INDATA_REG_B | CLOCK1 | Untyped |
WRCONTROL_WRADDRESS_REG_B | CLOCK1 | Untyped |
RDCONTROL_REG_B | CLOCK1 | Untyped |
ADDRESS_REG_B | CLOCK1 | Untyped |
OUTDATA_REG_B | UNREGISTERED | Untyped |
BYTEENA_REG_B | CLOCK1 | Untyped |
INDATA_ACLR_B | NONE | Untyped |
WRCONTROL_ACLR_B | NONE | Untyped |
ADDRESS_ACLR_B | NONE | Untyped |
OUTDATA_ACLR_B | NONE | Untyped |
RDCONTROL_ACLR_B | NONE | Untyped |
BYTEENA_ACLR_B | NONE | Untyped |
WIDTH_BYTEENA_A | 4 | Integer |
WIDTH_BYTEENA_B | 1 | Untyped |
RAM_BLOCK_TYPE | AUTO | Untyped |
BYTE_SIZE | 8 | Untyped |
READ_DURING_WRITE_MODE_MIXED_PORTS | OLD_DATA | Untyped |
INIT_FILE | cpu_ociram_default_contents.mif | Untyped |
INIT_FILE_LAYOUT | PORT_A | Untyped |
MAXIMUM_DEPTH | 0 | Untyped |
CLOCK_ENABLE_INPUT_A | NORMAL | Untyped |
CLOCK_ENABLE_INPUT_B | NORMAL | Untyped |
CLOCK_ENABLE_OUTPUT_A | NORMAL | Untyped |
CLOCK_ENABLE_OUTPUT_B | NORMAL | Untyped |
DEVICE_FAMILY | Stratix | Untyped |
CBXI_PARAMETER | altsyncram_8q62 | Untyped |
Parameter Settings for User Entity Instance: std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component |
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Parameter Name | Value | Type |
---|---|---|
lpm_file | String |
Parameter Settings for User Entity Instance: std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram |
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Parameter Name | Value | Type |
---|---|---|
BYTE_SIZE_BLOCK | 8 | Untyped |
AUTO_CARRY_CHAINS | ON | AUTO_CARRY |
IGNORE_CARRY_BUFFERS | OFF | IGNORE_CARRY |
AUTO_CASCADE_CHAINS | ON | AUTO_CASCADE |
IGNORE_CASCADE_BUFFERS | OFF | IGNORE_CASCADE |
OPERATION_MODE | BIDIR_DUAL_PORT | Untyped |
WIDTH_A | 36 | Integer |
WIDTHAD_A | 7 | Integer |
NUMWORDS_A | 128 | Integer |
OUTDATA_REG_A | UNREGISTERED | Untyped |
ADDRESS_ACLR_A | NONE | Untyped |
OUTDATA_ACLR_A | NONE | Untyped |
WRCONTROL_ACLR_A | NONE | Untyped |
INDATA_ACLR_A | NONE | Untyped |
BYTEENA_ACLR_A | NONE | Untyped |
WIDTH_B | 36 | Integer |
WIDTHAD_B | 7 | Integer |
NUMWORDS_B | 128 | Integer |
INDATA_REG_B | CLOCK1 | Untyped |
WRCONTROL_WRADDRESS_REG_B | CLOCK1 | Untyped |
RDCONTROL_REG_B | CLOCK1 | Untyped |
ADDRESS_REG_B | CLOCK1 | Untyped |
OUTDATA_REG_B | UNREGISTERED | Untyped |
BYTEENA_REG_B | CLOCK1 | Untyped |
INDATA_ACLR_B | NONE | Untyped |
WRCONTROL_ACLR_B | NONE | Untyped |
ADDRESS_ACLR_B | NONE | Untyped |
OUTDATA_ACLR_B | NONE | Untyped |
RDCONTROL_ACLR_B | NONE | Untyped |
BYTEENA_ACLR_B | NONE | Untyped |
WIDTH_BYTEENA_A | 1 | Untyped |
WIDTH_BYTEENA_B | 1 | Untyped |
RAM_BLOCK_TYPE | AUTO | Untyped |
BYTE_SIZE | 8 | Untyped |
READ_DURING_WRITE_MODE_MIXED_PORTS | OLD_DATA | Untyped |
INIT_FILE | Untyped | |
INIT_FILE_LAYOUT | PORT_A | Untyped |
MAXIMUM_DEPTH | 0 | Untyped |
CLOCK_ENABLE_INPUT_A | NORMAL | Untyped |
CLOCK_ENABLE_INPUT_B | NORMAL | Untyped |
CLOCK_ENABLE_OUTPUT_A | NORMAL | Untyped |
CLOCK_ENABLE_OUTPUT_B | NORMAL | Untyped |
DEVICE_FAMILY | Stratix | Untyped |
CBXI_PARAMETER | altsyncram_puv1 | Untyped |
Parameter Settings for User Entity Instance: std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1 |
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Parameter Name | Value | Type |
---|---|---|
sld_node_info | 286279168 | Integer |
Parameter Settings for User Entity Instance: std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo |
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Parameter Name | Value | Type |
---|---|---|
AUTO_CARRY_CHAINS | ON | AUTO_CARRY |
IGNORE_CARRY_BUFFERS | OFF | IGNORE_CARRY |
AUTO_CASCADE_CHAINS | ON | AUTO_CASCADE |
IGNORE_CASCADE_BUFFERS | OFF | IGNORE_CASCADE |
lpm_width | 8 | Integer |
LPM_NUMWORDS | 64 | Integer |
LPM_WIDTHU | 6 | Integer |
LPM_SHOWAHEAD | OFF | Untyped |
UNDERFLOW_CHECKING | OFF | Untyped |
OVERFLOW_CHECKING | OFF | Untyped |
ALLOW_RWCYCLE_WHEN_FULL | OFF | Untyped |
ADD_RAM_OUTPUT_REGISTER | OFF | Untyped |
ALMOST_FULL_VALUE | 0 | Untyped |
ALMOST_EMPTY_VALUE | 0 | Untyped |
USE_EAB | ON | Untyped |
MAXIMIZE_SPEED | 5 | Untyped |
DEVICE_FAMILY | Stratix | Untyped |
OPTIMIZE_FOR_SPEED | 9 | Untyped |
CBXI_PARAMETER | scfifo_gg21 | Untyped |
Parameter Settings for User Entity Instance: std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo |
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Parameter Name | Value | Type |
---|---|---|
AUTO_CARRY_CHAINS | ON | AUTO_CARRY |
IGNORE_CARRY_BUFFERS | OFF | IGNORE_CARRY |
AUTO_CASCADE_CHAINS | ON | AUTO_CASCADE |
IGNORE_CASCADE_BUFFERS | OFF | IGNORE_CASCADE |
lpm_width | 8 | Integer |
LPM_NUMWORDS | 64 | Integer |
LPM_WIDTHU | 6 | Integer |
LPM_SHOWAHEAD | OFF | Untyped |
UNDERFLOW_CHECKING | OFF | Untyped |
OVERFLOW_CHECKING | OFF | Untyped |
ALLOW_RWCYCLE_WHEN_FULL | OFF | Untyped |
ADD_RAM_OUTPUT_REGISTER | OFF | Untyped |
ALMOST_FULL_VALUE | 0 | Untyped |
ALMOST_EMPTY_VALUE | 0 | Untyped |
USE_EAB | ON | Untyped |
MAXIMIZE_SPEED | 5 | Untyped |
DEVICE_FAMILY | Stratix | Untyped |
OPTIMIZE_FOR_SPEED | 9 | Untyped |
CBXI_PARAMETER | scfifo_gg21 | Untyped |
Parameter Settings for User Entity Instance: std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic |
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Parameter Name | Value | Type |
---|---|---|
INSTANCE_ID | 0 | Integer |
SLD_NODE_INFO | 00001100000000000110111000000000 | Binary |
LOG2_TXFIFO_DEPTH | 6 | Integer |
LOG2_RXFIFO_DEPTH | 6 | Integer |
RESERVED | 0 | Integer |
DATA_WIDTH | 8 | Integer |
NODE_IR_WIDTH | 1 | Integer |
SCAN_LENGTH | 11 | Integer |
Parameter Settings for User Entity Instance: std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram |
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Parameter Name | Value | Type |
---|---|---|
BYTE_SIZE_BLOCK | 8 | Untyped |
AUTO_CARRY_CHAINS | ON | AUTO_CARRY |
IGNORE_CARRY_BUFFERS | OFF | IGNORE_CARRY |
AUTO_CASCADE_CHAINS | ON | AUTO_CASCADE |
IGNORE_CASCADE_BUFFERS | OFF | IGNORE_CASCADE |
OPERATION_MODE | SINGLE_PORT | Untyped |
WIDTH_A | 32 | Integer |
WIDTHAD_A | 14 | Integer |
NUMWORDS_A | 16384 | Integer |
OUTDATA_REG_A | UNREGISTERED | Untyped |
ADDRESS_ACLR_A | NONE | Untyped |
OUTDATA_ACLR_A | NONE | Untyped |
WRCONTROL_ACLR_A | NONE | Untyped |
INDATA_ACLR_A | NONE | Untyped |
BYTEENA_ACLR_A | NONE | Untyped |
WIDTH_B | 1 | Untyped |
WIDTHAD_B | 1 | Untyped |
NUMWORDS_B | 1 | Untyped |
INDATA_REG_B | CLOCK1 | Untyped |
WRCONTROL_WRADDRESS_REG_B | CLOCK1 | Untyped |
RDCONTROL_REG_B | CLOCK1 | Untyped |
ADDRESS_REG_B | CLOCK1 | Untyped |
OUTDATA_REG_B | UNREGISTERED | Untyped |
BYTEENA_REG_B | CLOCK1 | Untyped |
INDATA_ACLR_B | NONE | Untyped |
WRCONTROL_ACLR_B | NONE | Untyped |
ADDRESS_ACLR_B | NONE | Untyped |
OUTDATA_ACLR_B | NONE | Untyped |
RDCONTROL_ACLR_B | NONE | Untyped |
BYTEENA_ACLR_B | NONE | Untyped |
WIDTH_BYTEENA_A | 4 | Integer |
WIDTH_BYTEENA_B | 1 | Untyped |
RAM_BLOCK_TYPE | M-RAM | Untyped |
BYTE_SIZE | 8 | Integer |
READ_DURING_WRITE_MODE_MIXED_PORTS | DONT_CARE | Untyped |
INIT_FILE | UNUSED | Untyped |
INIT_FILE_LAYOUT | PORT_A | Untyped |
MAXIMUM_DEPTH | 0 | Untyped |
CLOCK_ENABLE_INPUT_A | NORMAL | Untyped |
CLOCK_ENABLE_INPUT_B | NORMAL | Untyped |
CLOCK_ENABLE_OUTPUT_A | NORMAL | Untyped |
CLOCK_ENABLE_OUTPUT_B | NORMAL | Untyped |
DEVICE_FAMILY | Stratix | Untyped |
CBXI_PARAMETER | altsyncram_7b71 | Untyped |
Parameter Settings for User Entity Instance: std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component |
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Parameter Name | Value | Type |
---|---|---|
OPERATION_MODE | NORMAL | Untyped |
PLL_TYPE | AUTO | Untyped |
QUALIFY_CONF_DONE | OFF | Untyped |
COMPENSATE_CLOCK | CLK0 | Untyped |
SCAN_CHAIN | LONG | Untyped |
PRIMARY_CLOCK | INCLK0 | Untyped |
INCLK0_INPUT_FREQUENCY | 20000 | Integer |
INCLK1_INPUT_FREQUENCY | 0 | Untyped |
GATE_LOCK_SIGNAL | NO | Untyped |
GATE_LOCK_COUNTER | 0 | Untyped |
LOCK_HIGH | 1 | Untyped |
LOCK_LOW | 1 | Untyped |
VALID_LOCK_MULTIPLIER | 1 | Untyped |
INVALID_LOCK_MULTIPLIER | 5 | Untyped |
SWITCH_OVER_ON_LOSSCLK | OFF | Untyped |
SWITCH_OVER_ON_GATED_LOCK | OFF | Untyped |
ENABLE_SWITCH_OVER_COUNTER | OFF | Untyped |
SKIP_VCO | OFF | Untyped |
SWITCH_OVER_COUNTER | 0 | Untyped |
SWITCH_OVER_TYPE | AUTO | Untyped |
FEEDBACK_SOURCE | EXTCLK0 | Untyped |
BANDWIDTH | 0 | Untyped |
BANDWIDTH_TYPE | AUTO | Untyped |
SPREAD_FREQUENCY | 0 | Integer |
DOWN_SPREAD | 0 | Untyped |
SELF_RESET_ON_GATED_LOSS_LOCK | OFF | Untyped |
CLK5_MULTIPLY_BY | 1 | Untyped |
CLK4_MULTIPLY_BY | 1 | Untyped |
CLK3_MULTIPLY_BY | 1 | Untyped |
CLK2_MULTIPLY_BY | 1 | Untyped |
CLK1_MULTIPLY_BY | 1 | Untyped |
CLK0_MULTIPLY_BY | 1 | Integer |
CLK5_DIVIDE_BY | 1 | Untyped |
CLK4_DIVIDE_BY | 1 | Untyped |
CLK3_DIVIDE_BY | 1 | Untyped |
CLK2_DIVIDE_BY | 1 | Untyped |
CLK1_DIVIDE_BY | 1 | Untyped |
CLK0_DIVIDE_BY | 1 | Integer |
CLK5_PHASE_SHIFT | 0 | Untyped |
CLK4_PHASE_SHIFT | 0 | Untyped |
CLK3_PHASE_SHIFT | 0 | Untyped |
CLK2_PHASE_SHIFT | 0 | Untyped |
CLK1_PHASE_SHIFT | 0 | Untyped |
CLK0_PHASE_SHIFT | 0 | Untyped |
CLK5_TIME_DELAY | 0 | Untyped |
CLK4_TIME_DELAY | 0 | Untyped |
CLK3_TIME_DELAY | 0 | Untyped |
CLK2_TIME_DELAY | 0 | Untyped |
CLK1_TIME_DELAY | 0 | Untyped |
CLK0_TIME_DELAY | 0 | Untyped |
CLK5_DUTY_CYCLE | 50 | Untyped |
CLK4_DUTY_CYCLE | 50 | Untyped |
CLK3_DUTY_CYCLE | 50 | Untyped |
CLK2_DUTY_CYCLE | 50 | Untyped |
CLK1_DUTY_CYCLE | 50 | Untyped |
CLK0_DUTY_CYCLE | 50 | Integer |
EXTCLK3_MULTIPLY_BY | 1 | Untyped |
EXTCLK2_MULTIPLY_BY | 1 | Untyped |
EXTCLK1_MULTIPLY_BY | 1 | Untyped |
EXTCLK0_MULTIPLY_BY | 1 | Integer |
EXTCLK3_DIVIDE_BY | 1 | Untyped |
EXTCLK2_DIVIDE_BY | 1 | Untyped |
EXTCLK1_DIVIDE_BY | 1 | Untyped |
EXTCLK0_DIVIDE_BY | 1 | Integer |
EXTCLK3_PHASE_SHIFT | 0 | Untyped |
EXTCLK2_PHASE_SHIFT | 0 | Untyped |
EXTCLK1_PHASE_SHIFT | 0 | Untyped |
EXTCLK0_PHASE_SHIFT | -3500 | Untyped |
EXTCLK3_TIME_DELAY | 0 | Untyped |
EXTCLK2_TIME_DELAY | 0 | Untyped |
EXTCLK1_TIME_DELAY | 0 | Untyped |
EXTCLK0_TIME_DELAY | 0 | Untyped |
EXTCLK3_DUTY_CYCLE | 50 | Untyped |
EXTCLK2_DUTY_CYCLE | 50 | Untyped |
EXTCLK1_DUTY_CYCLE | 50 | Untyped |
EXTCLK0_DUTY_CYCLE | 50 | Integer |
VCO_MULTIPLY_BY | 0 | Untyped |
VCO_DIVIDE_BY | 0 | Untyped |
SCLKOUT0_PHASE_SHIFT | 0 | Untyped |
SCLKOUT1_PHASE_SHIFT | 0 | Untyped |
VCO_MIN | 0 | Untyped |
VCO_MAX | 0 | Untyped |
VCO_CENTER | 0 | Untyped |
PFD_MIN | 0 | Untyped |
PFD_MAX | 0 | Untyped |
M_INITIAL | 0 | Untyped |
M | 0 | Untyped |
N | 1 | Untyped |
M2 | 1 | Untyped |
N2 | 1 | Untyped |
SS | 1 | Untyped |
C0_HIGH | 0 | Untyped |
C1_HIGH | 0 | Untyped |
C2_HIGH | 0 | Untyped |
C3_HIGH | 0 | Untyped |
C4_HIGH | 0 | Untyped |
C5_HIGH | 0 | Untyped |
C0_LOW | 0 | Untyped |
C1_LOW | 0 | Untyped |
C2_LOW | 0 | Untyped |
C3_LOW | 0 | Untyped |
C4_LOW | 0 | Untyped |
C5_LOW | 0 | Untyped |
C0_INITIAL | 0 | Untyped |
C1_INITIAL | 0 | Untyped |
C2_INITIAL | 0 | Untyped |
C3_INITIAL | 0 | Untyped |
C4_INITIAL | 0 | Untyped |
C5_INITIAL | 0 | Untyped |
C0_MODE | BYPASS | Untyped |
C1_MODE | BYPASS | Untyped |
C2_MODE | BYPASS | Untyped |
C3_MODE | BYPASS | Untyped |
C4_MODE | BYPASS | Untyped |
C5_MODE | BYPASS | Untyped |
C0_PH | 0 | Untyped |
C1_PH | 0 | Untyped |
C2_PH | 0 | Untyped |
C3_PH | 0 | Untyped |
C4_PH | 0 | Untyped |
C5_PH | 0 | Untyped |
L0_HIGH | 1 | Untyped |
L1_HIGH | 1 | Untyped |
G0_HIGH | 1 | Untyped |
G1_HIGH | 1 | Untyped |
G2_HIGH | 1 | Untyped |
G3_HIGH | 1 | Untyped |
E0_HIGH | 1 | Untyped |
E1_HIGH | 1 | Untyped |
E2_HIGH | 1 | Untyped |
E3_HIGH | 1 | Untyped |
L0_LOW | 1 | Untyped |
L1_LOW | 1 | Untyped |
G0_LOW | 1 | Untyped |
G1_LOW | 1 | Untyped |
G2_LOW | 1 | Untyped |
G3_LOW | 1 | Untyped |
E0_LOW | 1 | Untyped |
E1_LOW | 1 | Untyped |
E2_LOW | 1 | Untyped |
E3_LOW | 1 | Untyped |
L0_INITIAL | 1 | Untyped |
L1_INITIAL | 1 | Untyped |
G0_INITIAL | 1 | Untyped |
G1_INITIAL | 1 | Untyped |
G2_INITIAL | 1 | Untyped |
G3_INITIAL | 1 | Untyped |
E0_INITIAL | 1 | Untyped |
E1_INITIAL | 1 | Untyped |
E2_INITIAL | 1 | Untyped |
E3_INITIAL | 1 | Untyped |
L0_MODE | BYPASS | Untyped |
L1_MODE | BYPASS | Untyped |
G0_MODE | BYPASS | Untyped |
G1_MODE | BYPASS | Untyped |
G2_MODE | BYPASS | Untyped |
G3_MODE | BYPASS | Untyped |
E0_MODE | BYPASS | Untyped |
E1_MODE | BYPASS | Untyped |
E2_MODE | BYPASS | Untyped |
E3_MODE | BYPASS | Untyped |
L0_PH | 0 | Untyped |
L1_PH | 0 | Untyped |
G0_PH | 0 | Untyped |
G1_PH | 0 | Untyped |
G2_PH | 0 | Untyped |
G3_PH | 0 | Untyped |
E0_PH | 0 | Untyped |
E1_PH | 0 | Untyped |
E2_PH | 0 | Untyped |
E3_PH | 0 | Untyped |
M_PH | 0 | Untyped |
C1_USE_CASC_IN | 0 | Untyped |
C2_USE_CASC_IN | 0 | Untyped |
C3_USE_CASC_IN | 0 | Untyped |
C4_USE_CASC_IN | 0 | Untyped |
C5_USE_CASC_IN | 0 | Untyped |
CLK0_COUNTER | G0 | Untyped |
CLK1_COUNTER | G0 | Untyped |
CLK2_COUNTER | G0 | Untyped |
CLK3_COUNTER | G0 | Untyped |
CLK4_COUNTER | G0 | Untyped |
CLK5_COUNTER | G0 | Untyped |
L0_TIME_DELAY | 0 | Untyped |
L1_TIME_DELAY | 0 | Untyped |
G0_TIME_DELAY | 0 | Untyped |
G1_TIME_DELAY | 0 | Untyped |
G2_TIME_DELAY | 0 | Untyped |
G3_TIME_DELAY | 0 | Untyped |
E0_TIME_DELAY | 0 | Untyped |
E1_TIME_DELAY | 0 | Untyped |
E2_TIME_DELAY | 0 | Untyped |
E3_TIME_DELAY | 0 | Untyped |
M_TIME_DELAY | 0 | Untyped |
N_TIME_DELAY | 0 | Untyped |
EXTCLK3_COUNTER | E3 | Untyped |
EXTCLK2_COUNTER | E2 | Untyped |
EXTCLK1_COUNTER | E1 | Untyped |
EXTCLK0_COUNTER | E0 | Untyped |
ENABLE0_COUNTER | L0 | Untyped |
ENABLE1_COUNTER | L0 | Untyped |
CHARGE_PUMP_CURRENT | 2 | Untyped |
LOOP_FILTER_R | 1.000000 | Untyped |
LOOP_FILTER_C | 5 | Untyped |
VCO_POST_SCALE | 0 | Untyped |
CLK2_OUTPUT_FREQUENCY | 0 | Untyped |
CLK1_OUTPUT_FREQUENCY | 0 | Untyped |
CLK0_OUTPUT_FREQUENCY | 0 | Untyped |
INTENDED_DEVICE_FAMILY | Stratix | Untyped |
PORT_CLKENA0 | PORT_UNUSED | Untyped |
PORT_CLKENA1 | PORT_UNUSED | Untyped |
PORT_CLKENA2 | PORT_UNUSED | Untyped |
PORT_CLKENA3 | PORT_UNUSED | Untyped |
PORT_CLKENA4 | PORT_UNUSED | Untyped |
PORT_CLKENA5 | PORT_UNUSED | Untyped |
PORT_EXTCLKENA0 | PORT_UNUSED | Untyped |
PORT_EXTCLKENA1 | PORT_UNUSED | Untyped |
PORT_EXTCLKENA2 | PORT_UNUSED | Untyped |
PORT_EXTCLKENA3 | PORT_UNUSED | Untyped |
PORT_EXTCLK0 | PORT_USED | Untyped |
PORT_EXTCLK1 | PORT_UNUSED | Untyped |
PORT_EXTCLK2 | PORT_UNUSED | Untyped |
PORT_EXTCLK3 | PORT_UNUSED | Untyped |
PORT_CLKBAD0 | PORT_UNUSED | Untyped |
PORT_CLKBAD1 | PORT_UNUSED | Untyped |
PORT_CLK0 | PORT_USED | Untyped |
PORT_CLK1 | PORT_UNUSED | Untyped |
PORT_CLK2 | PORT_UNUSED | Untyped |
PORT_CLK3 | PORT_UNUSED | Untyped |
PORT_CLK4 | PORT_UNUSED | Untyped |
PORT_CLK5 | PORT_UNUSED | Untyped |
PORT_SCANDATA | PORT_UNUSED | Untyped |
PORT_SCANDATAOUT | PORT_UNUSED | Untyped |
PORT_SCANDONE | PORT_UNUSED | Untyped |
PORT_SCLKOUT1 | PORT_UNUSED | Untyped |
PORT_SCLKOUT0 | PORT_UNUSED | Untyped |
PORT_ACTIVECLOCK | PORT_UNUSED | Untyped |
PORT_CLKLOSS | PORT_UNUSED | Untyped |
PORT_INCLK1 | PORT_UNUSED | Untyped |
PORT_INCLK0 | PORT_USED | Untyped |
PORT_FBIN | PORT_UNUSED | Untyped |
PORT_PLLENA | PORT_UNUSED | Untyped |
PORT_CLKSWITCH | PORT_UNUSED | Untyped |
PORT_ARESET | PORT_UNUSED | Untyped |
PORT_PFDENA | PORT_UNUSED | Untyped |
PORT_SCANCLK | PORT_UNUSED | Untyped |
PORT_SCANACLR | PORT_UNUSED | Untyped |
PORT_SCANREAD | PORT_UNUSED | Untyped |
PORT_SCANWRITE | PORT_UNUSED | Untyped |
PORT_ENABLE0 | PORT_UNUSED | Untyped |
PORT_ENABLE1 | PORT_UNUSED | Untyped |
PORT_LOCKED | PORT_UNUSED | Untyped |
M_TEST_SOURCE | 5 | Untyped |
C0_TEST_SOURCE | 5 | Untyped |
C1_TEST_SOURCE | 5 | Untyped |
C2_TEST_SOURCE | 5 | Untyped |
C3_TEST_SOURCE | 5 | Untyped |
C4_TEST_SOURCE | 5 | Untyped |
C5_TEST_SOURCE | 5 | Untyped |
DEVICE_FAMILY | Stratix | Untyped |
AUTO_CARRY_CHAINS | ON | AUTO_CARRY |
IGNORE_CARRY_BUFFERS | OFF | IGNORE_CARRY |
AUTO_CASCADE_CHAINS | ON | AUTO_CASCADE |
IGNORE_CASCADE_BUFFERS | OFF | IGNORE_CASCADE |
Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst |
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Parameter Name | Value | Type |
---|---|---|
sld_hub_ip_version | 1 | Untyped |
sld_hub_ip_minor_version | 3 | Untyped |
sld_common_ip_version | 0 | Untyped |
device_family | Stratix | Untyped |
n_nodes | 2 | Untyped |
n_sel_bits | 2 | Untyped |
n_node_ir_bits | 5 | Untyped |
node_info | 0000110000000000011011100000000000010001000100000100011000000000 | Binary |
compilation_mode | 0 | Untyped |
Parameter Settings for Inferred Entity Instance: std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8 |
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Parameter Name | Value | Type |
---|---|---|
LPM_WIDTH | 33 | Untyped |
LPM_REPRESENTATION | UNSIGNED | Untyped |
LPM_DIRECTION | DEFAULT | Untyped |
ONE_INPUT_IS_CONSTANT | NO | Untyped |
LPM_PIPELINE | 0 | Untyped |
MAXIMIZE_SPEED | 5 | Untyped |
REGISTERED_AT_END | 0 | Untyped |
OPTIMIZE_FOR_SPEED | 9 | Untyped |
USE_CS_BUFFERS | 1 | Untyped |
CARRY_CHAIN | MANUAL | Untyped |
CARRY_CHAIN_LENGTH | 48 | CARRY_CHAIN_LENGTH |
DEVICE_FAMILY | Stratix | Untyped |
USE_WYS | OFF | Untyped |
STYLE | FAST | Untyped |
CBXI_PARAMETER | add_sub_4dg | Untyped |
AUTO_CARRY_CHAINS | ON | AUTO_CARRY |
IGNORE_CARRY_BUFFERS | OFF | IGNORE_CARRY |
AUTO_CASCADE_CHAINS | ON | AUTO_CASCADE |
IGNORE_CASCADE_BUFFERS | OFF | IGNORE_CASCADE |
altmult_add Parameter Settings by Entity Instance |
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Name | Value |
---|---|
Number of entity instances | 1 |
Entity Instance | std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add |
-- NUMBER_OF_MULTIPLIERS | 1 |
-- WIDTH_A | 32 |
-- WIDTH_B | 32 |
-- WIDTH_RESULT | 64 |
-- REPRESENTATION_A | UNUSED |
-- REPRESENTATION_B | UNUSED |
-- PORT_SIGNA | PORT_CONNECTIVITY |
-- PORT_SIGNB | PORT_CONNECTIVITY |
-- DEDICATED_MULTIPLIER_CIRCUITRY | YES |
scfifo Parameter Settings by Entity Instance |
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Name | Value |
---|---|
Number of entity instances | 2 |
Entity Instance | std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo |
-- FIFO Type | Single Clock |
-- lpm_width | 8 |
-- LPM_NUMWORDS | 64 |
-- LPM_SHOWAHEAD | OFF |
-- USE_EAB | ON |
Entity Instance | std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo |
-- FIFO Type | Single Clock |
-- lpm_width | 8 |
-- LPM_NUMWORDS | 64 |
-- LPM_SHOWAHEAD | OFF |
-- USE_EAB | ON |
Analysis & Synthesis Equations |
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Analysis & Synthesis Messages |
Top |
Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 6.0 Build 176 04/19/2006 SJ Full Version Info: Processing started: Fri Apr 21 02:55:29 2006 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off standard -c standard Info: Found 1 design units, including 1 entities, in source file standard.bdf Info: Found entity 1: standard Warning: Can't analyze file -- file /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/altera_europa_support.vhd is missing Info: Elaborating entity "standard" for the top level hierarchy Warning: Using design file std_1s10.vhd, which is not specified as a design file for the current project, but contains definitions for 64 design units and 32 entities in project Info: Found design unit 1: button_pio_s1_arbitrator-europa Info: Found design unit 2: clock_0_in_arbitrator-europa Info: Found design unit 3: clock_0_out_arbitrator-europa Info: Found design unit 4: cpu_jtag_debug_module_arbitrator-europa Info: Found design unit 5: cpu_data_master_arbitrator-europa Info: Found design unit 6: cpu_instruction_master_arbitrator-europa Info: Found design unit 7: ext_ram_bus_avalon_slave_arbitrator-europa Info: Found design unit 8: ext_ram_bus_bridge_arbitrator-europa Info: Found design unit 9: high_res_timer_s1_arbitrator-europa Info: Found design unit 10: jtag_uart_avalon_jtag_slave_arbitrator-europa Info: Found design unit 11: lcd_display_control_slave_arbitrator-europa Info: Found design unit 12: led_pio_s1_arbitrator-europa Info: Found design unit 13: onchip_ram_64_kbytes_s1_arbitrator-europa Info: Found design unit 14: pll_s1_arbitrator-europa Info: Found design unit 15: reconfig_request_pio_s1_arbitrator-europa Info: Found design unit 16: rdv_fifo_for_cpu_data_master_to_sdram_s1_module-europa Info: Found design unit 17: rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module-europa Info: Found design unit 18: sdram_s1_arbitrator-europa Info: Found design unit 19: seven_seg_pio_s1_arbitrator-europa Info: Found design unit 20: sys_clk_timer_s1_arbitrator-europa Info: Found design unit 21: sysid_control_slave_arbitrator-europa Info: Found design unit 22: uart1_s1_arbitrator-europa Info: Found design unit 23: std_1s10_reset_sys_clk_domain_synch_module-europa Info: Found design unit 24: std_1s10_reset_clk_domain_synch_module-europa Info: Found design unit 25: std_1s10-europa Info: Found design unit 26: ext_flash_lane0_module-europa Info: Found design unit 27: ext_flash-europa Info: Found design unit 28: ext_ram_lane0_module-europa Info: Found design unit 29: ext_ram_lane1_module-europa Info: Found design unit 30: ext_ram_lane2_module-europa Info: Found design unit 31: ext_ram_lane3_module-europa Info: Found design unit 32: ext_ram-europa Info: Found entity 1: button_pio_s1_arbitrator Info: Found entity 2: clock_0_in_arbitrator Info: Found entity 3: clock_0_out_arbitrator Info: Found entity 4: cpu_jtag_debug_module_arbitrator Info: Found entity 5: cpu_data_master_arbitrator Info: Found entity 6: cpu_instruction_master_arbitrator Info: Found entity 7: ext_ram_bus_avalon_slave_arbitrator Info: Found entity 8: ext_ram_bus_bridge_arbitrator Info: Found entity 9: high_res_timer_s1_arbitrator Info: Found entity 10: jtag_uart_avalon_jtag_slave_arbitrator Info: Found entity 11: lcd_display_control_slave_arbitrator Info: Found entity 12: led_pio_s1_arbitrator Info: Found entity 13: onchip_ram_64_kbytes_s1_arbitrator Info: Found entity 14: pll_s1_arbitrator Info: Found entity 15: reconfig_request_pio_s1_arbitrator Info: Found entity 16: rdv_fifo_for_cpu_data_master_to_sdram_s1_module Info: Found entity 17: rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module Info: Found entity 18: sdram_s1_arbitrator Info: Found entity 19: seven_seg_pio_s1_arbitrator Info: Found entity 20: sys_clk_timer_s1_arbitrator Info: Found entity 21: sysid_control_slave_arbitrator Info: Found entity 22: uart1_s1_arbitrator Info: Found entity 23: std_1s10_reset_sys_clk_domain_synch_module Info: Found entity 24: std_1s10_reset_clk_domain_synch_module Info: Found entity 25: std_1s10 Info: Found entity 26: ext_flash_lane0_module Info: Found entity 27: ext_flash Info: Found entity 28: ext_ram_lane0_module Info: Found entity 29: ext_ram_lane1_module Info: Found entity 30: ext_ram_lane2_module Info: Found entity 31: ext_ram_lane3_module Info: Found entity 32: ext_ram Info: Elaborating entity "std_1s10" for hierarchy "std_1s10:inst" Info: Elaborating entity "button_pio_s1_arbitrator" for hierarchy "std_1s10:inst|button_pio_s1_arbitrator:the_button_pio_s1" Warning: Using design file button_pio.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: button_pio-europa Info: Found entity 1: button_pio Info: Elaborating entity "button_pio" for hierarchy "std_1s10:inst|button_pio:the_button_pio" Info: Elaborating entity "clock_0_in_arbitrator" for hierarchy "std_1s10:inst|clock_0_in_arbitrator:the_clock_0_in" Info: Elaborating entity "clock_0_out_arbitrator" for hierarchy "std_1s10:inst|clock_0_out_arbitrator:the_clock_0_out" Warning: Using design file clock_0.vhd, which is not specified as a design file for the current project, but contains definitions for 18 design units and 9 entities in project Info: Found design unit 1: clock_0_master_read_done_sync_module-europa Info: Found design unit 2: clock_0_master_write_done_sync_module-europa Info: Found design unit 3: clock_0_edge_to_pulse-europa Info: Found design unit 4: clock_0_slave_FSM-europa Info: Found design unit 5: clock_0_slave_read_request_sync_module-europa Info: Found design unit 6: clock_0_slave_write_request_sync_module-europa Info: Found design unit 7: clock_0_master_FSM-europa Info: Found design unit 8: clock_0_bit_pipe-europa Info: Found design unit 9: clock_0-europa Info: Found entity 1: clock_0_master_read_done_sync_module Info: Found entity 2: clock_0_master_write_done_sync_module Info: Found entity 3: clock_0_edge_to_pulse Info: Found entity 4: clock_0_slave_FSM Info: Found entity 5: clock_0_slave_read_request_sync_module Info: Found entity 6: clock_0_slave_write_request_sync_module Info: Found entity 7: clock_0_master_FSM Info: Found entity 8: clock_0_bit_pipe Info: Found entity 9: clock_0 Info: Elaborating entity "clock_0" for hierarchy "std_1s10:inst|clock_0:the_clock_0" Info: Elaborating entity "clock_0_master_read_done_sync_module" for hierarchy "std_1s10:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync" Info: Elaborating entity "clock_0_master_write_done_sync_module" for hierarchy "std_1s10:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync" Info: Elaborating entity "clock_0_edge_to_pulse" for hierarchy "std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse" Info: Elaborating entity "clock_0_slave_FSM" for hierarchy "std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM" Info: Elaborating entity "clock_0_slave_read_request_sync_module" for hierarchy "std_1s10:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync" Info: Elaborating entity "clock_0_slave_write_request_sync_module" for hierarchy "std_1s10:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync" Info: Elaborating entity "clock_0_master_FSM" for hierarchy "std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM" Info: Elaborating entity "clock_0_bit_pipe" for hierarchy "std_1s10:inst|clock_0:the_clock_0|clock_0_bit_pipe:endofpacket_bit_pipe" Info: Elaborating entity "cpu_jtag_debug_module_arbitrator" for hierarchy "std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module" Info: Elaborating entity "cpu_data_master_arbitrator" for hierarchy "std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master" Info: Elaborating entity "cpu_instruction_master_arbitrator" for hierarchy "std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master" Warning: Using design file cpu.vhd, which is not specified as a design file for the current project, but contains definitions for 52 design units and 26 entities in project Info: Found design unit 1: cpu_ic_data_module-europa Info: Found design unit 2: cpu_ic_tag_module-europa Info: Found design unit 3: cpu_register_bank_a_module-europa Info: Found design unit 4: cpu_register_bank_b_module-europa Info: Found design unit 5: cpu_nios2_oci_debug-europa Info: Found design unit 6: cpu_ociram_lpm_dram_bdp_component_module-europa Info: Found design unit 7: cpu_nios2_ocimem-europa Info: Found design unit 8: cpu_nios2_avalon_reg-europa Info: Found design unit 9: cpu_nios2_oci_break-europa Info: Found design unit 10: cpu_nios2_oci_xbrk-europa Info: Found design unit 11: cpu_nios2_oci_match_paired-europa Info: Found design unit 12: cpu_nios2_oci_match_single-europa Info: Found design unit 13: cpu_nios2_oci_dbrk-europa Info: Found design unit 14: cpu_nios2_oci_itrace-europa Info: Found design unit 15: cpu_nios2_oci_td_mode-europa Info: Found design unit 16: cpu_nios2_oci_dtrace-europa Info: Found design unit 17: cpu_nios2_oci_compute_tm_count-europa Info: Found design unit 18: cpu_nios2_oci_fifowp_inc-europa Info: Found design unit 19: cpu_nios2_oci_fifocount_inc-europa Info: Found design unit 20: cpu_nios2_oci_fifo-europa Info: Found design unit 21: cpu_nios2_oci_pib-europa Info: Found design unit 22: cpu_traceram_lpm_dram_bdp_component_module-europa Info: Found design unit 23: cpu_nios2_oci_im-europa Info: Found design unit 24: cpu_nios2_performance_monitors-europa Info: Found design unit 25: cpu_nios2_oci-europa Info: Found design unit 26: cpu-europa Info: Found entity 1: cpu_ic_data_module Info: Found entity 2: cpu_ic_tag_module Info: Found entity 3: cpu_register_bank_a_module Info: Found entity 4: cpu_register_bank_b_module Info: Found entity 5: cpu_nios2_oci_debug Info: Found entity 6: cpu_ociram_lpm_dram_bdp_component_module Info: Found entity 7: cpu_nios2_ocimem Info: Found entity 8: cpu_nios2_avalon_reg Info: Found entity 9: cpu_nios2_oci_break Info: Found entity 10: cpu_nios2_oci_xbrk Info: Found entity 11: cpu_nios2_oci_match_paired Info: Found entity 12: cpu_nios2_oci_match_single Info: Found entity 13: cpu_nios2_oci_dbrk Info: Found entity 14: cpu_nios2_oci_itrace Info: Found entity 15: cpu_nios2_oci_td_mode Info: Found entity 16: cpu_nios2_oci_dtrace Info: Found entity 17: cpu_nios2_oci_compute_tm_count Info: Found entity 18: cpu_nios2_oci_fifowp_inc Info: Found entity 19: cpu_nios2_oci_fifocount_inc Info: Found entity 20: cpu_nios2_oci_fifo Info: Found entity 21: cpu_nios2_oci_pib Info: Found entity 22: cpu_traceram_lpm_dram_bdp_component_module Info: Found entity 23: cpu_nios2_oci_im Info: Found entity 24: cpu_nios2_performance_monitors Info: Found entity 25: cpu_nios2_oci Info: Found entity 26: cpu Info: Elaborating entity "cpu" for hierarchy "std_1s10:inst|cpu:the_cpu" Warning: Using design file cpu_test_bench.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: cpu_test_bench-europa Info: Found entity 1: cpu_test_bench Info: Elaborating entity "cpu_test_bench" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench" Info: Elaborating entity "cpu_ic_data_module" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data" Info: Found 1 design units, including 1 entities, in source file /tools/quartus/6.0/176/libraries/megafunctions/altsyncram.tdf Info: Found entity 1: altsyncram Info: Elaborating entity "altsyncram" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram" Info: Found 1 design units, including 1 entities, in source file db/altsyncram_nnb1.tdf Info: Found entity 1: altsyncram_nnb1 Info: Elaborating entity "altsyncram_nnb1" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated" Info: Elaborating entity "cpu_ic_tag_module" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag" Info: Elaborating entity "altsyncram" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram" Info: Found 1 design units, including 1 entities, in source file db/altsyncram_t9e1.tdf Info: Found entity 1: altsyncram_t9e1 Info: Elaborating entity "altsyncram_t9e1" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated" Info: Elaborating entity "cpu_register_bank_a_module" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a" Info: Elaborating entity "altsyncram" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram" Info: Found 1 design units, including 1 entities, in source file db/altsyncram_00e1.tdf Info: Found entity 1: altsyncram_00e1 Info: Elaborating entity "altsyncram_00e1" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated" Info: Elaborating entity "cpu_register_bank_b_module" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b" Info: Elaborating entity "altsyncram" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram" Info: Found 1 design units, including 1 entities, in source file db/altsyncram_10e1.tdf Info: Found entity 1: altsyncram_10e1 Info: Elaborating entity "altsyncram_10e1" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated" Warning: Using design file cpu_mult_cell.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: cpu_mult_cell-europa Info: Found entity 1: cpu_mult_cell Info: Elaborating entity "cpu_mult_cell" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell" Info: Found 1 design units, including 1 entities, in source file /tools/quartus/6.0/176/libraries/megafunctions/altmult_add.tdf Info: Found entity 1: altmult_add Info: Elaborating entity "altmult_add" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add" Info: Elaborated megafunction instantiation "std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add" Info: Found 1 design units, including 1 entities, in source file db/mult_add_1f72.tdf Info: Found entity 1: mult_add_1f72 Info: Elaborating entity "mult_add_1f72" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated" Info: Elaborating entity "cpu_nios2_oci" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci" Info: Elaborating entity "cpu_nios2_oci_debug" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug" Info: Elaborating entity "cpu_nios2_ocimem" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem" Info: Elaborating entity "cpu_ociram_lpm_dram_bdp_component_module" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component" Info: Elaborating entity "altsyncram" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram" Info: Found 1 design units, including 1 entities, in source file db/altsyncram_8q62.tdf Info: Found entity 1: altsyncram_8q62 Info: Elaborating entity "altsyncram_8q62" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated" Info: Elaborating entity "cpu_nios2_avalon_reg" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg" Info: Elaborating entity "cpu_nios2_oci_break" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break" Info: Elaborating entity "cpu_nios2_oci_xbrk" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk" Info: Elaborating entity "cpu_nios2_oci_dbrk" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk" Info: Elaborating entity "cpu_nios2_oci_match_paired" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|cpu_nios2_oci_match_paired:cpu_nios2_oci_dbrk_hit0_match_paired" Info: Elaborating entity "cpu_nios2_oci_match_single" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|cpu_nios2_oci_match_single:cpu_nios2_oci_dbrk_hit0_match_single" Info: Elaborating entity "cpu_nios2_oci_itrace" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_itrace:the_cpu_nios2_oci_itrace" Info: Elaborating entity "cpu_nios2_oci_dtrace" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace" Info: Elaborating entity "cpu_nios2_oci_td_mode" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dtrace:the_cpu_nios2_oci_dtrace|cpu_nios2_oci_td_mode:cpu_nios2_oci_trc_ctrl_td_mode" Info: Elaborating entity "cpu_nios2_oci_fifo" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo" Info: Elaborating entity "cpu_nios2_oci_compute_tm_count" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_compute_tm_count:cpu_nios2_oci_compute_tm_count_tm_count" Info: Elaborating entity "cpu_nios2_oci_fifowp_inc" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_fifowp_inc:cpu_nios2_oci_fifowp_inc_fifowp" Info: Elaborating entity "cpu_nios2_oci_fifocount_inc" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_fifo:the_cpu_nios2_oci_fifo|cpu_nios2_oci_fifocount_inc:cpu_nios2_oci_fifocount_inc_fifocount" Info: Elaborating entity "cpu_nios2_oci_pib" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_pib:the_cpu_nios2_oci_pib" Info: Elaborating entity "cpu_nios2_oci_im" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im" Info: Elaborating entity "cpu_traceram_lpm_dram_bdp_component_module" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component" Info: Elaborating entity "altsyncram" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram" Info: Found 1 design units, including 1 entities, in source file db/altsyncram_puv1.tdf Info: Found entity 1: altsyncram_puv1 Info: Elaborating entity "altsyncram_puv1" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated" Warning: Using design file cpu_jtag_debug_module_wrapper.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: cpu_jtag_debug_module_wrapper-europa Info: Found entity 1: cpu_jtag_debug_module_wrapper Info: Elaborating entity "cpu_jtag_debug_module_wrapper" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper" Warning: Using design file cpu_jtag_debug_module.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: cpu_jtag_debug_module-europa Info: Found entity 1: cpu_jtag_debug_module Info: Elaborating entity "cpu_jtag_debug_module" for hierarchy "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1" Warning (10492): VHDL Process Statement warning at cpu_jtag_debug_module.vhd(253): signal "usr1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list Warning (10492): VHDL Process Statement warning at cpu_jtag_debug_module.vhd(253): signal "ena" is read inside the Process Statement but isn't in the Process Statement's sensivitity list Warning (10492): VHDL Process Statement warning at cpu_jtag_debug_module.vhd(256): signal "usr1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list Warning (10492): VHDL Process Statement warning at cpu_jtag_debug_module.vhd(256): signal "ena" is read inside the Process Statement but isn't in the Process Statement's sensivitity list Info: Elaborating entity "ext_ram_bus_avalon_slave_arbitrator" for hierarchy "std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave" Info: Elaborating entity "high_res_timer_s1_arbitrator" for hierarchy "std_1s10:inst|high_res_timer_s1_arbitrator:the_high_res_timer_s1" Warning: Using design file high_res_timer.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: high_res_timer-europa Info: Found entity 1: high_res_timer Info: Elaborating entity "high_res_timer" for hierarchy "std_1s10:inst|high_res_timer:the_high_res_timer" Info: Elaborating entity "jtag_uart_avalon_jtag_slave_arbitrator" for hierarchy "std_1s10:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave" Warning: Using design file jtag_uart.vhd, which is not specified as a design file for the current project, but contains definitions for 14 design units and 7 entities in project Info: Found design unit 1: jtag_uart_log_module-europa Info: Found design unit 2: jtag_uart_sim_scfifo_w-europa Info: Found design unit 3: jtag_uart_scfifo_w-europa Info: Found design unit 4: jtag_uart_drom_module-europa Info: Found design unit 5: jtag_uart_sim_scfifo_r-europa Info: Found design unit 6: jtag_uart_scfifo_r-europa Info: Found design unit 7: jtag_uart-europa Info: Found entity 1: jtag_uart_log_module Info: Found entity 2: jtag_uart_sim_scfifo_w Info: Found entity 3: jtag_uart_scfifo_w Info: Found entity 4: jtag_uart_drom_module Info: Found entity 5: jtag_uart_sim_scfifo_r Info: Found entity 6: jtag_uart_scfifo_r Info: Found entity 7: jtag_uart Info: Elaborating entity "jtag_uart" for hierarchy "std_1s10:inst|jtag_uart:the_jtag_uart" Info: Elaborating entity "jtag_uart_scfifo_w" for hierarchy "std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w" Info: Found 1 design units, including 1 entities, in source file /tools/quartus/6.0/176/libraries/megafunctions/scfifo.tdf Info: Found entity 1: scfifo Info: Elaborating entity "scfifo" for hierarchy "std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo" Info: Elaborated megafunction instantiation "std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo" Info: Found 1 design units, including 1 entities, in source file db/scfifo_gg21.tdf Info: Found entity 1: scfifo_gg21 Info: Elaborating entity "scfifo_gg21" for hierarchy "std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated" Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_jm21.tdf Info: Found entity 1: a_dpfifo_jm21 Info: Elaborating entity "a_dpfifo_jm21" for hierarchy "std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo" Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf Info: Found entity 1: a_fefifo_7cf Info: Elaborating entity "a_fefifo_7cf" for hierarchy "std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state" Info: Found 1 design units, including 1 entities, in source file db/cntr_bd7.tdf Info: Found entity 1: cntr_bd7 Info: Elaborating entity "cntr_bd7" for hierarchy "std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw" Info: Found 1 design units, including 1 entities, in source file db/dpram_ga21.tdf Info: Found entity 1: dpram_ga21 Info: Elaborating entity "dpram_ga21" for hierarchy "std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram" Info: Found 1 design units, including 1 entities, in source file db/altsyncram_kml1.tdf Info: Found entity 1: altsyncram_kml1 Info: Elaborating entity "altsyncram_kml1" for hierarchy "std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1" Info: Found 1 design units, including 1 entities, in source file db/cntr_te8.tdf Info: Found entity 1: cntr_te8 Info: Elaborating entity "cntr_te8" for hierarchy "std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count" Info: Elaborating entity "jtag_uart_scfifo_r" for hierarchy "std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r" Info: Found 1 design units, including 1 entities, in source file /tools/quartus/6.0/176/libraries/megafunctions/alt_jtag_atlantic.v Info: Found entity 1: alt_jtag_atlantic Info: Elaborating entity "alt_jtag_atlantic" for hierarchy "std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic" Info: Elaborated megafunction instantiation "std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic" Info: Elaborating entity "lcd_display_control_slave_arbitrator" for hierarchy "std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave" Warning: Using design file lcd_display.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: lcd_display-europa Info: Found entity 1: lcd_display Info: Elaborating entity "lcd_display" for hierarchy "std_1s10:inst|lcd_display:the_lcd_display" Info: Elaborating entity "led_pio_s1_arbitrator" for hierarchy "std_1s10:inst|led_pio_s1_arbitrator:the_led_pio_s1" Warning: Using design file led_pio.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: led_pio-europa Info: Found entity 1: led_pio Info: Elaborating entity "led_pio" for hierarchy "std_1s10:inst|led_pio:the_led_pio" Info: Elaborating entity "onchip_ram_64_kbytes_s1_arbitrator" for hierarchy "std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1" Warning: Using design file onchip_ram_64_kbytes.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: onchip_ram_64_kbytes-europa Info: Found entity 1: onchip_ram_64_kbytes Info: Elaborating entity "onchip_ram_64_kbytes" for hierarchy "std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes" Info: Elaborating entity "altsyncram" for hierarchy "std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram" Info: Elaborated megafunction instantiation "std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram" Info: Found 1 design units, including 1 entities, in source file db/altsyncram_7b71.tdf Info: Found entity 1: altsyncram_7b71 Info: Elaborating entity "altsyncram_7b71" for hierarchy "std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated" Info: Elaborating entity "pll_s1_arbitrator" for hierarchy "std_1s10:inst|pll_s1_arbitrator:the_pll_s1" Warning: Using design file pll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: pll-europa Info: Found entity 1: pll Info: Elaborating entity "pll" for hierarchy "std_1s10:inst|pll:the_pll" Warning (10492): VHDL Process Statement warning at pll.vhd(176): signal "reset_input1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list Warning: Using design file altpllpll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: altpllpll-SYN Info: Found entity 1: altpllpll Info: Elaborating entity "altpllpll" for hierarchy "std_1s10:inst|pll:the_pll|altpllpll:the_pll" Info: Found 1 design units, including 1 entities, in source file /tools/quartus/6.0/176/libraries/megafunctions/altpll.tdf Info: Found entity 1: altpll Info: Elaborating entity "altpll" for hierarchy "std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component" Info: Elaborated megafunction instantiation "std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component" Info: Elaborating entity "reconfig_request_pio_s1_arbitrator" for hierarchy "std_1s10:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1" Warning: Using design file reconfig_request_pio.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: reconfig_request_pio-europa Info: Found entity 1: reconfig_request_pio Info: Elaborating entity "reconfig_request_pio" for hierarchy "std_1s10:inst|reconfig_request_pio:the_reconfig_request_pio" Info: Elaborating entity "sdram_s1_arbitrator" for hierarchy "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1" Info: Elaborating entity "rdv_fifo_for_cpu_data_master_to_sdram_s1_module" for hierarchy "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1" Info: Elaborating entity "rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module" for hierarchy "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1" Warning: Using design file sdram.vhd, which is not specified as a design file for the current project, but contains definitions for 4 design units and 2 entities in project Info: Found design unit 1: sdram_input_efifo_module-europa Info: Found design unit 2: sdram-europa Info: Found entity 1: sdram_input_efifo_module Info: Found entity 2: sdram Info: Elaborating entity "sdram" for hierarchy "std_1s10:inst|sdram:the_sdram" Info: Elaborating entity "sdram_input_efifo_module" for hierarchy "std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module" Info: Elaborating entity "seven_seg_pio_s1_arbitrator" for hierarchy "std_1s10:inst|seven_seg_pio_s1_arbitrator:the_seven_seg_pio_s1" Warning: Using design file seven_seg_pio.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: seven_seg_pio-europa Info: Found entity 1: seven_seg_pio Info: Elaborating entity "seven_seg_pio" for hierarchy "std_1s10:inst|seven_seg_pio:the_seven_seg_pio" Info: Elaborating entity "sys_clk_timer_s1_arbitrator" for hierarchy "std_1s10:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1" Warning: Using design file sys_clk_timer.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: sys_clk_timer-europa Info: Found entity 1: sys_clk_timer Info: Elaborating entity "sys_clk_timer" for hierarchy "std_1s10:inst|sys_clk_timer:the_sys_clk_timer" Info: Elaborating entity "sysid_control_slave_arbitrator" for hierarchy "std_1s10:inst|sysid_control_slave_arbitrator:the_sysid_control_slave" Warning: Using design file sysid.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: sysid-europa Info: Found entity 1: sysid Info: Elaborating entity "sysid" for hierarchy "std_1s10:inst|sysid:the_sysid" Info: Elaborating entity "uart1_s1_arbitrator" for hierarchy "std_1s10:inst|uart1_s1_arbitrator:the_uart1_s1" Warning: Using design file uart1.vhd, which is not specified as a design file for the current project, but contains definitions for 14 design units and 7 entities in project Info: Found design unit 1: uart1_log_module-europa Info: Found design unit 2: uart1_tx-europa Info: Found design unit 3: uart1_rx_stimulus_source_character_source_rom_module-europa Info: Found design unit 4: uart1_rx_stimulus_source-europa Info: Found design unit 5: uart1_rx-europa Info: Found design unit 6: uart1_regs-europa Info: Found design unit 7: uart1-europa Info: Found entity 1: uart1_log_module Info: Found entity 2: uart1_tx Info: Found entity 3: uart1_rx_stimulus_source_character_source_rom_module Info: Found entity 4: uart1_rx_stimulus_source Info: Found entity 5: uart1_rx Info: Found entity 6: uart1_regs Info: Found entity 7: uart1 Info: Elaborating entity "uart1" for hierarchy "std_1s10:inst|uart1:the_uart1" Info: Elaborating entity "uart1_tx" for hierarchy "std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx" Info: Elaborating entity "uart1_rx" for hierarchy "std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx" Info: Elaborating entity "uart1_rx_stimulus_source" for hierarchy "std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|uart1_rx_stimulus_source:the_uart1_rx_stimulus_source" Info: Elaborating entity "uart1_regs" for hierarchy "std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs" Info: Elaborating entity "std_1s10_reset_sys_clk_domain_synch_module" for hierarchy "std_1s10:inst|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch" Info: Elaborating entity "std_1s10_reset_clk_domain_synch_module" for hierarchy "std_1s10:inst|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch" Info: Found 6 design units, including 2 entities, in source file /tools/quartus/6.0/176/libraries/megafunctions/sld_hub.vhd Info: Found design unit 1: HUB_PACK Info: Found design unit 2: JTAG_PACK Info: Found design unit 3: sld_hub-rtl Info: Found design unit 4: sld_jtag_state_machine-rtl Info: Found entity 1: sld_hub Info: Found entity 2: sld_jtag_state_machine Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst" Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Stratix" Info: Found 1 design units, including 1 entities, in source file /tools/quartus/6.0/176/libraries/megafunctions/lpm_shiftreg.tdf Info: Found entity 1: lpm_shiftreg Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Stratix" Info: Found 1 design units, including 1 entities, in source file /tools/quartus/6.0/176/libraries/megafunctions/lpm_decode.tdf Info: Found entity 1: lpm_decode Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|lpm_decode:instruction_decoder", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Stratix" Info: Found 1 design units, including 1 entities, in source file db/decode_lhi.tdf Info: Found entity 1: decode_lhi Info: Found 2 design units, including 1 entities, in source file /tools/quartus/6.0/176/libraries/megafunctions/sld_dffex.vhd Info: Found design unit 1: sld_dffex-DFFEX Info: Found entity 1: sld_dffex Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:RESET", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Stratix" Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:IRSR", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Stratix" Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Stratix" Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:IRF_ENA", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Stratix" Info: Found 2 design units, including 1 entities, in source file /tools/quartus/6.0/176/libraries/megafunctions/sld_rom_sr.vhd Info: Found design unit 1: sld_rom_sr-INFO_REG Info: Found entity 1: sld_rom_sr Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG", which is child of megafunction instantiation "sld_hub:sld_hub_inst" Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter: Info: Parameter "SLD_HUB_IP_VERSION" = "1" Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3" Info: Parameter "SLD_COMMON_IP_VERSION" = "0" Info: Parameter "N_NODES" = "2" Info: Parameter "N_SEL_BITS" = "2" Info: Parameter "N_NODE_IR_BITS" = "5" Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000" Info: Parameter "COMPILATION_MODE" = "0" Info: Parameter "DEVICE_FAMILY" = "Stratix" Warning: Reduced register "std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[10]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[11]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[12]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[13]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[14]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[15]" with stuck data_in port to stuck value GND Info: Power-up level of register "std_1s10:inst|sdram:the_sdram|i_addr[4]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|sdram:the_sdram|i_addr[4]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|sdram:the_sdram|i_addr[5]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|sdram:the_sdram|i_addr[5]" with stuck data_in port to stuck value VCC Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[0]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[1]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[2]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[3]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[4]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[5]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[6]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[7]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[8]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[9]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[10]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[11]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[12]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[13]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[14]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|pll:the_pll|status_reg_out[15]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|d1_reasons_to_wait" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[31]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[30]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[29]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[28]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[27]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[26]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[25]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[24]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[23]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[22]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[21]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[20]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[19]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[18]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[17]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[16]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[15]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[14]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[13]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[12]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[11]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[10]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[9]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[8]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[7]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|M_ipending_reg[6]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|internal_trc_wrap" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|internal_trc_im_addr[0]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|internal_trc_im_addr[1]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|internal_trc_im_addr[2]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|internal_trc_im_addr[3]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|internal_trc_im_addr[4]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|internal_trc_im_addr[5]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|internal_trc_im_addr[6]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_break_pulse" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_goto0" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|dbrk_goto1" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_hit0" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_hit1" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_hit2" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_hit3" with stuck data_in port to stuck value GND Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[6]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[6]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[7]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[7]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[8]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[8]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[9]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[9]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[10]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[10]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[11]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[11]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[12]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[12]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[13]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[13]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[14]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[14]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[15]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[15]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[16]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[16]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[17]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[17]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[18]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[18]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[19]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[19]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[20]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[20]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[21]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[21]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[22]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[22]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[23]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[23]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[24]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[24]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[25]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[25]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[26]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[26]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[27]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[27]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[28]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[28]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[29]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[29]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[30]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[30]" with stuck data_in port to stuck value VCC Info: Power-up level of register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[31]" is not specified -- using power-up level of High to minimize register Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[31]" with stuck data_in port to stuck value VCC Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|xbrk_break" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|E_xbrk_goto0" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_xbrk:the_cpu_nios2_oci_xbrk|E_xbrk_goto1" with stuck data_in port to stuck value GND Warning: Synthesized away the following node(s): Warning: Synthesized away the following RAM node(s): Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[0]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[1]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[2]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[3]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[4]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[5]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[6]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[7]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[8]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[9]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[10]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[11]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[12]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[13]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[14]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[15]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[16]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[17]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[18]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[19]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[20]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[21]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[22]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[23]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[24]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[25]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[26]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[27]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[28]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[29]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[30]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[31]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[32]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[33]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[34]" Warning: Synthesized away node "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_im:the_cpu_nios2_oci_im|cpu_traceram_lpm_dram_bdp_component_module:cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_puv1:auto_generated|q_a[35]" Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk_hit3_latch" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk_hit2_latch" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk_hit1_latch" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|dbrk_hit0_latch" with stuck data_in port to stuck value GND Info: Duplicate registers merged to single register Info: Duplicate register "std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|delayed_unxsync_rxdxx1" merged to single register "std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|delayed_unxsync_rxdxx2" Info: Duplicate register "std_1s10:inst|sdram:the_sdram|i_addr[1]" merged to single register "std_1s10:inst|sdram:the_sdram|i_addr[0]" Info: Duplicate register "std_1s10:inst|sdram:the_sdram|i_addr[2]" merged to single register "std_1s10:inst|sdram:the_sdram|i_addr[0]" Info: Duplicate register "std_1s10:inst|sdram:the_sdram|i_addr[3]" merged to single register "std_1s10:inst|sdram:the_sdram|i_addr[0]" Info: Duplicate register "std_1s10:inst|sdram:the_sdram|i_addr[6]" merged to single register "std_1s10:inst|sdram:the_sdram|i_addr[0]" Info: Duplicate register "std_1s10:inst|sdram:the_sdram|i_addr[7]" merged to single register "std_1s10:inst|sdram:the_sdram|i_addr[0]" Info: Duplicate register "std_1s10:inst|sdram:the_sdram|i_addr[8]" merged to single register "std_1s10:inst|sdram:the_sdram|i_addr[0]" Info: Duplicate register "std_1s10:inst|sdram:the_sdram|i_addr[9]" merged to single register "std_1s10:inst|sdram:the_sdram|i_addr[0]" Info: Duplicate register "std_1s10:inst|sdram:the_sdram|i_addr[10]" merged to single register "std_1s10:inst|sdram:the_sdram|i_addr[0]" Info: Duplicate register "std_1s10:inst|sdram:the_sdram|i_addr[11]" merged to single register "std_1s10:inst|sdram:the_sdram|i_addr[0]" Info: Duplicate register "std_1s10:inst|pll_s1_arbitrator:the_pll_s1|d1_pll_s1_end_xfer" merged to single register "std_1s10:inst|pll_s1_arbitrator:the_pll_s1|d1_reasons_to_wait", power-up level changed Info: Duplicate register "std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|wrote_half_cycle_ext_ram_s1_last_time" merged to single register "std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_local", power-up level changed Info: Duplicate register "std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_reasons_to_wait" merged to single register "std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer", power-up level changed Info: Duplicate register "std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_cpu_jtag_debug_module_end_xfer" merged to single register "std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_reasons_to_wait", power-up level changed Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|trigger_state" with stuck data_in port to stuck value GND Info: Duplicate registers merged to single register Info: Duplicate register "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|full_0" merged to single register "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_0" Info: Duplicate register "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|full_1" merged to single register "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_1" Info: Duplicate register "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|full_2" merged to single register "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_2" Info: Duplicate register "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|full_3" merged to single register "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_3" Info: Duplicate register "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|full_4" merged to single register "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_4" Info: Duplicate register "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|full_5" merged to single register "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_5" Info: Duplicate register "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|full_6" merged to single register "std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_6" Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_dbrk:the_cpu_nios2_oci_dbrk|internal_dbrk_break" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|trigbrktype" with stuck data_in port to stuck value GND Info: Duplicate registers merged to single register Info: Duplicate register "std_1s10:inst|sdram:the_sdram|m_next[2]" merged to single register "std_1s10:inst|sdram:the_sdram|m_next[1]" Info: Duplicate register "std_1s10:inst|sdram:the_sdram|m_next[5]" merged to single register "std_1s10:inst|sdram:the_sdram|m_next[1]" Info: Duplicate register "std_1s10:inst|sdram:the_sdram|m_next[6]" merged to single register "std_1s10:inst|sdram:the_sdram|m_next[1]" Info: Duplicate register "std_1s10:inst|sdram:the_sdram|m_next[8]" merged to single register "std_1s10:inst|sdram:the_sdram|m_next[1]" Info: Duplicate register "std_1s10:inst|sdram:the_sdram|i_next[2]" merged to single register "std_1s10:inst|sdram:the_sdram|i_next[0]" Info: Duplicate register "std_1s10:inst|cpu:the_cpu|E_compare_op[1]" merged to single register "std_1s10:inst|cpu:the_cpu|E_logic_op[1]" Info: Duplicate register "std_1s10:inst|cpu:the_cpu|E_compare_op[0]" merged to single register "std_1s10:inst|cpu:the_cpu|E_logic_op[0]" Warning: Reduced register "std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[2]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_share_counter[2]" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_arb_share_counter[2]" with stuck data_in port to stuck value GND Info: Duplicate registers merged to single register Info: Duplicate register "std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_arb_addend[0]" merged to single register "std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_arb_addend[1]", power-up level changed Warning: Reduced register "std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_slavearbiterlockenable" with stuck data_in port to stuck value GND Warning: Reduced register "std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_slavearbiterlockenable" with stuck data_in port to stuck value GND Info: Found 1 design units, including 1 entities, in source file /tools/quartus/6.0/176/libraries/megafunctions/lpm_add_sub.tdf Info: Found entity 1: lpm_add_sub Info: Elaborated megafunction instantiation "std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8" Info: Found 1 design units, including 1 entities, in source file /tools/quartus/6.0/176/libraries/megafunctions/alt_stratix_add_sub.tdf Info: Found entity 1: alt_stratix_add_sub Info: Elaborated megafunction instantiation "std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder", which is child of megafunction instantiation "std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8" Info: Instantiated megafunction "std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8" with the following parameter: Info: Parameter "LPM_WIDTH" = "33" Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED" Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO" Warning: Ignore assignments for "PLD_CLOCKINPUT"[2] because it is an invalid assignment target -- "PLD_CLOCKINPUT" is a single bit, and cannot have members Info: Duplicate registers merged to single register Info: Duplicate register "std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read1" merged to single register "std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[1]" Info: Duplicate registers merged to single register Info: Duplicate register "std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_write1" merged to single register "std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[2]" Warning: Output pins are stuck at VCC or GND Warning: Pin "ENET_ADS_N" stuck at GND Warning: Pin "ENET_AEN" stuck at GND Warning: Pin "zs_cke_from_the_sdram" stuck at VCC Info: Registers with preset signals will power-up high Info: Implemented 4887 device resources after synthesis - the final resource count might be different Info: Implemented 12 input pins Info: Implemented 94 output pins Info: Implemented 73 bidirectional pins Info: Implemented 4556 logic cells Info: Implemented 142 RAM segments Info: Implemented 1 ClockLock PLLs Info: Implemented 8 DSP elements Info: Quartus II Analysis & Synthesis was successful. 0 errors, 177 warnings Info: Processing ended: Fri Apr 21 02:59:18 2006 Info: Elapsed time: 00:03:49