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--Q1_ior_n_to_the_lan91c111 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ior_n_to_the_lan91c111
--operation mode is normal
Q1_ior_n_to_the_lan91c111_lut_out = !Q1_ext_ram_bus_avalon_slave_begins_xfer & (Q1L82 # L1_internal_d_read & Q1L48);
Q1_ior_n_to_the_lan91c111 = DFFEAS(Q1_ior_n_to_the_lan91c111_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_write_n_to_the_ext_flash is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_flash
--operation mode is normal
Q1_write_n_to_the_ext_flash_lut_out = Q1L136 & !Q1_ext_ram_bus_avalon_slave_begins_xfer & (Q1_ext_flash_s1_wait_counter[3] $ !Q1L288);
Q1_write_n_to_the_ext_flash = DFFEAS(Q1_write_n_to_the_ext_flash_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_iow_n_to_the_lan91c111 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|iow_n_to_the_lan91c111
--operation mode is normal
Q1_iow_n_to_the_lan91c111_lut_out = L1_internal_d_write & Q1L48 & Q1L256 & !Q1_ext_ram_bus_avalon_slave_begins_xfer;
Q1_iow_n_to_the_lan91c111 = DFFEAS(Q1_iow_n_to_the_lan91c111_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_read_n_to_the_ext_flash is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_flash
--operation mode is normal
Q1_read_n_to_the_ext_flash_lut_out = !Q1_ext_ram_bus_avalon_slave_begins_xfer & !Q1_ext_flash_s1_wait_counter[3] & (Q1L63 # Q1L80);
Q1_read_n_to_the_ext_flash = DFFEAS(Q1_read_n_to_the_ext_flash_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_read_n_to_the_ext_ram is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram
--operation mode is normal
Q1_read_n_to_the_ext_ram_lut_out = Q1L81 # L1_internal_d_read & Q1L47;
Q1_read_n_to_the_ext_ram = DFFEAS(Q1_read_n_to_the_ext_ram_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_select_n_to_the_ext_ram is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram
--operation mode is normal
Q1_select_n_to_the_ext_ram_lut_out = Q1L81 # Q1L56 & (Q1L24 # Q1L26);
Q1_select_n_to_the_ext_ram = DFFEAS(Q1_select_n_to_the_ext_ram_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_write_n_to_the_ext_ram_local is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_local
--operation mode is normal
Q1_write_n_to_the_ext_ram_local_lut_out = L1_internal_d_write & Q1L56 & (Q1L24 # Q1L26);
Q1_write_n_to_the_ext_ram_local = DFFEAS(Q1_write_n_to_the_ext_ram_local_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_write_n_to_the_ext_ram_mask is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_mask
--operation mode is normal
Q1_write_n_to_the_ext_ram_mask_lut_out = Q1_write_n_to_the_ext_ram_local;
Q1_write_n_to_the_ext_ram_mask = DFFEAS(Q1_write_n_to_the_ext_ram_mask_lut_out, !DE1__clk0, E1_data_out, , , , , , );
--Q1L301 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram~0
--operation mode is normal
Q1L301 = Q1_write_n_to_the_ext_ram_local & (!Q1_write_n_to_the_ext_ram_mask);
--FB1_m_cmd[1] is std_1s10:inst|sdram:the_sdram|m_cmd[1]
--operation mode is normal
FB1_m_cmd[1]_lut_out = !FB1L262 & (FB1_m_state[7] & FB1L263 # !FB1_m_state[7] & (FB1L265));
FB1_m_cmd[1] = DFFEAS(FB1_m_cmd[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_cmd[3] is std_1s10:inst|sdram:the_sdram|m_cmd[3]
--operation mode is normal
FB1_m_cmd[3]_lut_out = FB1_m_state[7] & (FB1L256 & FB1L257) # !FB1_m_state[7] & !FB1L255;
FB1_m_cmd[3] = DFFEAS(FB1_m_cmd[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_cmd[2] is std_1s10:inst|sdram:the_sdram|m_cmd[2]
--operation mode is normal
FB1_m_cmd[2]_lut_out = !FB1L258 & !FB1L259 & (FB1L261 # !FB1L260);
FB1_m_cmd[2] = DFFEAS(FB1_m_cmd[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_cmd[0] is std_1s10:inst|sdram:the_sdram|m_cmd[0]
--operation mode is normal
FB1_m_cmd[0]_lut_out = FB1L267 & FB1L269 & (!FB1L268 # !FB1L171);
FB1_m_cmd[0] = DFFEAS(FB1_m_cmd[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--L1_M_alu_result[2] is std_1s10:inst|cpu:the_cpu|M_alu_result[2]
--operation mode is normal
L1_M_alu_result[2] = AMPP_FUNCTION(DE1__clk0, L1L410, E1_data_out, L1_W_stall);
--L1_M_alu_result[3] is std_1s10:inst|cpu:the_cpu|M_alu_result[3]
--operation mode is normal
L1_M_alu_result[3] = AMPP_FUNCTION(DE1__clk0, L1L411, E1_data_out, L1_W_stall);
--L1_M_alu_result[7] is std_1s10:inst|cpu:the_cpu|M_alu_result[7]
--operation mode is normal
L1_M_alu_result[7] = AMPP_FUNCTION(DE1__clk0, L1L7, L1L520, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_internal_d_read is std_1s10:inst|cpu:the_cpu|internal_d_read
--operation mode is normal
L1_internal_d_read = AMPP_FUNCTION(DE1__clk0, L1L328, L1L800, L1_E_ctrl_ld, L1_W_stall, E1_data_out);
--L1_M_alu_result[4] is std_1s10:inst|cpu:the_cpu|M_alu_result[4]
--operation mode is normal
L1_M_alu_result[4] = AMPP_FUNCTION(DE1__clk0, L1L412, E1_data_out, L1_W_stall);
--L1_M_alu_result[22] is std_1s10:inst|cpu:the_cpu|M_alu_result[22]
--operation mode is normal
L1_M_alu_result[22] = AMPP_FUNCTION(DE1__clk0, L1L11, L1L535, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[21] is std_1s10:inst|cpu:the_cpu|M_alu_result[21]
--operation mode is normal
L1_M_alu_result[21] = AMPP_FUNCTION(DE1__clk0, L1L12, L1L534, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[24] is std_1s10:inst|cpu:the_cpu|M_alu_result[24]
--operation mode is normal
L1_M_alu_result[24] = AMPP_FUNCTION(DE1__clk0, L1L13, L1L537, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[19] is std_1s10:inst|cpu:the_cpu|M_alu_result[19]
--operation mode is normal
L1_M_alu_result[19] = AMPP_FUNCTION(DE1__clk0, L1L14, L1L532, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--AB1L6 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_requests_onchip_ram_64_kbytes_s1~297
--operation mode is normal
AB1L6 = !L1_M_alu_result[22] & !L1_M_alu_result[21] & !L1_M_alu_result[24] & !L1_M_alu_result[19];
--L1_M_alu_result[18] is std_1s10:inst|cpu:the_cpu|M_alu_result[18]
--operation mode is normal
L1_M_alu_result[18] = AMPP_FUNCTION(DE1__clk0, L1L15, L1L531, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[17] is std_1s10:inst|cpu:the_cpu|M_alu_result[17]
--operation mode is normal
L1_M_alu_result[17] = AMPP_FUNCTION(DE1__clk0, L1L16, L1L530, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--AB1L7 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_requests_onchip_ram_64_kbytes_s1~298
--operation mode is normal
AB1L7 = !L1_M_alu_result[18] & !L1_M_alu_result[17];
--L1_M_alu_result[16] is std_1s10:inst|cpu:the_cpu|M_alu_result[16]
--operation mode is normal
L1_M_alu_result[16] = AMPP_FUNCTION(DE1__clk0, L1L17, L1L529, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[23] is std_1s10:inst|cpu:the_cpu|M_alu_result[23]
--operation mode is normal
L1_M_alu_result[23] = AMPP_FUNCTION(DE1__clk0, L1L18, L1L536, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[25] is std_1s10:inst|cpu:the_cpu|M_alu_result[25]
--operation mode is normal
L1_M_alu_result[25] = AMPP_FUNCTION(DE1__clk0, L1L19, L1L538, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[20] is std_1s10:inst|cpu:the_cpu|M_alu_result[20]
--operation mode is normal
L1_M_alu_result[20] = AMPP_FUNCTION(DE1__clk0, L1L20, L1L533, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--P1L5 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~305
--operation mode is normal
P1L5 = L1_M_alu_result[16] & L1_M_alu_result[23] & !L1_M_alu_result[25] & !L1_M_alu_result[20];
--L1_M_alu_result[15] is std_1s10:inst|cpu:the_cpu|M_alu_result[15]
--operation mode is normal
L1_M_alu_result[15] = AMPP_FUNCTION(DE1__clk0, L1L21, L1L528, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[14] is std_1s10:inst|cpu:the_cpu|M_alu_result[14]
--operation mode is normal
L1_M_alu_result[14] = AMPP_FUNCTION(DE1__clk0, L1L22, L1L527, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[13] is std_1s10:inst|cpu:the_cpu|M_alu_result[13]
--operation mode is normal
L1_M_alu_result[13] = AMPP_FUNCTION(DE1__clk0, L1L23, L1L526, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[12] is std_1s10:inst|cpu:the_cpu|M_alu_result[12]
--operation mode is normal
L1_M_alu_result[12] = AMPP_FUNCTION(DE1__clk0, L1L24, L1L525, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--P1L6 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~306
--operation mode is normal
P1L6 = !L1_M_alu_result[15] & !L1_M_alu_result[14] & !L1_M_alu_result[13] & !L1_M_alu_result[12];
--P1L7 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~307
--operation mode is normal
P1L7 = AB1L6 & AB1L7 & P1L5 & P1L6;
--L1_M_alu_result[11] is std_1s10:inst|cpu:the_cpu|M_alu_result[11]
--operation mode is normal
L1_M_alu_result[11] = AMPP_FUNCTION(DE1__clk0, L1L25, L1L524, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[10] is std_1s10:inst|cpu:the_cpu|M_alu_result[10]
--operation mode is normal
L1_M_alu_result[10] = AMPP_FUNCTION(DE1__clk0, L1L26, L1L523, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[9] is std_1s10:inst|cpu:the_cpu|M_alu_result[9]
--operation mode is normal
L1_M_alu_result[9] = AMPP_FUNCTION(DE1__clk0, L1L27, L1L522, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[8] is std_1s10:inst|cpu:the_cpu|M_alu_result[8]
--operation mode is normal
L1_M_alu_result[8] = AMPP_FUNCTION(DE1__clk0, L1L28, L1L521, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--NB1L2 is std_1s10:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~58
--operation mode is normal
NB1L2 = L1_M_alu_result[11] & !L1_M_alu_result[10] & !L1_M_alu_result[9] & !L1_M_alu_result[8];
--L1_M_alu_result[5] is std_1s10:inst|cpu:the_cpu|M_alu_result[5]
--operation mode is normal
L1_M_alu_result[5] = AMPP_FUNCTION(DE1__clk0, L1L413, E1_data_out, L1_W_stall);
--L1_internal_d_write is std_1s10:inst|cpu:the_cpu|internal_d_write
--operation mode is normal
L1_internal_d_write = AMPP_FUNCTION(DE1__clk0, KB1L7, L1_E_ctrl_st, L1L800, L1L1443, E1_data_out);
--QB1L4 is std_1s10:inst|uart1_s1_arbitrator:the_uart1_s1|internal_cpu_data_master_requests_uart1_s1~0
--operation mode is normal
QB1L4 = L1_internal_d_write # L1_internal_d_read;
--L1_M_alu_result[6] is std_1s10:inst|cpu:the_cpu|M_alu_result[6]
--operation mode is normal
L1_M_alu_result[6] = AMPP_FUNCTION(DE1__clk0, L1L32, L1L519, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--G1L1 is std_1s10:inst|button_pio_s1_arbitrator:the_button_pio_s1|cpu_data_master_requests_button_pio_s1~52
--operation mode is normal
G1L1 = L1_M_alu_result[4] & P1L7 & NB1L2 & EB1L4;
--W1_lcd_display_control_slave_wait_counter[1] is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[1]
--operation mode is normal
W1_lcd_display_control_slave_wait_counter[1]_lut_out = W1L1 & !W1L15 & (!W1L16 # !QB1L4);
W1_lcd_display_control_slave_wait_counter[1] = DFFEAS(W1_lcd_display_control_slave_wait_counter[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--W1_lcd_display_control_slave_wait_counter[0] is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[0]
--operation mode is normal
W1_lcd_display_control_slave_wait_counter[0]_lut_out = W1L19 # W1L3 & W1L17 & !W1L15;
W1_lcd_display_control_slave_wait_counter[0] = DFFEAS(W1_lcd_display_control_slave_wait_counter[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--W1_lcd_display_control_slave_wait_counter[3] is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[3]
--operation mode is normal
W1_lcd_display_control_slave_wait_counter[3]_lut_out = !W1L19 & (W1L5 & !W1L15 # !W1L17);
W1_lcd_display_control_slave_wait_counter[3] = DFFEAS(W1_lcd_display_control_slave_wait_counter[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--W1_lcd_display_control_slave_wait_counter[2] is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[2]
--operation mode is normal
W1_lcd_display_control_slave_wait_counter[2]_lut_out = W1L19 # W1L7 & W1L17 & !W1L15;
W1_lcd_display_control_slave_wait_counter[2] = DFFEAS(W1_lcd_display_control_slave_wait_counter[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--W1L28 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|LessThan0~88
--operation mode is normal
W1L28 = !W1_lcd_display_control_slave_wait_counter[1] & !W1_lcd_display_control_slave_wait_counter[0] # !W1_lcd_display_control_slave_wait_counter[2] # !W1_lcd_display_control_slave_wait_counter[3];
--W1_lcd_display_control_slave_wait_counter[5] is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[5]
--operation mode is normal
W1_lcd_display_control_slave_wait_counter[5]_lut_out = W1L19 # W1L9 & W1L17 & !W1L15;
W1_lcd_display_control_slave_wait_counter[5] = DFFEAS(W1_lcd_display_control_slave_wait_counter[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--W1_lcd_display_control_slave_wait_counter[4] is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[4]
--operation mode is normal
W1_lcd_display_control_slave_wait_counter[4]_lut_out = !W1L19 & (W1L10 & !W1L15 # !W1L17);
W1_lcd_display_control_slave_wait_counter[4] = DFFEAS(W1_lcd_display_control_slave_wait_counter[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--W1L29 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|LessThan0~89
--operation mode is normal
W1L29 = !W1_lcd_display_control_slave_wait_counter[5] & !W1_lcd_display_control_slave_wait_counter[4];
--V1L1 is std_1s10:inst|lcd_display:the_lcd_display|LCD_E~441
--operation mode is normal
V1L1 = L1_M_alu_result[7] & L1_internal_d_read & G1L1 & W1L30;
--W1L18 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_in_a_write_cycle~36
--operation mode is normal
W1L18 = L1_M_alu_result[7] & L1_internal_d_write & G1L1;
--L1_M_mem_byte_en[0] is std_1s10:inst|cpu:the_cpu|M_mem_byte_en[0]
--operation mode is normal
L1_M_mem_byte_en[0] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[4], L1_E_iw[3], HC1_result[0], HC1_result[1], E1_data_out, L1_W_stall);
--V1L2 is std_1s10:inst|lcd_display:the_lcd_display|LCD_E~442
--operation mode is normal
V1L2 = W1_lcd_display_control_slave_wait_counter[1] & (W1_lcd_display_control_slave_wait_counter[2] # W1_lcd_display_control_slave_wait_counter[4]) # !W1_lcd_display_control_slave_wait_counter[1] & W1_lcd_display_control_slave_wait_counter[2] & (W1_lcd_display_control_slave_wait_counter[4] # W1_lcd_display_control_slave_wait_counter[0]);
--V1L3 is std_1s10:inst|lcd_display:the_lcd_display|LCD_E~443
--operation mode is normal
V1L3 = L1_M_mem_byte_en[0] & !W1_lcd_display_control_slave_wait_counter[5] & !V1L5;
--W1_d1_reasons_to_wait is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|d1_reasons_to_wait
--operation mode is normal
W1_d1_reasons_to_wait_lut_out = L1_M_alu_result[7] & G1L1 & (!W1L15 # !W1_d1_reasons_to_wait);
W1_d1_reasons_to_wait = DFFEAS(W1_d1_reasons_to_wait_lut_out, DE1__clk0, E1_data_out, , , , , , );
--W1L16 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_begintransfer~38
--operation mode is normal
W1L16 = L1_M_alu_result[7] & G1L1 & (!W1_d1_reasons_to_wait);
--V1L4 is std_1s10:inst|lcd_display:the_lcd_display|LCD_E~444
--operation mode is normal
V1L4 = !W1L16 & (V1L1 # W1L18 & V1L3);
--KE1_txd is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|txd
--operation mode is normal
KE1_txd_lut_out = HE1_control_reg[9] # KE1_pre_txd;
KE1_txd = DFFEAS(KE1_txd_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_select_n_to_the_ext_flash is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_flash
--operation mode is normal
Q1_select_n_to_the_ext_flash_lut_out = Q1L287;
Q1_select_n_to_the_ext_flash = DFFEAS(Q1_select_n_to_the_ext_flash_lut_out, DE1__clk0, E1_data_out, , , , , , );
--DE1__clk0 is std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0
DE1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(PLD_CLOCKINPUT), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());
--DE1__extclk0 is std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_extclk0
DE1__extclk0 = PLL.EXTCLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(PLD_CLOCKINPUT), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());
--Q1_be_n_to_the_ext_ram[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[3]
--operation mode is normal
Q1_be_n_to_the_ext_ram[3]_lut_out = L1_M_mem_byte_en[3] # !Q1L24 & !Q1L26 # !Q1L56;
Q1_be_n_to_the_ext_ram[3] = DFFEAS(Q1_be_n_to_the_ext_ram[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_be_n_to_the_ext_ram[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[2]
--operation mode is normal
Q1_be_n_to_the_ext_ram[2]_lut_out = L1_M_mem_byte_en[2] # !Q1L24 & !Q1L26 # !Q1L56;
Q1_be_n_to_the_ext_ram[2] = DFFEAS(Q1_be_n_to_the_ext_ram[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_be_n_to_the_ext_ram[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[1]
--operation mode is normal
Q1_be_n_to_the_ext_ram[1]_lut_out = L1_M_mem_byte_en[1] # !Q1L24 & !Q1L26 # !Q1L56;
Q1_be_n_to_the_ext_ram[1] = DFFEAS(Q1_be_n_to_the_ext_ram[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_be_n_to_the_ext_ram[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[0]
--operation mode is normal
Q1_be_n_to_the_ext_ram[0]_lut_out = L1_M_mem_byte_en[0] # !Q1L24 & !Q1L26 # !Q1L56;
Q1_be_n_to_the_ext_ram[0] = DFFEAS(Q1_be_n_to_the_ext_ram[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_byteenablen_to_the_lan91c111[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[3]
--operation mode is normal
Q1_byteenablen_to_the_lan91c111[3]_lut_out = L1_M_mem_byte_en[3] # !Q1L8 & !Q1L10 # !Q1L58;
Q1_byteenablen_to_the_lan91c111[3] = DFFEAS(Q1_byteenablen_to_the_lan91c111[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_byteenablen_to_the_lan91c111[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[2]
--operation mode is normal
Q1_byteenablen_to_the_lan91c111[2]_lut_out = L1_M_mem_byte_en[2] # !Q1L8 & !Q1L10 # !Q1L58;
Q1_byteenablen_to_the_lan91c111[2] = DFFEAS(Q1_byteenablen_to_the_lan91c111[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_byteenablen_to_the_lan91c111[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[1]
--operation mode is normal
Q1_byteenablen_to_the_lan91c111[1]_lut_out = L1_M_mem_byte_en[1] # !Q1L8 & !Q1L10 # !Q1L58;
Q1_byteenablen_to_the_lan91c111[1] = DFFEAS(Q1_byteenablen_to_the_lan91c111[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_byteenablen_to_the_lan91c111[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[0]
--operation mode is normal
Q1_byteenablen_to_the_lan91c111[0]_lut_out = L1_M_mem_byte_en[0] # !Q1L8 & !Q1L10 # !Q1L58;
Q1_byteenablen_to_the_lan91c111[0] = DFFEAS(Q1_byteenablen_to_the_lan91c111[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[22] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22]
--operation mode is normal
Q1_ext_ram_bus_address[22]_lut_out = Q1L281 & (Q1L282 # L1_M_alu_result[22] & Q1L46);
Q1_ext_ram_bus_address[22] = DFFEAS(Q1_ext_ram_bus_address[22]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[21] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21]
--operation mode is normal
Q1_ext_ram_bus_address[21]_lut_out = Q1L281 & (Q1L280 # L1_M_alu_result[21] & Q1L46);
Q1_ext_ram_bus_address[21] = DFFEAS(Q1_ext_ram_bus_address[21]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[20] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20]
--operation mode is normal
Q1_ext_ram_bus_address[20]_lut_out = Q1L281 & (Q1L279 # L1_M_alu_result[20] & Q1L46);
Q1_ext_ram_bus_address[20] = DFFEAS(Q1_ext_ram_bus_address[20]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[19] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[19]
--operation mode is normal
Q1_ext_ram_bus_address[19]_lut_out = Q1L281 & (Q1L283 & L1_ic_fill_tag[7] # !Q1L283 & (L1_M_alu_result[19]));
Q1_ext_ram_bus_address[19] = DFFEAS(Q1_ext_ram_bus_address[19]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[18] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[18]
--operation mode is normal
Q1_ext_ram_bus_address[18]_lut_out = Q1L281 & (Q1L283 & L1_ic_fill_tag[6] # !Q1L283 & (L1_M_alu_result[18]));
Q1_ext_ram_bus_address[18] = DFFEAS(Q1_ext_ram_bus_address[18]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[17] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]
--operation mode is normal
Q1_ext_ram_bus_address[17]_lut_out = Q1L281 & (Q1L283 & L1_ic_fill_tag[5] # !Q1L283 & (L1_M_alu_result[17]));
Q1_ext_ram_bus_address[17] = DFFEAS(Q1_ext_ram_bus_address[17]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[16] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[16]
--operation mode is normal
Q1_ext_ram_bus_address[16]_lut_out = Q1L281 & (Q1L283 & L1_ic_fill_tag[4] # !Q1L283 & (L1_M_alu_result[16]));
Q1_ext_ram_bus_address[16] = DFFEAS(Q1_ext_ram_bus_address[16]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[15] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[15]
--operation mode is normal
Q1_ext_ram_bus_address[15]_lut_out = Q1L278 & (Q1L48 & L1_M_alu_result[15] # !Q1L48 & (L1_ic_fill_tag[3])) # !Q1L278 & L1_M_alu_result[15];
Q1_ext_ram_bus_address[15] = DFFEAS(Q1_ext_ram_bus_address[15]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[14] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[14]
--operation mode is normal
Q1_ext_ram_bus_address[14]_lut_out = Q1L278 & (Q1L48 & L1_M_alu_result[14] # !Q1L48 & (L1_ic_fill_tag[2])) # !Q1L278 & L1_M_alu_result[14];
Q1_ext_ram_bus_address[14] = DFFEAS(Q1_ext_ram_bus_address[14]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[13] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[13]
--operation mode is normal
Q1_ext_ram_bus_address[13]_lut_out = Q1L278 & (Q1L48 & L1_M_alu_result[13] # !Q1L48 & (L1_ic_fill_tag[1])) # !Q1L278 & L1_M_alu_result[13];
Q1_ext_ram_bus_address[13] = DFFEAS(Q1_ext_ram_bus_address[13]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[12] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[12]
--operation mode is normal
Q1_ext_ram_bus_address[12]_lut_out = Q1L278 & (Q1L48 & L1_M_alu_result[12] # !Q1L48 & (L1_ic_fill_tag[0])) # !Q1L278 & L1_M_alu_result[12];
Q1_ext_ram_bus_address[12] = DFFEAS(Q1_ext_ram_bus_address[12]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[11] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[11]
--operation mode is normal
Q1_ext_ram_bus_address[11]_lut_out = Q1L278 & (Q1L48 & L1_M_alu_result[11] # !Q1L48 & (L1_ic_fill_line[6])) # !Q1L278 & L1_M_alu_result[11];
Q1_ext_ram_bus_address[11] = DFFEAS(Q1_ext_ram_bus_address[11]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[10] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[10]
--operation mode is normal
Q1_ext_ram_bus_address[10]_lut_out = Q1L278 & (Q1L48 & L1_M_alu_result[10] # !Q1L48 & (L1_ic_fill_line[5])) # !Q1L278 & L1_M_alu_result[10];
Q1_ext_ram_bus_address[10] = DFFEAS(Q1_ext_ram_bus_address[10]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[9] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[9]
--operation mode is normal
Q1_ext_ram_bus_address[9]_lut_out = Q1L278 & (Q1L48 & L1_M_alu_result[9] # !Q1L48 & (L1_ic_fill_line[4])) # !Q1L278 & L1_M_alu_result[9];
Q1_ext_ram_bus_address[9] = DFFEAS(Q1_ext_ram_bus_address[9]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[8] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[8]
--operation mode is normal
Q1_ext_ram_bus_address[8]_lut_out = Q1L278 & (Q1L48 & L1_M_alu_result[8] # !Q1L48 & (L1_ic_fill_line[3])) # !Q1L278 & L1_M_alu_result[8];
Q1_ext_ram_bus_address[8] = DFFEAS(Q1_ext_ram_bus_address[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[7] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[7]
--operation mode is normal
Q1_ext_ram_bus_address[7]_lut_out = Q1L278 & (Q1L48 & L1_M_alu_result[7] # !Q1L48 & (L1_ic_fill_line[2])) # !Q1L278 & L1_M_alu_result[7];
Q1_ext_ram_bus_address[7] = DFFEAS(Q1_ext_ram_bus_address[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[6] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[6]
--operation mode is normal
Q1_ext_ram_bus_address[6]_lut_out = Q1L278 & (Q1L48 & L1_M_alu_result[6] # !Q1L48 & (L1_ic_fill_line[1])) # !Q1L278 & L1_M_alu_result[6];
Q1_ext_ram_bus_address[6] = DFFEAS(Q1_ext_ram_bus_address[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[5] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[5]
--operation mode is normal
Q1_ext_ram_bus_address[5]_lut_out = Q1L278 & (Q1L48 & L1_M_alu_result[5] # !Q1L48 & (L1_ic_fill_line[0])) # !Q1L278 & L1_M_alu_result[5];
Q1_ext_ram_bus_address[5] = DFFEAS(Q1_ext_ram_bus_address[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[4] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[4]
--operation mode is normal
Q1_ext_ram_bus_address[4]_lut_out = Q1L278 & (Q1L48 & L1_M_alu_result[4] # !Q1L48 & (L1_ic_fill_ap_offset[2])) # !Q1L278 & L1_M_alu_result[4];
Q1_ext_ram_bus_address[4] = DFFEAS(Q1_ext_ram_bus_address[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[3]
--operation mode is normal
Q1_ext_ram_bus_address[3]_lut_out = Q1L278 & (Q1L48 & L1_M_alu_result[3] # !Q1L48 & (L1_ic_fill_ap_offset[1])) # !Q1L278 & L1_M_alu_result[3];
Q1_ext_ram_bus_address[3] = DFFEAS(Q1_ext_ram_bus_address[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[2]
--operation mode is normal
Q1_ext_ram_bus_address[2]_lut_out = Q1L278 & (Q1L48 & L1_M_alu_result[2] # !Q1L48 & (L1_ic_fill_ap_offset[0])) # !Q1L278 & L1_M_alu_result[2];
Q1_ext_ram_bus_address[2] = DFFEAS(Q1_ext_ram_bus_address[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[1]
--operation mode is normal
Q1_ext_ram_bus_address[1]_lut_out = Q1L281 & (Q1L277 # L1_M_alu_result[1] & Q1L274) # !Q1L281 & L1_M_alu_result[1] & Q1L274;
Q1_ext_ram_bus_address[1] = DFFEAS(Q1_ext_ram_bus_address[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_ram_bus_address[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[0]
--operation mode is normal
Q1_ext_ram_bus_address[0]_lut_out = Q1L281 & (Q1L275 # Q1L274 & L1_M_alu_result[0]) # !Q1L281 & Q1L274 & L1_M_alu_result[0];
Q1_ext_ram_bus_address[0] = DFFEAS(Q1_ext_ram_bus_address[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--X1_data_out[7] is std_1s10:inst|led_pio:the_led_pio|data_out[7]
--operation mode is normal
X1_data_out[7]_lut_out = L1_M_st_data[7];
X1_data_out[7] = DFFEAS(X1_data_out[7]_lut_out, DE1__clk0, E1_data_out, , X1L10, , , , );
--X1_data_out[6] is std_1s10:inst|led_pio:the_led_pio|data_out[6]
--operation mode is normal
X1_data_out[6]_lut_out = L1_M_st_data[6];
X1_data_out[6] = DFFEAS(X1_data_out[6]_lut_out, DE1__clk0, E1_data_out, , X1L10, , , , );
--X1_data_out[5] is std_1s10:inst|led_pio:the_led_pio|data_out[5]
--operation mode is normal
X1_data_out[5]_lut_out = L1_M_st_data[5];
X1_data_out[5] = DFFEAS(X1_data_out[5]_lut_out, DE1__clk0, E1_data_out, , X1L10, , , , );
--X1_data_out[4] is std_1s10:inst|led_pio:the_led_pio|data_out[4]
--operation mode is normal
X1_data_out[4]_lut_out = L1_M_st_data[4];
X1_data_out[4] = DFFEAS(X1_data_out[4]_lut_out, DE1__clk0, E1_data_out, , X1L10, , , , );
--X1_data_out[3] is std_1s10:inst|led_pio:the_led_pio|data_out[3]
--operation mode is normal
X1_data_out[3]_lut_out = L1_M_st_data[3];
X1_data_out[3] = DFFEAS(X1_data_out[3]_lut_out, DE1__clk0, E1_data_out, , X1L10, , , , );
--X1_data_out[2] is std_1s10:inst|led_pio:the_led_pio|data_out[2]
--operation mode is normal
X1_data_out[2]_lut_out = L1_M_st_data[2];
X1_data_out[2] = DFFEAS(X1_data_out[2]_lut_out, DE1__clk0, E1_data_out, , X1L10, , , , );
--X1_data_out[1] is std_1s10:inst|led_pio:the_led_pio|data_out[1]
--operation mode is normal
X1_data_out[1]_lut_out = L1_M_st_data[1];
X1_data_out[1] = DFFEAS(X1_data_out[1]_lut_out, DE1__clk0, E1_data_out, , X1L10, , , , );
--X1_data_out[0] is std_1s10:inst|led_pio:the_led_pio|data_out[0]
--operation mode is normal
X1_data_out[0]_lut_out = L1_M_st_data[0];
X1_data_out[0] = DFFEAS(X1_data_out[0]_lut_out, DE1__clk0, E1_data_out, , X1L10, , , , );
--HB1_data_out[15] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[15]
--operation mode is normal
HB1_data_out[15]_lut_out = L1_M_st_data[15];
HB1_data_out[15] = DFFEAS(HB1_data_out[15]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[14] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[14]
--operation mode is normal
HB1_data_out[14]_lut_out = L1_M_st_data[14];
HB1_data_out[14] = DFFEAS(HB1_data_out[14]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[13] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[13]
--operation mode is normal
HB1_data_out[13]_lut_out = L1_M_st_data[13];
HB1_data_out[13] = DFFEAS(HB1_data_out[13]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[12] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[12]
--operation mode is normal
HB1_data_out[12]_lut_out = L1_M_st_data[12];
HB1_data_out[12] = DFFEAS(HB1_data_out[12]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[11] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[11]
--operation mode is normal
HB1_data_out[11]_lut_out = L1_M_st_data[11];
HB1_data_out[11] = DFFEAS(HB1_data_out[11]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[10] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[10]
--operation mode is normal
HB1_data_out[10]_lut_out = L1_M_st_data[10];
HB1_data_out[10] = DFFEAS(HB1_data_out[10]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[9] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[9]
--operation mode is normal
HB1_data_out[9]_lut_out = L1_M_st_data[9];
HB1_data_out[9] = DFFEAS(HB1_data_out[9]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[8] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[8]
--operation mode is normal
HB1_data_out[8]_lut_out = L1_M_st_data[8];
HB1_data_out[8] = DFFEAS(HB1_data_out[8]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[7] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[7]
--operation mode is normal
HB1_data_out[7]_lut_out = L1_M_st_data[7];
HB1_data_out[7] = DFFEAS(HB1_data_out[7]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[6] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[6]
--operation mode is normal
HB1_data_out[6]_lut_out = L1_M_st_data[6];
HB1_data_out[6] = DFFEAS(HB1_data_out[6]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[5] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[5]
--operation mode is normal
HB1_data_out[5]_lut_out = L1_M_st_data[5];
HB1_data_out[5] = DFFEAS(HB1_data_out[5]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[4] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[4]
--operation mode is normal
HB1_data_out[4]_lut_out = L1_M_st_data[4];
HB1_data_out[4] = DFFEAS(HB1_data_out[4]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[3] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[3]
--operation mode is normal
HB1_data_out[3]_lut_out = L1_M_st_data[3];
HB1_data_out[3] = DFFEAS(HB1_data_out[3]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[2] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[2]
--operation mode is normal
HB1_data_out[2]_lut_out = L1_M_st_data[2];
HB1_data_out[2] = DFFEAS(HB1_data_out[2]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[1] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[1]
--operation mode is normal
HB1_data_out[1]_lut_out = L1_M_st_data[1];
HB1_data_out[1] = DFFEAS(HB1_data_out[1]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--HB1_data_out[0] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[0]
--operation mode is normal
HB1_data_out[0]_lut_out = L1_M_st_data[0];
HB1_data_out[0] = DFFEAS(HB1_data_out[0]_lut_out, DE1__clk0, E1_data_out, , HB1L18, , , , );
--FB1_m_addr[11] is std_1s10:inst|sdram:the_sdram|m_addr[11]
--operation mode is normal
FB1_m_addr[11]_lut_out = FB1L432 & FB1_m_addr[11] # !FB1L432 & (FB1L430 # FB1_m_addr[11] & FB1L431);
FB1_m_addr[11] = DFFEAS(FB1_m_addr[11]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_addr[10] is std_1s10:inst|sdram:the_sdram|m_addr[10]
--operation mode is normal
FB1_m_addr[10]_lut_out = FB1L432 & FB1_m_addr[10] # !FB1L432 & (FB1L437 # FB1_m_addr[10] & FB1L431);
FB1_m_addr[10] = DFFEAS(FB1_m_addr[10]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_addr[9] is std_1s10:inst|sdram:the_sdram|m_addr[9]
--operation mode is normal
FB1_m_addr[9]_lut_out = FB1L432 & FB1_m_addr[9] # !FB1L432 & (FB1L442 # FB1_m_addr[9] & FB1L431);
FB1_m_addr[9] = DFFEAS(FB1_m_addr[9]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_addr[8] is std_1s10:inst|sdram:the_sdram|m_addr[8]
--operation mode is normal
FB1_m_addr[8]_lut_out = FB1L432 & FB1_m_addr[8] # !FB1L432 & (FB1L447 # FB1_m_addr[8] & FB1L431);
FB1_m_addr[8] = DFFEAS(FB1_m_addr[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_addr[7] is std_1s10:inst|sdram:the_sdram|m_addr[7]
--operation mode is normal
FB1_m_addr[7]_lut_out = FB1L432 & FB1_m_addr[7] # !FB1L432 & (FB1L454 # FB1_m_addr[7] & FB1_m_state[6]);
FB1_m_addr[7] = DFFEAS(FB1_m_addr[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_addr[6] is std_1s10:inst|sdram:the_sdram|m_addr[6]
--operation mode is normal
FB1_m_addr[6]_lut_out = FB1L456 # FB1L461 & !FB1_m_state[6] & !FB1L432;
FB1_m_addr[6] = DFFEAS(FB1_m_addr[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_addr[5] is std_1s10:inst|sdram:the_sdram|m_addr[5]
--operation mode is normal
FB1_m_addr[5]_lut_out = FB1L463 # FB1L468 & !FB1_m_state[6] & !FB1L432;
FB1_m_addr[5] = DFFEAS(FB1_m_addr[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_addr[4] is std_1s10:inst|sdram:the_sdram|m_addr[4]
--operation mode is normal
FB1_m_addr[4]_lut_out = FB1L470 # FB1L475 & !FB1_m_state[6] & !FB1L432;
FB1_m_addr[4] = DFFEAS(FB1_m_addr[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_addr[3] is std_1s10:inst|sdram:the_sdram|m_addr[3]
--operation mode is normal
FB1_m_addr[3]_lut_out = FB1L477 # FB1L482 & !FB1_m_state[6] & !FB1L432;
FB1_m_addr[3] = DFFEAS(FB1_m_addr[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_addr[2] is std_1s10:inst|sdram:the_sdram|m_addr[2]
--operation mode is normal
FB1_m_addr[2]_lut_out = FB1L484 # FB1L489 & !FB1_m_state[6] & !FB1L432;
FB1_m_addr[2] = DFFEAS(FB1_m_addr[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_addr[1] is std_1s10:inst|sdram:the_sdram|m_addr[1]
--operation mode is normal
FB1_m_addr[1]_lut_out = FB1L491 # FB1L496 & !FB1_m_state[6] & !FB1L432;
FB1_m_addr[1] = DFFEAS(FB1_m_addr[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_addr[0] is std_1s10:inst|sdram:the_sdram|m_addr[0]
--operation mode is normal
FB1_m_addr[0]_lut_out = FB1L498 # FB1L503 & !FB1_m_state[6] & !FB1L432;
FB1_m_addr[0] = DFFEAS(FB1_m_addr[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_bank[1] is std_1s10:inst|sdram:the_sdram|m_bank[1]
--operation mode is normal
FB1_m_bank[1]_lut_out = FB1L506 & (FB1L511 & FB1L505 # !FB1L511 & (FB1_m_bank[1])) # !FB1L506 & (FB1_m_bank[1]);
FB1_m_bank[1] = DFFEAS(FB1_m_bank[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_bank[0] is std_1s10:inst|sdram:the_sdram|m_bank[0]
--operation mode is normal
FB1_m_bank[0]_lut_out = FB1L506 & (FB1L511 & FB1L507 # !FB1L511 & (FB1_m_bank[0])) # !FB1L506 & (FB1_m_bank[0]);
FB1_m_bank[0] = DFFEAS(FB1_m_bank[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_dqm[3] is std_1s10:inst|sdram:the_sdram|m_dqm[3]
--operation mode is normal
FB1_m_dqm[3]_lut_out = FB1L506 & (FB1L511 & FB1L543 # !FB1L511 & (FB1_m_dqm[3])) # !FB1L506 & (FB1_m_dqm[3]);
FB1_m_dqm[3] = DFFEAS(FB1_m_dqm[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_dqm[2] is std_1s10:inst|sdram:the_sdram|m_dqm[2]
--operation mode is normal
FB1_m_dqm[2]_lut_out = FB1L506 & (FB1L511 & FB1L544 # !FB1L511 & (FB1_m_dqm[2])) # !FB1L506 & (FB1_m_dqm[2]);
FB1_m_dqm[2] = DFFEAS(FB1_m_dqm[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_dqm[1] is std_1s10:inst|sdram:the_sdram|m_dqm[1]
--operation mode is normal
FB1_m_dqm[1]_lut_out = FB1L506 & (FB1L511 & FB1L545 # !FB1L511 & (FB1_m_dqm[1])) # !FB1L506 & (FB1_m_dqm[1]);
FB1_m_dqm[1] = DFFEAS(FB1_m_dqm[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_dqm[0] is std_1s10:inst|sdram:the_sdram|m_dqm[0]
--operation mode is normal
FB1_m_dqm[0]_lut_out = FB1L506 & (FB1L511 & FB1L546 # !FB1L511 & (FB1_m_dqm[0])) # !FB1L506 & (FB1_m_dqm[0]);
FB1_m_dqm[0] = DFFEAS(FB1_m_dqm[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--A1L7 is altera_internal_jtag~TDO
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);
--A1L8 is altera_internal_jtag~TMSUTAP
A1L8 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);
--A1L6 is altera_internal_jtag~TCKUTAP
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);
--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);
--A1L5 is altera_internal_jtag~SHIFTUSER
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);
--A1L9 is altera_internal_jtag~UPDATEUSER
A1L9 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);
--A1L4 is altera_internal_jtag~RUNIDLEUSER
A1L4 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);
--L1_internal_i_read is std_1s10:inst|cpu:the_cpu|internal_i_read
--operation mode is normal
L1_internal_i_read = AMPP_FUNCTION(DE1__clk0, L1_internal_i_read, L1_ic_fill_ap_cnt[3], N1L114, L1_D_ic_fill_starting, E1_data_out);
--L1_ic_fill_tag[11] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[11]
--operation mode is normal
L1_ic_fill_tag[11] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[21], E1_data_out, L1_D_ic_fill_starting);
--L1_ic_fill_tag[8] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[8]
--operation mode is normal
L1_ic_fill_tag[8] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[18], E1_data_out, L1_D_ic_fill_starting);
--L1_ic_fill_tag[9] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[9]
--operation mode is normal
L1_ic_fill_tag[9] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[19], E1_data_out, L1_D_ic_fill_starting);
--L1_ic_fill_tag[10] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[10]
--operation mode is normal
L1_ic_fill_tag[10] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[20], E1_data_out, L1_D_ic_fill_starting);
--Q1L131 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal3~112
--operation mode is normal
Q1L131 = L1_ic_fill_tag[11] & !L1_ic_fill_tag[8] & !L1_ic_fill_tag[9] & !L1_ic_fill_tag[10];
--L1_ic_fill_tag[12] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[12]
--operation mode is normal
L1_ic_fill_tag[12] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[22], E1_data_out, L1_D_ic_fill_starting);
--L1_ic_fill_tag[5] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[5]
--operation mode is normal
L1_ic_fill_tag[5] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[15], E1_data_out, L1_D_ic_fill_starting);
--L1_ic_fill_tag[6] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[6]
--operation mode is normal
L1_ic_fill_tag[6] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[16], E1_data_out, L1_D_ic_fill_starting);
--L1_ic_fill_tag[7] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[7]
--operation mode is normal
L1_ic_fill_tag[7] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[17], E1_data_out, L1_D_ic_fill_starting);
--Q1L132 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal3~113
--operation mode is normal
Q1L132 = !L1_ic_fill_tag[12] & !L1_ic_fill_tag[5] & !L1_ic_fill_tag[6] & !L1_ic_fill_tag[7];
--L1_ic_fill_tag[4] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[4]
--operation mode is normal
L1_ic_fill_tag[4] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[14], E1_data_out, L1_D_ic_fill_starting);
--L1_ic_fill_tag[13] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[13]
--operation mode is normal
L1_ic_fill_tag[13] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[23], E1_data_out, L1_D_ic_fill_starting);
--Q1L133 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal3~114
--operation mode is normal
Q1L133 = Q1L131 & Q1L132 & !L1_ic_fill_tag[4] & !L1_ic_fill_tag[13];
--Q1L243 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_in_a_read_cycle~50
--operation mode is normal
Q1L243 = L1_internal_i_read & Q1L133;
--Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable_lut_out = Q1L291 & (Q1L192 & Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable # !Q1L192 & (Q1L203)) # !Q1L291 & Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable;
Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable = DFFEAS(Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1
--operation mode is normal
Q1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1_lut_out = Q1_cpu_data_master_requests_ext_ram_s1 & (Q1L1 # Q1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1 & !Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);
Q1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1 = DFFEAS(Q1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L73 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_ram_s1~274
--operation mode is normal
Q1L73 = L1_M_alu_result[25] & !L1_M_alu_result[22] & !L1_M_alu_result[21] & !L1_M_alu_result[20];
--Q1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1
--operation mode is normal
Q1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1_lut_out = Q1_cpu_data_master_requests_ext_flash_s1 & (Q1L178 # Q1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1 & !Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);
Q1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1 = DFFEAS(Q1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_cpu_data_master_requests_ext_flash_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_flash_s1
--operation mode is normal
Q1_cpu_data_master_requests_ext_flash_s1 = QB1L4 & !L1_M_alu_result[24] & !L1_M_alu_result[25] & !L1_M_alu_result[23];
--Q1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1
--operation mode is normal
Q1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1_lut_out = Q1_cpu_data_master_requests_lan91c111_s1 & (Q1L174 # Q1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1 & !Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);
Q1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1 = DFFEAS(Q1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L75 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1~271
--operation mode is normal
Q1L75 = L1_M_alu_result[23] & (!L1_M_alu_result[25] & !L1_M_alu_result[20]);
--Q1_cpu_data_master_requests_lan91c111_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1
--operation mode is normal
Q1_cpu_data_master_requests_lan91c111_s1 = AB1L6 & AB1L7 & Q1L75 & AB1L9;
--Q1L44 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~108
--operation mode is normal
Q1L44 = Q1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1 & (Q1_cpu_data_master_requests_ext_flash_s1 # Q1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1 & Q1_cpu_data_master_requests_lan91c111_s1) # !Q1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1 & (Q1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1 & Q1_cpu_data_master_requests_lan91c111_s1);
--Q1L45 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~109
--operation mode is normal
Q1L45 = Q1L44 # Q1L71 & Q1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1 & Q1L73;
--GE1_fifo_contains_ones_n is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n
--operation mode is normal
GE1_fifo_contains_ones_n_lut_out = GE1L2 # GE1L3 # GE1L4 # GE1L6;
GE1_fifo_contains_ones_n = DFFEAS(GE1_fifo_contains_ones_n_lut_out, DE1__clk0, E1_data_out, , GE1L27, , , , );
--N1_internal_cpu_instruction_master_latency_counter[0] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0]
--operation mode is normal
N1_internal_cpu_instruction_master_latency_counter[0]_lut_out = N1L153 & AB1L16 # !N1L153 & (N1_internal_cpu_instruction_master_latency_counter[1] & !N1_internal_cpu_instruction_master_latency_counter[0]);
N1_internal_cpu_instruction_master_latency_counter[0] = DFFEAS(N1_internal_cpu_instruction_master_latency_counter[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--N1_internal_cpu_instruction_master_latency_counter[1] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[1]
--operation mode is normal
N1_internal_cpu_instruction_master_latency_counter[1]_lut_out = N1L153 & N1L152 # !N1L153 & (N1_internal_cpu_instruction_master_latency_counter[0] & N1_internal_cpu_instruction_master_latency_counter[1]);
N1_internal_cpu_instruction_master_latency_counter[1] = DFFEAS(N1_internal_cpu_instruction_master_latency_counter[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L204 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_cpu_instruction_master_qualified_request_ext_ram_s1~90
--operation mode is normal
Q1L204 = L1_internal_i_read & (GE1_fifo_contains_ones_n # N1_internal_cpu_instruction_master_latency_counter[0] & N1_internal_cpu_instruction_master_latency_counter[1]);
--Q1L244 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_in_a_read_cycle~51
--operation mode is normal
Q1L244 = Q1L243 & !Q1L204 & (!Q1L45 # !Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable);
--Q1L4 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~352
--operation mode is arithmetic
Q1L4 = Q1_ext_ram_bus_avalon_slave_arb_addend[0] $ Q1L244;
--Q1L5 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~353
--operation mode is arithmetic
Q1L5 = CARRY(!Q1_ext_ram_bus_avalon_slave_arb_addend[0] & !Q1L244);
--Q1L6 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~354
--operation mode is arithmetic
Q1L6 = Q1L6_carry_eqn $ (!Q1L205 & Q1L243);
--Q1L7 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~355
--operation mode is arithmetic
Q1L7 = CARRY(!Q1L25 & (Q1L205 # !Q1L243));
--Q1L82 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_granted_lan91c111_s1~66
--operation mode is normal
Q1L82 = Q1L244 & (Q1L4 # Q1L6);
--Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0]
--operation mode is normal
Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0]_lut_out = L1_internal_d_read & Q1L48 & Q1L93;
Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] = DFFEAS(Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1]
--operation mode is normal
Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1]_lut_out = Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0];
Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1] = DFFEAS(Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L57 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~69
--operation mode is normal
Q1L57 = Q1_cpu_data_master_requests_lan91c111_s1 & (!Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] & !Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1] # !L1_internal_d_read);
--Q1L284 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~37
--operation mode is normal
Q1L284 = !L1_ic_fill_tag[8] & !L1_ic_fill_tag[9] & !L1_ic_fill_tag[10];
--Q1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1
--operation mode is normal
Q1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1_lut_out = Q1L286 & (Q1L180 # Q1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1 & !Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);
Q1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1 = DFFEAS(Q1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1_lut_out, DE1__clk0, E1_data_out, , , , , , );
--AB1L13 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_requests_onchip_ram_64_kbytes_s1~48
--operation mode is normal
AB1L13 = L1_internal_i_read & L1_ic_fill_tag[13] & !L1_ic_fill_tag[11] & !L1_ic_fill_tag[12];
--Q1L78 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~3
--operation mode is normal
Q1L78 = Q1L284 & Q1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1 & AB1L13;
--Q1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1
--operation mode is normal
Q1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1_lut_out = Q1L243 & (Q1L172 # Q1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1 & !Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);
Q1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1 = DFFEAS(Q1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L79 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~54
--operation mode is normal
Q1L79 = Q1L78 # L1_internal_i_read & Q1L133 & Q1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1;
--Q1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1
--operation mode is normal
Q1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1_lut_out = Q1L94 & (Q1L176 # Q1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 & !Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);
Q1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 = DFFEAS(Q1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L94 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_requests_ext_flash_s1~26
--operation mode is normal
Q1L94 = L1_internal_i_read & !L1_ic_fill_tag[11] & !L1_ic_fill_tag[13] & !L1_ic_fill_tag[12];
--Q1L77 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~1
--operation mode is normal
Q1L77 = Q1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 & Q1L94;
--Q1L58 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~70
--operation mode is normal
Q1L58 = Q1L57 & (!Q1_cpu_instruction_master_arbiterlock);
--Q1L8 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~356
--operation mode is arithmetic
Q1L8 = Q1_ext_ram_bus_avalon_slave_arb_addend[1] $ Q1L58 $ !Q1L8_carry_eqn;
--Q1L9 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~357
--operation mode is arithmetic
Q1L9 = CARRY(Q1_ext_ram_bus_avalon_slave_arb_addend[1] & Q1L58 & !Q1L5 # !Q1_ext_ram_bus_avalon_slave_arb_addend[1] & (Q1L58 # !Q1L5));
--Q1L10 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~358
--operation mode is arithmetic
Q1L10 = Q1L58 $ (!Q1L10_carry_eqn);
--Q1L11 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~359
--operation mode is arithmetic
--Q1_d1_ext_ram_bus_avalon_slave_end_xfer is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer
--operation mode is normal
Q1_d1_ext_ram_bus_avalon_slave_end_xfer_lut_out = Q1L192;
Q1_d1_ext_ram_bus_avalon_slave_end_xfer = DFFEAS(Q1_d1_ext_ram_bus_avalon_slave_end_xfer_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1]
--operation mode is normal
Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1]_lut_out = Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0];
Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] = DFFEAS(Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0]
--operation mode is normal
Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0]_lut_out = Q1L134 & Q1L63 & (Q1_d1_ext_ram_bus_avalon_slave_end_xfer # Q1L190);
Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] = DFFEAS(Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L49 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~143
--operation mode is normal
Q1L49 = !Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] & !Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] # !L1_internal_d_read;
--M1_internal_cpu_data_master_dbs_address[1] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1]
--operation mode is normal
M1_internal_cpu_data_master_dbs_address[1]_lut_out = M1_internal_cpu_data_master_dbs_address[1] $ (Q1_cpu_data_master_requests_ext_flash_s1 & M1_internal_cpu_data_master_dbs_address[0] & M1L307);
M1_internal_cpu_data_master_dbs_address[1] = DFFEAS(M1_internal_cpu_data_master_dbs_address[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--L1_M_mem_byte_en[3] is std_1s10:inst|cpu:the_cpu|M_mem_byte_en[3]
--operation mode is normal
L1_M_mem_byte_en[3] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[4], HC1_result[1], HC1_result[0], L1_E_iw[3], E1_data_out, L1_W_stall);
--L1_M_mem_byte_en[2] is std_1s10:inst|cpu:the_cpu|M_mem_byte_en[2]
--operation mode is normal
L1_M_mem_byte_en[2] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[4], HC1_result[1], L1_E_iw[3], HC1_result[0], E1_data_out, L1_W_stall);
--M1_internal_cpu_data_master_dbs_address[0] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[0]
--operation mode is normal
M1_internal_cpu_data_master_dbs_address[0]_lut_out = M1_internal_cpu_data_master_dbs_address[0] $ (Q1_cpu_data_master_requests_ext_flash_s1 & M1L307);
M1_internal_cpu_data_master_dbs_address[0] = DFFEAS(M1_internal_cpu_data_master_dbs_address[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L42 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_byteenable_ext_flash_s1~310
--operation mode is normal
Q1L42 = M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & L1_M_mem_byte_en[3] # !M1_internal_cpu_data_master_dbs_address[0] & (L1_M_mem_byte_en[2]));
--L1_M_mem_byte_en[1] is std_1s10:inst|cpu:the_cpu|M_mem_byte_en[1]
--operation mode is normal
L1_M_mem_byte_en[1] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[4], HC1_result[0], L1_E_iw[3], HC1_result[1], E1_data_out, L1_W_stall);
--Q1L43 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_byteenable_ext_flash_s1~311
--operation mode is normal
Q1L43 = !M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & L1_M_mem_byte_en[1] # !M1_internal_cpu_data_master_dbs_address[0] & (L1_M_mem_byte_en[0]));
--M1_internal_cpu_data_master_no_byte_enables_and_last_term is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_no_byte_enables_and_last_term
--operation mode is normal
M1_internal_cpu_data_master_no_byte_enables_and_last_term_lut_out = L1_internal_d_write & M1_internal_cpu_data_master_dbs_address[1] & M1_internal_cpu_data_master_dbs_address[0] & !L1_M_mem_byte_en[3];
M1_internal_cpu_data_master_no_byte_enables_and_last_term = DFFEAS(M1_internal_cpu_data_master_no_byte_enables_and_last_term_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L50 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~144
--operation mode is normal
Q1L50 = !M1_internal_cpu_data_master_no_byte_enables_and_last_term & (Q1L42 # Q1L43);
--Q1L51 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~145
--operation mode is normal
Q1L51 = Q1_cpu_data_master_requests_ext_flash_s1 & Q1L49 & (Q1L50 # !L1_internal_d_write);
--Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1]
--operation mode is normal
Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1]_lut_out = Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0];
Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] = DFFEAS(Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]
--operation mode is normal
Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]_lut_out = L1_internal_d_read & Q1L47 & !Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0];
Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] = DFFEAS(Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L53 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~127
--operation mode is normal
Q1L53 = !Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] # !L1_internal_d_read;
--M1_internal_cpu_data_master_waitrequest is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest
--operation mode is normal
M1_internal_cpu_data_master_waitrequest_lut_out = !M1L3 & !M1L8 & !M1L9 & !M1L17;
M1_internal_cpu_data_master_waitrequest = DFFEAS(M1_internal_cpu_data_master_waitrequest_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L54 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~128
--operation mode is normal
Q1L54 = !Q1_write_n_to_the_ext_ram_local & !M1_internal_cpu_data_master_waitrequest # !L1_internal_d_write;
--Q1L55 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~129
--operation mode is normal
Q1L55 = Q1L71 & Q1L73 & Q1L53 & Q1L54;
--M1L1 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1042
--operation mode is normal
M1L1 = Q1_cpu_instruction_master_arbiterlock # !Q1L57 & !Q1L51 & !Q1L55;
--Q1L285 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~38
--operation mode is normal
Q1L285 = Q1L286 & !Q1L204 & (!Q1L45 # !Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable);
--N1L146 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]~36
--operation mode is normal
N1L146 = Q1L94 & !Q1L204 & (!Q1L45 # !Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable);
--Q1L190 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_begins_xfer~52
--operation mode is normal
Q1L190 = M1L1 & !Q1L244 & !Q1L285 & !N1L146;
--Q1_ext_ram_bus_avalon_slave_begins_xfer is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_begins_xfer
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_begins_xfer = !Q1_d1_ext_ram_bus_avalon_slave_end_xfer & !Q1L190;
--E1_data_out is std_1s10:inst|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch|data_out
--operation mode is normal
E1_data_out_lut_out = E1_data_in_d1;
E1_data_out = DFFEAS(E1_data_out_lut_out, DE1__clk0, !B1L1, , , , , , );
--Q1L52 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~146
--operation mode is normal
Q1L52 = Q1L51 & (!Q1L79 & !Q1L77 # !Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable);
--Q1L12 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~360
--operation mode is arithmetic
Q1L12 = Q1_ext_ram_bus_avalon_slave_arb_addend[3] $ Q1L52 $ !Q1L12_carry_eqn;
--Q1L13 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~361
--operation mode is arithmetic
Q1L13 = CARRY(Q1_ext_ram_bus_avalon_slave_arb_addend[3] & Q1L52 & !Q1L17 # !Q1_ext_ram_bus_avalon_slave_arb_addend[3] & (Q1L52 # !Q1L17));
--Q1L14 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~362
--operation mode is arithmetic
Q1L14 = Q1L52 $ (!Q1L14_carry_eqn);
--Q1L15 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~363
--operation mode is arithmetic
Q1L15 = CARRY(Q1L52 # !Q1L19);
--Q1L136 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_counter_load_value[1]~149
--operation mode is normal
Q1L136 = L1_internal_d_write & Q1L52 & (Q1L12 # Q1L14);
--Q1_ext_flash_s1_wait_counter[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3]
--operation mode is normal
Q1_ext_flash_s1_wait_counter[3]_lut_out = Q1L138 # Q1_ext_flash_s1_wait_counter[3] & (Q1_ext_flash_s1_wait_counter[0] # !Q1L288);
Q1_ext_flash_s1_wait_counter[3] = DFFEAS(Q1_ext_flash_s1_wait_counter[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_flash_s1_wait_counter[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[2]
--operation mode is normal
Q1_ext_flash_s1_wait_counter[2]_lut_out = !Q1L134 & !Q1L138 & (Q1_ext_flash_s1_wait_counter[2] $ !Q1L31);
Q1_ext_flash_s1_wait_counter[2] = DFFEAS(Q1_ext_flash_s1_wait_counter[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_ext_flash_s1_wait_counter[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[1]
--operation mode is normal
Q1_ext_flash_s1_wait_counter[1]_lut_out = Q1_ext_ram_bus_avalon_slave_begins_xfer & !Q1_ext_flash_s1_in_a_read_cycle & (Q1L137 # Q1L136) # !Q1_ext_ram_bus_avalon_slave_begins_xfer & Q1L137;
Q1_ext_flash_s1_wait_counter[1] = DFFEAS(Q1_ext_flash_s1_wait_counter[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L288 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_write_n_to_the_ext_flash~108
--operation mode is normal
Q1L288 = !Q1_ext_flash_s1_wait_counter[2] & !Q1_ext_flash_s1_wait_counter[1];
--Q1_lan91c111_s1_wait_counter[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[0]
--operation mode is normal
Q1_lan91c111_s1_wait_counter[0]_lut_out = Q1L242 # Q1L256 & !Q1_lan91c111_s1_wait_counter[0] & !Q1L2;
Q1_lan91c111_s1_wait_counter[0] = DFFEAS(Q1_lan91c111_s1_wait_counter[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_lan91c111_s1_wait_counter[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[3]
--operation mode is normal
Q1_lan91c111_s1_wait_counter[3]_lut_out = Q1L29 # Q1_ext_ram_bus_avalon_slave_begins_xfer & (Q1L82 # Q1L193);
Q1_lan91c111_s1_wait_counter[3] = DFFEAS(Q1_lan91c111_s1_wait_counter[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_lan91c111_s1_wait_counter[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[2]
--operation mode is normal
Q1_lan91c111_s1_wait_counter[2]_lut_out = !Q1L241 & Q1L256 & (Q1_lan91c111_s1_wait_counter[2] $ Q1L30);
Q1_lan91c111_s1_wait_counter[2] = DFFEAS(Q1_lan91c111_s1_wait_counter[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_lan91c111_s1_wait_counter[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[1]
--operation mode is normal
Q1_lan91c111_s1_wait_counter[1]_lut_out = !Q1L241 & Q1L256 & (Q1_lan91c111_s1_wait_counter[0] $ !Q1_lan91c111_s1_wait_counter[1]);
Q1_lan91c111_s1_wait_counter[1] = DFFEAS(Q1_lan91c111_s1_wait_counter[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L256 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|LessThan1~82
--operation mode is normal
Q1L256 = Q1_lan91c111_s1_wait_counter[0] # Q1_lan91c111_s1_wait_counter[3] # Q1_lan91c111_s1_wait_counter[2] # Q1_lan91c111_s1_wait_counter[1];
--Q1L63 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register_in~13
--operation mode is normal
Q1L63 = L1_internal_d_read & Q1L52 & (Q1L12 # Q1L14);
--Q1L16 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~364
--operation mode is arithmetic
Q1L16 = Q1_ext_ram_bus_avalon_slave_arb_addend[2] $ N1L146 $ Q1L16_carry_eqn;
--Q1L17 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~365
--operation mode is arithmetic
Q1L17 = CARRY(Q1_ext_ram_bus_avalon_slave_arb_addend[2] & (!Q1L9 # !N1L146) # !Q1_ext_ram_bus_avalon_slave_arb_addend[2] & !N1L146 & !Q1L9);
--Q1L18 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~366
--operation mode is arithmetic
Q1L18 = Q1L18_carry_eqn $ (!Q1L205 & Q1L94);
--Q1L19 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~367
--operation mode is arithmetic
Q1L19 = CARRY(!Q1L11 & (Q1L205 # !Q1L94));
--Q1L80 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_granted_ext_flash_s1~38
--operation mode is normal
Q1L80 = N1L146 & (Q1L16 # Q1L18);
--Q1L20 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~368
--operation mode is arithmetic
Q1L20 = Q1_ext_ram_bus_avalon_slave_arb_addend[4] $ Q1L285 $ Q1L20_carry_eqn;
--Q1L21 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~369
--operation mode is arithmetic
Q1L21 = CARRY(Q1_ext_ram_bus_avalon_slave_arb_addend[4] & (!Q1L13 # !Q1L285) # !Q1_ext_ram_bus_avalon_slave_arb_addend[4] & !Q1L285 & !Q1L13);
--Q1L22 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~370
--operation mode is arithmetic
Q1L22 = Q1L22_carry_eqn $ (Q1L286 & !Q1L205);
--Q1L23 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~371
--operation mode is arithmetic
Q1L23 = CARRY(!Q1L15 & (Q1L205 # !Q1L286));
--Q1L81 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_granted_ext_ram_s1~31
--operation mode is normal
Q1L81 = Q1L285 & (Q1L20 # Q1L22);
--Q1L56 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~130
--operation mode is normal
Q1L56 = Q1L55 & (!Q1L79 & !Q1L77 # !Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable);
--Q1L24 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~372
--operation mode is arithmetic
Q1L24 = Q1_ext_ram_bus_avalon_slave_arb_addend[5] $ Q1L56 $ !Q1L24_carry_eqn;
--Q1L25 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~373
--operation mode is arithmetic
Q1L25 = CARRY(Q1_ext_ram_bus_avalon_slave_arb_addend[5] & Q1L56 & !Q1L21 # !Q1_ext_ram_bus_avalon_slave_arb_addend[5] & (Q1L56 # !Q1L21));
--Q1L26 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~374
--operation mode is normal
Q1L26 = Q1L56 $ (!Q1L26_carry_eqn);
--Q1L47 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_ext_ram_s1~76
--operation mode is normal
Q1L47 = Q1L56 & (Q1L24 # Q1L26);
--FB1_m_state[6] is std_1s10:inst|sdram:the_sdram|m_state[6]
--operation mode is normal
FB1_m_state[6]_lut_out = FB1L279 # FB1L299 & (FB1L280 # FB1L283);
FB1_m_state[6] = DFFEAS(FB1_m_state[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_state[1] is std_1s10:inst|sdram:the_sdram|m_state[1]
--operation mode is normal
FB1_m_state[1]_lut_out = FB1L311 # FB1L312 & (FB1L285 # FB1L314);
FB1_m_state[1] = DFFEAS(FB1_m_state[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_state[8] is std_1s10:inst|sdram:the_sdram|m_state[8]
--operation mode is normal
FB1_m_state[8]_lut_out = FB1_m_state[8] $ (FB1L547 & FB1L275 & FB1L274);
FB1_m_state[8] = DFFEAS(FB1_m_state[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_state[5] is std_1s10:inst|sdram:the_sdram|m_state[5]
--operation mode is normal
FB1_m_state[5]_lut_out = FB1L287 # FB1L284 & (FB1L285 # FB1L288);
FB1_m_state[5] = DFFEAS(FB1_m_state[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_state[2] is std_1s10:inst|sdram:the_sdram|m_state[2]
--operation mode is normal
FB1_m_state[2]_lut_out = FB1L300 # FB1L301 & (FB1L305 # FB1L308);
FB1_m_state[2] = DFFEAS(FB1_m_state[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1L424 is std_1s10:inst|sdram:the_sdram|Mux104~1565
--operation mode is normal
FB1L424 = !FB1_m_state[8] & !FB1_m_state[5] & !FB1_m_state[2];
--FB1L262 is std_1s10:inst|sdram:the_sdram|Mux19~1734
--operation mode is normal
FB1L262 = FB1_m_state[6] # FB1_m_state[1] # !FB1L424;
--FB1_m_state[7] is std_1s10:inst|sdram:the_sdram|m_state[7]
--operation mode is normal
FB1_m_state[7]_lut_out = FB1L277 # FB1_m_state[7] & (!FB1L257 # !FB1L256);
FB1_m_state[7] = DFFEAS(FB1_m_state[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_state[4] is std_1s10:inst|sdram:the_sdram|m_state[4]
--operation mode is normal
FB1_m_state[4]_lut_out = FB1L289 # FB1L547 & FB1L293 & FB1L365;
FB1_m_state[4] = DFFEAS(FB1_m_state[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_state[3] is std_1s10:inst|sdram:the_sdram|m_state[3]
--operation mode is normal
FB1_m_state[3]_lut_out = FB1L295 # FB1L547 & FB1L296 & FB1L297;
FB1_m_state[3] = DFFEAS(FB1_m_state[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_state[0] is std_1s10:inst|sdram:the_sdram|m_state[0]
--operation mode is normal
FB1_m_state[0]_lut_out = !FB1L315 & (FB1_m_state[0] # !FB1L574 & FB1L30);
FB1_m_state[0] = DFFEAS(FB1_m_state[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1L263 is std_1s10:inst|sdram:the_sdram|Mux19~1735
--operation mode is normal
FB1L263 = FB1_m_state[0] & (!FB1_m_state[4] & !FB1_m_state[3] # !FB1_m_state[7]);
--FB1_f_pop is std_1s10:inst|sdram:the_sdram|f_pop
--operation mode is normal
FB1_f_pop_lut_out = FB1L392 & (FB1L394 # FB1L304 & FB1_m_state[0]);
FB1_f_pop = DFFEAS(FB1_f_pop_lut_out, DE1__clk0, E1_data_out, , , , , , );
--EE1_rd_address is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_address
--operation mode is normal
EE1_rd_address_lut_out = EE1_rd_address $ (!FB1L554 & FB1_f_pop & EE1L127);
EE1_rd_address = DFFEAS(EE1_rd_address_lut_out, DE1__clk0, E1_data_out, , , , , , );
--EE1_entry_0[45] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[45]
--operation mode is normal
EE1_entry_0[45]_lut_out = GB1L39;
EE1_entry_0[45] = DFFEAS(EE1_entry_0[45]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[45] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[45]
--operation mode is normal
EE1_entry_1[45]_lut_out = GB1L39;
EE1_entry_1[45] = DFFEAS(EE1_entry_1[45]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_addr[9] is std_1s10:inst|sdram:the_sdram|active_addr[9]
--operation mode is normal
FB1_active_addr[9]_lut_out = E1_data_out & (FB1L395 & FB1L422 # !FB1L395 & (FB1_active_addr[9])) # !E1_data_out & (FB1_active_addr[9]);
FB1_active_addr[9] = DFFEAS(FB1_active_addr[9]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L106 is std_1s10:inst|sdram:the_sdram|Equal4~447
--operation mode is normal
FB1L106 = FB1_active_addr[9] $ (EE1_rd_address & (EE1_entry_1[45]) # !EE1_rd_address & EE1_entry_0[45]);
--EE1_entry_0[44] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[44]
--operation mode is normal
EE1_entry_0[44]_lut_out = GB1L38;
EE1_entry_0[44] = DFFEAS(EE1_entry_0[44]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[44] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[44]
--operation mode is normal
EE1_entry_1[44]_lut_out = GB1L38;
EE1_entry_1[44] = DFFEAS(EE1_entry_1[44]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_addr[8] is std_1s10:inst|sdram:the_sdram|active_addr[8]
--operation mode is normal
FB1_active_addr[8]_lut_out = FB1L12 & (FB1L14 & (EE1L173) # !FB1L14 & FB1_active_addr[8]) # !FB1L12 & FB1_active_addr[8];
FB1_active_addr[8] = DFFEAS(FB1_active_addr[8]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L104 is std_1s10:inst|sdram:the_sdram|Equal3~74
--operation mode is normal
FB1L104 = FB1_active_addr[8] $ (EE1_rd_address & (EE1_entry_1[44]) # !EE1_rd_address & EE1_entry_0[44]);
--EE1_entry_0[50] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[50]
--operation mode is normal
EE1_entry_0[50]_lut_out = GB1L44;
EE1_entry_0[50] = DFFEAS(EE1_entry_0[50]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[50] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[50]
--operation mode is normal
EE1_entry_1[50]_lut_out = GB1L44;
EE1_entry_1[50] = DFFEAS(EE1_entry_1[50]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_addr[14] is std_1s10:inst|sdram:the_sdram|active_addr[14]
--operation mode is normal
FB1_active_addr[14]_lut_out = E1_data_out & (FB1L395 & FB1L410 # !FB1L395 & (FB1_active_addr[14])) # !E1_data_out & (FB1_active_addr[14]);
FB1_active_addr[14] = DFFEAS(FB1_active_addr[14]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L107 is std_1s10:inst|sdram:the_sdram|Equal4~448
--operation mode is normal
FB1L107 = FB1_active_addr[14] $ (EE1_rd_address & (EE1_entry_1[50]) # !EE1_rd_address & EE1_entry_0[50]);
--EE1_entry_0[49] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[49]
--operation mode is normal
EE1_entry_0[49]_lut_out = GB1L43;
EE1_entry_0[49] = DFFEAS(EE1_entry_0[49]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[49] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[49]
--operation mode is normal
EE1_entry_1[49]_lut_out = GB1L43;
EE1_entry_1[49] = DFFEAS(EE1_entry_1[49]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_addr[13] is std_1s10:inst|sdram:the_sdram|active_addr[13]
--operation mode is normal
FB1_active_addr[13]_lut_out = E1_data_out & (FB1L395 & FB1L412 # !FB1L395 & (FB1_active_addr[13])) # !E1_data_out & (FB1_active_addr[13]);
FB1_active_addr[13] = DFFEAS(FB1_active_addr[13]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L108 is std_1s10:inst|sdram:the_sdram|Equal4~449
--operation mode is normal
FB1L108 = FB1_active_addr[13] $ (EE1_rd_address & (EE1_entry_1[49]) # !EE1_rd_address & EE1_entry_0[49]);
--FB1L550 is std_1s10:inst|sdram:the_sdram|pending~245
--operation mode is normal
FB1L550 = FB1L106 # FB1L104 # FB1L107 # FB1L108;
--EE1_entry_0[47] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[47]
--operation mode is normal
EE1_entry_0[47]_lut_out = GB1L41;
EE1_entry_0[47] = DFFEAS(EE1_entry_0[47]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[47] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[47]
--operation mode is normal
EE1_entry_1[47]_lut_out = GB1L41;
EE1_entry_1[47] = DFFEAS(EE1_entry_1[47]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_addr[11] is std_1s10:inst|sdram:the_sdram|active_addr[11]
--operation mode is normal
FB1_active_addr[11]_lut_out = E1_data_out & (FB1L395 & FB1L416 # !FB1L395 & (FB1_active_addr[11])) # !E1_data_out & (FB1_active_addr[11]);
FB1_active_addr[11] = DFFEAS(FB1_active_addr[11]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L109 is std_1s10:inst|sdram:the_sdram|Equal4~450
--operation mode is normal
FB1L109 = FB1_active_addr[11] $ (EE1_rd_address & (EE1_entry_1[47]) # !EE1_rd_address & EE1_entry_0[47]);
--EE1_entry_0[57] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[57]
--operation mode is normal
EE1_entry_0[57]_lut_out = GB1L51;
EE1_entry_0[57] = DFFEAS(EE1_entry_0[57]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[57] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[57]
--operation mode is normal
EE1_entry_1[57]_lut_out = GB1L51;
EE1_entry_1[57] = DFFEAS(EE1_entry_1[57]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_addr[21] is std_1s10:inst|sdram:the_sdram|active_addr[21]
--operation mode is normal
FB1_active_addr[21]_lut_out = FB1L12 & (FB1L14 & (EE1L174) # !FB1L14 & FB1_active_addr[21]) # !FB1L12 & FB1_active_addr[21];
FB1_active_addr[21] = DFFEAS(FB1_active_addr[21]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L105 is std_1s10:inst|sdram:the_sdram|Equal3~75
--operation mode is normal
FB1L105 = FB1_active_addr[21] $ (EE1_rd_address & (EE1_entry_1[57]) # !EE1_rd_address & EE1_entry_0[57]);
--EE1_entry_0[52] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[52]
--operation mode is normal
EE1_entry_0[52]_lut_out = GB1L46;
EE1_entry_0[52] = DFFEAS(EE1_entry_0[52]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[52] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[52]
--operation mode is normal
EE1_entry_1[52]_lut_out = GB1L46;
EE1_entry_1[52] = DFFEAS(EE1_entry_1[52]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_addr[16] is std_1s10:inst|sdram:the_sdram|active_addr[16]
--operation mode is normal
FB1_active_addr[16]_lut_out = E1_data_out & (FB1L395 & FB1L406 # !FB1L395 & (FB1_active_addr[16])) # !E1_data_out & (FB1_active_addr[16]);
FB1_active_addr[16] = DFFEAS(FB1_active_addr[16]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L110 is std_1s10:inst|sdram:the_sdram|Equal4~451
--operation mode is normal
FB1L110 = FB1_active_addr[16] $ (EE1_rd_address & (EE1_entry_1[52]) # !EE1_rd_address & EE1_entry_0[52]);
--EE1_entry_0[51] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[51]
--operation mode is normal
EE1_entry_0[51]_lut_out = GB1L45;
EE1_entry_0[51] = DFFEAS(EE1_entry_0[51]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[51] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[51]
--operation mode is normal
EE1_entry_1[51]_lut_out = GB1L45;
EE1_entry_1[51] = DFFEAS(EE1_entry_1[51]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_addr[15] is std_1s10:inst|sdram:the_sdram|active_addr[15]
--operation mode is normal
FB1_active_addr[15]_lut_out = E1_data_out & (FB1L395 & FB1L408 # !FB1L395 & (FB1_active_addr[15])) # !E1_data_out & (FB1_active_addr[15]);
FB1_active_addr[15] = DFFEAS(FB1_active_addr[15]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L111 is std_1s10:inst|sdram:the_sdram|Equal4~452
--operation mode is normal
FB1L111 = FB1_active_addr[15] $ (EE1_rd_address & (EE1_entry_1[51]) # !EE1_rd_address & EE1_entry_0[51]);
--FB1L551 is std_1s10:inst|sdram:the_sdram|pending~246
--operation mode is normal
FB1L551 = FB1L109 # FB1L105 # FB1L110 # FB1L111;
--EE1_entry_0[53] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[53]
--operation mode is normal
EE1_entry_0[53]_lut_out = GB1L47;
EE1_entry_0[53] = DFFEAS(EE1_entry_0[53]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[53] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[53]
--operation mode is normal
EE1_entry_1[53]_lut_out = GB1L47;
EE1_entry_1[53] = DFFEAS(EE1_entry_1[53]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_addr[17] is std_1s10:inst|sdram:the_sdram|active_addr[17]
--operation mode is normal
FB1_active_addr[17]_lut_out = E1_data_out & (FB1L395 & FB1L404 # !FB1L395 & (FB1_active_addr[17])) # !E1_data_out & (FB1_active_addr[17]);
FB1_active_addr[17] = DFFEAS(FB1_active_addr[17]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L112 is std_1s10:inst|sdram:the_sdram|Equal4~453
--operation mode is normal
FB1L112 = FB1_active_addr[17] $ (EE1_rd_address & (EE1_entry_1[53]) # !EE1_rd_address & EE1_entry_0[53]);
--EE1_entry_0[46] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[46]
--operation mode is normal
EE1_entry_0[46]_lut_out = GB1L40;
EE1_entry_0[46] = DFFEAS(EE1_entry_0[46]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[46] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[46]
--operation mode is normal
EE1_entry_1[46]_lut_out = GB1L40;
EE1_entry_1[46] = DFFEAS(EE1_entry_1[46]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_addr[10] is std_1s10:inst|sdram:the_sdram|active_addr[10]
--operation mode is normal
FB1_active_addr[10]_lut_out = E1_data_out & (FB1L395 & FB1L418 # !FB1L395 & (FB1_active_addr[10])) # !E1_data_out & (FB1_active_addr[10]);
FB1_active_addr[10] = DFFEAS(FB1_active_addr[10]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L113 is std_1s10:inst|sdram:the_sdram|Equal4~454
--operation mode is normal
FB1L113 = FB1_active_addr[10] $ (EE1_rd_address & (EE1_entry_1[46]) # !EE1_rd_address & EE1_entry_0[46]);
--EE1_entry_0[58] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[58]
--operation mode is normal
EE1_entry_0[58]_lut_out = !GB1_sdram_s1_in_a_write_cycle;
EE1_entry_0[58] = DFFEAS(EE1_entry_0[58]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[58] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[58]
--operation mode is normal
EE1_entry_1[58]_lut_out = !GB1_sdram_s1_in_a_write_cycle;
EE1_entry_1[58] = DFFEAS(EE1_entry_1[58]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_rnw is std_1s10:inst|sdram:the_sdram|active_rnw
--operation mode is normal
FB1_active_rnw_lut_out = FB1L12 & (FB1L14 & (EE1L175) # !FB1L14 & FB1_active_rnw) # !FB1L12 & FB1_active_rnw;
FB1_active_rnw = DFFEAS(FB1_active_rnw_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L575 is std_1s10:inst|sdram:the_sdram|rnw_match~0
--operation mode is normal
FB1L575 = FB1_active_rnw $ (EE1_rd_address & (EE1_entry_1[58]) # !EE1_rd_address & EE1_entry_0[58]);
--EE1_entry_0[56] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56]
--operation mode is normal
EE1_entry_0[56]_lut_out = GB1L50;
EE1_entry_0[56] = DFFEAS(EE1_entry_0[56]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[56] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[56]
--operation mode is normal
EE1_entry_1[56]_lut_out = GB1L50;
EE1_entry_1[56] = DFFEAS(EE1_entry_1[56]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_addr[20] is std_1s10:inst|sdram:the_sdram|active_addr[20]
--operation mode is normal
FB1_active_addr[20]_lut_out = E1_data_out & (FB1L395 & FB1L398 # !FB1L395 & (FB1_active_addr[20])) # !E1_data_out & (FB1_active_addr[20]);
FB1_active_addr[20] = DFFEAS(FB1_active_addr[20]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L114 is std_1s10:inst|sdram:the_sdram|Equal4~455
--operation mode is normal
FB1L114 = FB1_active_addr[20] $ (EE1_rd_address & (EE1_entry_1[56]) # !EE1_rd_address & EE1_entry_0[56]);
--FB1L552 is std_1s10:inst|sdram:the_sdram|pending~247
--operation mode is normal
FB1L552 = FB1L112 # FB1L113 # FB1L575 # FB1L114;
--EE1_entry_0[54] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[54]
--operation mode is normal
EE1_entry_0[54]_lut_out = GB1L48;
EE1_entry_0[54] = DFFEAS(EE1_entry_0[54]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[54] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[54]
--operation mode is normal
EE1_entry_1[54]_lut_out = GB1L48;
EE1_entry_1[54] = DFFEAS(EE1_entry_1[54]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_addr[18] is std_1s10:inst|sdram:the_sdram|active_addr[18]
--operation mode is normal
FB1_active_addr[18]_lut_out = E1_data_out & (FB1L395 & FB1L402 # !FB1L395 & (FB1_active_addr[18])) # !E1_data_out & (FB1_active_addr[18]);
FB1_active_addr[18] = DFFEAS(FB1_active_addr[18]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L115 is std_1s10:inst|sdram:the_sdram|Equal4~456
--operation mode is normal
FB1L115 = FB1_active_addr[18] $ (EE1_rd_address & (EE1_entry_1[54]) # !EE1_rd_address & EE1_entry_0[54]);
--EE1_entry_0[48] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[48]
--operation mode is normal
EE1_entry_0[48]_lut_out = GB1L42;
EE1_entry_0[48] = DFFEAS(EE1_entry_0[48]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[48] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[48]
--operation mode is normal
EE1_entry_1[48]_lut_out = GB1L42;
EE1_entry_1[48] = DFFEAS(EE1_entry_1[48]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_addr[12] is std_1s10:inst|sdram:the_sdram|active_addr[12]
--operation mode is normal
FB1_active_addr[12]_lut_out = E1_data_out & (FB1L395 & FB1L414 # !FB1L395 & (FB1_active_addr[12])) # !E1_data_out & (FB1_active_addr[12]);
FB1_active_addr[12] = DFFEAS(FB1_active_addr[12]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L116 is std_1s10:inst|sdram:the_sdram|Equal4~457
--operation mode is normal
FB1L116 = FB1_active_addr[12] $ (EE1_rd_address & (EE1_entry_1[48]) # !EE1_rd_address & EE1_entry_0[48]);
--FB1_active_cs_n is std_1s10:inst|sdram:the_sdram|active_cs_n
--operation mode is normal
FB1_active_cs_n_lut_out = FB1L32 & (FB1_refresh_request # FB1_active_cs_n & !EE1L127) # !FB1L32 & (FB1_active_cs_n);
FB1_active_cs_n = DFFEAS(FB1_active_cs_n_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_0[55] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[55]
--operation mode is normal
EE1_entry_0[55]_lut_out = GB1L49;
EE1_entry_0[55] = DFFEAS(EE1_entry_0[55]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1_entry_1[55] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[55]
--operation mode is normal
EE1_entry_1[55]_lut_out = GB1L49;
EE1_entry_1[55] = DFFEAS(EE1_entry_1[55]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--FB1_active_addr[19] is std_1s10:inst|sdram:the_sdram|active_addr[19]
--operation mode is normal
FB1_active_addr[19]_lut_out = E1_data_out & (FB1L395 & FB1L400 # !FB1L395 & (FB1_active_addr[19])) # !E1_data_out & (FB1_active_addr[19]);
FB1_active_addr[19] = DFFEAS(FB1_active_addr[19]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L117 is std_1s10:inst|sdram:the_sdram|Equal4~458
--operation mode is normal
FB1L117 = FB1_active_addr[19] $ (EE1_rd_address & (EE1_entry_1[55]) # !EE1_rd_address & EE1_entry_0[55]);
--FB1L553 is std_1s10:inst|sdram:the_sdram|pending~248
--operation mode is normal
FB1L553 = FB1L115 # FB1L116 # FB1_active_cs_n # FB1L117;
--FB1L554 is std_1s10:inst|sdram:the_sdram|pending~249
--operation mode is normal
FB1L554 = FB1L550 # FB1L551 # FB1L552 # FB1L553;
--EE1_entries[0] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entries[0]
--operation mode is normal
EE1_entries[0]_lut_out = FB1_f_select $ (FB1L237 & !EE1_entries[1] & !EE1_entries[0] # !FB1L237 & (EE1_entries[0]));
EE1_entries[0] = DFFEAS(EE1_entries[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--EE1_entries[1] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entries[1]
--operation mode is normal
EE1_entries[1]_lut_out = EE1_entries[0] & (EE1_entries[1] $ (!FB1_f_select & FB1L237)) # !EE1_entries[0] & (EE1_entries[1] & !FB1_f_select # !EE1_entries[1] & FB1_f_select & !FB1L237);
EE1_entries[1] = DFFEAS(EE1_entries[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--EE1L127 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|Equal1~94
--operation mode is normal
EE1L127 = EE1_entries[0] # EE1_entries[1];
--FB1L264 is std_1s10:inst|sdram:the_sdram|Mux19~1736
--operation mode is normal
FB1L264 = FB1_m_state[4] $ FB1_m_state[3];
--FB1_init_done is std_1s10:inst|sdram:the_sdram|init_done
--operation mode is normal
FB1_init_done_lut_out = FB1_init_done # FB1_i_state[0] & FB1_i_state[2] & !FB1_i_state[1];
FB1_init_done = DFFEAS(FB1_init_done_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_i_cmd[1] is std_1s10:inst|sdram:the_sdram|i_cmd[1]
--operation mode is normal
FB1_i_cmd[1]_lut_out = FB1_i_state[2] # FB1_i_state[1] & (!FB1_i_state[0]);
FB1_i_cmd[1] = DFFEAS(FB1_i_cmd[1]_lut_out, DE1__clk0, E1_data_out, , FB1L125, , , , );
--FB1L348 is std_1s10:inst|sdram:the_sdram|Mux40~1435
--operation mode is normal
FB1L348 = !FB1_m_state[4] & !FB1_m_state[3];
--FB1L265 is std_1s10:inst|sdram:the_sdram|Mux19~1737
--operation mode is normal
FB1L265 = FB1L263 & !FB1L171 & FB1L264 # !FB1L263 & (FB1L266);
--FB1_i_cmd[3] is std_1s10:inst|sdram:the_sdram|i_cmd[3]
--operation mode is normal
FB1_i_cmd[3]_lut_out = FB1_i_state[0] # FB1_i_state[2] # FB1_i_state[1];
FB1_i_cmd[3] = DFFEAS(FB1_i_cmd[3]_lut_out, DE1__clk0, E1_data_out, , FB1L125, , , , );
--FB1_refresh_request is std_1s10:inst|sdram:the_sdram|refresh_request
--operation mode is normal
FB1_refresh_request_lut_out = FB1_init_done & !FB1_ack_refresh_request & (FB1_refresh_request # FB1L103);
FB1_refresh_request = DFFEAS(FB1_refresh_request_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1L245 is std_1s10:inst|sdram:the_sdram|Mux17~1798
--operation mode is normal
FB1L245 = FB1_init_done & (!FB1_refresh_request) # !FB1_init_done & !FB1_i_cmd[3];
--FB1L246 is std_1s10:inst|sdram:the_sdram|Mux17~1799
--operation mode is normal
FB1L246 = !FB1_m_state[3] & !FB1_m_state[8] & !FB1_m_state[5] & !FB1_m_state[1];
--FB1L247 is std_1s10:inst|sdram:the_sdram|Mux17~1800
--operation mode is normal
FB1L247 = FB1_m_state[4] & (!FB1_m_state[0] # !FB1L246) # !FB1_m_state[4] & !FB1_m_state[0] & (FB1L245 # !FB1L246);
--FB1L248 is std_1s10:inst|sdram:the_sdram|Mux17~1801
--operation mode is normal
FB1L248 = FB1_m_state[5] & !FB1_m_state[1] & !FB1_m_state[8] & !FB1_m_state[3] # !FB1_m_state[5] & (FB1_m_state[1] & !FB1_m_state[8] & !FB1_m_state[3] # !FB1_m_state[1] & (FB1_m_state[8] $ FB1_m_state[3]));
--FB1L249 is std_1s10:inst|sdram:the_sdram|Mux17~1802
--operation mode is normal
FB1L249 = FB1_m_state[0] & (FB1_active_cs_n # !FB1_m_state[4] & !FB1L248);
--FB1L250 is std_1s10:inst|sdram:the_sdram|Mux17~1803
--operation mode is normal
FB1L250 = !FB1_m_state[2] & !FB1_m_state[6] & (FB1L247 # FB1L249);
--FB1L251 is std_1s10:inst|sdram:the_sdram|Mux17~1804
--operation mode is normal
FB1L251 = FB1_m_state[0] & !FB1_m_state[2] & (FB1_refresh_request # !FB1_active_cs_n);
--FB1L252 is std_1s10:inst|sdram:the_sdram|Mux17~1805
--operation mode is normal
FB1L252 = FB1_m_state[6] & (FB1_m_state[4] # !FB1L251 # !FB1L246);
--FB1_m_next[7] is std_1s10:inst|sdram:the_sdram|m_next[7]
--operation mode is normal
FB1_m_next[7]_lut_out = FB1_m_state[8] & FB1_m_next[7] & (FB1L321 # !FB1L341) # !FB1_m_state[8] & (FB1L321);
FB1_m_next[7] = DFFEAS(FB1_m_next[7]_lut_out, DE1__clk0, E1_data_out, , FB1L342, , , , );
--FB1_m_next[0] is std_1s10:inst|sdram:the_sdram|m_next[0]
--operation mode is normal
FB1_m_next[0]_lut_out = FB1_m_state[8] & FB1_m_next[0] & (FB1L347 # !FB1L341) # !FB1_m_state[8] & (!FB1L347);
FB1_m_next[0] = DFFEAS(FB1_m_next[0]_lut_out, DE1__clk0, E1_data_out, , FB1L342, , , , );
--FB1_m_next[1] is std_1s10:inst|sdram:the_sdram|m_next[1]
--operation mode is normal
FB1_m_next[1]_lut_out = FB1_m_state[8] & FB1_m_next[1] & (FB1L340 # !FB1L341) # !FB1_m_state[8] & (FB1L340);
FB1_m_next[1] = DFFEAS(FB1_m_next[1]_lut_out, DE1__clk0, E1_data_out, , FB1L342, , , , );
--FB1_m_next[3] is std_1s10:inst|sdram:the_sdram|m_next[3]
--operation mode is normal
FB1_m_next[3]_lut_out = FB1_m_state[7] & FB1_m_next[3] & (FB1L334 # !FB1L448) # !FB1_m_state[7] & (FB1L334);
FB1_m_next[3] = DFFEAS(FB1_m_next[3]_lut_out, DE1__clk0, E1_data_out, , FB1L342, , , , );
--FB1_m_next[4] is std_1s10:inst|sdram:the_sdram|m_next[4]
--operation mode is normal
FB1_m_next[4]_lut_out = FB1_m_state[7] & FB1_m_next[4] & (FB1L327 # !FB1L448) # !FB1_m_state[7] & (FB1L327);
FB1_m_next[4] = DFFEAS(FB1_m_next[4]_lut_out, DE1__clk0, E1_data_out, , FB1L342, , , , );
--FB1L118 is std_1s10:inst|sdram:the_sdram|Equal5~50
--operation mode is normal
FB1L118 = FB1_m_next[0] & !FB1_m_next[1] & !FB1_m_next[3] & !FB1_m_next[4];
--FB1L253 is std_1s10:inst|sdram:the_sdram|Mux17~1806
--operation mode is normal
FB1L253 = FB1_m_state[0] & FB1L246 & (!FB1_m_state[4]);
--FB1L254 is std_1s10:inst|sdram:the_sdram|Mux17~1807
--operation mode is normal
FB1L254 = FB1_active_cs_n & (!FB1L118 # !FB1_m_next[7]) # !FB1L253;
--FB1L255 is std_1s10:inst|sdram:the_sdram|Mux17~1808
--operation mode is normal
FB1L255 = FB1L250 # FB1L252 # FB1_m_state[2] & FB1L254;
--FB1L256 is std_1s10:inst|sdram:the_sdram|Mux17~1809
--operation mode is normal
FB1L256 = FB1_m_state[0] & (!FB1_m_state[2]);
--FB1L257 is std_1s10:inst|sdram:the_sdram|Mux17~1810
--operation mode is normal
FB1L257 = FB1L246 & (!FB1_m_state[4] & !FB1_m_state[6]);
--FB1_i_cmd[2] is std_1s10:inst|sdram:the_sdram|i_cmd[2]
--operation mode is normal
FB1_i_cmd[2]_lut_out = FB1_i_state[2] # FB1_i_state[0] $ FB1_i_state[1];
FB1_i_cmd[2] = DFFEAS(FB1_i_cmd[2]_lut_out, DE1__clk0, E1_data_out, , FB1L125, , , , );
--FB1L284 is std_1s10:inst|sdram:the_sdram|Mux25~1249
--operation mode is normal
FB1L284 = !FB1_m_state[7] & !FB1_m_state[6] & !FB1_m_state[1];
--FB1L258 is std_1s10:inst|sdram:the_sdram|Mux18~1358
--operation mode is normal
FB1L258 = !FB1_m_state[0] & (FB1_init_done # !FB1L284 # !FB1_i_cmd[2]);
--FB1L299 is std_1s10:inst|sdram:the_sdram|Mux28~1601
--operation mode is normal
FB1L299 = !FB1_m_state[7] & !FB1_m_state[1];
--FB1L259 is std_1s10:inst|sdram:the_sdram|Mux18~1359
--operation mode is normal
FB1L259 = FB1_m_state[6] & !FB1L299 # !FB1L424 # !FB1L348;
--FB1L260 is std_1s10:inst|sdram:the_sdram|Mux18~1360
--operation mode is normal
FB1L260 = FB1_m_state[0] & (!FB1_m_state[6]);
--FB1L261 is std_1s10:inst|sdram:the_sdram|Mux18~1361
--operation mode is normal
FB1L261 = FB1_m_state[7] $ FB1_m_state[1];
--FB1L267 is std_1s10:inst|sdram:the_sdram|Mux20~1311
--operation mode is normal
FB1L267 = !FB1_m_state[7] & FB1L246 & !FB1_m_state[2];
--FB1L268 is std_1s10:inst|sdram:the_sdram|Mux20~1312
--operation mode is normal
FB1L268 = FB1_m_state[4] # FB1_init_done & !FB1_m_state[0];
--FB1_i_cmd[0] is std_1s10:inst|sdram:the_sdram|i_cmd[0]
--operation mode is normal
FB1_i_cmd[0]_lut_out = FB1_i_state[2] # FB1_i_state[0] & (!FB1_i_state[1]);
FB1_i_cmd[0] = DFFEAS(FB1_i_cmd[0]_lut_out, DE1__clk0, E1_data_out, , FB1L125, , , , );
--FB1L269 is std_1s10:inst|sdram:the_sdram|Mux20~1313
--operation mode is normal
FB1L269 = FB1_m_state[0] & (FB1_m_state[6] $ (FB1L268)) # !FB1_m_state[0] & !FB1_m_state[6] & FB1_i_cmd[0] & !FB1L268;
--L1_E_control_rd_data_without_mmu_regs[2] is std_1s10:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[2]
--operation mode is normal
L1_E_control_rd_data_without_mmu_regs[2] = AMPP_FUNCTION(DE1__clk0, L1_M_ipending_reg[2], L1_M_ienable_reg[2], L1_D_iw[8], L1L186, E1_data_out, L1_W_stall);
--L1_E_logic_op[1] is std_1s10:inst|cpu:the_cpu|E_logic_op[1]
--operation mode is normal
L1_E_logic_op[1] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[4], L1_D_iw[15], L1_D_iw[5], L1L808, E1_data_out, L1_W_stall);
--L1_E_src1_prelim[2] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[2]
--operation mode is normal
L1_E_src1_prelim[2] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[2], L1_W_wr_data[2], L1L1346, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_E_src1_hazard_M is std_1s10:inst|cpu:the_cpu|E_src1_hazard_M
--operation mode is normal
L1_E_src1_hazard_M = AMPP_FUNCTION(DE1__clk0, L1L803, L1L188, L1L364, L1L365, E1_data_out, L1_W_stall);
--L1_M_mul_shift_rot_result[2] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[2]
--operation mode is normal
L1_M_mul_shift_rot_result[2] = AMPP_FUNCTION(DE1__clk0, QC1_result[2], QC1_result[34], L1L1218, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1_M_ctrl_mul_shift_rot is std_1s10:inst|cpu:the_cpu|M_ctrl_mul_shift_rot
--operation mode is normal
L1_M_ctrl_mul_shift_rot = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_mul_shift_rot, E1_data_out, L1_W_stall);
--L1L1344 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[2]~3645
--operation mode is normal
L1L1344 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[2], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[2] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[2]
--operation mode is normal
L1_av_ld_data_aligned_or_div[2] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[2], L1_d_readdata_d1[18], L1L130, L1_M_ld_align_sh16, E1_data_out, L1_M_ld_align_sh8);
--L1_av_ld_or_div_done is std_1s10:inst|cpu:the_cpu|av_ld_or_div_done
--operation mode is normal
L1_av_ld_or_div_done = AMPP_FUNCTION(DE1__clk0, L1_av_ld_aligning_data, E1_data_out);
--L1L1345 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[2]~3646
--operation mode is normal
L1L1345 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[2], L1_M_alu_result[2], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L586 is std_1s10:inst|cpu:the_cpu|E_src1[2]~1965
--operation mode is normal
L1L586 = AMPP_FUNCTION(L1_E_src1_prelim[2], L1_E_src1_hazard_M, L1L1344, L1L1345);
--L1_E_src2_imm[2] is std_1s10:inst|cpu:the_cpu|E_src2_imm[2]
--operation mode is normal
L1_E_src2_imm[2] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[8], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1L1292 is std_1s10:inst|cpu:the_cpu|M_st_data[10]~COMBOUT
--operation mode is normal
L1L1292 = AMPP_FUNCTION(L1_E_src2_prelim[2], L1L1346, L1_E_src2_hazard_M);
--L1_M_st_data[10] is std_1s10:inst|cpu:the_cpu|M_st_data[10]
--operation mode is normal
L1_M_st_data[10] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[2], L1L1346, L1L792, L1_E_src2_hazard_M, E1_data_out, L1L826, L1_W_stall);
--L1_E_ctrl_src2_is_imm is std_1s10:inst|cpu:the_cpu|E_ctrl_src2_is_imm
--operation mode is normal
L1_E_ctrl_src2_is_imm = AMPP_FUNCTION(DE1__clk0, L1_D_ctrl_b_not_src, L1L228, L1L203, L1L402, E1_data_out, L1_W_stall);
--L1L652 is std_1s10:inst|cpu:the_cpu|E_src2[2]~1491
--operation mode is normal
L1L652 = AMPP_FUNCTION(L1_E_src2_imm[2], L1L1292, L1_E_ctrl_src2_is_imm);
--L1_E_logic_op[0] is std_1s10:inst|cpu:the_cpu|E_logic_op[0]
--operation mode is normal
L1_E_logic_op[0] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[14], L1_D_iw[3], L1L811, L1L808, E1_data_out, L1_W_stall);
--L1L1 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12881
--operation mode is normal
L1L1 = AMPP_FUNCTION(L1_E_logic_op[1], L1L586, L1L652, L1_E_logic_op[0]);
--L1_E_extra_pc[0] is std_1s10:inst|cpu:the_cpu|E_extra_pc[0]
--operation mode is normal
L1_E_extra_pc[0] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[0], L1_D_br_taken_waddr_partial[0], L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[2] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[2]
--operation mode is arithmetic
HC1_result[2] = AMPP_FUNCTION(L1L652, L1L586, HC1L5, L1_E_ctrl_alu_subtract);
--HC1L7 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT
--operation mode is arithmetic
HC1L7 = AMPP_FUNCTION(L1L652, L1L586, HC1L5, L1_E_ctrl_alu_subtract);
--L1_E_ctrl_dst_data_sel_pc_plus_one is std_1s10:inst|cpu:the_cpu|E_ctrl_dst_data_sel_pc_plus_one
--operation mode is normal
L1_E_ctrl_dst_data_sel_pc_plus_one = AMPP_FUNCTION(DE1__clk0, L1L188, L1L219, L1L822, L1L208, E1_data_out, L1_W_stall);
--L1L2 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12882
--operation mode is normal
L1L2 = AMPP_FUNCTION(L1_E_extra_pc[0], HC1_result[2], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_ctrl_dst_data_sel_logic_result is std_1s10:inst|cpu:the_cpu|E_ctrl_dst_data_sel_logic_result
--operation mode is normal
L1_E_ctrl_dst_data_sel_logic_result = AMPP_FUNCTION(DE1__clk0, L1_D_iw[13], L1L228, L1_D_iw[16], L1L207, E1_data_out, L1_W_stall);
--L1L3 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12883
--operation mode is normal
L1L3 = AMPP_FUNCTION(L1L1, L1L2, L1_E_ctrl_dst_data_sel_logic_result);
--L1_E_ctrl_rdctl_inst is std_1s10:inst|cpu:the_cpu|E_ctrl_rdctl_inst
--operation mode is normal
L1_E_ctrl_rdctl_inst = AMPP_FUNCTION(DE1__clk0, L1L823, L1L228, E1_data_out, L1_W_stall);
--L1_E_ctrl_dst_data_sel_cmp is std_1s10:inst|cpu:the_cpu|E_ctrl_dst_data_sel_cmp
--operation mode is normal
L1_E_ctrl_dst_data_sel_cmp = AMPP_FUNCTION(DE1__clk0, L1L204, L1L205, L1L193, L1L206, E1_data_out, L1_W_stall);
--L1L410 is std_1s10:inst|cpu:the_cpu|E_alu_result[2]~2246
--operation mode is normal
L1L410 = AMPP_FUNCTION(L1_E_control_rd_data_without_mmu_regs[2], L1L3, L1_E_ctrl_rdctl_inst, L1_E_ctrl_dst_data_sel_cmp);
--L1_M_mul_shift_rot_stall is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_stall
--operation mode is normal
L1_M_mul_shift_rot_stall = AMPP_FUNCTION(DE1__clk0, L1_M_valid_mul_shift_rot_entered_M, L1L800, L1_E_ctrl_mul_shift_rot, L1_W_stall, E1_data_out);
--L1_M_valid_from_E is std_1s10:inst|cpu:the_cpu|M_valid_from_E
--operation mode is normal
L1_M_valid_from_E = AMPP_FUNCTION(DE1__clk0, L1L800, E1_data_out, L1_W_stall);
--L1_M_ctrl_ld is std_1s10:inst|cpu:the_cpu|M_ctrl_ld
--operation mode is normal
L1_M_ctrl_ld = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_ld, E1_data_out, L1_W_stall);
--L1L1443 is std_1s10:inst|cpu:the_cpu|W_stall~19
--operation mode is normal
L1L1443 = AMPP_FUNCTION(L1_M_mul_shift_rot_stall, L1_M_valid_from_E, L1_M_ctrl_ld, L1_av_ld_or_div_done);
--KB1L7 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|control_wr_strobe~28
--operation mode is normal
KB1L7 = L1_internal_d_write & (!M1_internal_cpu_data_master_waitrequest);
--L1_E_control_rd_data_without_mmu_regs[3] is std_1s10:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[3]
--operation mode is normal
L1_E_control_rd_data_without_mmu_regs[3] = AMPP_FUNCTION(DE1__clk0, L1_M_ipending_reg[3], L1_M_ienable_reg[3], L1_D_iw[8], L1L186, E1_data_out, L1_W_stall);
--L1_E_src1_prelim[3] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[3]
--operation mode is normal
L1_E_src1_prelim[3] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[3], L1_W_wr_data[3], L1L1349, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[3] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[3]
--operation mode is normal
L1_M_mul_shift_rot_result[3] = AMPP_FUNCTION(DE1__clk0, QC1_result[3], QC1_result[35], L1L1219, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1347 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[3]~3647
--operation mode is normal
L1L1347 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[3], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[3] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[3]
--operation mode is normal
L1_av_ld_data_aligned_or_div[3] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[3], L1_d_readdata_d1[19], L1L132, L1_M_ld_align_sh16, E1_data_out, L1_M_ld_align_sh8);
--L1L1348 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[3]~3648
--operation mode is normal
L1L1348 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[3], L1_M_alu_result[3], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L587 is std_1s10:inst|cpu:the_cpu|E_src1[3]~1966
--operation mode is normal
L1L587 = AMPP_FUNCTION(L1_E_src1_prelim[3], L1_E_src1_hazard_M, L1L1347, L1L1348);
--L1_E_src2_imm[3] is std_1s10:inst|cpu:the_cpu|E_src2_imm[3]
--operation mode is normal
L1_E_src2_imm[3] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[9], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1L1294 is std_1s10:inst|cpu:the_cpu|M_st_data[11]~COMBOUT
--operation mode is normal
L1L1294 = AMPP_FUNCTION(L1_E_src2_prelim[3], L1L1349, L1_E_src2_hazard_M);
--L1_M_st_data[11] is std_1s10:inst|cpu:the_cpu|M_st_data[11]
--operation mode is normal
L1_M_st_data[11] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[3], L1L1349, L1L793, L1_E_src2_hazard_M, E1_data_out, L1L826, L1_W_stall);
--L1L653 is std_1s10:inst|cpu:the_cpu|E_src2[3]~1492
--operation mode is normal
L1L653 = AMPP_FUNCTION(L1_E_src2_imm[3], L1L1294, L1_E_ctrl_src2_is_imm);
--L1L4 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12884
--operation mode is normal
L1L4 = AMPP_FUNCTION(L1_E_logic_op[1], L1L587, L1L653, L1_E_logic_op[0]);
--L1_E_extra_pc[1] is std_1s10:inst|cpu:the_cpu|E_extra_pc[1]
--operation mode is normal
L1_E_extra_pc[1] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[1], L1_D_br_taken_waddr_partial[1], L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[3] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[3]
--operation mode is arithmetic
HC1_result[3] = AMPP_FUNCTION(L1L653, L1L587, HC1L7, L1_E_ctrl_alu_subtract);
--HC1L9 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT
--operation mode is arithmetic
HC1L9 = AMPP_FUNCTION(L1L653, L1L587, HC1L7, L1_E_ctrl_alu_subtract);
--L1L5 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12885
--operation mode is normal
L1L5 = AMPP_FUNCTION(L1_E_extra_pc[1], HC1_result[3], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1L6 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12886
--operation mode is normal
L1L6 = AMPP_FUNCTION(L1L4, L1L5, L1_E_ctrl_dst_data_sel_logic_result);
--L1L411 is std_1s10:inst|cpu:the_cpu|E_alu_result[3]~2247
--operation mode is normal
L1L411 = AMPP_FUNCTION(L1_E_control_rd_data_without_mmu_regs[3], L1L6, L1_E_ctrl_rdctl_inst, L1_E_ctrl_dst_data_sel_cmp);
--L1_E_extra_pc[5] is std_1s10:inst|cpu:the_cpu|E_extra_pc[5]
--operation mode is normal
L1_E_extra_pc[5] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[5], L1_D_br_taken_waddr_partial[5], L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[7] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[7]
--operation mode is arithmetic
HC1_result[7] = AMPP_FUNCTION(L1L657, L1L591, HC1L15, L1_E_ctrl_alu_subtract);
--HC1L17 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[7]~COUT
--operation mode is arithmetic
HC1L17 = AMPP_FUNCTION(L1L657, L1L591, HC1L15, L1_E_ctrl_alu_subtract);
--L1L7 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12887
--operation mode is normal
L1L7 = AMPP_FUNCTION(L1_E_extra_pc[5], HC1_result[7], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src1_prelim[7] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[7]
--operation mode is normal
L1_E_src1_prelim[7] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[7], L1_W_wr_data[7], L1L1361, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[7] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[7]
--operation mode is normal
L1_M_mul_shift_rot_result[7] = AMPP_FUNCTION(DE1__clk0, QC1_result[7], QC1_result[39], L1L1223, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1359 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[7]~3649
--operation mode is normal
L1L1359 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[7], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[7] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[7]
--operation mode is normal
L1_av_ld_data_aligned_or_div[7] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[7], L1_d_readdata_d1[23], L1L140, L1_M_ld_align_sh16, E1_data_out, L1_M_ld_align_sh8);
--L1L1360 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[7]~3650
--operation mode is normal
L1L1360 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[7], L1_M_alu_result[7], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L591 is std_1s10:inst|cpu:the_cpu|E_src1[7]~1967
--operation mode is normal
L1L591 = AMPP_FUNCTION(L1_E_src1_prelim[7], L1_E_src1_hazard_M, L1L1359, L1L1360);
--L1_E_src2_imm[7] is std_1s10:inst|cpu:the_cpu|E_src2_imm[7]
--operation mode is normal
L1_E_src2_imm[7] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[13], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1L1302 is std_1s10:inst|cpu:the_cpu|M_st_data[15]~COMBOUT
--operation mode is normal
L1L1302 = AMPP_FUNCTION(L1_E_src2_prelim[7], L1L1361, L1_E_src2_hazard_M);
--L1_M_st_data[15] is std_1s10:inst|cpu:the_cpu|M_st_data[15]
--operation mode is normal
L1_M_st_data[15] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[7], L1L1361, L1L797, L1_E_src2_hazard_M, E1_data_out, L1L826, L1_W_stall);
--L1L657 is std_1s10:inst|cpu:the_cpu|E_src2[7]~1493
--operation mode is normal
L1L657 = AMPP_FUNCTION(L1_E_src2_imm[7], L1L1302, L1_E_ctrl_src2_is_imm);
--L1L520 is std_1s10:inst|cpu:the_cpu|E_logic_result[7]~16117
--operation mode is normal
L1L520 = AMPP_FUNCTION(L1_E_logic_op[1], L1L591, L1L657, L1_E_logic_op[0]);
--L1L328 is std_1s10:inst|cpu:the_cpu|d_read_nxt~0
--operation mode is normal
L1L328 = AMPP_FUNCTION(L1_internal_d_read, M1_internal_cpu_data_master_waitrequest);
--L1_E_valid_from_D is std_1s10:inst|cpu:the_cpu|E_valid_from_D
--operation mode is normal
L1_E_valid_from_D = AMPP_FUNCTION(DE1__clk0, L1_M_pipe_flush, L1_D_issue, E1_data_out, L1_W_stall);
--L1_M_pipe_flush is std_1s10:inst|cpu:the_cpu|M_pipe_flush
--operation mode is normal
L1_M_pipe_flush = AMPP_FUNCTION(DE1__clk0, L1L799, L1_E_hbreak_req, L1_E_ctrl_flush_pipe_always, L1L1251, E1_data_out, L1_W_stall);
--L1L799 is std_1s10:inst|cpu:the_cpu|E_valid~28
--operation mode is normal
L1L799 = AMPP_FUNCTION(L1_E_valid_from_D, L1_M_pipe_flush);
--L1_E_iw[11] is std_1s10:inst|cpu:the_cpu|E_iw[11]
--operation mode is normal
L1_E_iw[11] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[11], E1_data_out, L1_W_stall);
--L1_E_iw[4] is std_1s10:inst|cpu:the_cpu|E_iw[4]
--operation mode is normal
L1_E_iw[4] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[4], E1_data_out, L1_W_stall);
--L1_E_iw[3] is std_1s10:inst|cpu:the_cpu|E_iw[3]
--operation mode is normal
L1_E_iw[3] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[3], E1_data_out, L1_W_stall);
--L1_E_iw[5] is std_1s10:inst|cpu:the_cpu|E_iw[5]
--operation mode is normal
L1_E_iw[5] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[5], E1_data_out, L1_W_stall);
--L1_E_iw[12] is std_1s10:inst|cpu:the_cpu|E_iw[12]
--operation mode is normal
L1_E_iw[12] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[12], E1_data_out, L1_W_stall);
--L1L545 is std_1s10:inst|cpu:the_cpu|E_op_eret~64
--operation mode is normal
L1L545 = AMPP_FUNCTION(L1_E_iw[4], L1_E_iw[3], L1_E_iw[5], L1_E_iw[12]);
--L1_E_iw[1] is std_1s10:inst|cpu:the_cpu|E_iw[1]
--operation mode is normal
L1_E_iw[1] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[1], E1_data_out, L1_W_stall);
--L1_E_iw[2] is std_1s10:inst|cpu:the_cpu|E_iw[2]
--operation mode is normal
L1_E_iw[2] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[2], E1_data_out, L1_W_stall);
--L1_E_iw[0] is std_1s10:inst|cpu:the_cpu|E_iw[0]
--operation mode is normal
L1_E_iw[0] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[0], E1_data_out, L1_W_stall);
--L1L546 is std_1s10:inst|cpu:the_cpu|E_op_eret~65
--operation mode is normal
L1L546 = AMPP_FUNCTION(L1_E_iw[1], L1_E_iw[2], L1_E_iw[0]);
--L1_E_iw[16] is std_1s10:inst|cpu:the_cpu|E_iw[16]
--operation mode is normal
L1_E_iw[16] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[16], E1_data_out, L1_W_stall);
--L1_E_iw[15] is std_1s10:inst|cpu:the_cpu|E_iw[15]
--operation mode is normal
L1_E_iw[15] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[15], E1_data_out, L1_W_stall);
--L1L482 is std_1s10:inst|cpu:the_cpu|E_hbreak_req~62
--operation mode is normal
L1L482 = AMPP_FUNCTION(L1_E_valid_from_D, L1_M_pipe_flush, L1_E_iw[16], L1_E_iw[15]);
--L1L483 is std_1s10:inst|cpu:the_cpu|E_hbreak_req~63
--operation mode is normal
L1L483 = AMPP_FUNCTION(L1_E_iw[11], L1L545, L1L546, L1L482);
--L1_E_iw[13] is std_1s10:inst|cpu:the_cpu|E_iw[13]
--operation mode is normal
L1_E_iw[13] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[13], E1_data_out, L1_W_stall);
--L1_E_iw[14] is std_1s10:inst|cpu:the_cpu|E_iw[14]
--operation mode is normal
L1_E_iw[14] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[14], E1_data_out, L1_W_stall);
--L1L484 is std_1s10:inst|cpu:the_cpu|E_hbreak_req~64
--operation mode is normal
L1L484 = AMPP_FUNCTION(L1_E_iw[13], L1_E_iw[14]);
--VC1_jtag_break is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|jtag_break
--operation mode is normal
VC1_jtag_break = AMPP_FUNCTION(DE1__clk0, VC1_probepresent, VC1_jtag_break, VC1L1, E1_data_out, !C1_CLR_SIGNAL, DD1L190);
--L1_latched_oci_tb_hbreak_req is std_1s10:inst|cpu:the_cpu|latched_oci_tb_hbreak_req
--operation mode is normal
L1_latched_oci_tb_hbreak_req = AMPP_FUNCTION(DE1__clk0, L1L799, L1L968, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, E1_data_out);
--L1_hbreak_enabled is std_1s10:inst|cpu:the_cpu|hbreak_enabled
--operation mode is normal
L1_hbreak_enabled = AMPP_FUNCTION(DE1__clk0, L1L963, L1L966, L1L967, L1_hbreak_enabled, E1_data_out);
--L1_wait_for_one_post_bret_inst is std_1s10:inst|cpu:the_cpu|wait_for_one_post_bret_inst
--operation mode is normal
L1_wait_for_one_post_bret_inst = AMPP_FUNCTION(DE1__clk0, SC1_internal_oci_single_step_mode1, L1_hbreak_enabled, L1_wait_for_one_post_bret_inst, L1L80, E1_data_out);
--L1L968 is std_1s10:inst|cpu:the_cpu|hbreak_req~30
--operation mode is normal
L1L968 = AMPP_FUNCTION(VC1_jtag_break, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1_wait_for_one_post_bret_inst);
--L1L800 is std_1s10:inst|cpu:the_cpu|E_valid~29
--operation mode is normal
L1L800 = AMPP_FUNCTION(L1L799, L1L483, L1L484, L1L968);
--L1_E_ctrl_ld is std_1s10:inst|cpu:the_cpu|E_ctrl_ld
--operation mode is normal
L1_E_ctrl_ld = AMPP_FUNCTION(DE1__clk0, L1_D_iw[4], L1_D_iw[2], L1_D_iw[1], L1_D_iw[0], E1_data_out, L1_W_stall);
--L1_E_control_rd_data_without_mmu_regs[4] is std_1s10:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[4]
--operation mode is normal
L1_E_control_rd_data_without_mmu_regs[4] = AMPP_FUNCTION(DE1__clk0, L1_M_ipending_reg[4], L1_M_ienable_reg[4], L1_D_iw[8], L1L186, E1_data_out, L1_W_stall);
--L1_E_src1_prelim[4] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[4]
--operation mode is normal
L1_E_src1_prelim[4] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[4], L1_W_wr_data[4], L1L1352, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[4] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[4]
--operation mode is normal
L1_M_mul_shift_rot_result[4] = AMPP_FUNCTION(DE1__clk0, QC1_result[4], QC1_result[36], L1L1220, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1350 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[4]~3651
--operation mode is normal
L1L1350 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[4], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[4] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[4]
--operation mode is normal
L1_av_ld_data_aligned_or_div[4] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[4], L1_d_readdata_d1[20], L1L134, L1_M_ld_align_sh16, E1_data_out, L1_M_ld_align_sh8);
--L1L1351 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[4]~3652
--operation mode is normal
L1L1351 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[4], L1_M_alu_result[4], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L588 is std_1s10:inst|cpu:the_cpu|E_src1[4]~1968
--operation mode is normal
L1L588 = AMPP_FUNCTION(L1_E_src1_prelim[4], L1_E_src1_hazard_M, L1L1350, L1L1351);
--L1_E_src2_imm[4] is std_1s10:inst|cpu:the_cpu|E_src2_imm[4]
--operation mode is normal
L1_E_src2_imm[4] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[10], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1L1296 is std_1s10:inst|cpu:the_cpu|M_st_data[12]~COMBOUT
--operation mode is normal
L1L1296 = AMPP_FUNCTION(L1_E_src2_prelim[4], L1L1352, L1_E_src2_hazard_M);
--L1_M_st_data[12] is std_1s10:inst|cpu:the_cpu|M_st_data[12]
--operation mode is normal
L1_M_st_data[12] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[4], L1L1352, L1L794, L1_E_src2_hazard_M, E1_data_out, L1L826, L1_W_stall);
--L1L654 is std_1s10:inst|cpu:the_cpu|E_src2[4]~1494
--operation mode is normal
L1L654 = AMPP_FUNCTION(L1_E_src2_imm[4], L1L1296, L1_E_ctrl_src2_is_imm);
--L1L8 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12888
--operation mode is normal
L1L8 = AMPP_FUNCTION(L1_E_logic_op[1], L1L588, L1L654, L1_E_logic_op[0]);
--L1_E_extra_pc[2] is std_1s10:inst|cpu:the_cpu|E_extra_pc[2]
--operation mode is normal
L1_E_extra_pc[2] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[2], L1_D_br_taken_waddr_partial[2], L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[4] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[4]
--operation mode is arithmetic
HC1_result[4] = AMPP_FUNCTION(L1L654, L1L588, HC1L9, L1_E_ctrl_alu_subtract);
--HC1L11 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT
--operation mode is arithmetic
HC1L11 = AMPP_FUNCTION(L1L654, L1L588, HC1L9, L1_E_ctrl_alu_subtract);
--L1L9 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12889
--operation mode is normal
L1L9 = AMPP_FUNCTION(L1_E_extra_pc[2], HC1_result[4], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1L10 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12890
--operation mode is normal
L1L10 = AMPP_FUNCTION(L1L8, L1L9, L1_E_ctrl_dst_data_sel_logic_result);
--L1L412 is std_1s10:inst|cpu:the_cpu|E_alu_result[4]~2248
--operation mode is normal
L1L412 = AMPP_FUNCTION(L1_E_control_rd_data_without_mmu_regs[4], L1L10, L1_E_ctrl_rdctl_inst, L1_E_ctrl_dst_data_sel_cmp);
--L1_E_extra_pc[20] is std_1s10:inst|cpu:the_cpu|E_extra_pc[20]
--operation mode is normal
L1_E_extra_pc[20] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[20], L1L81, L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[22] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[22]
--operation mode is arithmetic
HC1_result[22] = AMPP_FUNCTION(L1L672, L1L606, HC1L45, L1_E_ctrl_alu_subtract);
--HC1L47 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[22]~COUT
--operation mode is arithmetic
HC1L47 = AMPP_FUNCTION(L1L672, L1L606, HC1L45, L1_E_ctrl_alu_subtract);
--L1L11 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12891
--operation mode is normal
L1L11 = AMPP_FUNCTION(L1_E_extra_pc[20], HC1_result[22], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src1_prelim[22] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[22]
--operation mode is normal
L1_E_src1_prelim[22] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[22], L1_W_wr_data[22], L1L1406, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[22] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[22]
--operation mode is normal
L1_M_mul_shift_rot_result[22] = AMPP_FUNCTION(DE1__clk0, QC1_result[22], QC1_result[54], L1L1238, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1404 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[22]~3653
--operation mode is normal
L1L1404 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[22], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[22] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[22]
--operation mode is normal
L1_av_ld_data_aligned_or_div[22] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[22], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1L1405 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[22]~3654
--operation mode is normal
L1L1405 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[22], L1_M_alu_result[22], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L606 is std_1s10:inst|cpu:the_cpu|E_src1[22]~1969
--operation mode is normal
L1L606 = AMPP_FUNCTION(L1_E_src1_prelim[22], L1_E_src1_hazard_M, L1L1404, L1L1405);
--L1_E_src2_imm[22] is std_1s10:inst|cpu:the_cpu|E_src2_imm[22]
--operation mode is normal
L1_E_src2_imm[22] = AMPP_FUNCTION(DE1__clk0, L1L391, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1L1316 is std_1s10:inst|cpu:the_cpu|M_st_data[22]~COMBOUT
--operation mode is normal
L1L1316 = AMPP_FUNCTION(L1_E_src2_prelim[22], L1L1406, L1_E_src2_hazard_M);
--L1_M_st_data[22] is std_1s10:inst|cpu:the_cpu|M_st_data[22]
--operation mode is normal
L1_M_st_data[22] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[22], L1L1406, L1L1300, L1_E_src2_hazard_M, E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L672 is std_1s10:inst|cpu:the_cpu|E_src2[22]~1495
--operation mode is normal
L1L672 = AMPP_FUNCTION(L1_E_src2_imm[22], L1L1316, L1_E_ctrl_src2_is_imm);
--L1L535 is std_1s10:inst|cpu:the_cpu|E_logic_result[22]~16118
--operation mode is normal
L1L535 = AMPP_FUNCTION(L1_E_logic_op[1], L1L606, L1L672, L1_E_logic_op[0]);
--L1_E_extra_pc[19] is std_1s10:inst|cpu:the_cpu|E_extra_pc[19]
--operation mode is normal
L1_E_extra_pc[19] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[19], L1L83, L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[21] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[21]
--operation mode is arithmetic
HC1_result[21] = AMPP_FUNCTION(L1L671, L1L605, HC1L43, L1_E_ctrl_alu_subtract);
--HC1L45 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[21]~COUT
--operation mode is arithmetic
HC1L45 = AMPP_FUNCTION(L1L671, L1L605, HC1L43, L1_E_ctrl_alu_subtract);
--L1L12 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12892
--operation mode is normal
L1L12 = AMPP_FUNCTION(L1_E_extra_pc[19], HC1_result[21], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src1_prelim[21] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[21]
--operation mode is normal
L1_E_src1_prelim[21] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[21], L1_W_wr_data[21], L1L1403, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[21] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[21]
--operation mode is normal
L1_M_mul_shift_rot_result[21] = AMPP_FUNCTION(DE1__clk0, QC1_result[21], QC1_result[53], L1L1237, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1401 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[21]~3655
--operation mode is normal
L1L1401 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[21], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[21] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[21]
--operation mode is normal
L1_av_ld_data_aligned_or_div[21] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[21], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1L1402 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[21]~3656
--operation mode is normal
L1L1402 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[21], L1_M_alu_result[21], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L605 is std_1s10:inst|cpu:the_cpu|E_src1[21]~1970
--operation mode is normal
L1L605 = AMPP_FUNCTION(L1_E_src1_prelim[21], L1_E_src1_hazard_M, L1L1401, L1L1402);
--L1_E_src2_imm[21] is std_1s10:inst|cpu:the_cpu|E_src2_imm[21]
--operation mode is normal
L1_E_src2_imm[21] = AMPP_FUNCTION(DE1__clk0, L1L390, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1L1314 is std_1s10:inst|cpu:the_cpu|M_st_data[21]~COMBOUT
--operation mode is normal
L1L1314 = AMPP_FUNCTION(L1_E_src2_prelim[21], L1L1403, L1_E_src2_hazard_M);
--L1_M_st_data[21] is std_1s10:inst|cpu:the_cpu|M_st_data[21]
--operation mode is normal
L1_M_st_data[21] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[21], L1L1403, L1L1298, L1_E_src2_hazard_M, E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L671 is std_1s10:inst|cpu:the_cpu|E_src2[21]~1496
--operation mode is normal
L1L671 = AMPP_FUNCTION(L1_E_src2_imm[21], L1L1314, L1_E_ctrl_src2_is_imm);
--L1L534 is std_1s10:inst|cpu:the_cpu|E_logic_result[21]~16119
--operation mode is normal
L1L534 = AMPP_FUNCTION(L1_E_logic_op[1], L1L605, L1L671, L1_E_logic_op[0]);
--L1_E_extra_pc[22] is std_1s10:inst|cpu:the_cpu|E_extra_pc[22]
--operation mode is normal
L1_E_extra_pc[22] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[22], L1L85, L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[24] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[24]
--operation mode is arithmetic
HC1_result[24] = AMPP_FUNCTION(L1L674, L1L608, HC1L49, L1_E_ctrl_alu_subtract);
--HC1L51 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[24]~COUT
--operation mode is arithmetic
HC1L51 = AMPP_FUNCTION(L1L674, L1L608, HC1L49, L1_E_ctrl_alu_subtract);
--L1L13 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12893
--operation mode is normal
L1L13 = AMPP_FUNCTION(L1_E_extra_pc[22], HC1_result[24], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src2_imm[24] is std_1s10:inst|cpu:the_cpu|E_src2_imm[24]
--operation mode is normal
L1_E_src2_imm[24] = AMPP_FUNCTION(DE1__clk0, L1L393, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[24] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[24]
--operation mode is normal
L1_E_src2_prelim[24] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[24], L1_W_wr_data[24], L1L1412, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_E_src2_hazard_M is std_1s10:inst|cpu:the_cpu|E_src2_hazard_M
--operation mode is normal
L1_E_src2_hazard_M = AMPP_FUNCTION(DE1__clk0, L1L803, L1L376, L1_E_dst_regnum[2], L1_D_iw[24], E1_data_out, L1_W_stall);
--L1_M_mul_shift_rot_result[24] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[24]
--operation mode is normal
L1_M_mul_shift_rot_result[24] = AMPP_FUNCTION(DE1__clk0, QC1_result[24], QC1_result[56], L1L1240, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1410 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[24]~3657
--operation mode is normal
L1L1410 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[24], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[24] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[24]
--operation mode is normal
L1_av_ld_data_aligned_or_div[24] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[24], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1L1411 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[24]~3658
--operation mode is normal
L1L1411 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[24], L1_M_alu_result[24], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L782 is std_1s10:inst|cpu:the_cpu|E_src2_reg[24]~472
--operation mode is normal
L1L782 = AMPP_FUNCTION(L1_E_src2_prelim[24], L1_E_src2_hazard_M, L1L1410, L1L1411);
--L1L674 is std_1s10:inst|cpu:the_cpu|E_src2[24]~1497
--operation mode is normal
L1L674 = AMPP_FUNCTION(L1_E_src2_imm[24], L1L782, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[24] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[24]
--operation mode is normal
L1_E_src1_prelim[24] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[24], L1_W_wr_data[24], L1L1412, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L608 is std_1s10:inst|cpu:the_cpu|E_src1[24]~1971
--operation mode is normal
L1L608 = AMPP_FUNCTION(L1_E_src1_prelim[24], L1_E_src1_hazard_M, L1L1410, L1L1411);
--L1L537 is std_1s10:inst|cpu:the_cpu|E_logic_result[24]~16120
--operation mode is normal
L1L537 = AMPP_FUNCTION(L1_E_logic_op[1], L1L674, L1L608, L1_E_logic_op[0]);
--L1_E_extra_pc[17] is std_1s10:inst|cpu:the_cpu|E_extra_pc[17]
--operation mode is normal
L1_E_extra_pc[17] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[17], L1L87, L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[19] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[19]
--operation mode is arithmetic
HC1_result[19] = AMPP_FUNCTION(L1L669, L1L603, HC1L39, L1_E_ctrl_alu_subtract);
--HC1L41 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[19]~COUT
--operation mode is arithmetic
HC1L41 = AMPP_FUNCTION(L1L669, L1L603, HC1L39, L1_E_ctrl_alu_subtract);
--L1L14 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12894
--operation mode is normal
L1L14 = AMPP_FUNCTION(L1_E_extra_pc[17], HC1_result[19], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src1_prelim[19] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[19]
--operation mode is normal
L1_E_src1_prelim[19] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[19], L1_W_wr_data[19], L1L1397, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[19] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[19]
--operation mode is normal
L1_M_mul_shift_rot_result[19] = AMPP_FUNCTION(DE1__clk0, QC1_result[19], QC1_result[51], L1L1235, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1395 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[19]~3659
--operation mode is normal
L1L1395 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[19], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[19] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[19]
--operation mode is normal
L1_av_ld_data_aligned_or_div[19] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[19], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1L1396 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[19]~3660
--operation mode is normal
L1L1396 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[19], L1_M_alu_result[19], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L603 is std_1s10:inst|cpu:the_cpu|E_src1[19]~1972
--operation mode is normal
L1L603 = AMPP_FUNCTION(L1_E_src1_prelim[19], L1_E_src1_hazard_M, L1L1395, L1L1396);
--L1_E_src2_imm[19] is std_1s10:inst|cpu:the_cpu|E_src2_imm[19]
--operation mode is normal
L1_E_src2_imm[19] = AMPP_FUNCTION(DE1__clk0, L1L388, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1L1310 is std_1s10:inst|cpu:the_cpu|M_st_data[19]~COMBOUT
--operation mode is normal
L1L1310 = AMPP_FUNCTION(L1_E_src2_prelim[19], L1L1397, L1_E_src2_hazard_M);
--L1_M_st_data[19] is std_1s10:inst|cpu:the_cpu|M_st_data[19]
--operation mode is normal
L1_M_st_data[19] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[19], L1L1397, L1L1294, L1_E_src2_hazard_M, E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L669 is std_1s10:inst|cpu:the_cpu|E_src2[19]~1498
--operation mode is normal
L1L669 = AMPP_FUNCTION(L1_E_src2_imm[19], L1L1310, L1_E_ctrl_src2_is_imm);
--L1L532 is std_1s10:inst|cpu:the_cpu|E_logic_result[19]~16121
--operation mode is normal
L1L532 = AMPP_FUNCTION(L1_E_logic_op[1], L1L603, L1L669, L1_E_logic_op[0]);
--L1_E_extra_pc[16] is std_1s10:inst|cpu:the_cpu|E_extra_pc[16]
--operation mode is normal
L1_E_extra_pc[16] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[16], L1L89, L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[18] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[18]
--operation mode is arithmetic
HC1_result[18] = AMPP_FUNCTION(L1L668, L1L602, HC1L37, L1_E_ctrl_alu_subtract);
--HC1L39 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[18]~COUT
--operation mode is arithmetic
HC1L39 = AMPP_FUNCTION(L1L668, L1L602, HC1L37, L1_E_ctrl_alu_subtract);
--L1L15 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12895
--operation mode is normal
L1L15 = AMPP_FUNCTION(L1_E_extra_pc[16], HC1_result[18], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src1_prelim[18] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[18]
--operation mode is normal
L1_E_src1_prelim[18] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[18], L1_W_wr_data[18], L1L1394, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[18] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[18]
--operation mode is normal
L1_M_mul_shift_rot_result[18] = AMPP_FUNCTION(DE1__clk0, QC1_result[18], QC1_result[50], L1L1234, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1392 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[18]~3661
--operation mode is normal
L1L1392 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[18], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[18] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[18]
--operation mode is normal
L1_av_ld_data_aligned_or_div[18] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[18], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1L1393 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[18]~3662
--operation mode is normal
L1L1393 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[18], L1_M_alu_result[18], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L602 is std_1s10:inst|cpu:the_cpu|E_src1[18]~1973
--operation mode is normal
L1L602 = AMPP_FUNCTION(L1_E_src1_prelim[18], L1_E_src1_hazard_M, L1L1392, L1L1393);
--L1_E_src2_imm[18] is std_1s10:inst|cpu:the_cpu|E_src2_imm[18]
--operation mode is normal
L1_E_src2_imm[18] = AMPP_FUNCTION(DE1__clk0, L1L387, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1L1308 is std_1s10:inst|cpu:the_cpu|M_st_data[18]~COMBOUT
--operation mode is normal
L1L1308 = AMPP_FUNCTION(L1_E_src2_prelim[18], L1L1394, L1_E_src2_hazard_M);
--L1_M_st_data[18] is std_1s10:inst|cpu:the_cpu|M_st_data[18]
--operation mode is normal
L1_M_st_data[18] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[18], L1L1394, L1L1292, L1_E_src2_hazard_M, E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L668 is std_1s10:inst|cpu:the_cpu|E_src2[18]~1499
--operation mode is normal
L1L668 = AMPP_FUNCTION(L1_E_src2_imm[18], L1L1308, L1_E_ctrl_src2_is_imm);
--L1L531 is std_1s10:inst|cpu:the_cpu|E_logic_result[18]~16122
--operation mode is normal
L1L531 = AMPP_FUNCTION(L1_E_logic_op[1], L1L602, L1L668, L1_E_logic_op[0]);
--L1_E_extra_pc[15] is std_1s10:inst|cpu:the_cpu|E_extra_pc[15]
--operation mode is normal
L1_E_extra_pc[15] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[15], L1L91, L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[17] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[17]
--operation mode is arithmetic
HC1_result[17] = AMPP_FUNCTION(L1L667, L1L601, HC1L35, L1_E_ctrl_alu_subtract);
--HC1L37 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[17]~COUT
--operation mode is arithmetic
HC1L37 = AMPP_FUNCTION(L1L667, L1L601, HC1L35, L1_E_ctrl_alu_subtract);
--L1L16 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12896
--operation mode is normal
L1L16 = AMPP_FUNCTION(L1_E_extra_pc[15], HC1_result[17], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src1_prelim[17] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[17]
--operation mode is normal
L1_E_src1_prelim[17] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[17], L1_W_wr_data[17], L1L1391, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[17] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[17]
--operation mode is normal
L1_M_mul_shift_rot_result[17] = AMPP_FUNCTION(DE1__clk0, QC1_result[17], QC1_result[49], L1L1233, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1389 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[17]~3663
--operation mode is normal
L1L1389 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[17], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[17] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[17]
--operation mode is normal
L1_av_ld_data_aligned_or_div[17] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[17], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1L1390 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[17]~3664
--operation mode is normal
L1L1390 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[17], L1_M_alu_result[17], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L601 is std_1s10:inst|cpu:the_cpu|E_src1[17]~1974
--operation mode is normal
L1L601 = AMPP_FUNCTION(L1_E_src1_prelim[17], L1_E_src1_hazard_M, L1L1389, L1L1390);
--L1_E_src2_imm[17] is std_1s10:inst|cpu:the_cpu|E_src2_imm[17]
--operation mode is normal
L1_E_src2_imm[17] = AMPP_FUNCTION(DE1__clk0, L1L386, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1L1306 is std_1s10:inst|cpu:the_cpu|M_st_data[17]~COMBOUT
--operation mode is normal
L1L1306 = AMPP_FUNCTION(L1_E_src2_prelim[17], L1L1391, L1_E_src2_hazard_M);
--L1_M_st_data[17] is std_1s10:inst|cpu:the_cpu|M_st_data[17]
--operation mode is normal
L1_M_st_data[17] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[17], L1L1391, L1L1290, L1_E_src2_hazard_M, E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L667 is std_1s10:inst|cpu:the_cpu|E_src2[17]~1500
--operation mode is normal
L1L667 = AMPP_FUNCTION(L1_E_src2_imm[17], L1L1306, L1_E_ctrl_src2_is_imm);
--L1L530 is std_1s10:inst|cpu:the_cpu|E_logic_result[17]~16123
--operation mode is normal
L1L530 = AMPP_FUNCTION(L1_E_logic_op[1], L1L601, L1L667, L1_E_logic_op[0]);
--L1_E_extra_pc[14] is std_1s10:inst|cpu:the_cpu|E_extra_pc[14]
--operation mode is normal
L1_E_extra_pc[14] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[14], L1L93, L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[16] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[16]
--operation mode is arithmetic
HC1_result[16] = AMPP_FUNCTION(L1L666, L1L600, HC1L33, L1_E_ctrl_alu_subtract);
--HC1L35 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[16]~COUT
--operation mode is arithmetic
HC1L35 = AMPP_FUNCTION(L1L666, L1L600, HC1L33, L1_E_ctrl_alu_subtract);
--L1L17 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12897
--operation mode is normal
L1L17 = AMPP_FUNCTION(L1_E_extra_pc[14], HC1_result[16], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src1_prelim[16] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[16]
--operation mode is normal
L1_E_src1_prelim[16] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[16], L1_W_wr_data[16], L1L1388, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[16] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[16]
--operation mode is normal
L1_M_mul_shift_rot_result[16] = AMPP_FUNCTION(DE1__clk0, QC1_result[16], QC1_result[48], L1L1232, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1386 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[16]~3665
--operation mode is normal
L1L1386 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[16], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[16] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[16]
--operation mode is normal
L1_av_ld_data_aligned_or_div[16] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[16], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1L1387 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[16]~3666
--operation mode is normal
L1L1387 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[16], L1_M_alu_result[16], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L600 is std_1s10:inst|cpu:the_cpu|E_src1[16]~1975
--operation mode is normal
L1L600 = AMPP_FUNCTION(L1_E_src1_prelim[16], L1_E_src1_hazard_M, L1L1386, L1L1387);
--L1_E_src2_imm[16] is std_1s10:inst|cpu:the_cpu|E_src2_imm[16]
--operation mode is normal
L1_E_src2_imm[16] = AMPP_FUNCTION(DE1__clk0, L1L385, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1L1304 is std_1s10:inst|cpu:the_cpu|M_st_data[16]~COMBOUT
--operation mode is normal
L1L1304 = AMPP_FUNCTION(L1_E_src2_prelim[16], L1L1388, L1_E_src2_hazard_M);
--L1_M_st_data[16] is std_1s10:inst|cpu:the_cpu|M_st_data[16]
--operation mode is normal
L1_M_st_data[16] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[16], L1L1388, L1L1288, L1_E_src2_hazard_M, E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L666 is std_1s10:inst|cpu:the_cpu|E_src2[16]~1501
--operation mode is normal
L1L666 = AMPP_FUNCTION(L1_E_src2_imm[16], L1L1304, L1_E_ctrl_src2_is_imm);
--L1L529 is std_1s10:inst|cpu:the_cpu|E_logic_result[16]~16124
--operation mode is normal
L1L529 = AMPP_FUNCTION(L1_E_logic_op[1], L1L600, L1L666, L1_E_logic_op[0]);
--L1_E_extra_pc[21] is std_1s10:inst|cpu:the_cpu|E_extra_pc[21]
--operation mode is normal
L1_E_extra_pc[21] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[21], L1L95, L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[23] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[23]
--operation mode is arithmetic
HC1_result[23] = AMPP_FUNCTION(L1L673, L1L607, HC1L47, L1_E_ctrl_alu_subtract);
--HC1L49 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[23]~COUT
--operation mode is arithmetic
HC1L49 = AMPP_FUNCTION(L1L673, L1L607, HC1L47, L1_E_ctrl_alu_subtract);
--L1L18 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12898
--operation mode is normal
L1L18 = AMPP_FUNCTION(L1_E_extra_pc[21], HC1_result[23], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src1_prelim[23] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[23]
--operation mode is normal
L1_E_src1_prelim[23] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[23], L1_W_wr_data[23], L1L1409, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[23] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[23]
--operation mode is normal
L1_M_mul_shift_rot_result[23] = AMPP_FUNCTION(DE1__clk0, QC1_result[23], QC1_result[55], L1L1239, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1407 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[23]~3667
--operation mode is normal
L1L1407 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[23], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[23] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[23]
--operation mode is normal
L1_av_ld_data_aligned_or_div[23] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[23], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1L1408 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[23]~3668
--operation mode is normal
L1L1408 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[23], L1_M_alu_result[23], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L607 is std_1s10:inst|cpu:the_cpu|E_src1[23]~1976
--operation mode is normal
L1L607 = AMPP_FUNCTION(L1_E_src1_prelim[23], L1_E_src1_hazard_M, L1L1407, L1L1408);
--L1_E_src2_imm[23] is std_1s10:inst|cpu:the_cpu|E_src2_imm[23]
--operation mode is normal
L1_E_src2_imm[23] = AMPP_FUNCTION(DE1__clk0, L1L392, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1L1318 is std_1s10:inst|cpu:the_cpu|M_st_data[23]~COMBOUT
--operation mode is normal
L1L1318 = AMPP_FUNCTION(L1_E_src2_prelim[23], L1L1409, L1_E_src2_hazard_M);
--L1_M_st_data[23] is std_1s10:inst|cpu:the_cpu|M_st_data[23]
--operation mode is normal
L1_M_st_data[23] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[23], L1L1409, L1L1302, L1_E_src2_hazard_M, E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L673 is std_1s10:inst|cpu:the_cpu|E_src2[23]~1502
--operation mode is normal
L1L673 = AMPP_FUNCTION(L1_E_src2_imm[23], L1L1318, L1_E_ctrl_src2_is_imm);
--L1L536 is std_1s10:inst|cpu:the_cpu|E_logic_result[23]~16125
--operation mode is normal
L1L536 = AMPP_FUNCTION(L1_E_logic_op[1], L1L607, L1L673, L1_E_logic_op[0]);
--L1_E_extra_pc[23] is std_1s10:inst|cpu:the_cpu|E_extra_pc[23]
--operation mode is normal
L1_E_extra_pc[23] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[23], L1L97, L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[25] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[25]
--operation mode is arithmetic
HC1_result[25] = AMPP_FUNCTION(L1L675, L1L609, HC1L51, L1_E_ctrl_alu_subtract);
--HC1L53 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[25]~COUT
--operation mode is arithmetic
HC1L53 = AMPP_FUNCTION(L1L675, L1L609, HC1L51, L1_E_ctrl_alu_subtract);
--L1L19 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12899
--operation mode is normal
L1L19 = AMPP_FUNCTION(L1_E_extra_pc[23], HC1_result[25], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src2_imm[25] is std_1s10:inst|cpu:the_cpu|E_src2_imm[25]
--operation mode is normal
L1_E_src2_imm[25] = AMPP_FUNCTION(DE1__clk0, L1L394, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[25] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[25]
--operation mode is normal
L1_E_src2_prelim[25] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[25], L1_W_wr_data[25], L1L1415, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_M_mul_shift_rot_result[25] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[25]
--operation mode is normal
L1_M_mul_shift_rot_result[25] = AMPP_FUNCTION(DE1__clk0, QC1_result[25], QC1_result[57], L1L1241, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1413 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[25]~3669
--operation mode is normal
L1L1413 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[25], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[25] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25]
--operation mode is normal
L1_av_ld_data_aligned_or_div[25] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[25], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1L1414 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[25]~3670
--operation mode is normal
L1L1414 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[25], L1_M_alu_result[25], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L783 is std_1s10:inst|cpu:the_cpu|E_src2_reg[25]~473
--operation mode is normal
L1L783 = AMPP_FUNCTION(L1_E_src2_prelim[25], L1_E_src2_hazard_M, L1L1413, L1L1414);
--L1L675 is std_1s10:inst|cpu:the_cpu|E_src2[25]~1503
--operation mode is normal
L1L675 = AMPP_FUNCTION(L1_E_src2_imm[25], L1L783, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[25] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[25]
--operation mode is normal
L1_E_src1_prelim[25] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[25], L1_W_wr_data[25], L1L1415, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L609 is std_1s10:inst|cpu:the_cpu|E_src1[25]~1977
--operation mode is normal
L1L609 = AMPP_FUNCTION(L1_E_src1_prelim[25], L1_E_src1_hazard_M, L1L1413, L1L1414);
--L1L538 is std_1s10:inst|cpu:the_cpu|E_logic_result[25]~16126
--operation mode is normal
L1L538 = AMPP_FUNCTION(L1_E_logic_op[1], L1L675, L1L609, L1_E_logic_op[0]);
--L1_E_extra_pc[18] is std_1s10:inst|cpu:the_cpu|E_extra_pc[18]
--operation mode is normal
L1_E_extra_pc[18] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[18], L1L98, L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[20] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[20]
--operation mode is arithmetic
HC1_result[20] = AMPP_FUNCTION(L1L670, L1L604, HC1L41, L1_E_ctrl_alu_subtract);
--HC1L43 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[20]~COUT
--operation mode is arithmetic
HC1L43 = AMPP_FUNCTION(L1L670, L1L604, HC1L41, L1_E_ctrl_alu_subtract);
--L1L20 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12900
--operation mode is normal
L1L20 = AMPP_FUNCTION(L1_E_extra_pc[18], HC1_result[20], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src1_prelim[20] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[20]
--operation mode is normal
L1_E_src1_prelim[20] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[20], L1_W_wr_data[20], L1L1400, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[20] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[20]
--operation mode is normal
L1_M_mul_shift_rot_result[20] = AMPP_FUNCTION(DE1__clk0, QC1_result[20], QC1_result[52], L1L1236, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1398 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[20]~3671
--operation mode is normal
L1L1398 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[20], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[20] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[20]
--operation mode is normal
L1_av_ld_data_aligned_or_div[20] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[20], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1L1399 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[20]~3672
--operation mode is normal
L1L1399 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[20], L1_M_alu_result[20], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L604 is std_1s10:inst|cpu:the_cpu|E_src1[20]~1978
--operation mode is normal
L1L604 = AMPP_FUNCTION(L1_E_src1_prelim[20], L1_E_src1_hazard_M, L1L1398, L1L1399);
--L1_E_src2_imm[20] is std_1s10:inst|cpu:the_cpu|E_src2_imm[20]
--operation mode is normal
L1_E_src2_imm[20] = AMPP_FUNCTION(DE1__clk0, L1L389, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1L1312 is std_1s10:inst|cpu:the_cpu|M_st_data[20]~COMBOUT
--operation mode is normal
L1L1312 = AMPP_FUNCTION(L1_E_src2_prelim[20], L1L1400, L1_E_src2_hazard_M);
--L1_M_st_data[20] is std_1s10:inst|cpu:the_cpu|M_st_data[20]
--operation mode is normal
L1_M_st_data[20] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[20], L1L1400, L1L1296, L1_E_src2_hazard_M, E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L670 is std_1s10:inst|cpu:the_cpu|E_src2[20]~1504
--operation mode is normal
L1L670 = AMPP_FUNCTION(L1_E_src2_imm[20], L1L1312, L1_E_ctrl_src2_is_imm);
--L1L533 is std_1s10:inst|cpu:the_cpu|E_logic_result[20]~16127
--operation mode is normal
L1L533 = AMPP_FUNCTION(L1_E_logic_op[1], L1L604, L1L670, L1_E_logic_op[0]);
--L1_E_extra_pc[13] is std_1s10:inst|cpu:the_cpu|E_extra_pc[13]
--operation mode is normal
L1_E_extra_pc[13] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[13], L1L100, L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[15] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[15]
--operation mode is arithmetic
HC1_result[15] = AMPP_FUNCTION(L1L665, L1L599, HC1L31, L1_E_ctrl_alu_subtract);
--HC1L33 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[15]~COUT
--operation mode is arithmetic
HC1L33 = AMPP_FUNCTION(L1L665, L1L599, HC1L31, L1_E_ctrl_alu_subtract);
--L1L21 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12901
--operation mode is normal
L1L21 = AMPP_FUNCTION(L1_E_extra_pc[13], HC1_result[15], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src2_imm[15] is std_1s10:inst|cpu:the_cpu|E_src2_imm[15]
--operation mode is normal
L1_E_src2_imm[15] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[21], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[15] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[15]
--operation mode is normal
L1_E_src2_prelim[15] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[15], L1_W_wr_data[15], L1L1385, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_M_mul_shift_rot_result[15] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[15]
--operation mode is normal
L1_M_mul_shift_rot_result[15] = AMPP_FUNCTION(DE1__clk0, QC1_result[15], QC1_result[47], L1L1231, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1383 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[15]~3673
--operation mode is normal
L1L1383 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[15], L1_M_ctrl_mul_shift_rot);
--L1L140 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[15]~COMBOUT
--operation mode is normal
L1L140 = AMPP_FUNCTION(L1_d_readdata_d1[15], L1_d_readdata_d1[31], L1_M_ld_align_sh16);
--L1_av_ld_data_aligned_or_div[15] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[15]
--operation mode is normal
L1_av_ld_data_aligned_or_div[15] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[15], L1_d_readdata_d1[31], L1_av_fill_bit, L1_M_ld_align_sh16, E1_data_out, L1L827);
--L1L1384 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[15]~3674
--operation mode is normal
L1L1384 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[15], L1_M_alu_result[15], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L797 is std_1s10:inst|cpu:the_cpu|E_sth_data[15]~472
--operation mode is normal
L1L797 = AMPP_FUNCTION(L1_E_src2_prelim[15], L1_E_src2_hazard_M, L1L1383, L1L1384);
--L1L665 is std_1s10:inst|cpu:the_cpu|E_src2[15]~1505
--operation mode is normal
L1L665 = AMPP_FUNCTION(L1_E_src2_imm[15], L1L797, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[15] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[15]
--operation mode is normal
L1_E_src1_prelim[15] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[15], L1_W_wr_data[15], L1L1385, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L599 is std_1s10:inst|cpu:the_cpu|E_src1[15]~1979
--operation mode is normal
L1L599 = AMPP_FUNCTION(L1_E_src1_prelim[15], L1_E_src1_hazard_M, L1L1383, L1L1384);
--L1L528 is std_1s10:inst|cpu:the_cpu|E_logic_result[15]~16128
--operation mode is normal
L1L528 = AMPP_FUNCTION(L1_E_logic_op[1], L1L665, L1L599, L1_E_logic_op[0]);
--L1_E_extra_pc[12] is std_1s10:inst|cpu:the_cpu|E_extra_pc[12]
--operation mode is normal
L1_E_extra_pc[12] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[12], L1L102, L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[14] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[14]
--operation mode is arithmetic
HC1_result[14] = AMPP_FUNCTION(L1L664, L1L598, HC1L29, L1_E_ctrl_alu_subtract);
--HC1L31 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[14]~COUT
--operation mode is arithmetic
HC1L31 = AMPP_FUNCTION(L1L664, L1L598, HC1L29, L1_E_ctrl_alu_subtract);
--L1L22 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12902
--operation mode is normal
L1L22 = AMPP_FUNCTION(L1_E_extra_pc[12], HC1_result[14], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src2_imm[14] is std_1s10:inst|cpu:the_cpu|E_src2_imm[14]
--operation mode is normal
L1_E_src2_imm[14] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[20], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[14] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[14]
--operation mode is normal
L1_E_src2_prelim[14] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[14], L1_W_wr_data[14], L1L1382, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_M_mul_shift_rot_result[14] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[14]
--operation mode is normal
L1_M_mul_shift_rot_result[14] = AMPP_FUNCTION(DE1__clk0, QC1_result[14], QC1_result[46], L1L1230, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1380 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[14]~3675
--operation mode is normal
L1L1380 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[14], L1_M_ctrl_mul_shift_rot);
--L1L138 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[14]~COMBOUT
--operation mode is normal
L1L138 = AMPP_FUNCTION(L1_d_readdata_d1[14], L1_d_readdata_d1[30], L1_M_ld_align_sh16);
--L1_av_ld_data_aligned_or_div[14] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[14]
--operation mode is normal
L1_av_ld_data_aligned_or_div[14] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[14], L1_d_readdata_d1[30], L1_av_fill_bit, L1_M_ld_align_sh16, E1_data_out, L1L827);
--L1L1381 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[14]~3676
--operation mode is normal
L1L1381 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[14], L1_M_alu_result[14], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L796 is std_1s10:inst|cpu:the_cpu|E_sth_data[14]~473
--operation mode is normal
L1L796 = AMPP_FUNCTION(L1_E_src2_prelim[14], L1_E_src2_hazard_M, L1L1380, L1L1381);
--L1L664 is std_1s10:inst|cpu:the_cpu|E_src2[14]~1506
--operation mode is normal
L1L664 = AMPP_FUNCTION(L1_E_src2_imm[14], L1L796, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[14] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[14]
--operation mode is normal
L1_E_src1_prelim[14] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[14], L1_W_wr_data[14], L1L1382, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L598 is std_1s10:inst|cpu:the_cpu|E_src1[14]~1980
--operation mode is normal
L1L598 = AMPP_FUNCTION(L1_E_src1_prelim[14], L1_E_src1_hazard_M, L1L1380, L1L1381);
--L1L527 is std_1s10:inst|cpu:the_cpu|E_logic_result[14]~16129
--operation mode is normal
L1L527 = AMPP_FUNCTION(L1_E_logic_op[1], L1L664, L1L598, L1_E_logic_op[0]);
--L1_E_extra_pc[11] is std_1s10:inst|cpu:the_cpu|E_extra_pc[11]
--operation mode is normal
L1_E_extra_pc[11] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[11], L1L104, L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[13] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[13]
--operation mode is arithmetic
HC1_result[13] = AMPP_FUNCTION(L1L663, L1L597, HC1L27, L1_E_ctrl_alu_subtract);
--HC1L29 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[13]~COUT
--operation mode is arithmetic
HC1L29 = AMPP_FUNCTION(L1L663, L1L597, HC1L27, L1_E_ctrl_alu_subtract);
--L1L23 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12903
--operation mode is normal
L1L23 = AMPP_FUNCTION(L1_E_extra_pc[11], HC1_result[13], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src2_imm[13] is std_1s10:inst|cpu:the_cpu|E_src2_imm[13]
--operation mode is normal
L1_E_src2_imm[13] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[19], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[13] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[13]
--operation mode is normal
L1_E_src2_prelim[13] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[13], L1_W_wr_data[13], L1L1379, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_M_mul_shift_rot_result[13] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[13]
--operation mode is normal
L1_M_mul_shift_rot_result[13] = AMPP_FUNCTION(DE1__clk0, QC1_result[13], QC1_result[45], L1L1229, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1377 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[13]~3677
--operation mode is normal
L1L1377 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[13], L1_M_ctrl_mul_shift_rot);
--L1L136 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[13]~COMBOUT
--operation mode is normal
L1L136 = AMPP_FUNCTION(L1_d_readdata_d1[13], L1_d_readdata_d1[29], L1_M_ld_align_sh16);
--L1_av_ld_data_aligned_or_div[13] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[13]
--operation mode is normal
L1_av_ld_data_aligned_or_div[13] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[13], L1_d_readdata_d1[29], L1_av_fill_bit, L1_M_ld_align_sh16, E1_data_out, L1L827);
--L1L1378 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[13]~3678
--operation mode is normal
L1L1378 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[13], L1_M_alu_result[13], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L795 is std_1s10:inst|cpu:the_cpu|E_sth_data[13]~474
--operation mode is normal
L1L795 = AMPP_FUNCTION(L1_E_src2_prelim[13], L1_E_src2_hazard_M, L1L1377, L1L1378);
--L1L663 is std_1s10:inst|cpu:the_cpu|E_src2[13]~1507
--operation mode is normal
L1L663 = AMPP_FUNCTION(L1_E_src2_imm[13], L1L795, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[13] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[13]
--operation mode is normal
L1_E_src1_prelim[13] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[13], L1_W_wr_data[13], L1L1379, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L597 is std_1s10:inst|cpu:the_cpu|E_src1[13]~1981
--operation mode is normal
L1L597 = AMPP_FUNCTION(L1_E_src1_prelim[13], L1_E_src1_hazard_M, L1L1377, L1L1378);
--L1L526 is std_1s10:inst|cpu:the_cpu|E_logic_result[13]~16130
--operation mode is normal
L1L526 = AMPP_FUNCTION(L1_E_logic_op[1], L1L663, L1L597, L1_E_logic_op[0]);
--L1_E_extra_pc[10] is std_1s10:inst|cpu:the_cpu|E_extra_pc[10]
--operation mode is normal
L1_E_extra_pc[10] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[10], L1L106, L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[12] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[12]
--operation mode is arithmetic
HC1_result[12] = AMPP_FUNCTION(L1L662, L1L596, HC1L25, L1_E_ctrl_alu_subtract);
--HC1L27 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[12]~COUT
--operation mode is arithmetic
HC1L27 = AMPP_FUNCTION(L1L662, L1L596, HC1L25, L1_E_ctrl_alu_subtract);
--L1L24 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12904
--operation mode is normal
L1L24 = AMPP_FUNCTION(L1_E_extra_pc[10], HC1_result[12], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src2_imm[12] is std_1s10:inst|cpu:the_cpu|E_src2_imm[12]
--operation mode is normal
L1_E_src2_imm[12] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[18], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[12] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[12]
--operation mode is normal
L1_E_src2_prelim[12] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[12], L1_W_wr_data[12], L1L1376, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_M_mul_shift_rot_result[12] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[12]
--operation mode is normal
L1_M_mul_shift_rot_result[12] = AMPP_FUNCTION(DE1__clk0, QC1_result[12], QC1_result[44], L1L1228, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1374 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[12]~3679
--operation mode is normal
L1L1374 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[12], L1_M_ctrl_mul_shift_rot);
--L1L134 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[12]~COMBOUT
--operation mode is normal
L1L134 = AMPP_FUNCTION(L1_d_readdata_d1[12], L1_d_readdata_d1[28], L1_M_ld_align_sh16);
--L1_av_ld_data_aligned_or_div[12] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[12]
--operation mode is normal
L1_av_ld_data_aligned_or_div[12] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[12], L1_d_readdata_d1[28], L1_av_fill_bit, L1_M_ld_align_sh16, E1_data_out, L1L827);
--L1L1375 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[12]~3680
--operation mode is normal
L1L1375 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[12], L1_M_alu_result[12], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L794 is std_1s10:inst|cpu:the_cpu|E_sth_data[12]~475
--operation mode is normal
L1L794 = AMPP_FUNCTION(L1_E_src2_prelim[12], L1_E_src2_hazard_M, L1L1374, L1L1375);
--L1L662 is std_1s10:inst|cpu:the_cpu|E_src2[12]~1508
--operation mode is normal
L1L662 = AMPP_FUNCTION(L1_E_src2_imm[12], L1L794, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[12] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[12]
--operation mode is normal
L1_E_src1_prelim[12] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[12], L1_W_wr_data[12], L1L1376, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L596 is std_1s10:inst|cpu:the_cpu|E_src1[12]~1982
--operation mode is normal
L1L596 = AMPP_FUNCTION(L1_E_src1_prelim[12], L1_E_src1_hazard_M, L1L1374, L1L1375);
--L1L525 is std_1s10:inst|cpu:the_cpu|E_logic_result[12]~16131
--operation mode is normal
L1L525 = AMPP_FUNCTION(L1_E_logic_op[1], L1L662, L1L596, L1_E_logic_op[0]);
--L1_E_extra_pc[9] is std_1s10:inst|cpu:the_cpu|E_extra_pc[9]
--operation mode is normal
L1_E_extra_pc[9] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[9], L1_D_br_taken_waddr_partial[9], L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[11] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[11]
--operation mode is arithmetic
HC1_result[11] = AMPP_FUNCTION(L1L661, L1L595, HC1L23, L1_E_ctrl_alu_subtract);
--HC1L25 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[11]~COUT
--operation mode is arithmetic
HC1L25 = AMPP_FUNCTION(L1L661, L1L595, HC1L23, L1_E_ctrl_alu_subtract);
--L1L25 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12905
--operation mode is normal
L1L25 = AMPP_FUNCTION(L1_E_extra_pc[9], HC1_result[11], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src2_imm[11] is std_1s10:inst|cpu:the_cpu|E_src2_imm[11]
--operation mode is normal
L1_E_src2_imm[11] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[17], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[11] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[11]
--operation mode is normal
L1_E_src2_prelim[11] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[11], L1_W_wr_data[11], L1L1373, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_M_mul_shift_rot_result[11] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[11]
--operation mode is normal
L1_M_mul_shift_rot_result[11] = AMPP_FUNCTION(DE1__clk0, QC1_result[11], QC1_result[43], L1L1227, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1371 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[11]~3681
--operation mode is normal
L1L1371 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[11], L1_M_ctrl_mul_shift_rot);
--L1L132 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[11]~COMBOUT
--operation mode is normal
L1L132 = AMPP_FUNCTION(L1_d_readdata_d1[11], L1_d_readdata_d1[27], L1_M_ld_align_sh16);
--L1_av_ld_data_aligned_or_div[11] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[11]
--operation mode is normal
L1_av_ld_data_aligned_or_div[11] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[11], L1_d_readdata_d1[27], L1_av_fill_bit, L1_M_ld_align_sh16, E1_data_out, L1L827);
--L1L1372 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[11]~3682
--operation mode is normal
L1L1372 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[11], L1_M_alu_result[11], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L793 is std_1s10:inst|cpu:the_cpu|E_sth_data[11]~476
--operation mode is normal
L1L793 = AMPP_FUNCTION(L1_E_src2_prelim[11], L1_E_src2_hazard_M, L1L1371, L1L1372);
--L1L661 is std_1s10:inst|cpu:the_cpu|E_src2[11]~1509
--operation mode is normal
L1L661 = AMPP_FUNCTION(L1_E_src2_imm[11], L1L793, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[11] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[11]
--operation mode is normal
L1_E_src1_prelim[11] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[11], L1_W_wr_data[11], L1L1373, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L595 is std_1s10:inst|cpu:the_cpu|E_src1[11]~1983
--operation mode is normal
L1L595 = AMPP_FUNCTION(L1_E_src1_prelim[11], L1_E_src1_hazard_M, L1L1371, L1L1372);
--L1L524 is std_1s10:inst|cpu:the_cpu|E_logic_result[11]~16132
--operation mode is normal
L1L524 = AMPP_FUNCTION(L1_E_logic_op[1], L1L661, L1L595, L1_E_logic_op[0]);
--L1_E_extra_pc[8] is std_1s10:inst|cpu:the_cpu|E_extra_pc[8]
--operation mode is normal
L1_E_extra_pc[8] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[8], L1_D_br_taken_waddr_partial[8], L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[10] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[10]
--operation mode is arithmetic
HC1_result[10] = AMPP_FUNCTION(L1L660, L1L594, HC1L21, L1_E_ctrl_alu_subtract);
--HC1L23 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[10]~COUT
--operation mode is arithmetic
HC1L23 = AMPP_FUNCTION(L1L660, L1L594, HC1L21, L1_E_ctrl_alu_subtract);
--L1L26 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12906
--operation mode is normal
L1L26 = AMPP_FUNCTION(L1_E_extra_pc[8], HC1_result[10], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src2_imm[10] is std_1s10:inst|cpu:the_cpu|E_src2_imm[10]
--operation mode is normal
L1_E_src2_imm[10] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[16], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[10] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[10]
--operation mode is normal
L1_E_src2_prelim[10] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[10], L1_W_wr_data[10], L1L1370, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_M_mul_shift_rot_result[10] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[10]
--operation mode is normal
L1_M_mul_shift_rot_result[10] = AMPP_FUNCTION(DE1__clk0, QC1_result[10], QC1_result[42], L1L1226, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1368 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[10]~3683
--operation mode is normal
L1L1368 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[10], L1_M_ctrl_mul_shift_rot);
--L1L130 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[10]~COMBOUT
--operation mode is normal
L1L130 = AMPP_FUNCTION(L1_d_readdata_d1[10], L1_d_readdata_d1[26], L1_M_ld_align_sh16);
--L1_av_ld_data_aligned_or_div[10] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[10]
--operation mode is normal
L1_av_ld_data_aligned_or_div[10] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[10], L1_d_readdata_d1[26], L1_av_fill_bit, L1_M_ld_align_sh16, E1_data_out, L1L827);
--L1L1369 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[10]~3684
--operation mode is normal
L1L1369 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[10], L1_M_alu_result[10], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L792 is std_1s10:inst|cpu:the_cpu|E_sth_data[10]~477
--operation mode is normal
L1L792 = AMPP_FUNCTION(L1_E_src2_prelim[10], L1_E_src2_hazard_M, L1L1368, L1L1369);
--L1L660 is std_1s10:inst|cpu:the_cpu|E_src2[10]~1510
--operation mode is normal
L1L660 = AMPP_FUNCTION(L1_E_src2_imm[10], L1L792, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[10] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[10]
--operation mode is normal
L1_E_src1_prelim[10] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[10], L1_W_wr_data[10], L1L1370, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L594 is std_1s10:inst|cpu:the_cpu|E_src1[10]~1984
--operation mode is normal
L1L594 = AMPP_FUNCTION(L1_E_src1_prelim[10], L1_E_src1_hazard_M, L1L1368, L1L1369);
--L1L523 is std_1s10:inst|cpu:the_cpu|E_logic_result[10]~16133
--operation mode is normal
L1L523 = AMPP_FUNCTION(L1_E_logic_op[1], L1L660, L1L594, L1_E_logic_op[0]);
--L1_E_extra_pc[7] is std_1s10:inst|cpu:the_cpu|E_extra_pc[7]
--operation mode is normal
L1_E_extra_pc[7] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[7], L1_D_br_taken_waddr_partial[7], L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[9] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[9]
--operation mode is arithmetic
HC1_result[9] = AMPP_FUNCTION(L1L659, L1L593, HC1L19, L1_E_ctrl_alu_subtract);
--HC1L21 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[9]~COUT
--operation mode is arithmetic
HC1L21 = AMPP_FUNCTION(L1L659, L1L593, HC1L19, L1_E_ctrl_alu_subtract);
--L1L27 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12907
--operation mode is normal
L1L27 = AMPP_FUNCTION(L1_E_extra_pc[7], HC1_result[9], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src2_imm[9] is std_1s10:inst|cpu:the_cpu|E_src2_imm[9]
--operation mode is normal
L1_E_src2_imm[9] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[15], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[9] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[9]
--operation mode is normal
L1_E_src2_prelim[9] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[9], L1_W_wr_data[9], L1L1367, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_M_mul_shift_rot_result[9] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[9]
--operation mode is normal
L1_M_mul_shift_rot_result[9] = AMPP_FUNCTION(DE1__clk0, QC1_result[9], QC1_result[41], L1L1225, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1365 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[9]~3685
--operation mode is normal
L1L1365 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[9], L1_M_ctrl_mul_shift_rot);
--L1L128 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[9]~COMBOUT
--operation mode is normal
L1L128 = AMPP_FUNCTION(L1_d_readdata_d1[9], L1_d_readdata_d1[25], L1_M_ld_align_sh16);
--L1_av_ld_data_aligned_or_div[9] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[9]
--operation mode is normal
L1_av_ld_data_aligned_or_div[9] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[9], L1_d_readdata_d1[25], L1_av_fill_bit, L1_M_ld_align_sh16, E1_data_out, L1L827);
--L1L1366 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[9]~3686
--operation mode is normal
L1L1366 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[9], L1_M_alu_result[9], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L791 is std_1s10:inst|cpu:the_cpu|E_sth_data[9]~478
--operation mode is normal
L1L791 = AMPP_FUNCTION(L1_E_src2_prelim[9], L1_E_src2_hazard_M, L1L1365, L1L1366);
--L1L659 is std_1s10:inst|cpu:the_cpu|E_src2[9]~1511
--operation mode is normal
L1L659 = AMPP_FUNCTION(L1_E_src2_imm[9], L1L791, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[9] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[9]
--operation mode is normal
L1_E_src1_prelim[9] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[9], L1_W_wr_data[9], L1L1367, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L593 is std_1s10:inst|cpu:the_cpu|E_src1[9]~1985
--operation mode is normal
L1L593 = AMPP_FUNCTION(L1_E_src1_prelim[9], L1_E_src1_hazard_M, L1L1365, L1L1366);
--L1L522 is std_1s10:inst|cpu:the_cpu|E_logic_result[9]~16134
--operation mode is normal
L1L522 = AMPP_FUNCTION(L1_E_logic_op[1], L1L659, L1L593, L1_E_logic_op[0]);
--L1_E_extra_pc[6] is std_1s10:inst|cpu:the_cpu|E_extra_pc[6]
--operation mode is normal
L1_E_extra_pc[6] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[6], L1_D_br_taken_waddr_partial[6], L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[8] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[8]
--operation mode is arithmetic
HC1_result[8] = AMPP_FUNCTION(L1L658, L1L592, HC1L17, L1_E_ctrl_alu_subtract);
--HC1L19 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[8]~COUT
--operation mode is arithmetic
HC1L19 = AMPP_FUNCTION(L1L658, L1L592, HC1L17, L1_E_ctrl_alu_subtract);
--L1L28 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12908
--operation mode is normal
L1L28 = AMPP_FUNCTION(L1_E_extra_pc[6], HC1_result[8], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src2_imm[8] is std_1s10:inst|cpu:the_cpu|E_src2_imm[8]
--operation mode is normal
L1_E_src2_imm[8] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[14], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[8] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[8]
--operation mode is normal
L1_E_src2_prelim[8] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[8], L1_W_wr_data[8], L1L1364, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_M_mul_shift_rot_result[8] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[8]
--operation mode is normal
L1_M_mul_shift_rot_result[8] = AMPP_FUNCTION(DE1__clk0, QC1_result[8], QC1_result[40], L1L1224, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1362 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[8]~3687
--operation mode is normal
L1L1362 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[8], L1_M_ctrl_mul_shift_rot);
--L1L126 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[8]~COMBOUT
--operation mode is normal
L1L126 = AMPP_FUNCTION(L1_d_readdata_d1[8], L1_d_readdata_d1[24], L1_M_ld_align_sh16);
--L1_av_ld_data_aligned_or_div[8] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[8]
--operation mode is normal
L1_av_ld_data_aligned_or_div[8] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[8], L1_d_readdata_d1[24], L1_av_fill_bit, L1_M_ld_align_sh16, E1_data_out, L1L827);
--L1L1363 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[8]~3688
--operation mode is normal
L1L1363 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[8], L1_M_alu_result[8], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L790 is std_1s10:inst|cpu:the_cpu|E_sth_data[8]~479
--operation mode is normal
L1L790 = AMPP_FUNCTION(L1_E_src2_prelim[8], L1_E_src2_hazard_M, L1L1362, L1L1363);
--L1L658 is std_1s10:inst|cpu:the_cpu|E_src2[8]~1512
--operation mode is normal
L1L658 = AMPP_FUNCTION(L1_E_src2_imm[8], L1L790, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[8] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[8]
--operation mode is normal
L1_E_src1_prelim[8] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[8], L1_W_wr_data[8], L1L1364, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L592 is std_1s10:inst|cpu:the_cpu|E_src1[8]~1986
--operation mode is normal
L1L592 = AMPP_FUNCTION(L1_E_src1_prelim[8], L1_E_src1_hazard_M, L1L1362, L1L1363);
--L1L521 is std_1s10:inst|cpu:the_cpu|E_logic_result[8]~16135
--operation mode is normal
L1L521 = AMPP_FUNCTION(L1_E_logic_op[1], L1L658, L1L592, L1_E_logic_op[0]);
--L1_E_control_rd_data_without_mmu_regs[5] is std_1s10:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[5]
--operation mode is normal
L1_E_control_rd_data_without_mmu_regs[5] = AMPP_FUNCTION(DE1__clk0, L1_M_ipending_reg[5], L1_M_ienable_reg[5], L1_D_iw[8], L1L186, E1_data_out, L1_W_stall);
--L1_E_src1_prelim[5] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[5]
--operation mode is normal
L1_E_src1_prelim[5] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[5], L1_W_wr_data[5], L1L1355, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[5] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[5]
--operation mode is normal
L1_M_mul_shift_rot_result[5] = AMPP_FUNCTION(DE1__clk0, QC1_result[5], QC1_result[37], L1L1221, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1353 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[5]~3689
--operation mode is normal
L1L1353 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[5], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[5] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[5]
--operation mode is normal
L1_av_ld_data_aligned_or_div[5] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[5], L1_d_readdata_d1[21], L1L136, L1_M_ld_align_sh16, E1_data_out, L1_M_ld_align_sh8);
--L1L1354 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[5]~3690
--operation mode is normal
L1L1354 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[5], L1_M_alu_result[5], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L589 is std_1s10:inst|cpu:the_cpu|E_src1[5]~1987
--operation mode is normal
L1L589 = AMPP_FUNCTION(L1_E_src1_prelim[5], L1_E_src1_hazard_M, L1L1353, L1L1354);
--L1_E_src2_imm[5] is std_1s10:inst|cpu:the_cpu|E_src2_imm[5]
--operation mode is normal
L1_E_src2_imm[5] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[11], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1L1298 is std_1s10:inst|cpu:the_cpu|M_st_data[13]~COMBOUT
--operation mode is normal
L1L1298 = AMPP_FUNCTION(L1_E_src2_prelim[5], L1L1355, L1_E_src2_hazard_M);
--L1_M_st_data[13] is std_1s10:inst|cpu:the_cpu|M_st_data[13]
--operation mode is normal
L1_M_st_data[13] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[5], L1L1355, L1L795, L1_E_src2_hazard_M, E1_data_out, L1L826, L1_W_stall);
--L1L655 is std_1s10:inst|cpu:the_cpu|E_src2[5]~1513
--operation mode is normal
L1L655 = AMPP_FUNCTION(L1_E_src2_imm[5], L1L1298, L1_E_ctrl_src2_is_imm);
--L1L29 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12909
--operation mode is normal
L1L29 = AMPP_FUNCTION(L1_E_logic_op[1], L1L589, L1L655, L1_E_logic_op[0]);
--L1_E_extra_pc[3] is std_1s10:inst|cpu:the_cpu|E_extra_pc[3]
--operation mode is normal
L1_E_extra_pc[3] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[3], L1_D_br_taken_waddr_partial[3], L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[5] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[5]
--operation mode is arithmetic
HC1_result[5] = AMPP_FUNCTION(L1L655, L1L589, HC1L11, L1_E_ctrl_alu_subtract);
--HC1L13 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[5]~COUT
--operation mode is arithmetic
HC1L13 = AMPP_FUNCTION(L1L655, L1L589, HC1L11, L1_E_ctrl_alu_subtract);
--L1L30 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12910
--operation mode is normal
L1L30 = AMPP_FUNCTION(L1_E_extra_pc[3], HC1_result[5], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1L31 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12911
--operation mode is normal
L1L31 = AMPP_FUNCTION(L1L29, L1L30, L1_E_ctrl_dst_data_sel_logic_result);
--L1L413 is std_1s10:inst|cpu:the_cpu|E_alu_result[5]~2249
--operation mode is normal
L1L413 = AMPP_FUNCTION(L1_E_control_rd_data_without_mmu_regs[5], L1L31, L1_E_ctrl_rdctl_inst, L1_E_ctrl_dst_data_sel_cmp);
--L1_E_ctrl_st is std_1s10:inst|cpu:the_cpu|E_ctrl_st
--operation mode is normal
L1_E_ctrl_st = AMPP_FUNCTION(DE1__clk0, L1_D_iw[0], L1_D_iw[1], E1_data_out, L1_W_stall);
--L1_E_extra_pc[4] is std_1s10:inst|cpu:the_cpu|E_extra_pc[4]
--operation mode is normal
L1_E_extra_pc[4] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[4], L1_D_br_taken_waddr_partial[4], L1L199, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[6] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[6]
--operation mode is arithmetic
HC1_result[6] = AMPP_FUNCTION(L1L656, L1L590, HC1L13, L1_E_ctrl_alu_subtract);
--HC1L15 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[6]~COUT
--operation mode is arithmetic
HC1L15 = AMPP_FUNCTION(L1L656, L1L590, HC1L13, L1_E_ctrl_alu_subtract);
--L1L32 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12912
--operation mode is normal
L1L32 = AMPP_FUNCTION(L1_E_extra_pc[4], HC1_result[6], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src1_prelim[6] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[6]
--operation mode is normal
L1_E_src1_prelim[6] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[6], L1_W_wr_data[6], L1L1358, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[6] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[6]
--operation mode is normal
L1_M_mul_shift_rot_result[6] = AMPP_FUNCTION(DE1__clk0, QC1_result[6], QC1_result[38], L1L1222, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1356 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[6]~3691
--operation mode is normal
L1L1356 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[6], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[6] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[6]
--operation mode is normal
L1_av_ld_data_aligned_or_div[6] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[6], L1_d_readdata_d1[22], L1L138, L1_M_ld_align_sh16, E1_data_out, L1_M_ld_align_sh8);
--L1L1357 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[6]~3692
--operation mode is normal
L1L1357 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[6], L1_M_alu_result[6], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L590 is std_1s10:inst|cpu:the_cpu|E_src1[6]~1988
--operation mode is normal
L1L590 = AMPP_FUNCTION(L1_E_src1_prelim[6], L1_E_src1_hazard_M, L1L1356, L1L1357);
--L1_E_src2_imm[6] is std_1s10:inst|cpu:the_cpu|E_src2_imm[6]
--operation mode is normal
L1_E_src2_imm[6] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[12], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1L1300 is std_1s10:inst|cpu:the_cpu|M_st_data[14]~COMBOUT
--operation mode is normal
L1L1300 = AMPP_FUNCTION(L1_E_src2_prelim[6], L1L1358, L1_E_src2_hazard_M);
--L1_M_st_data[14] is std_1s10:inst|cpu:the_cpu|M_st_data[14]
--operation mode is normal
L1_M_st_data[14] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[6], L1L1358, L1L796, L1_E_src2_hazard_M, E1_data_out, L1L826, L1_W_stall);
--L1L656 is std_1s10:inst|cpu:the_cpu|E_src2[6]~1514
--operation mode is normal
L1L656 = AMPP_FUNCTION(L1_E_src2_imm[6], L1L1300, L1_E_ctrl_src2_is_imm);
--L1L519 is std_1s10:inst|cpu:the_cpu|E_logic_result[6]~16136
--operation mode is normal
L1L519 = AMPP_FUNCTION(L1_E_logic_op[1], L1L590, L1L656, L1_E_logic_op[0]);
--W1L1 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~99
--operation mode is arithmetic
W1L1 = W1_lcd_display_control_slave_wait_counter[1] $ (!W1L1_carry_eqn);
--W1L2 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~100
--operation mode is arithmetic
W1L2 = CARRY(!W1_lcd_display_control_slave_wait_counter[1] & (!W1L4));
--W1L23 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[1]~60
--operation mode is normal
W1L23 = !W1_lcd_display_control_slave_wait_counter[1] & !W1_lcd_display_control_slave_wait_counter[2];
--W1L15 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Equal2~91
--operation mode is normal
W1L15 = W1L29 & W1L23 & !W1_lcd_display_control_slave_wait_counter[0] & !W1_lcd_display_control_slave_wait_counter[3];
--W1L19 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_in_a_write_cycle~37
--operation mode is normal
W1L19 = L1_M_alu_result[7] & L1_internal_d_write & G1L1 & !W1_d1_reasons_to_wait;
--W1L3 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~101
--operation mode is arithmetic
W1L3 = !W1_lcd_display_control_slave_wait_counter[0];
--W1L4 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~102
--operation mode is arithmetic
W1L4 = CARRY(W1_lcd_display_control_slave_wait_counter[0]);
--W1L17 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_counter_load_value~1
--operation mode is normal
W1L17 = W1_d1_reasons_to_wait # !G1L1 # !L1_internal_d_read # !L1_M_alu_result[7];
--W1L5 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~103
--operation mode is arithmetic
W1L5 = W1_lcd_display_control_slave_wait_counter[3] $ (!W1L5_carry_eqn);
--W1L6 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~104
--operation mode is arithmetic
W1L6 = CARRY(!W1_lcd_display_control_slave_wait_counter[3] & (!W1L8));
--W1L7 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~105
--operation mode is arithmetic
W1L7 = W1_lcd_display_control_slave_wait_counter[2] $ (W1L7_carry_eqn);
--W1L8 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~106
--operation mode is arithmetic
W1L8 = CARRY(W1_lcd_display_control_slave_wait_counter[2] # !W1L2);
--W1L9 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~107
--operation mode is normal
W1L9 = W1_lcd_display_control_slave_wait_counter[5] $ (!W1L9_carry_eqn);
--W1L10 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~109
--operation mode is arithmetic
W1L10 = W1_lcd_display_control_slave_wait_counter[4] $ (W1L10_carry_eqn);
--W1L11 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~110
--operation mode is arithmetic
W1L11 = CARRY(W1_lcd_display_control_slave_wait_counter[4] # !W1L6);
--HC1_result[0] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[0]
--operation mode is arithmetic
HC1_result[0] = AMPP_FUNCTION(L1L650, L1L584);
--HC1L3 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUT
--operation mode is arithmetic
HC1L3 = AMPP_FUNCTION(L1L650, L1L584, L1_E_ctrl_alu_subtract);
--HC1_result[1] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[1]
--operation mode is arithmetic
HC1_result[1] = AMPP_FUNCTION(L1L651, L1L585, HC1L3, L1_E_ctrl_alu_subtract);
--HC1L5 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUT
--operation mode is arithmetic
HC1L5 = AMPP_FUNCTION(L1L651, L1L585, HC1L3, L1_E_ctrl_alu_subtract);
--HE1_control_reg[9] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[9]
--operation mode is normal
HE1_control_reg[9]_lut_out = L1_M_st_data[9];
HE1_control_reg[9] = DFFEAS(HE1_control_reg[9]_lut_out, DE1__clk0, E1_data_out, , HE1L13, , , , );
--KE1_pre_txd is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd
--operation mode is normal
KE1_pre_txd_lut_out = !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] & (KE1_pre_txd # !KE1L28);
KE1_pre_txd = DFFEAS(KE1_pre_txd_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L287 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_select_n_to_the_ext_flash~0
--operation mode is normal
Q1L287 = Q1L80 # Q1L52 & (Q1L12 # Q1L14);
--Q1L281 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[22]~3312
--operation mode is normal
Q1L281 = !Q1L82 & (!Q1L8 & !Q1L10 # !Q1L58);
--Q1L46 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_ext_flash_s1~55
--operation mode is normal
Q1L46 = Q1L52 & (Q1L12 # Q1L14);
--Q1L282 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[22]~3313
--operation mode is normal
Q1L282 = L1_ic_fill_tag[10] & !Q1L46 & (Q1L80 # !Q1L47);
--Q1L280 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[21]~3315
--operation mode is normal
Q1L280 = L1_ic_fill_tag[9] & !Q1L46 & (Q1L80 # !Q1L47);
--Q1L279 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[20]~3317
--operation mode is normal
Q1L279 = L1_ic_fill_tag[8] & !Q1L46 & (Q1L80 # !Q1L47);
--Q1L283 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[22]~3319
--operation mode is normal
Q1L283 = !Q1L46 & (Q1L80 # !Q1L47);
--L1_ic_fill_tag[3] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[3]
--operation mode is normal
L1_ic_fill_tag[3] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[13], E1_data_out, L1_D_ic_fill_starting);
--Q1L278 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[15]~3324
--operation mode is normal
Q1L278 = Q1L82 # !Q1L46 & (Q1L80 # !Q1L47);
--L1_ic_fill_tag[2] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[2]
--operation mode is normal
L1_ic_fill_tag[2] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[12], E1_data_out, L1_D_ic_fill_starting);
--L1_ic_fill_tag[1] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[1]
--operation mode is normal
L1_ic_fill_tag[1] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[11], E1_data_out, L1_D_ic_fill_starting);
--L1_ic_fill_tag[0] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[0]
--operation mode is normal
L1_ic_fill_tag[0] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[10], E1_data_out, L1_D_ic_fill_starting);
--L1_ic_fill_line[6] is std_1s10:inst|cpu:the_cpu|ic_fill_line[6]
--operation mode is normal
L1_ic_fill_line[6] = AMPP_FUNCTION(DE1__clk0, L1L1089, E1_data_out);
--L1_ic_fill_line[5] is std_1s10:inst|cpu:the_cpu|ic_fill_line[5]
--operation mode is normal
L1_ic_fill_line[5] = AMPP_FUNCTION(DE1__clk0, L1L1087, E1_data_out);
--L1_ic_fill_line[4] is std_1s10:inst|cpu:the_cpu|ic_fill_line[4]
--operation mode is normal
L1_ic_fill_line[4] = AMPP_FUNCTION(DE1__clk0, L1L1085, E1_data_out);
--L1_ic_fill_line[3] is std_1s10:inst|cpu:the_cpu|ic_fill_line[3]
--operation mode is normal
L1_ic_fill_line[3] = AMPP_FUNCTION(DE1__clk0, L1L1083, E1_data_out);
--L1_ic_fill_line[2] is std_1s10:inst|cpu:the_cpu|ic_fill_line[2]
--operation mode is normal
L1_ic_fill_line[2] = AMPP_FUNCTION(DE1__clk0, L1L1081, E1_data_out);
--L1_ic_fill_line[1] is std_1s10:inst|cpu:the_cpu|ic_fill_line[1]
--operation mode is normal
L1_ic_fill_line[1] = AMPP_FUNCTION(DE1__clk0, L1L1079, E1_data_out);
--L1_ic_fill_line[0] is std_1s10:inst|cpu:the_cpu|ic_fill_line[0]
--operation mode is normal
L1_ic_fill_line[0] = AMPP_FUNCTION(DE1__clk0, L1L1038, E1_data_out);
--L1_ic_fill_ap_offset[2] is std_1s10:inst|cpu:the_cpu|ic_fill_ap_offset[2]
--operation mode is normal
L1_ic_fill_ap_offset[2] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[2], L1_ic_fill_ap_offset[2], L1L110, L1_D_ic_fill_starting, E1_data_out, N1L153);
--L1_ic_fill_ap_offset[1] is std_1s10:inst|cpu:the_cpu|ic_fill_ap_offset[1]
--operation mode is normal
L1_ic_fill_ap_offset[1] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[1], L1_ic_fill_ap_offset[1], L1L111, L1_D_ic_fill_starting, E1_data_out, N1L153);
--L1_ic_fill_ap_offset[0] is std_1s10:inst|cpu:the_cpu|ic_fill_ap_offset[0]
--operation mode is normal
L1_ic_fill_ap_offset[0] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[0], L1_ic_fill_ap_offset[0], L1L1013, L1_D_ic_fill_starting, E1_data_out, N1L153);
--L1_M_alu_result[1] is std_1s10:inst|cpu:the_cpu|M_alu_result[1]
--operation mode is normal
L1_M_alu_result[1] = AMPP_FUNCTION(DE1__clk0, L1L409, E1_data_out, L1_W_stall);
--Q1L276 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[1]~3339
--operation mode is normal
Q1L276 = !Q1L82 & (!Q1L16 & !Q1L18 # !N1L146);
--Q1L274 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[0]~3340
--operation mode is normal
Q1L274 = Q1L48 # Q1L47 & Q1L276 & !Q1L46;
--N1_internal_cpu_instruction_master_dbs_address[1] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]
--operation mode is normal
N1_internal_cpu_instruction_master_dbs_address[1]_lut_out = N1_internal_cpu_instruction_master_dbs_address[1] $ (Q1L80 & N1_internal_cpu_instruction_master_dbs_address[0] & N1L147);
N1_internal_cpu_instruction_master_dbs_address[1] = DFFEAS(N1_internal_cpu_instruction_master_dbs_address[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L277 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[1]~3341
--operation mode is normal
Q1L277 = Q1L46 & M1_internal_cpu_data_master_dbs_address[1] # !Q1L46 & (Q1L80 & N1_internal_cpu_instruction_master_dbs_address[1]);
--L1_M_alu_result[0] is std_1s10:inst|cpu:the_cpu|M_alu_result[0]
--operation mode is normal
L1_M_alu_result[0] = AMPP_FUNCTION(DE1__clk0, L1L406, E1_data_out, L1_W_stall);
--N1_internal_cpu_instruction_master_dbs_address[0] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[0]
--operation mode is normal
N1_internal_cpu_instruction_master_dbs_address[0]_lut_out = N1_internal_cpu_instruction_master_dbs_address[0] $ (Q1_d1_ext_ram_bus_avalon_slave_end_xfer & Q1L134 & Q1L80);
N1_internal_cpu_instruction_master_dbs_address[0] = DFFEAS(N1_internal_cpu_instruction_master_dbs_address[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L275 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[0]~3343
--operation mode is normal
Q1L275 = Q1L46 & M1_internal_cpu_data_master_dbs_address[0] # !Q1L46 & (Q1L80 & N1_internal_cpu_instruction_master_dbs_address[0]);
--L1_M_st_data[7] is std_1s10:inst|cpu:the_cpu|M_st_data[7]
--operation mode is normal
L1_M_st_data[7] = AMPP_FUNCTION(DE1__clk0, L1L1302, E1_data_out, L1_W_stall);
--X1L11 is std_1s10:inst|led_pio:the_led_pio|process0~51
--operation mode is normal
X1L11 = L1_M_alu_result[7] & (!L1_M_alu_result[5]);
--HE1L14 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~98
--operation mode is normal
HE1L14 = !L1_M_alu_result[2] & !L1_M_alu_result[3];
--X1L12 is std_1s10:inst|led_pio:the_led_pio|process0~52
--operation mode is normal
X1L12 = L1_internal_d_write & HE1L14 & !L1_M_alu_result[6] & !M1_internal_cpu_data_master_waitrequest;
--X1L10 is std_1s10:inst|led_pio:the_led_pio|process0~1
--operation mode is normal
X1L10 = L1_M_mem_byte_en[0] & X1L13 & X1L12 & !L1_M_alu_result[4];
--L1_M_st_data[6] is std_1s10:inst|cpu:the_cpu|M_st_data[6]
--operation mode is normal
L1_M_st_data[6] = AMPP_FUNCTION(DE1__clk0, L1L1300, E1_data_out, L1_W_stall);
--L1_M_st_data[5] is std_1s10:inst|cpu:the_cpu|M_st_data[5]
--operation mode is normal
L1_M_st_data[5] = AMPP_FUNCTION(DE1__clk0, L1L1298, E1_data_out, L1_W_stall);
--L1_M_st_data[4] is std_1s10:inst|cpu:the_cpu|M_st_data[4]
--operation mode is normal
L1_M_st_data[4] = AMPP_FUNCTION(DE1__clk0, L1L1296, E1_data_out, L1_W_stall);
--L1_M_st_data[3] is std_1s10:inst|cpu:the_cpu|M_st_data[3]
--operation mode is normal
L1_M_st_data[3] = AMPP_FUNCTION(DE1__clk0, L1L1294, E1_data_out, L1_W_stall);
--L1_M_st_data[2] is std_1s10:inst|cpu:the_cpu|M_st_data[2]
--operation mode is normal
L1_M_st_data[2] = AMPP_FUNCTION(DE1__clk0, L1L1292, E1_data_out, L1_W_stall);
--L1_M_st_data[1] is std_1s10:inst|cpu:the_cpu|M_st_data[1]
--operation mode is normal
L1_M_st_data[1] = AMPP_FUNCTION(DE1__clk0, L1L1290, E1_data_out, L1_W_stall);
--L1_M_st_data[0] is std_1s10:inst|cpu:the_cpu|M_st_data[0]
--operation mode is normal
L1_M_st_data[0] = AMPP_FUNCTION(DE1__clk0, L1L1288, E1_data_out, L1_W_stall);
--HB1L18 is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|process0~1
--operation mode is normal
HB1L18 = L1_M_alu_result[4] & X1L13 & X1L12;
--L1L1290 is std_1s10:inst|cpu:the_cpu|M_st_data[9]~COMBOUT
--operation mode is normal
L1L1290 = AMPP_FUNCTION(L1_E_src2_prelim[1], L1L1343, L1_E_src2_hazard_M);
--L1_M_st_data[9] is std_1s10:inst|cpu:the_cpu|M_st_data[9]
--operation mode is normal
L1_M_st_data[9] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[1], L1L1343, L1L791, L1_E_src2_hazard_M, E1_data_out, L1L826, L1_W_stall);
--L1L1288 is std_1s10:inst|cpu:the_cpu|M_st_data[8]~COMBOUT
--operation mode is normal
L1L1288 = AMPP_FUNCTION(L1_E_src2_prelim[0], L1L1340, L1_E_src2_hazard_M);
--L1_M_st_data[8] is std_1s10:inst|cpu:the_cpu|M_st_data[8]
--operation mode is normal
L1_M_st_data[8] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[0], L1L1340, L1L790, L1_E_src2_hazard_M, E1_data_out, L1L826, L1_W_stall);
--FB1L425 is std_1s10:inst|sdram:the_sdram|Mux104~1566
--operation mode is normal
FB1L425 = FB1_m_state[0] & !FB1_m_state[4] & !FB1_m_state[3] & !FB1_m_state[6];
--FB1_i_addr[0] is std_1s10:inst|sdram:the_sdram|i_addr[0]
--operation mode is normal
FB1_i_addr[0]_lut_out = FB1_i_state[0] & FB1_i_state[2] & FB1_i_state[1];
FB1_i_addr[0] = DFFEAS(FB1_i_addr[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1L426 is std_1s10:inst|sdram:the_sdram|Mux104~1567
--operation mode is normal
FB1L426 = FB1_init_done & FB1_m_addr[11] # !FB1_init_done & (FB1L348 & (!FB1_i_addr[0]) # !FB1L348 & FB1_m_addr[11]);
--FB1L427 is std_1s10:inst|sdram:the_sdram|Mux104~1568
--operation mode is normal
FB1L427 = FB1_m_addr[11] & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L428 is std_1s10:inst|sdram:the_sdram|Mux104~1569
--operation mode is normal
FB1L428 = FB1_m_state[6] & (!FB1_m_state[0]) # !FB1_m_state[6] & (FB1_m_state[0] & (FB1L427) # !FB1_m_state[0] & FB1L426);
--FB1L429 is std_1s10:inst|sdram:the_sdram|Mux104~1570
--operation mode is normal
FB1L429 = FB1_m_state[6] & (FB1_m_addr[11] # FB1L348 & !FB1L428) # !FB1_m_state[6] & (FB1L428);
--FB1L430 is std_1s10:inst|sdram:the_sdram|Mux104~1571
--operation mode is normal
FB1L430 = FB1_m_state[1] & FB1_active_addr[20] & FB1L425 # !FB1_m_state[1] & (FB1L429);
--FB1L431 is std_1s10:inst|sdram:the_sdram|Mux104~1572
--operation mode is normal
FB1L431 = FB1_m_state[1] & (!FB1L425);
--FB1L432 is std_1s10:inst|sdram:the_sdram|Mux104~1573
--operation mode is normal
FB1L432 = FB1_m_state[7] # FB1_m_state[8] # FB1_m_state[5] # FB1_m_state[2];
--FB1L433 is std_1s10:inst|sdram:the_sdram|Mux105~1395
--operation mode is normal
FB1L433 = FB1_init_done & FB1_m_addr[10] # !FB1_init_done & (FB1L348 & (!FB1_i_addr[0]) # !FB1L348 & FB1_m_addr[10]);
--FB1L434 is std_1s10:inst|sdram:the_sdram|Mux105~1396
--operation mode is normal
FB1L434 = FB1_m_addr[10] & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L435 is std_1s10:inst|sdram:the_sdram|Mux105~1397
--operation mode is normal
FB1L435 = FB1_m_state[6] & (!FB1_m_state[0]) # !FB1_m_state[6] & (FB1_m_state[0] & (FB1L434) # !FB1_m_state[0] & FB1L433);
--FB1L436 is std_1s10:inst|sdram:the_sdram|Mux105~1398
--operation mode is normal
FB1L436 = FB1_m_state[6] & (FB1_m_addr[10] # FB1L348 & !FB1L435) # !FB1_m_state[6] & (FB1L435);
--FB1L437 is std_1s10:inst|sdram:the_sdram|Mux105~1399
--operation mode is normal
FB1L437 = FB1_m_state[1] & FB1_active_addr[19] & FB1L425 # !FB1_m_state[1] & (FB1L436);
--FB1L438 is std_1s10:inst|sdram:the_sdram|Mux106~1395
--operation mode is normal
FB1L438 = FB1_init_done & FB1_m_addr[9] # !FB1_init_done & (FB1L348 & (!FB1_i_addr[0]) # !FB1L348 & FB1_m_addr[9]);
--FB1L439 is std_1s10:inst|sdram:the_sdram|Mux106~1396
--operation mode is normal
FB1L439 = FB1_m_addr[9] & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L440 is std_1s10:inst|sdram:the_sdram|Mux106~1397
--operation mode is normal
FB1L440 = FB1_m_state[6] & (!FB1_m_state[0]) # !FB1_m_state[6] & (FB1_m_state[0] & (FB1L439) # !FB1_m_state[0] & FB1L438);
--FB1L441 is std_1s10:inst|sdram:the_sdram|Mux106~1398
--operation mode is normal
FB1L441 = FB1_m_state[6] & (FB1_m_addr[9] # FB1L348 & !FB1L440) # !FB1_m_state[6] & (FB1L440);
--FB1L442 is std_1s10:inst|sdram:the_sdram|Mux106~1399
--operation mode is normal
FB1L442 = FB1_m_state[1] & FB1_active_addr[18] & FB1L425 # !FB1_m_state[1] & (FB1L441);
--FB1L443 is std_1s10:inst|sdram:the_sdram|Mux107~1395
--operation mode is normal
FB1L443 = FB1_init_done & FB1_m_addr[8] # !FB1_init_done & (FB1L348 & (!FB1_i_addr[0]) # !FB1L348 & FB1_m_addr[8]);
--FB1L444 is std_1s10:inst|sdram:the_sdram|Mux107~1396
--operation mode is normal
FB1L444 = FB1_m_addr[8] & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L445 is std_1s10:inst|sdram:the_sdram|Mux107~1397
--operation mode is normal
FB1L445 = FB1_m_state[6] & (!FB1_m_state[0]) # !FB1_m_state[6] & (FB1_m_state[0] & (FB1L444) # !FB1_m_state[0] & FB1L443);
--FB1L446 is std_1s10:inst|sdram:the_sdram|Mux107~1398
--operation mode is normal
FB1L446 = FB1_m_state[6] & (FB1_m_addr[8] # FB1L348 & !FB1L445) # !FB1_m_state[6] & (FB1L445);
--FB1L447 is std_1s10:inst|sdram:the_sdram|Mux107~1399
--operation mode is normal
FB1L447 = FB1_m_state[1] & FB1_active_addr[17] & FB1L425 # !FB1_m_state[1] & (FB1L446);
--FB1L448 is std_1s10:inst|sdram:the_sdram|Mux108~1481
--operation mode is normal
FB1L448 = FB1_m_state[0] & !FB1_m_state[4] & !FB1_m_state[3] & !FB1_m_state[1];
--FB1L449 is std_1s10:inst|sdram:the_sdram|Mux108~1482
--operation mode is normal
FB1L449 = FB1_m_state[4] & FB1_m_addr[7] # !FB1_m_state[4] & (FB1_m_state[3] & FB1_m_addr[7] # !FB1_m_state[3] & (FB1_active_addr[16]));
--FB1L450 is std_1s10:inst|sdram:the_sdram|Mux108~1483
--operation mode is normal
FB1L450 = FB1_init_done & FB1_m_addr[7] # !FB1_init_done & (FB1L348 & (!FB1_i_addr[0]) # !FB1L348 & FB1_m_addr[7]);
--EE1_entry_1[43] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[43]
--operation mode is normal
EE1_entry_1[43]_lut_out = GB1L37;
EE1_entry_1[43] = DFFEAS(EE1_entry_1[43]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[43] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[43]
--operation mode is normal
EE1_entry_0[43]_lut_out = GB1L37;
EE1_entry_0[43] = DFFEAS(EE1_entry_0[43]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L172 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[43]~495
--operation mode is normal
EE1L172 = EE1_rd_address & EE1_entry_1[43] # !EE1_rd_address & (EE1_entry_0[43]);
--FB1_active_addr[7] is std_1s10:inst|sdram:the_sdram|active_addr[7]
--operation mode is normal
FB1_active_addr[7]_lut_out = FB1L12 & (FB1L14 & (EE1L172) # !FB1L14 & FB1_active_addr[7]) # !FB1L12 & FB1_active_addr[7];
FB1_active_addr[7] = DFFEAS(FB1_active_addr[7]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L451 is std_1s10:inst|sdram:the_sdram|Mux108~1484
--operation mode is normal
FB1L451 = FB1L264 & (FB1_f_select & EE1L172 # !FB1_f_select & (FB1_active_addr[7]));
--FB1L452 is std_1s10:inst|sdram:the_sdram|Mux108~1485
--operation mode is normal
FB1L452 = FB1_m_state[1] & (!FB1_m_state[0]) # !FB1_m_state[1] & (FB1_m_state[0] & (FB1L455) # !FB1_m_state[0] & FB1L450);
--FB1L453 is std_1s10:inst|sdram:the_sdram|Mux108~1486
--operation mode is normal
FB1L453 = FB1_m_state[1] & (FB1L452 & (FB1_m_addr[7]) # !FB1L452 & FB1L449) # !FB1_m_state[1] & (FB1L452);
--FB1L454 is std_1s10:inst|sdram:the_sdram|Mux108~1487
--operation mode is normal
FB1L454 = FB1_m_state[6] & FB1L448 # !FB1_m_state[6] & (FB1L453);
--FB1L456 is std_1s10:inst|sdram:the_sdram|Mux109~1348
--operation mode is normal
FB1L456 = FB1L432 & FB1_m_addr[6] # !FB1L432 & FB1_m_state[6] & (FB1_m_addr[6] # FB1L448);
--FB1L457 is std_1s10:inst|sdram:the_sdram|Mux109~1349
--operation mode is normal
FB1L457 = FB1_m_state[4] & FB1_m_addr[6] # !FB1_m_state[4] & (FB1_m_state[3] & FB1_m_addr[6] # !FB1_m_state[3] & (FB1_active_addr[15]));
--FB1L458 is std_1s10:inst|sdram:the_sdram|Mux109~1350
--operation mode is normal
FB1L458 = FB1_init_done & FB1_m_addr[6] # !FB1_init_done & (FB1L348 & (!FB1_i_addr[0]) # !FB1L348 & FB1_m_addr[6]);
--EE1_entry_1[42] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[42]
--operation mode is normal
EE1_entry_1[42]_lut_out = GB1L36;
EE1_entry_1[42] = DFFEAS(EE1_entry_1[42]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[42] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[42]
--operation mode is normal
EE1_entry_0[42]_lut_out = GB1L36;
EE1_entry_0[42] = DFFEAS(EE1_entry_0[42]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L171 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[42]~496
--operation mode is normal
EE1L171 = EE1_rd_address & EE1_entry_1[42] # !EE1_rd_address & (EE1_entry_0[42]);
--FB1_active_addr[6] is std_1s10:inst|sdram:the_sdram|active_addr[6]
--operation mode is normal
FB1_active_addr[6]_lut_out = FB1L12 & (FB1L14 & (EE1L171) # !FB1L14 & FB1_active_addr[6]) # !FB1L12 & FB1_active_addr[6];
FB1_active_addr[6] = DFFEAS(FB1_active_addr[6]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L459 is std_1s10:inst|sdram:the_sdram|Mux109~1351
--operation mode is normal
FB1L459 = FB1L264 & (FB1_f_select & EE1L171 # !FB1_f_select & (FB1_active_addr[6]));
--FB1L460 is std_1s10:inst|sdram:the_sdram|Mux109~1352
--operation mode is normal
FB1L460 = FB1_m_state[1] & (!FB1_m_state[0]) # !FB1_m_state[1] & (FB1_m_state[0] & (FB1L462) # !FB1_m_state[0] & FB1L458);
--FB1L461 is std_1s10:inst|sdram:the_sdram|Mux109~1353
--operation mode is normal
FB1L461 = FB1_m_state[1] & (FB1L460 & (FB1_m_addr[6]) # !FB1L460 & FB1L457) # !FB1_m_state[1] & (FB1L460);
--FB1L463 is std_1s10:inst|sdram:the_sdram|Mux110~1388
--operation mode is normal
FB1L463 = FB1L432 & FB1_m_addr[5] # !FB1L432 & FB1_m_state[6] & (FB1_m_addr[5] # FB1L448);
--FB1L464 is std_1s10:inst|sdram:the_sdram|Mux110~1389
--operation mode is normal
FB1L464 = FB1_m_state[4] & FB1_m_addr[5] # !FB1_m_state[4] & (FB1_m_state[3] & FB1_m_addr[5] # !FB1_m_state[3] & (FB1_active_addr[14]));
--FB1L465 is std_1s10:inst|sdram:the_sdram|Mux110~1390
--operation mode is normal
FB1L465 = FB1_m_addr[5] # !FB1_m_state[4] & !FB1_m_state[3] & !FB1_init_done;
--EE1_entry_1[41] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[41]
--operation mode is normal
EE1_entry_1[41]_lut_out = GB1L35;
EE1_entry_1[41] = DFFEAS(EE1_entry_1[41]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[41] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[41]
--operation mode is normal
EE1_entry_0[41]_lut_out = GB1L35;
EE1_entry_0[41] = DFFEAS(EE1_entry_0[41]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L170 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[41]~497
--operation mode is normal
EE1L170 = EE1_rd_address & EE1_entry_1[41] # !EE1_rd_address & (EE1_entry_0[41]);
--FB1_active_addr[5] is std_1s10:inst|sdram:the_sdram|active_addr[5]
--operation mode is normal
FB1_active_addr[5]_lut_out = FB1L12 & (FB1L14 & (EE1L170) # !FB1L14 & FB1_active_addr[5]) # !FB1L12 & FB1_active_addr[5];
FB1_active_addr[5] = DFFEAS(FB1_active_addr[5]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L466 is std_1s10:inst|sdram:the_sdram|Mux110~1391
--operation mode is normal
FB1L466 = FB1L264 & (FB1_f_select & EE1L170 # !FB1_f_select & (FB1_active_addr[5]));
--FB1L467 is std_1s10:inst|sdram:the_sdram|Mux110~1392
--operation mode is normal
FB1L467 = FB1_m_state[1] & (!FB1_m_state[0]) # !FB1_m_state[1] & (FB1_m_state[0] & (FB1L469) # !FB1_m_state[0] & FB1L465);
--FB1L468 is std_1s10:inst|sdram:the_sdram|Mux110~1393
--operation mode is normal
FB1L468 = FB1_m_state[1] & (FB1L467 & (FB1_m_addr[5]) # !FB1L467 & FB1L464) # !FB1_m_state[1] & (FB1L467);
--FB1L470 is std_1s10:inst|sdram:the_sdram|Mux111~1315
--operation mode is normal
FB1L470 = FB1L432 & FB1_m_addr[4] # !FB1L432 & FB1_m_state[6] & (FB1_m_addr[4] # FB1L448);
--FB1L471 is std_1s10:inst|sdram:the_sdram|Mux111~1316
--operation mode is normal
FB1L471 = FB1_m_state[4] & FB1_m_addr[4] # !FB1_m_state[4] & (FB1_m_state[3] & FB1_m_addr[4] # !FB1_m_state[3] & (FB1_active_addr[13]));
--FB1L472 is std_1s10:inst|sdram:the_sdram|Mux111~1317
--operation mode is normal
FB1L472 = FB1_m_addr[4] # !FB1_m_state[4] & !FB1_m_state[3] & !FB1_init_done;
--EE1_entry_1[40] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[40]
--operation mode is normal
EE1_entry_1[40]_lut_out = GB1L34;
EE1_entry_1[40] = DFFEAS(EE1_entry_1[40]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[40] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[40]
--operation mode is normal
EE1_entry_0[40]_lut_out = GB1L34;
EE1_entry_0[40] = DFFEAS(EE1_entry_0[40]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L169 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[40]~498
--operation mode is normal
EE1L169 = EE1_rd_address & EE1_entry_1[40] # !EE1_rd_address & (EE1_entry_0[40]);
--FB1_active_addr[4] is std_1s10:inst|sdram:the_sdram|active_addr[4]
--operation mode is normal
FB1_active_addr[4]_lut_out = FB1L12 & (FB1L14 & (EE1L169) # !FB1L14 & FB1_active_addr[4]) # !FB1L12 & FB1_active_addr[4];
FB1_active_addr[4] = DFFEAS(FB1_active_addr[4]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L473 is std_1s10:inst|sdram:the_sdram|Mux111~1318
--operation mode is normal
FB1L473 = FB1L264 & (FB1_f_select & EE1L169 # !FB1_f_select & (FB1_active_addr[4]));
--FB1L474 is std_1s10:inst|sdram:the_sdram|Mux111~1319
--operation mode is normal
FB1L474 = FB1_m_state[1] & (!FB1_m_state[0]) # !FB1_m_state[1] & (FB1_m_state[0] & (FB1L476) # !FB1_m_state[0] & FB1L472);
--FB1L475 is std_1s10:inst|sdram:the_sdram|Mux111~1320
--operation mode is normal
FB1L475 = FB1_m_state[1] & (FB1L474 & (FB1_m_addr[4]) # !FB1L474 & FB1L471) # !FB1_m_state[1] & (FB1L474);
--FB1L477 is std_1s10:inst|sdram:the_sdram|Mux112~1347
--operation mode is normal
FB1L477 = FB1L432 & FB1_m_addr[3] # !FB1L432 & FB1_m_state[6] & (FB1_m_addr[3] # FB1L448);
--FB1L478 is std_1s10:inst|sdram:the_sdram|Mux112~1348
--operation mode is normal
FB1L478 = FB1_m_state[4] & FB1_m_addr[3] # !FB1_m_state[4] & (FB1_m_state[3] & FB1_m_addr[3] # !FB1_m_state[3] & (FB1_active_addr[12]));
--FB1L479 is std_1s10:inst|sdram:the_sdram|Mux112~1349
--operation mode is normal
FB1L479 = FB1_init_done & FB1_m_addr[3] # !FB1_init_done & (FB1L348 & (!FB1_i_addr[0]) # !FB1L348 & FB1_m_addr[3]);
--EE1_entry_1[39] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[39]
--operation mode is normal
EE1_entry_1[39]_lut_out = GB1L33;
EE1_entry_1[39] = DFFEAS(EE1_entry_1[39]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[39] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[39]
--operation mode is normal
EE1_entry_0[39]_lut_out = GB1L33;
EE1_entry_0[39] = DFFEAS(EE1_entry_0[39]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L168 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[39]~499
--operation mode is normal
EE1L168 = EE1_rd_address & EE1_entry_1[39] # !EE1_rd_address & (EE1_entry_0[39]);
--FB1_active_addr[3] is std_1s10:inst|sdram:the_sdram|active_addr[3]
--operation mode is normal
FB1_active_addr[3]_lut_out = FB1L12 & (FB1L14 & (EE1L168) # !FB1L14 & FB1_active_addr[3]) # !FB1L12 & FB1_active_addr[3];
FB1_active_addr[3] = DFFEAS(FB1_active_addr[3]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L480 is std_1s10:inst|sdram:the_sdram|Mux112~1350
--operation mode is normal
FB1L480 = FB1L264 & (FB1_f_select & EE1L168 # !FB1_f_select & (FB1_active_addr[3]));
--FB1L481 is std_1s10:inst|sdram:the_sdram|Mux112~1351
--operation mode is normal
FB1L481 = FB1_m_state[1] & (!FB1_m_state[0]) # !FB1_m_state[1] & (FB1_m_state[0] & (FB1L483) # !FB1_m_state[0] & FB1L479);
--FB1L482 is std_1s10:inst|sdram:the_sdram|Mux112~1352
--operation mode is normal
FB1L482 = FB1_m_state[1] & (FB1L481 & (FB1_m_addr[3]) # !FB1L481 & FB1L478) # !FB1_m_state[1] & (FB1L481);
--FB1L484 is std_1s10:inst|sdram:the_sdram|Mux113~1347
--operation mode is normal
FB1L484 = FB1L432 & FB1_m_addr[2] # !FB1L432 & FB1_m_state[6] & (FB1_m_addr[2] # FB1L448);
--FB1L485 is std_1s10:inst|sdram:the_sdram|Mux113~1348
--operation mode is normal
FB1L485 = FB1_m_state[4] & FB1_m_addr[2] # !FB1_m_state[4] & (FB1_m_state[3] & FB1_m_addr[2] # !FB1_m_state[3] & (FB1_active_addr[11]));
--FB1L486 is std_1s10:inst|sdram:the_sdram|Mux113~1349
--operation mode is normal
FB1L486 = FB1_init_done & FB1_m_addr[2] # !FB1_init_done & (FB1L348 & (!FB1_i_addr[0]) # !FB1L348 & FB1_m_addr[2]);
--EE1_entry_1[38] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[38]
--operation mode is normal
EE1_entry_1[38]_lut_out = GB1L32;
EE1_entry_1[38] = DFFEAS(EE1_entry_1[38]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[38] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[38]
--operation mode is normal
EE1_entry_0[38]_lut_out = GB1L32;
EE1_entry_0[38] = DFFEAS(EE1_entry_0[38]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L167 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[38]~500
--operation mode is normal
EE1L167 = EE1_rd_address & EE1_entry_1[38] # !EE1_rd_address & (EE1_entry_0[38]);
--FB1_active_addr[2] is std_1s10:inst|sdram:the_sdram|active_addr[2]
--operation mode is normal
FB1_active_addr[2]_lut_out = FB1L12 & (FB1L14 & (EE1L167) # !FB1L14 & FB1_active_addr[2]) # !FB1L12 & FB1_active_addr[2];
FB1_active_addr[2] = DFFEAS(FB1_active_addr[2]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L487 is std_1s10:inst|sdram:the_sdram|Mux113~1350
--operation mode is normal
FB1L487 = FB1L264 & (FB1_f_select & EE1L167 # !FB1_f_select & (FB1_active_addr[2]));
--FB1L488 is std_1s10:inst|sdram:the_sdram|Mux113~1351
--operation mode is normal
FB1L488 = FB1_m_state[1] & (!FB1_m_state[0]) # !FB1_m_state[1] & (FB1_m_state[0] & (FB1L490) # !FB1_m_state[0] & FB1L486);
--FB1L489 is std_1s10:inst|sdram:the_sdram|Mux113~1352
--operation mode is normal
FB1L489 = FB1_m_state[1] & (FB1L488 & (FB1_m_addr[2]) # !FB1L488 & FB1L485) # !FB1_m_state[1] & (FB1L488);
--FB1L491 is std_1s10:inst|sdram:the_sdram|Mux114~1347
--operation mode is normal
FB1L491 = FB1L432 & FB1_m_addr[1] # !FB1L432 & FB1_m_state[6] & (FB1_m_addr[1] # FB1L448);
--FB1L492 is std_1s10:inst|sdram:the_sdram|Mux114~1348
--operation mode is normal
FB1L492 = FB1_m_state[4] & FB1_m_addr[1] # !FB1_m_state[4] & (FB1_m_state[3] & FB1_m_addr[1] # !FB1_m_state[3] & (FB1_active_addr[10]));
--FB1L493 is std_1s10:inst|sdram:the_sdram|Mux114~1349
--operation mode is normal
FB1L493 = FB1_init_done & FB1_m_addr[1] # !FB1_init_done & (FB1L348 & (!FB1_i_addr[0]) # !FB1L348 & FB1_m_addr[1]);
--EE1_entry_1[37] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[37]
--operation mode is normal
EE1_entry_1[37]_lut_out = GB1L31;
EE1_entry_1[37] = DFFEAS(EE1_entry_1[37]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[37] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[37]
--operation mode is normal
EE1_entry_0[37]_lut_out = GB1L31;
EE1_entry_0[37] = DFFEAS(EE1_entry_0[37]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L166 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[37]~501
--operation mode is normal
EE1L166 = EE1_rd_address & EE1_entry_1[37] # !EE1_rd_address & (EE1_entry_0[37]);
--FB1_active_addr[1] is std_1s10:inst|sdram:the_sdram|active_addr[1]
--operation mode is normal
FB1_active_addr[1]_lut_out = FB1L12 & (FB1L14 & (EE1L166) # !FB1L14 & FB1_active_addr[1]) # !FB1L12 & FB1_active_addr[1];
FB1_active_addr[1] = DFFEAS(FB1_active_addr[1]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L494 is std_1s10:inst|sdram:the_sdram|Mux114~1350
--operation mode is normal
FB1L494 = FB1L264 & (FB1_f_select & EE1L166 # !FB1_f_select & (FB1_active_addr[1]));
--FB1L495 is std_1s10:inst|sdram:the_sdram|Mux114~1351
--operation mode is normal
FB1L495 = FB1_m_state[1] & (!FB1_m_state[0]) # !FB1_m_state[1] & (FB1_m_state[0] & (FB1L497) # !FB1_m_state[0] & FB1L493);
--FB1L496 is std_1s10:inst|sdram:the_sdram|Mux114~1352
--operation mode is normal
FB1L496 = FB1_m_state[1] & (FB1L495 & (FB1_m_addr[1]) # !FB1L495 & FB1L492) # !FB1_m_state[1] & (FB1L495);
--FB1L498 is std_1s10:inst|sdram:the_sdram|Mux115~1347
--operation mode is normal
FB1L498 = FB1L432 & FB1_m_addr[0] # !FB1L432 & FB1_m_state[6] & (FB1_m_addr[0] # FB1L448);
--FB1L499 is std_1s10:inst|sdram:the_sdram|Mux115~1348
--operation mode is normal
FB1L499 = FB1_m_state[4] & FB1_m_addr[0] # !FB1_m_state[4] & (FB1_m_state[3] & FB1_m_addr[0] # !FB1_m_state[3] & (FB1_active_addr[9]));
--FB1L500 is std_1s10:inst|sdram:the_sdram|Mux115~1349
--operation mode is normal
FB1L500 = FB1_init_done & FB1_m_addr[0] # !FB1_init_done & (FB1L348 & (!FB1_i_addr[0]) # !FB1L348 & FB1_m_addr[0]);
--EE1_entry_1[36] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[36]
--operation mode is normal
EE1_entry_1[36]_lut_out = GB1L30;
EE1_entry_1[36] = DFFEAS(EE1_entry_1[36]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[36] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[36]
--operation mode is normal
EE1_entry_0[36]_lut_out = GB1L30;
EE1_entry_0[36] = DFFEAS(EE1_entry_0[36]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L165 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[36]~502
--operation mode is normal
EE1L165 = EE1_rd_address & EE1_entry_1[36] # !EE1_rd_address & (EE1_entry_0[36]);
--FB1_active_addr[0] is std_1s10:inst|sdram:the_sdram|active_addr[0]
--operation mode is normal
FB1_active_addr[0]_lut_out = FB1L12 & (FB1L14 & (EE1L165) # !FB1L14 & FB1_active_addr[0]) # !FB1L12 & FB1_active_addr[0];
FB1_active_addr[0] = DFFEAS(FB1_active_addr[0]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1L501 is std_1s10:inst|sdram:the_sdram|Mux115~1350
--operation mode is normal
FB1L501 = FB1L264 & (FB1_f_select & EE1L165 # !FB1_f_select & (FB1_active_addr[0]));
--FB1L502 is std_1s10:inst|sdram:the_sdram|Mux115~1351
--operation mode is normal
FB1L502 = FB1_m_state[1] & (!FB1_m_state[0]) # !FB1_m_state[1] & (FB1_m_state[0] & (FB1L504) # !FB1_m_state[0] & FB1L500);
--FB1L503 is std_1s10:inst|sdram:the_sdram|Mux115~1352
--operation mode is normal
FB1L503 = FB1_m_state[1] & (FB1L502 & (FB1_m_addr[0]) # !FB1L502 & FB1L499) # !FB1_m_state[1] & (FB1L502);
--EE1L174 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[57]~503
--operation mode is normal
EE1L174 = EE1_rd_address & EE1_entry_1[57] # !EE1_rd_address & (EE1_entry_0[57]);
--FB1L505 is std_1s10:inst|sdram:the_sdram|Mux116~1300
--operation mode is normal
FB1L505 = FB1_f_select & (FB1_m_state[1] & FB1_active_addr[21] # !FB1_m_state[1] & (EE1L174)) # !FB1_f_select & FB1_active_addr[21];
--FB1L506 is std_1s10:inst|sdram:the_sdram|Mux116~1301
--operation mode is normal
FB1L506 = FB1_m_state[4] & !FB1_m_state[3] & !FB1_m_state[1] # !FB1_m_state[4] & (FB1_m_state[3] $ FB1_m_state[1]);
--FB1L278 is std_1s10:inst|sdram:the_sdram|Mux24~1458
--operation mode is normal
FB1L278 = FB1_m_state[0] & (!FB1_m_state[7] & !FB1_m_state[2]);
--FB1L310 is std_1s10:inst|sdram:the_sdram|Mux29~1320
--operation mode is normal
FB1L310 = !FB1_m_state[5] & !FB1_m_state[6];
--EE1L173 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[44]~504
--operation mode is normal
EE1L173 = EE1_rd_address & EE1_entry_1[44] # !EE1_rd_address & (EE1_entry_0[44]);
--FB1L507 is std_1s10:inst|sdram:the_sdram|Mux117~1184
--operation mode is normal
FB1L507 = FB1_f_select & (FB1_m_state[1] & FB1_active_addr[8] # !FB1_m_state[1] & (EE1L173)) # !FB1_f_select & FB1_active_addr[8];
--FB1_active_dqm[3] is std_1s10:inst|sdram:the_sdram|active_dqm[3]
--operation mode is normal
FB1_active_dqm[3]_lut_out = FB1L12 & (FB1L14 & (EE1L164) # !FB1L14 & FB1_active_dqm[3]) # !FB1L12 & FB1_active_dqm[3];
FB1_active_dqm[3] = DFFEAS(FB1_active_dqm[3]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[35] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[35]
--operation mode is normal
EE1_entry_1[35]_lut_out = FB1L236;
EE1_entry_1[35] = DFFEAS(EE1_entry_1[35]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[35] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[35]
--operation mode is normal
EE1_entry_0[35]_lut_out = FB1L236;
EE1_entry_0[35] = DFFEAS(EE1_entry_0[35]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L164 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[35]~505
--operation mode is normal
EE1L164 = EE1_rd_address & EE1_entry_1[35] # !EE1_rd_address & (EE1_entry_0[35]);
--FB1L543 is std_1s10:inst|sdram:the_sdram|Mux150~1184
--operation mode is normal
FB1L543 = FB1_f_select & (FB1_m_state[1] & FB1_active_dqm[3] # !FB1_m_state[1] & (EE1L164)) # !FB1_f_select & FB1_active_dqm[3];
--FB1_active_dqm[2] is std_1s10:inst|sdram:the_sdram|active_dqm[2]
--operation mode is normal
FB1_active_dqm[2]_lut_out = FB1L12 & (FB1L14 & (EE1L163) # !FB1L14 & FB1_active_dqm[2]) # !FB1L12 & FB1_active_dqm[2];
FB1_active_dqm[2] = DFFEAS(FB1_active_dqm[2]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[34] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[34]
--operation mode is normal
EE1_entry_1[34]_lut_out = FB1L235;
EE1_entry_1[34] = DFFEAS(EE1_entry_1[34]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[34] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[34]
--operation mode is normal
EE1_entry_0[34]_lut_out = FB1L235;
EE1_entry_0[34] = DFFEAS(EE1_entry_0[34]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L163 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[34]~506
--operation mode is normal
EE1L163 = EE1_rd_address & EE1_entry_1[34] # !EE1_rd_address & (EE1_entry_0[34]);
--FB1L544 is std_1s10:inst|sdram:the_sdram|Mux151~1184
--operation mode is normal
FB1L544 = FB1_f_select & (FB1_m_state[1] & FB1_active_dqm[2] # !FB1_m_state[1] & (EE1L163)) # !FB1_f_select & FB1_active_dqm[2];
--FB1_active_dqm[1] is std_1s10:inst|sdram:the_sdram|active_dqm[1]
--operation mode is normal
FB1_active_dqm[1]_lut_out = FB1L12 & (FB1L14 & (EE1L162) # !FB1L14 & FB1_active_dqm[1]) # !FB1L12 & FB1_active_dqm[1];
FB1_active_dqm[1] = DFFEAS(FB1_active_dqm[1]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[33] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[33]
--operation mode is normal
EE1_entry_1[33]_lut_out = FB1L234;
EE1_entry_1[33] = DFFEAS(EE1_entry_1[33]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[33] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[33]
--operation mode is normal
EE1_entry_0[33]_lut_out = FB1L234;
EE1_entry_0[33] = DFFEAS(EE1_entry_0[33]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L162 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[33]~507
--operation mode is normal
EE1L162 = EE1_rd_address & EE1_entry_1[33] # !EE1_rd_address & (EE1_entry_0[33]);
--FB1L545 is std_1s10:inst|sdram:the_sdram|Mux152~1184
--operation mode is normal
FB1L545 = FB1_f_select & (FB1_m_state[1] & FB1_active_dqm[1] # !FB1_m_state[1] & (EE1L162)) # !FB1_f_select & FB1_active_dqm[1];
--FB1_active_dqm[0] is std_1s10:inst|sdram:the_sdram|active_dqm[0]
--operation mode is normal
FB1_active_dqm[0]_lut_out = FB1L12 & (FB1L14 & (EE1L161) # !FB1L14 & FB1_active_dqm[0]) # !FB1L12 & FB1_active_dqm[0];
FB1_active_dqm[0] = DFFEAS(FB1_active_dqm[0]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[32] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[32]
--operation mode is normal
EE1_entry_1[32]_lut_out = FB1L233;
EE1_entry_1[32] = DFFEAS(EE1_entry_1[32]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[32] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[32]
--operation mode is normal
EE1_entry_0[32]_lut_out = FB1L233;
EE1_entry_0[32] = DFFEAS(EE1_entry_0[32]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L161 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[32]~508
--operation mode is normal
EE1L161 = EE1_rd_address & EE1_entry_1[32] # !EE1_rd_address & (EE1_entry_0[32]);
--FB1L546 is std_1s10:inst|sdram:the_sdram|Mux153~1184
--operation mode is normal
FB1L546 = FB1_f_select & (FB1_m_state[1] & FB1_active_dqm[0] # !FB1_m_state[1] & (EE1L161)) # !FB1_f_select & FB1_active_dqm[0];
--C1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo
--operation mode is normal
C1_hub_tdo = AMPP_FUNCTION(A1L6, C1L15, RE1_state[4], RE1_state[3], C1_hub_tdo, !RE1_state[8]);
--L1_ic_fill_ap_cnt[3] is std_1s10:inst|cpu:the_cpu|ic_fill_ap_cnt[3]
--operation mode is normal
L1_ic_fill_ap_cnt[3] = AMPP_FUNCTION(DE1__clk0, L1_internal_i_read, N1L114, L1_ic_fill_ap_cnt[3], L1L112, E1_data_out, L1L1027);
--N1L157 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~1
--operation mode is normal
N1L157 = Q1L16 # Q1L18 # !N1L146;
--N1L158 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~3
--operation mode is normal
N1L158 = Q1L20 # Q1L22 # !Q1L285;
--Q1_ext_flash_s1_wait_counter[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[0]
--operation mode is normal
Q1_ext_flash_s1_wait_counter[0]_lut_out = !Q1L135 & !Q1_ext_flash_s1_wait_counter[0] & !Q1L138;
Q1_ext_flash_s1_wait_counter[0] = DFFEAS(Q1_ext_flash_s1_wait_counter[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1L134 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal10~110
--operation mode is normal
Q1L134 = !Q1_ext_flash_s1_wait_counter[3] & !Q1_ext_flash_s1_wait_counter[2] & !Q1_ext_flash_s1_wait_counter[1] & !Q1_ext_flash_s1_wait_counter[0];
--N1L147 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]~37
--operation mode is normal
N1L147 = Q1_d1_ext_ram_bus_avalon_slave_end_xfer & Q1L134;
--N1L160 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~14
--operation mode is normal
N1L160 = N1_internal_cpu_instruction_master_dbs_address[1] & N1_internal_cpu_instruction_master_dbs_address[0] & N1L147 # !N1L146;
--N1L107 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~136
--operation mode is normal
N1L107 = N1L160 & (Q1L4 # Q1L6 # !Q1L244);
--N1L159 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~8
--operation mode is normal
N1L159 = Q1_d1_ext_ram_bus_avalon_slave_end_xfer & !Q1L256 # !Q1L244;
--GB1_sdram_s1_arb_addend[1] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[1]
--operation mode is normal
GB1_sdram_s1_arb_addend[1]_lut_out = GB1_WideOr1 & GB1L56 # !GB1_WideOr1 & (GB1_sdram_s1_arb_addend[1]);
GB1_sdram_s1_arb_addend[1] = DFFEAS(GB1_sdram_s1_arb_addend[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FE1_fifo_contains_ones_n is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n
--operation mode is normal
FE1_fifo_contains_ones_n_lut_out = FE1L2 # FE1L3 # FE1L4 # FE1L6;
FE1_fifo_contains_ones_n = DFFEAS(FE1_fifo_contains_ones_n_lut_out, DE1__clk0, E1_data_out, , GE1L27, , , , );
--GB1L16 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_qualified_request_sdram_s1~108
--operation mode is normal
GB1L16 = M1_internal_cpu_data_master_waitrequest & !L1_internal_d_write & (!L1_internal_d_read) # !M1_internal_cpu_data_master_waitrequest & (!L1_internal_d_read # !FE1_fifo_contains_ones_n);
--GB1_sdram_s1_slavearbiterlockenable is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable
--operation mode is normal
GB1_sdram_s1_slavearbiterlockenable_lut_out = GB1L29 & (GB1L75 & GB1_sdram_s1_slavearbiterlockenable # !GB1L75 & (GB1L82)) # !GB1L29 & GB1_sdram_s1_slavearbiterlockenable;
GB1_sdram_s1_slavearbiterlockenable = DFFEAS(GB1_sdram_s1_slavearbiterlockenable_lut_out, DE1__clk0, E1_data_out, , , , , , );
--GB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|last_cycle_cpu_instruction_master_granted_slave_sdram_s1
--operation mode is normal
GB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1_lut_out = GB1L22 & (GB1L72 # GB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 & !GB1L74);
GB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 = DFFEAS(GB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1_lut_out, DE1__clk0, E1_data_out, , , , , , );
--GB1L70 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[5]~540
--operation mode is normal
GB1L70 = L1_internal_i_read & L1_ic_fill_tag[12] & GB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 & !L1_ic_fill_tag[13];
--GB1L17 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_qualified_request_sdram_s1~109
--operation mode is normal
GB1L17 = GB1L18 & GB1L16 & (!GB1L70 # !GB1_sdram_s1_slavearbiterlockenable);
--GB1L22 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_requests_sdram_s1~37
--operation mode is normal
GB1L22 = L1_internal_i_read & L1_ic_fill_tag[12] & (!L1_ic_fill_tag[13]);
--GB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|last_cycle_cpu_data_master_granted_slave_sdram_s1
--operation mode is normal
GB1_last_cycle_cpu_data_master_granted_slave_sdram_s1_lut_out = GB1L18 & (GB1L1 # GB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 & !GB1L74);
GB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 = DFFEAS(GB1_last_cycle_cpu_data_master_granted_slave_sdram_s1_lut_out, DE1__clk0, E1_data_out, , , , , , );
--GB1L13 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_arbiterlock~19
--operation mode is normal
GB1L13 = L1_M_alu_result[24] & QB1L4 & GB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 & !L1_M_alu_result[25];
--GB1L24 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_qualified_request_sdram_s1~53
--operation mode is normal
GB1L24 = L1_internal_i_read & (N1_internal_cpu_instruction_master_latency_counter[0] # N1_internal_cpu_instruction_master_latency_counter[1]);
--GB1L20 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_qualified_request_sdram_s1~52
--operation mode is normal
GB1L20 = GB1L22 & !GB1L24 & (!GB1L13 # !GB1_sdram_s1_slavearbiterlockenable);
--GB1_sdram_s1_arb_addend[0] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[0]
--operation mode is normal
GB1_sdram_s1_arb_addend[0]_lut_out = GB1_WideOr1 & !GB1L54 # !GB1_WideOr1 & (GB1_sdram_s1_arb_addend[0]);
GB1_sdram_s1_arb_addend[0] = DFFEAS(GB1_sdram_s1_arb_addend[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--N1L163 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_2~8
--operation mode is normal
N1L163 = GB1_sdram_s1_arb_addend[1] & !GB1L17 # !GB1_sdram_s1_arb_addend[0] # !GB1L20;
--P1_cpu_jtag_debug_module_arb_addend[1] is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]
--operation mode is normal
P1_cpu_jtag_debug_module_arb_addend[1]_lut_out = P1L28 # P1L3 & (P1L35 # P1L29);
P1_cpu_jtag_debug_module_arb_addend[1] = DFFEAS(P1_cpu_jtag_debug_module_arb_addend[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--P1L39 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|internal_cpu_instruction_master_qualified_request_cpu_jtag_debug_module~31
--operation mode is normal
P1L39 = L1_internal_i_read & (GE1_fifo_contains_ones_n # N1_internal_cpu_instruction_master_latency_counter[0] # N1_internal_cpu_instruction_master_latency_counter[1]);
--P1L11 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~60
--operation mode is normal
P1L11 = L1_internal_i_read & L1_ic_fill_tag[4] & !L1_ic_fill_tag[3] & !L1_ic_fill_tag[2];
--P1L12 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~61
--operation mode is normal
P1L12 = Q1L131 & Q1L132 & P1L11 & !L1_ic_fill_tag[13];
--P1L13 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~62
--operation mode is normal
P1L13 = !L1_ic_fill_tag[1] & !L1_ic_fill_tag[0] & !L1_ic_fill_line[6];
--P1_cpu_jtag_debug_module_arb_addend[0] is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]
--operation mode is normal
P1_cpu_jtag_debug_module_arb_addend[0]_lut_out = !P1L26 & (P1L35 # P1L29 # !P1L3);
P1_cpu_jtag_debug_module_arb_addend[0] = DFFEAS(P1_cpu_jtag_debug_module_arb_addend[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--P1L1 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|Add2~331
--operation mode is normal
P1L1 = !P1_cpu_jtag_debug_module_arb_addend[0] & (P1L39 # !P1L13 # !P1L12);
--P1L2 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|Add2~332
--operation mode is normal
P1L2 = P1_cpu_jtag_debug_module_arb_addend[1] & (P1L1 # !P1L8 # !P1L7) # !P1_cpu_jtag_debug_module_arb_addend[1] & P1L1 & (!P1L8 # !P1L7);
--P1L10 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_qualified_request_cpu_jtag_debug_module~254
--operation mode is normal
P1L10 = P1L12 & P1L13 & (!P1L39);
--N1L108 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~137
--operation mode is normal
N1L108 = N1L163 & (P1L2 # !P1_cpu_jtag_debug_module_arb_addend[0] # !P1L10);
--Q1L205 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_cpu_instruction_master_qualified_request_ext_ram_s1~91
--operation mode is normal
Q1L205 = Q1L204 # Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable & Q1L45;
--N1L109 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~138
--operation mode is normal
N1L109 = !Q1L286 & !Q1L94 # !Q1L205;
--AB1L14 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_requests_onchip_ram_64_kbytes_s1~49
--operation mode is normal
AB1L14 = !L1_ic_fill_tag[4] & !L1_ic_fill_tag[5] & !L1_ic_fill_tag[6] & !L1_ic_fill_tag[7];
--AB1L15 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_requests_onchip_ram_64_kbytes_s1~50
--operation mode is normal
AB1L15 = L1_ic_fill_tag[8] & (!L1_ic_fill_tag[9] & !L1_ic_fill_tag[10]);
--AB1L17 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|internal_cpu_instruction_master_qualified_request_onchip_ram_64_kbytes_s1~29
--operation mode is normal
AB1L17 = L1_internal_i_read & (GE1_fifo_contains_ones_n # N1_internal_cpu_instruction_master_latency_counter[1]);
--AB1L11 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_qualified_request_onchip_ram_64_kbytes_s1~25
--operation mode is normal
AB1L11 = AB1L13 & AB1L14 & AB1L15 & !AB1L17;
--AB1_onchip_ram_64_kbytes_s1_arb_addend[1] is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_arb_addend[1]
--operation mode is normal
AB1_onchip_ram_64_kbytes_s1_arb_addend[1]_lut_out = AB1_onchip_ram_64_kbytes_s1_arb_addend[1] & (!AB1L2 # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !AB1_onchip_ram_64_kbytes_s1_arb_addend[1] & (AB1L11);
AB1_onchip_ram_64_kbytes_s1_arb_addend[1] = DFFEAS(AB1_onchip_ram_64_kbytes_s1_arb_addend[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--AB1L8 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_requests_onchip_ram_64_kbytes_s1~299
--operation mode is normal
AB1L8 = L1_M_alu_result[25] & L1_M_alu_result[20] & (!L1_M_alu_result[23]);
--AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_requests_onchip_ram_64_kbytes_s1
--operation mode is normal
AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 = AB1L6 & AB1L7 & AB1L9 & AB1L8;
--AB1_cpu_data_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register
--operation mode is normal
AB1_cpu_data_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register_lut_out = L1_internal_d_read & AB1L3 & (AB1_onchip_ram_64_kbytes_s1_arb_addend[1] # !AB1L11);
AB1_cpu_data_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register = DFFEAS(AB1_cpu_data_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register_lut_out, DE1__clk0, E1_data_out, , , , , , );
--AB1L2 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_qualified_request_onchip_ram_64_kbytes_s1~67
--operation mode is normal
AB1L2 = L1_internal_d_write & !M1_internal_cpu_data_master_waitrequest & (!AB1_cpu_data_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register # !L1_internal_d_read) # !L1_internal_d_write & (!AB1_cpu_data_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register # !L1_internal_d_read);
--N1L162 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_2~1
--operation mode is normal
N1L162 = !AB1L2 # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 # !AB1_onchip_ram_64_kbytes_s1_arb_addend[1] # !AB1L11;
--N1L161 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_2~0
--operation mode is normal
N1L161 = !AB1L17 # !AB1L15 # !AB1L14 # !AB1L13;
--GB1L25 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_qualified_request_sdram_s1~54
--operation mode is normal
GB1L25 = GB1L24 # GB1_sdram_s1_slavearbiterlockenable & GB1L13;
--EE1L126 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|Equal0~87
--operation mode is normal
EE1L126 = EE1_entries[1] & (!EE1_entries[0]);
--N1L110 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~139
--operation mode is normal
N1L110 = N1L161 & (!GB1L25 & !EE1L126 # !GB1L22);
--P1_d1_reasons_to_wait is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_reasons_to_wait
--operation mode is normal
P1_d1_reasons_to_wait_lut_out = P1L35;
P1_d1_reasons_to_wait = DFFEAS(P1_d1_reasons_to_wait_lut_out, DE1__clk0, E1_data_out, , , , , , );
--N1L111 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~140
--operation mode is normal
N1L111 = N1L110 & (P1_d1_reasons_to_wait & !P1L39 # !P1L14);
--N1L112 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~141
--operation mode is normal
N1L112 = N1L162 & N1L111 & (!Q1L243 # !Q1L205);
--N1L113 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~142
--operation mode is normal
N1L113 = N1L159 & N1L108 & N1L109 & N1L112;
--N1L114 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~143
--operation mode is normal
N1L114 = N1L157 & N1L158 & N1L107 & N1L113;
--L1_D_kill is std_1s10:inst|cpu:the_cpu|D_kill
--operation mode is normal
L1_D_kill = AMPP_FUNCTION(DE1__clk0, L1_F_kill, E1_data_out, L1_W_stall);
--L1_D_inst_ram_hit is std_1s10:inst|cpu:the_cpu|D_inst_ram_hit
--operation mode is normal
L1_D_inst_ram_hit = AMPP_FUNCTION(DE1__clk0, L1L857, L1L858, L1L859, L1L861, E1_data_out, L1_W_stall);
--L1_ic_fill_prevent_refill is std_1s10:inst|cpu:the_cpu|ic_fill_prevent_refill
--operation mode is normal
L1_ic_fill_prevent_refill = AMPP_FUNCTION(DE1__clk0, L1_ic_fill_prevent_refill, L1L240, L1L241, L1L1040, E1_data_out);
--L1_D_ic_fill_same_tag_line is std_1s10:inst|cpu:the_cpu|D_ic_fill_same_tag_line
--operation mode is normal
L1_D_ic_fill_same_tag_line = AMPP_FUNCTION(DE1__clk0, L1L844, L1L849, L1L850, L1L852, E1_data_out, L1_W_stall);
--L1L240 is std_1s10:inst|cpu:the_cpu|D_ic_fill_starting~63
--operation mode is normal
L1L240 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1_ic_fill_prevent_refill, L1_D_ic_fill_same_tag_line);
--L1_ic_fill_active is std_1s10:inst|cpu:the_cpu|ic_fill_active
--operation mode is normal
L1_ic_fill_active = AMPP_FUNCTION(DE1__clk0, L1_i_readdatavalid_d1, L1_ic_fill_active, L1_D_ic_fill_starting, L1L1005, E1_data_out);
--L1L241 is std_1s10:inst|cpu:the_cpu|D_ic_fill_starting~64
--operation mode is normal
L1L241 = AMPP_FUNCTION(L1_ic_fill_active, L1_M_pipe_flush);
--L1_D_pc[21] is std_1s10:inst|cpu:the_cpu|D_pc[21]
--operation mode is normal
L1_D_pc[21] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[21], E1_data_out, L1_W_stall);
--L1_D_pc[18] is std_1s10:inst|cpu:the_cpu|D_pc[18]
--operation mode is normal
L1_D_pc[18] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[18], E1_data_out, L1_W_stall);
--L1_D_pc[19] is std_1s10:inst|cpu:the_cpu|D_pc[19]
--operation mode is normal
L1_D_pc[19] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[19], E1_data_out, L1_W_stall);
--L1_D_pc[20] is std_1s10:inst|cpu:the_cpu|D_pc[20]
--operation mode is normal
L1_D_pc[20] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[20], E1_data_out, L1_W_stall);
--L1_D_pc[22] is std_1s10:inst|cpu:the_cpu|D_pc[22]
--operation mode is normal
L1_D_pc[22] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[22], E1_data_out, L1_W_stall);
--L1_D_pc[15] is std_1s10:inst|cpu:the_cpu|D_pc[15]
--operation mode is normal
L1_D_pc[15] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[15], E1_data_out, L1_W_stall);
--L1_D_pc[16] is std_1s10:inst|cpu:the_cpu|D_pc[16]
--operation mode is normal
L1_D_pc[16] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[16], E1_data_out, L1_W_stall);
--L1_D_pc[17] is std_1s10:inst|cpu:the_cpu|D_pc[17]
--operation mode is normal
L1_D_pc[17] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[17], E1_data_out, L1_W_stall);
--L1_D_pc[14] is std_1s10:inst|cpu:the_cpu|D_pc[14]
--operation mode is normal
L1_D_pc[14] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[14], E1_data_out, L1_W_stall);
--L1_D_pc[23] is std_1s10:inst|cpu:the_cpu|D_pc[23]
--operation mode is normal
L1_D_pc[23] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[23], E1_data_out, L1_W_stall);
--Q1_ext_ram_bus_avalon_slave_arb_share_counter[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[1]
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_share_counter[1]_lut_out = Q1L186 # !Q1L194 & (Q1L46 # Q1L80);
Q1_ext_ram_bus_avalon_slave_arb_share_counter[1] = DFFEAS(Q1_ext_ram_bus_avalon_slave_arb_share_counter[1]_lut_out, DE1__clk0, E1_data_out, , Q1L181, , , , );
--Q1L194 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_firsttransfer~137
--operation mode is normal
Q1L194 = Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable & (Q1L45 # Q1L79 # Q1L77);
--Q1L203 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~192
--operation mode is normal
Q1L203 = Q1L194 & Q1_ext_ram_bus_avalon_slave_arb_share_counter[1] # !Q1L194 & (Q1L287);
--Q1L289 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~60
--operation mode is normal
Q1L289 = !Q1L94 & (L1_M_alu_result[25] & !Q1L73 # !Q1L71);
--Q1L290 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~61
--operation mode is normal
Q1L290 = Q1L289 & !Q1_cpu_data_master_requests_lan91c111_s1 & !Q1L243 & !Q1L286;
--Q1L291 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~62
--operation mode is normal
--Q1L93 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register_in~11
--operation mode is normal
Q1L93 = !Q1L256 & (Q1_d1_ext_ram_bus_avalon_slave_end_xfer # Q1L190);
--Q1L191 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_end_xfer~79
--operation mode is normal
Q1L191 = !Q1L93 & (Q1L82 # QB1L4 & Q1L48);
--Q1L86 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register_in~12
--operation mode is normal
Q1L86 = Q1L134 & (Q1_d1_ext_ram_bus_avalon_slave_end_xfer # Q1L190);
--Q1L192 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_end_xfer~80
--operation mode is normal
Q1L192 = Q1L191 # !Q1L86 & (Q1L136 # Q1_ext_flash_s1_in_a_read_cycle);
--Q1_cpu_data_master_requests_ext_ram_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_ram_s1
--operation mode is normal
Q1_cpu_data_master_requests_ext_ram_s1 = Q1L71 & Q1L73;
--Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]_lut_out = Q1L47;
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5] = DFFEAS(Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]_lut_out, DE1__clk0, E1_data_out, , Q1L187, , , , );
--N1L5 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~42
--operation mode is normal
N1L5 = !Q1L82 & !Q1L80 & !Q1L81;
--Q1_WideOr6 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|WideOr6
--operation mode is normal
Q1_WideOr6 = Q1L48 # Q1L46 # Q1L47 # !N1L5;
--Q1L1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4222
--operation mode is normal
Q1L1 = Q1_WideOr6 & (Q1L194 & Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5] # !Q1L194 & (Q1L47)) # !Q1_WideOr6 & Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5];
--Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arbitration_holdoff_internal
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal = !Q1_d1_ext_ram_bus_avalon_slave_end_xfer & !Q1L190 & !Q1L194;
--Q1L178 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~COMBOUT
--operation mode is normal
Q1L178 = Q1L187 & (Q1L46) # !Q1L187 & Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[3];
--Q1_ext_ram_bus_avalon_slave_arb_addend[4] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_addend[4] = DFFEAS(Q1L178, DE1__clk0, E1_data_out, , Q1_WideOr6, Q1L81, , , Q1L192);
--Q1L174 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2]~COMBOUT
--operation mode is normal
Q1L174 = Q1L187 & (Q1L48) # !Q1L187 & Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[1];
--Q1_ext_ram_bus_avalon_slave_arb_addend[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2]
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_addend[2] = DFFEAS(Q1L174, DE1__clk0, E1_data_out, , Q1_WideOr6, Q1L80, , , Q1L192);
--GE1_how_many_ones[3] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[3]
--operation mode is normal
GE1_how_many_ones[3]_lut_out = GE1L2;
GE1_how_many_ones[3] = DFFEAS(GE1_how_many_ones[3]_lut_out, DE1__clk0, E1_data_out, , GE1L27, , , , );
--GB1L19 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_granted_sdram_s1~77
--operation mode is normal
GB1L19 = GB1L20 & (GB1_sdram_s1_arb_addend[1] & !GB1L17 # !GB1_sdram_s1_arb_addend[0]);
--GE1_how_many_ones[2] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[2]
--operation mode is normal
GE1_how_many_ones[2]_lut_out = GE1L3;
GE1_how_many_ones[2] = DFFEAS(GE1_how_many_ones[2]_lut_out, DE1__clk0, E1_data_out, , GE1L27, , , , );
--GE1_how_many_ones[1] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[1]
--operation mode is normal
GE1_how_many_ones[1]_lut_out = GE1L4;
GE1_how_many_ones[1] = DFFEAS(GE1_how_many_ones[1]_lut_out, DE1__clk0, E1_data_out, , GE1L27, , , , );
--GE1_how_many_ones[0] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[0]
--operation mode is normal
GE1_how_many_ones[0]_lut_out = GE1L6;
GE1_how_many_ones[0] = DFFEAS(GE1_how_many_ones[0]_lut_out, DE1__clk0, E1_data_out, , GE1L27, , , , );
--FB1_za_valid is std_1s10:inst|sdram:the_sdram|za_valid
--operation mode is normal
FB1_za_valid_lut_out = FB1_rd_valid[2];
FB1_za_valid = DFFEAS(FB1_za_valid_lut_out, DE1__clk0, E1_data_out, , , , , , );
--GE1_stage_0 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_0
--operation mode is normal
GE1_stage_0_lut_out = GE1_full_1 & GE1_stage_1 # !GE1_full_1 & (GB1L19);
GE1_stage_0 = DFFEAS(GE1_stage_0_lut_out, DE1__clk0, VCC, , GE1L26, , , , );
--GE1L35 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|updated_one_count~64
--operation mode is normal
GE1L35 = FB1_za_valid & GE1_stage_0;
--GE1L1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1199
--operation mode is normal
GE1L1 = GE1_how_many_ones[2] & GE1_how_many_ones[1] & GE1_how_many_ones[0] & !GE1L35 # !GE1_how_many_ones[2] & !GE1_how_many_ones[1] & !GE1_how_many_ones[0] & GE1L35;
--GE1L2 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1200
--operation mode is normal
GE1L2 = GE1_how_many_ones[3] $ (GE1L1 & (GE1L36 $ !GE1_how_many_ones[2]));
--GE1L3 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1201
--operation mode is normal
GE1L3 = GE1_how_many_ones[2] $ (GE1L5 & (GE1L36 $ !GE1_how_many_ones[1]));
--GE1L4 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1202
--operation mode is normal
GE1L4 = GE1_how_many_ones[1] $ (GE1L35 & !GE1L36 & !GE1_how_many_ones[0] # !GE1L35 & GE1L36 & GE1_how_many_ones[0]);
--GB1L14 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_granted_sdram_s1~30
--operation mode is normal
GB1L14 = GB1L17 & (GB1_sdram_s1_arb_addend[1] # !GB1L20 & !GB1_sdram_s1_arb_addend[0]);
--GB1L28 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|module_input5~28
--operation mode is normal
GB1L28 = !EE1L126 & (GB1L19 # L1_internal_d_read & GB1L14);
--GE1L27 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process15~0
--operation mode is normal
GE1L27 = FB1_za_valid # GB1L28;
--AB1L16 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_requests_onchip_ram_64_kbytes_s1~51
--operation mode is normal
AB1L16 = AB1L13 & AB1L14 & AB1L15;
--N1L115 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~144
--operation mode is normal
N1L115 = N1L157 & (Q1L20 # Q1L22 # !Q1L285);
--N1L153 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter~0
--operation mode is normal
N1L153 = L1_internal_i_read & N1L115 & N1L107 & N1L113;
--N1L151 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter[1]~145
--operation mode is normal
N1L151 = !L1_ic_fill_tag[11] & !L1_ic_fill_tag[12];
--N1L152 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter[1]~146
--operation mode is normal
N1L152 = Q1L133 # N1L151 & (Q1L284 # !L1_ic_fill_tag[13]);
--Q1_ext_ram_bus_avalon_slave_arb_addend[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0]
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_addend[0]_lut_out = Q1L192 & !Q1L82 # !Q1L192 & (Q1L180 # !Q1L3);
Q1_ext_ram_bus_avalon_slave_arb_addend[0] = DFFEAS(Q1_ext_ram_bus_avalon_slave_arb_addend[0]_lut_out, DE1__clk0, E1_data_out, , Q1_WideOr6, , , , );
--Q1L180 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~COMBOUT
--operation mode is normal
Q1L180 = Q1L187 & (Q1L81) # !Q1L187 & Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[4];
--Q1_ext_ram_bus_avalon_slave_arb_addend[5] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_addend[5] = DFFEAS(Q1L180, DE1__clk0, E1_data_out, , Q1_WideOr6, Q1L47, , , Q1L192);
--Q1L172 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]~COMBOUT
--operation mode is normal
Q1L172 = Q1L187 & (Q1L82) # !Q1L187 & Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[0];
--Q1_ext_ram_bus_avalon_slave_arb_addend[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_addend[1] = DFFEAS(Q1L172, DE1__clk0, E1_data_out, , Q1_WideOr6, Q1L48, , , Q1L192);
--Q1L176 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~COMBOUT
--operation mode is normal
Q1L176 = Q1L187 & (Q1L80) # !Q1L187 & Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[2];
--Q1_ext_ram_bus_avalon_slave_arb_addend[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_addend[3] = DFFEAS(Q1L176, DE1__clk0, E1_data_out, , Q1_WideOr6, Q1L46, , , Q1L192);
--M1L305 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|pre_dbs_count_enable~74
--operation mode is normal
M1L305 = Q1_cpu_data_master_requests_ext_flash_s1 & !M1_internal_cpu_data_master_no_byte_enables_and_last_term & !Q1L42 & !Q1L43;
--M1L306 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|pre_dbs_count_enable~75
--operation mode is normal
M1L306 = Q1L52 & N1L147 & (Q1L12 # Q1L14);
--M1L307 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|pre_dbs_count_enable~76
--operation mode is normal
M1L307 = Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] # L1_internal_d_write & (M1L305 # M1L306);
--GB1L15 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_granted_sdram_s1~31
--operation mode is normal
GB1L15 = GB1_sdram_s1_arb_addend[1] & (GB1L20 # GB1L17 # !GB1_sdram_s1_arb_addend[0]) # !GB1_sdram_s1_arb_addend[1] & (GB1L17 $ (GB1L20 # GB1_sdram_s1_arb_addend[0]));
--Q1L135 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal10~111
--operation mode is normal
Q1L135 = !Q1_ext_flash_s1_wait_counter[3] & !Q1_ext_flash_s1_wait_counter[2] & !Q1_ext_flash_s1_wait_counter[1];
--M1L313 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_1~137
--operation mode is normal
M1L313 = M1_internal_cpu_data_master_dbs_address[1] & M1_internal_cpu_data_master_dbs_address[0];
--M1L314 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_1~138
--operation mode is normal
M1L314 = Q1L135 & Q1_ext_flash_s1_wait_counter[0] & M1L313 # !L1_internal_d_write;
--M1L2 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1043
--operation mode is normal
M1L2 = M1L18 # Q1L28 # Q1L52 & !M1L314;
--M1L3 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1044
--operation mode is normal
M1L3 = M1L2 # L1_internal_d_read & (GB1L17 # !M1L1);
--W1L14 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Equal1~69
--operation mode is normal
W1L14 = W1_lcd_display_control_slave_wait_counter[0] & W1L29 & W1L23 & !W1_lcd_display_control_slave_wait_counter[3];
--Q1L59 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~71
--operation mode is normal
Q1L59 = P1_cpu_data_master_requests_cpu_jtag_debug_module & !P1_cpu_jtag_debug_module_arb_addend[1] & (P1L10 # P1_cpu_jtag_debug_module_arb_addend[0]);
--W1L12 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|cpu_data_master_granted_lcd_display_control_slave~105
--operation mode is normal
W1L12 = L1_M_alu_result[7] & G1L1;
--M1L4 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1045
--operation mode is normal
M1L4 = Q1L59 # L1_internal_d_read & W1L12 & !W1L14;
--M1L5 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1046
--operation mode is normal
M1L5 = Q1_lan91c111_s1_wait_counter[3] # Q1_lan91c111_s1_wait_counter[2] # Q1_lan91c111_s1_wait_counter[1] # !Q1_lan91c111_s1_wait_counter[0];
--M1L6 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1047
--operation mode is normal
M1L6 = L1_internal_d_write & !M1L5 & (Q1L8 # Q1L10) # !L1_internal_d_write & (Q1L8 # Q1L10);
--M1L7 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1048
--operation mode is normal
M1L7 = Q1L58 & (!M1L6) # !Q1L58 & Q1_cpu_data_master_requests_lan91c111_s1 & !Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0];
--M1L8 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1049
--operation mode is normal
M1L8 = M1L4 # M1L7 # W1L18 & !W1L14;
--M1L311 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_0~180
--operation mode is normal
M1L311 = Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] # L1_internal_d_write & (!L1_M_mem_byte_en[3]);
--M1L312 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_0~181
--operation mode is normal
M1L312 = Q1_cpu_data_master_requests_ext_flash_s1 & !Q1L52 & (!M1L311 # !M1L313);
--Q1L27 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~376
--operation mode is normal
Q1L27 = Q1L52 & (!Q1L12 & !Q1L14);
--AB1L3 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_qualified_request_onchip_ram_64_kbytes_s1~68
--operation mode is normal
AB1L3 = AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & AB1L2;
--M1L9 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1050
--operation mode is normal
M1L9 = M1L312 # Q1L27 # AB1L3 & AB1L1;
--EB1L2 is std_1s10:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1~44
--operation mode is normal
EB1L2 = P1L7 & NB1L2 & EB1L4 & !L1_M_alu_result[4];
--U1L2 is std_1s10:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave|cpu_data_master_requests_jtag_uart_avalon_jtag_slave~443
--operation mode is normal
U1L2 = !L1_M_alu_result[7] & !L1_M_alu_result[3];
--T1_internal_av_waitrequest is std_1s10:inst|jtag_uart:the_jtag_uart|internal_av_waitrequest
--operation mode is normal
T1_internal_av_waitrequest_lut_out = T1L56;
T1_internal_av_waitrequest = DFFEAS(T1_internal_av_waitrequest_lut_out, DE1__clk0, E1_data_out, , , , , , );
--T1L54 is std_1s10:inst|jtag_uart:the_jtag_uart|process2~42
--operation mode is normal
T1L54 = !T1_internal_av_waitrequest & (!L1_internal_d_write & !L1_internal_d_read # !M1_internal_cpu_data_master_waitrequest);
--M1L10 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1051
--operation mode is normal
M1L10 = GB1L18 & (GB1_sdram_s1_slavearbiterlockenable & GB1L70 # !GB1L16);
--FE1_stage_0 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_0
--operation mode is normal
FE1_stage_0_lut_out = GE1_full_1 & FE1_stage_1 # !GE1_full_1 & (GB1L14);
FE1_stage_0 = DFFEAS(FE1_stage_0_lut_out, DE1__clk0, VCC, , GE1L26, , , , );
--M1L11 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1052
--operation mode is normal
M1L11 = !FE1_stage_0 # !FB1_za_valid # !FE1_fifo_contains_ones_n;
--M1L12 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1053
--operation mode is normal
M1L12 = M1L10 & (M1L11 # AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & !AB1L2) # !M1L10 & (AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & !AB1L2);
--YB1_slave_state[0] is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[0]
--operation mode is normal
YB1_slave_state[0]_lut_out = !YB1L8 & (YB1_slave_state[2] # !YB1L9 & YB1L10);
YB1_slave_state[0] = DFFEAS(YB1_slave_state[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--XB2_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_done_edge_to_pulse|data_in_d1
--operation mode is normal
XB2_data_in_d1_lut_out = SB1_data_out;
XB2_data_in_d1 = DFFEAS(XB2_data_in_d1_lut_out, DE1__clk0, E1_data_out, , , , , , );
--SB1_data_out is std_1s10:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync|data_out
--operation mode is normal
SB1_data_out_lut_out = SB1_data_in_d1;
SB1_data_out = DFFEAS(SB1_data_out_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YB1_slave_state[1] is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[1]
--operation mode is normal
YB1_slave_state[1]_lut_out = !YB1L6 & (YB1_slave_state[1] & (YB1_slave_state[0]) # !YB1_slave_state[1] & J1L1 & !YB1_slave_state[0]);
YB1_slave_state[1] = DFFEAS(YB1_slave_state[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L13 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1054
--operation mode is normal
M1L13 = YB1_slave_state[0] & !YB1_slave_state[1] & (XB2_data_in_d1 $ !SB1_data_out);
--YB1_slave_state[2] is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[2]
--operation mode is normal
YB1_slave_state[2]_lut_out = !YB1_slave_state[1] & !YB1L5 & (YB1_slave_state[2] # YB1L4);
YB1_slave_state[2] = DFFEAS(YB1_slave_state[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YB1L10 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux3~66
--operation mode is normal
YB1L10 = YB1_slave_state[1] $ !YB1_slave_state[0];
--XB1_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse|data_in_d1
--operation mode is normal
XB1_data_in_d1_lut_out = RB1_data_out;
XB1_data_in_d1 = DFFEAS(XB1_data_in_d1_lut_out, DE1__clk0, E1_data_out, , , , , , );
--RB1_data_out is std_1s10:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_out
--operation mode is normal
RB1_data_out_lut_out = RB1_data_in_d1;
RB1_data_out = DFFEAS(RB1_data_out_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YB1L7 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux2~228
--operation mode is normal
YB1L7 = YB1_slave_state[1] & (XB1_data_in_d1 $ RB1_data_out);
--M1L14 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1055
--operation mode is normal
M1L14 = YB1_slave_state[2] & M1L13 # !YB1_slave_state[2] & (YB1L10 & !YB1L7);
--J1_cpu_data_master_requests_clock_0_in is std_1s10:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in
--operation mode is normal
J1_cpu_data_master_requests_clock_0_in = P1L7 & NB1L2 & X1L11 & J1L3;
--M1L15 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1056
--operation mode is normal
M1L15 = M1_internal_cpu_data_master_waitrequest # M1L14 & J1_cpu_data_master_requests_clock_0_in # !QB1L4;
--M1L16 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1057
--operation mode is normal
M1L16 = T1L56 # M1L12 # M1L15;
--M1L17 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1058
--operation mode is normal
M1L17 = M1L16 # Q1L56 & !Q1L24 & !Q1L26;
--E1_data_in_d1 is std_1s10:inst|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch|data_in_d1
--operation mode is normal
E1_data_in_d1_lut_out = VCC;
E1_data_in_d1 = DFFEAS(E1_data_in_d1_lut_out, DE1__clk0, !B1L1, , , , , , );
--VC1_resetrequest is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|resetrequest
--operation mode is normal
VC1_resetrequest = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[22], !C1_CLR_SIGNAL, DD1L190);
--BB1_count_done is std_1s10:inst|pll:the_pll|count_done
--operation mode is normal
BB1_count_done_lut_out = BB1_count_done # BB1_countup[4] & BB1_countup[5] & BB1L31;
BB1_count_done = DFFEAS(BB1_count_done_lut_out, PLD_CLOCKINPUT, BB1_not_areset, , , , , , );
--B1L1 is std_1s10:inst|reset_n_sources~17
--operation mode is normal
B1L1 = VC1_resetrequest # !PLD_CLEAR_N # !BB1_count_done;
--Q1L138 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_counter_load_value[3]~150
--operation mode is normal
Q1L138 = Q1_ext_ram_bus_avalon_slave_begins_xfer & (Q1L136 # Q1L63 # Q1L80);
--Q1L31 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add4~124
--operation mode is normal
Q1L31 = Q1_ext_flash_s1_wait_counter[1] # Q1_ext_flash_s1_wait_counter[0];
--Q1L137 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_counter_load_value[1]~153
--operation mode is normal
Q1L137 = Q1_ext_flash_s1_wait_counter[1] & Q1_ext_flash_s1_wait_counter[0] # !Q1_ext_flash_s1_wait_counter[1] & !Q1_ext_flash_s1_wait_counter[0] & (Q1_ext_flash_s1_wait_counter[3] # Q1_ext_flash_s1_wait_counter[2]);
--Q1L2 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4229
--operation mode is normal
Q1L2 = Q1_ext_ram_bus_avalon_slave_begins_xfer & (Q1L82 # L1_internal_d_read & Q1L48);
--Q1L29 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add3~125
--operation mode is normal
Q1L29 = Q1_lan91c111_s1_wait_counter[3] & (Q1_lan91c111_s1_wait_counter[0] # Q1_lan91c111_s1_wait_counter[2] # Q1_lan91c111_s1_wait_counter[1]);
--Q1L193 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_end_xfer~81
--operation mode is normal
Q1L193 = QB1L4 & Q1L58 & (Q1L8 # Q1L10);
--Q1L241 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_counter_load_value[3]~101
--operation mode is normal
Q1L241 = Q1_ext_ram_bus_avalon_slave_begins_xfer & (Q1L82 # QB1L4 & Q1L48);
--Q1L30 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add3~126
--operation mode is normal
Q1L30 = !Q1_lan91c111_s1_wait_counter[0] & !Q1_lan91c111_s1_wait_counter[1];
--FB1L279 is std_1s10:inst|sdram:the_sdram|Mux24~1459
--operation mode is normal
FB1L279 = FB1_m_state[6] & (FB1_m_state[4] # !FB1L278 # !FB1L246);
--FB1L176 is std_1s10:inst|sdram:the_sdram|m_count~759
--operation mode is normal
FB1L176 = FB1_init_done & FB1_refresh_request;
--FB1L280 is std_1s10:inst|sdram:the_sdram|Mux24~1460
--operation mode is normal
FB1L280 = FB1L348 & FB1L424 & FB1L176 & !FB1_m_state[0];
--FB1L281 is std_1s10:inst|sdram:the_sdram|Mux24~1461
--operation mode is normal
FB1L281 = FB1_m_state[0] & !FB1_m_state[4] & !FB1_m_state[3] & !FB1_m_state[8];
--FB1L282 is std_1s10:inst|sdram:the_sdram|Mux24~1462
--operation mode is normal
FB1L282 = FB1_m_state[5] & (!FB1_m_state[2]) # !FB1_m_state[5] & FB1_m_next[1] & FB1_m_state[2];
--FB1_m_count[2] is std_1s10:inst|sdram:the_sdram|m_count[2]
--operation mode is normal
FB1_m_count[2]_lut_out = FB1_m_state[8] & FB1_m_count[2] & (FB1L351 # FB1L363) # !FB1_m_state[8] & (FB1L363);
FB1_m_count[2] = DFFEAS(FB1_m_count[2]_lut_out, DE1__clk0, E1_data_out, , !FB1_m_state[6], , , , );
--FB1_m_count[1] is std_1s10:inst|sdram:the_sdram|m_count[1]
--operation mode is normal
FB1_m_count[1]_lut_out = FB1_m_state[4] & FB1_m_count[1] & (FB1L366 # FB1L376) # !FB1_m_state[4] & (FB1L376);
FB1_m_count[1] = DFFEAS(FB1_m_count[1]_lut_out, DE1__clk0, E1_data_out, , !FB1_m_state[6], , , , );
--FB1L149 is std_1s10:inst|sdram:the_sdram|LessThan1~52
--operation mode is normal
FB1L149 = FB1_m_count[2] # FB1_m_count[1];
--FB1L508 is std_1s10:inst|sdram:the_sdram|Mux118~1211
--operation mode is normal
FB1L508 = FB1_m_state[0] & !FB1_m_state[7] & !FB1_m_state[8] & !FB1_m_state[2];
--FB1L311 is std_1s10:inst|sdram:the_sdram|Mux29~1321
--operation mode is normal
FB1L311 = FB1_m_state[1] & (!FB1L310 # !FB1L508 # !FB1L348);
--FB1L312 is std_1s10:inst|sdram:the_sdram|Mux29~1322
--operation mode is normal
FB1L312 = !FB1_m_state[7] & !FB1_m_state[5] & !FB1_m_state[6];
--FB1L272 is std_1s10:inst|sdram:the_sdram|Mux22~1316
--operation mode is normal
FB1L272 = FB1_m_state[2] & (!FB1_m_count[2] & !FB1_m_count[1]);
--FB1L285 is std_1s10:inst|sdram:the_sdram|Mux25~1250
--operation mode is normal
FB1L285 = FB1_m_next[1] & FB1L272 & FB1L281;
--FB1L391 is std_1s10:inst|sdram:the_sdram|Mux44~1251
--operation mode is normal
FB1L391 = !FB1_m_state[4] & !FB1_m_state[3] & (EE1_entries[0] # EE1_entries[1]);
--FB1L313 is std_1s10:inst|sdram:the_sdram|Mux29~1323
--operation mode is normal
FB1L313 = !FB1_m_state[0] & !FB1_m_state[8] & !FB1_m_state[2];
--FB1L314 is std_1s10:inst|sdram:the_sdram|Mux29~1324
--operation mode is normal
FB1L314 = FB1_init_done & FB1L391 & FB1L313 & !FB1_refresh_request;
--FB1L547 is std_1s10:inst|sdram:the_sdram|Mux154~540
--operation mode is normal
FB1L547 = !FB1_m_state[7] & !FB1_m_state[5] & !FB1_m_state[6] & !FB1_m_state[1];
--FB1L574 is std_1s10:inst|sdram:the_sdram|refresh_request~91
--operation mode is normal
FB1L574 = !EE1_entries[0] & !EE1_entries[1] & !FB1_refresh_request;
--FB1L273 is std_1s10:inst|sdram:the_sdram|Mux22~1317
--operation mode is normal
FB1L273 = FB1L264 & !FB1_m_state[2] & (FB1L554 # !EE1L127);
--FB1L274 is std_1s10:inst|sdram:the_sdram|Mux22~1318
--operation mode is normal
FB1L274 = FB1_m_state[8] & FB1L348 # !FB1_m_state[8] & (FB1L273 # FB1L348 & FB1L276);
--FB1L286 is std_1s10:inst|sdram:the_sdram|Mux25~1251
--operation mode is normal
FB1L286 = FB1_m_state[8] # FB1_m_state[6] # FB1_m_count[2] # FB1_m_count[1];
--FB1L379 is std_1s10:inst|sdram:the_sdram|Mux42~1466
--operation mode is normal
FB1L379 = FB1_m_state[0] & (!FB1_m_state[4] & !FB1_m_state[3]);
--FB1L349 is std_1s10:inst|sdram:the_sdram|Mux40~1436
--operation mode is normal
FB1L349 = !FB1_m_state[7] & !FB1_m_state[2] & !FB1_m_state[1];
--FB1L287 is std_1s10:inst|sdram:the_sdram|Mux25~1252
--operation mode is normal
FB1L287 = FB1_m_state[5] & (FB1L286 # !FB1L349 # !FB1L379);
--FB1L423 is std_1s10:inst|sdram:the_sdram|Mux59~1274
--operation mode is normal
FB1L423 = FB1L391 & (!FB1_refresh_request);
--FB1L288 is std_1s10:inst|sdram:the_sdram|Mux25~1253
--operation mode is normal
FB1L288 = FB1L554 & FB1_m_state[8] & FB1L256 & FB1L423;
--FB1L300 is std_1s10:inst|sdram:the_sdram|Mux28~1602
--operation mode is normal
FB1L300 = FB1_m_state[2] & (FB1_m_state[8] # FB1L309 # !FB1L547);
--FB1L301 is std_1s10:inst|sdram:the_sdram|Mux28~1603
--operation mode is normal
FB1L301 = FB1_m_state[0] & (!FB1_m_state[5] & !FB1_m_state[2]);
--FB1L302 is std_1s10:inst|sdram:the_sdram|Mux28~1604
--operation mode is normal
FB1L302 = FB1_refresh_request & (!FB1_m_state[6] & !FB1_m_state[1]);
--FB1L303 is std_1s10:inst|sdram:the_sdram|Mux28~1605
--operation mode is normal
FB1L303 = FB1_m_state[8] & !FB1_m_state[4] & !FB1_m_state[3] & !FB1_m_state[7];
--FB1L304 is std_1s10:inst|sdram:the_sdram|Mux28~1606
--operation mode is normal
FB1L304 = FB1L264 & EE1L127 & !FB1L554 & !FB1_m_state[8];
--FB1L305 is std_1s10:inst|sdram:the_sdram|Mux28~1607
--operation mode is normal
FB1L305 = FB1L302 & (FB1L303 # FB1L304 & !FB1L261);
--FB1L306 is std_1s10:inst|sdram:the_sdram|Mux28~1608
--operation mode is normal
FB1L306 = !FB1_m_state[4] & !FB1_m_state[3] & !FB1_m_state[7] & !FB1_m_state[1];
--FB1L307 is std_1s10:inst|sdram:the_sdram|Mux28~1609
--operation mode is normal
FB1L307 = !FB1_m_state[4] & !FB1_m_state[3] & (FB1_m_state[7] $ FB1_m_state[1]);
--FB1L308 is std_1s10:inst|sdram:the_sdram|Mux28~1610
--operation mode is normal
FB1L308 = !FB1_m_state[8] & (FB1_m_state[6] & FB1L306 # !FB1_m_state[6] & (FB1L307));
--FB1L277 is std_1s10:inst|sdram:the_sdram|Mux23~1125
--operation mode is normal
FB1L277 = FB1_m_next[7] & FB1L547 & FB1L272 & FB1L281;
--FB1L289 is std_1s10:inst|sdram:the_sdram|Mux26~1221
--operation mode is normal
FB1L289 = FB1_m_state[4] & (FB1_m_state[3] # FB1L294 # !FB1L298);
--FB1L290 is std_1s10:inst|sdram:the_sdram|Mux26~1222
--operation mode is normal
FB1L290 = FB1_m_state[2] & !FB1_m_state[8] & !FB1_m_count[2] & !FB1_m_count[1];
--FB1L291 is std_1s10:inst|sdram:the_sdram|Mux26~1223
--operation mode is normal
FB1L291 = FB1_m_state[8] & (!FB1_m_state[2]);
--FB1L292 is std_1s10:inst|sdram:the_sdram|Mux26~1224
--operation mode is normal
FB1L292 = EE1L127 & FB1L291 & !FB1L554 & !FB1_refresh_request;
--EE1L175 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[58]~509
--operation mode is normal
EE1L175 = EE1_rd_address & EE1_entry_1[58] # !EE1_rd_address & (EE1_entry_0[58]);
--FB1L293 is std_1s10:inst|sdram:the_sdram|Mux26~1225
--operation mode is normal
FB1L293 = FB1_m_next[4] & (FB1L290 # FB1L292 & !EE1L175) # !FB1_m_next[4] & (FB1L292 & !EE1L175);
--FB1L365 is std_1s10:inst|sdram:the_sdram|Mux41~1448
--operation mode is normal
FB1L365 = FB1_m_state[0] & (!FB1_m_state[3]);
--FB1L295 is std_1s10:inst|sdram:the_sdram|Mux27~1226
--operation mode is normal
FB1L295 = FB1_m_state[3] & (FB1_m_state[4] # FB1L294 # !FB1L298);
--FB1L296 is std_1s10:inst|sdram:the_sdram|Mux27~1227
--operation mode is normal
FB1L296 = EE1L175 & (FB1L292 # FB1_m_next[3] & FB1L290) # !EE1L175 & FB1_m_next[3] & FB1L290;
--FB1L297 is std_1s10:inst|sdram:the_sdram|Mux27~1228
--operation mode is normal
FB1L297 = FB1_m_state[0] & (!FB1_m_state[4]);
--FB1L315 is std_1s10:inst|sdram:the_sdram|Mux30~1227
--operation mode is normal
FB1L315 = FB1L348 & FB1L547 & FB1L290 & !FB1_m_next[0];
--FB1L29 is std_1s10:inst|sdram:the_sdram|active_cs_n~277
--operation mode is normal
FB1L29 = FB1_init_done & !FB1_m_state[4] & !FB1_m_state[3] & !FB1_m_state[8];
--FB1L30 is std_1s10:inst|sdram:the_sdram|active_cs_n~278
--operation mode is normal
FB1L30 = FB1L547 & FB1L29 & (!FB1_m_state[2]);
--FB1L392 is std_1s10:inst|sdram:the_sdram|Mux44~1252
--operation mode is normal
FB1L392 = FB1L547 & !FB1_m_state[2] & !FB1_refresh_request;
--FB1L393 is std_1s10:inst|sdram:the_sdram|Mux44~1253
--operation mode is normal
FB1L393 = FB1_m_state[0] & (FB1_m_state[8]) # !FB1_m_state[0] & FB1_init_done & !FB1_m_state[8];
--FB1L394 is std_1s10:inst|sdram:the_sdram|Mux44~1254
--operation mode is normal
FB1L394 = FB1L391 & FB1L393 & (!FB1_m_state[0] # !FB1L554);
--GB1L39 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[9]~154
--operation mode is normal
GB1L39 = GB1L14 & L1_M_alu_result[11] # !GB1L14 & (L1_ic_fill_line[6]);
--FB1L237 is std_1s10:inst|sdram:the_sdram|module_input~19
--operation mode is normal
FB1L237 = GB1L19 # GB1L14 & (L1_internal_d_write # L1_internal_d_read);
--EE1_wr_address is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|wr_address
--operation mode is normal
EE1_wr_address_lut_out = EE1_wr_address $ (FB1L237 & (EE1_entries[0] # !EE1_entries[1]));
EE1_wr_address = DFFEAS(EE1_wr_address_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1L419 is std_1s10:inst|sdram:the_sdram|Mux58~1328
--operation mode is normal
FB1L419 = EE1_rd_address & EE1_entry_1[45] # !EE1_rd_address & (EE1_entry_0[45]);
--FB1L396 is std_1s10:inst|sdram:the_sdram|Mux47~1287
--operation mode is normal
FB1L396 = FB1L264 & EE1L127 & !FB1L554 & !FB1_refresh_request;
--FB1L420 is std_1s10:inst|sdram:the_sdram|Mux58~1329
--operation mode is normal
FB1L420 = FB1L423 & (FB1_m_state[0] & !FB1L554 # !FB1_m_state[0] & (FB1_init_done));
--FB1L421 is std_1s10:inst|sdram:the_sdram|Mux58~1330
--operation mode is normal
FB1L421 = FB1_m_state[8] & (FB1_m_state[0] & FB1L420) # !FB1_m_state[8] & (FB1_m_state[0] & FB1L396 # !FB1_m_state[0] & (FB1L420));
--FB1L422 is std_1s10:inst|sdram:the_sdram|Mux58~1331
--operation mode is normal
FB1L422 = FB1L421 & (FB1L419) # !FB1L421 & FB1_active_addr[9];
--FB1L395 is std_1s10:inst|sdram:the_sdram|Mux44~1256
--operation mode is normal
FB1L395 = FB1L547 & (!FB1_m_state[2]);
--GB1L38 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[8]~155
--operation mode is normal
GB1L38 = GB1L14 & L1_M_alu_result[10] # !GB1L14 & (L1_ic_fill_line[5]);
--FB1L12 is std_1s10:inst|sdram:the_sdram|active_addr[8]~4927
--operation mode is normal
FB1L12 = E1_data_out & FB1L395 & (FB1_init_done # FB1_m_state[0]);
--FB1L13 is std_1s10:inst|sdram:the_sdram|active_addr[8]~4928
--operation mode is normal
FB1L13 = FB1_m_state[0] & (!FB1_m_state[8] # !FB1L554);
--FB1L14 is std_1s10:inst|sdram:the_sdram|active_addr[8]~4929
--operation mode is normal
FB1L14 = FB1_m_state[8] & FB1L423 & (FB1L13) # !FB1_m_state[8] & (FB1L13 & (FB1L396) # !FB1L13 & FB1L423);
--GB1L44 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[14]~156
--operation mode is normal
GB1L44 = GB1L14 & L1_M_alu_result[16] # !GB1L14 & (L1_ic_fill_tag[4]);
--FB1L409 is std_1s10:inst|sdram:the_sdram|Mux53~1277
--operation mode is normal
FB1L409 = EE1_rd_address & EE1_entry_1[50] # !EE1_rd_address & (EE1_entry_0[50]);
--FB1L410 is std_1s10:inst|sdram:the_sdram|Mux53~1278
--operation mode is normal
FB1L410 = FB1L421 & (FB1L409) # !FB1L421 & FB1_active_addr[14];
--GB1L43 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[13]~157
--operation mode is normal
GB1L43 = GB1L14 & L1_M_alu_result[15] # !GB1L14 & (L1_ic_fill_tag[3]);
--FB1L411 is std_1s10:inst|sdram:the_sdram|Mux54~1277
--operation mode is normal
FB1L411 = EE1_rd_address & EE1_entry_1[49] # !EE1_rd_address & (EE1_entry_0[49]);
--FB1L412 is std_1s10:inst|sdram:the_sdram|Mux54~1278
--operation mode is normal
FB1L412 = FB1L421 & (FB1L411) # !FB1L421 & FB1_active_addr[13];
--GB1L41 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[11]~158
--operation mode is normal
GB1L41 = GB1L14 & L1_M_alu_result[13] # !GB1L14 & (L1_ic_fill_tag[1]);
--FB1L415 is std_1s10:inst|sdram:the_sdram|Mux56~1277
--operation mode is normal
FB1L415 = EE1_rd_address & EE1_entry_1[47] # !EE1_rd_address & (EE1_entry_0[47]);
--FB1L416 is std_1s10:inst|sdram:the_sdram|Mux56~1278
--operation mode is normal
FB1L416 = FB1L421 & (FB1L415) # !FB1L421 & FB1_active_addr[11];
--GB1L51 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[21]~159
--operation mode is normal
GB1L51 = GB1L14 & L1_M_alu_result[23] # !GB1L14 & (L1_ic_fill_tag[11]);
--GB1L46 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[16]~160
--operation mode is normal
GB1L46 = GB1L14 & L1_M_alu_result[18] # !GB1L14 & (L1_ic_fill_tag[6]);
--FB1L405 is std_1s10:inst|sdram:the_sdram|Mux51~1277
--operation mode is normal
FB1L405 = EE1_rd_address & EE1_entry_1[52] # !EE1_rd_address & (EE1_entry_0[52]);
--FB1L406 is std_1s10:inst|sdram:the_sdram|Mux51~1278
--operation mode is normal
FB1L406 = FB1L421 & (FB1L405) # !FB1L421 & FB1_active_addr[16];
--GB1L45 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[15]~161
--operation mode is normal
GB1L45 = GB1L14 & L1_M_alu_result[17] # !GB1L14 & (L1_ic_fill_tag[5]);
--FB1L407 is std_1s10:inst|sdram:the_sdram|Mux52~1277
--operation mode is normal
FB1L407 = EE1_rd_address & EE1_entry_1[51] # !EE1_rd_address & (EE1_entry_0[51]);
--FB1L408 is std_1s10:inst|sdram:the_sdram|Mux52~1278
--operation mode is normal
FB1L408 = FB1L421 & (FB1L407) # !FB1L421 & FB1_active_addr[15];
--GB1L47 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[17]~162
--operation mode is normal
GB1L47 = GB1L14 & L1_M_alu_result[19] # !GB1L14 & (L1_ic_fill_tag[7]);
--FB1L403 is std_1s10:inst|sdram:the_sdram|Mux50~1277
--operation mode is normal
FB1L403 = EE1_rd_address & EE1_entry_1[53] # !EE1_rd_address & (EE1_entry_0[53]);
--FB1L404 is std_1s10:inst|sdram:the_sdram|Mux50~1278
--operation mode is normal
FB1L404 = FB1L421 & (FB1L403) # !FB1L421 & FB1_active_addr[17];
--GB1L40 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[10]~163
--operation mode is normal
GB1L40 = GB1L14 & L1_M_alu_result[12] # !GB1L14 & (L1_ic_fill_tag[0]);
--FB1L417 is std_1s10:inst|sdram:the_sdram|Mux57~1277
--operation mode is normal
FB1L417 = EE1_rd_address & EE1_entry_1[46] # !EE1_rd_address & (EE1_entry_0[46]);
--FB1L418 is std_1s10:inst|sdram:the_sdram|Mux57~1278
--operation mode is normal
FB1L418 = FB1L421 & (FB1L417) # !FB1L421 & FB1_active_addr[10];
--GB1_sdram_s1_in_a_write_cycle is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_in_a_write_cycle
--operation mode is normal
GB1_sdram_s1_in_a_write_cycle = L1_internal_d_write & GB1L14;
--GB1L50 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[20]~164
--operation mode is normal
GB1L50 = GB1L14 & L1_M_alu_result[22] # !GB1L14 & (L1_ic_fill_tag[10]);
--FB1L397 is std_1s10:inst|sdram:the_sdram|Mux47~1288
--operation mode is normal
FB1L397 = EE1_rd_address & EE1_entry_1[56] # !EE1_rd_address & (EE1_entry_0[56]);
--FB1L398 is std_1s10:inst|sdram:the_sdram|Mux47~1289
--operation mode is normal
FB1L398 = FB1L421 & (FB1L397) # !FB1L421 & FB1_active_addr[20];
--GB1L48 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[18]~165
--operation mode is normal
GB1L48 = GB1L14 & L1_M_alu_result[20] # !GB1L14 & (L1_ic_fill_tag[8]);
--FB1L401 is std_1s10:inst|sdram:the_sdram|Mux49~1277
--operation mode is normal
FB1L401 = EE1_rd_address & EE1_entry_1[54] # !EE1_rd_address & (EE1_entry_0[54]);
--FB1L402 is std_1s10:inst|sdram:the_sdram|Mux49~1278
--operation mode is normal
FB1L402 = FB1L421 & (FB1L401) # !FB1L421 & FB1_active_addr[18];
--GB1L42 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[12]~166
--operation mode is normal
GB1L42 = GB1L14 & L1_M_alu_result[14] # !GB1L14 & (L1_ic_fill_tag[2]);
--FB1L413 is std_1s10:inst|sdram:the_sdram|Mux55~1277
--operation mode is normal
FB1L413 = EE1_rd_address & EE1_entry_1[48] # !EE1_rd_address & (EE1_entry_0[48]);
--FB1L414 is std_1s10:inst|sdram:the_sdram|Mux55~1278
--operation mode is normal
FB1L414 = FB1L421 & (FB1L413) # !FB1L421 & FB1_active_addr[12];
--FB1L31 is std_1s10:inst|sdram:the_sdram|active_cs_n~279
--operation mode is normal
FB1L31 = E1_data_out & (!FB1_m_state[0]);
--FB1L32 is std_1s10:inst|sdram:the_sdram|active_cs_n~280
--operation mode is normal
FB1L32 = FB1L547 & FB1L29 & FB1L31 & !FB1_m_state[2];
--GB1L49 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[19]~167
--operation mode is normal
GB1L49 = GB1L14 & L1_M_alu_result[21] # !GB1L14 & (L1_ic_fill_tag[9]);
--FB1L399 is std_1s10:inst|sdram:the_sdram|Mux48~1277
--operation mode is normal
FB1L399 = EE1_rd_address & EE1_entry_1[55] # !EE1_rd_address & (EE1_entry_0[55]);
--FB1L400 is std_1s10:inst|sdram:the_sdram|Mux48~1278
--operation mode is normal
FB1L400 = FB1L421 & (FB1L399) # !FB1L421 & FB1_active_addr[19];
--FB1_i_state[0] is std_1s10:inst|sdram:the_sdram|i_state[0]
--operation mode is normal
FB1_i_state[0]_lut_out = FB1L241 # FB1L138 & (FB1_i_state[1] # FB1L103);
FB1_i_state[0] = DFFEAS(FB1_i_state[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_i_state[2] is std_1s10:inst|sdram:the_sdram|i_state[2]
--operation mode is normal
FB1_i_state[2]_lut_out = FB1_i_state[0] & (FB1_i_state[2] & (!FB1_i_state[1]) # !FB1_i_state[2] & FB1L238 & FB1_i_state[1]);
FB1_i_state[2] = DFFEAS(FB1_i_state[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_i_state[1] is std_1s10:inst|sdram:the_sdram|i_state[1]
--operation mode is normal
FB1_i_state[1]_lut_out = FB1_i_state[0] & (FB1_i_state[1] & (FB1L239 # FB1_i_state[2]) # !FB1_i_state[1] & (!FB1_i_state[2])) # !FB1_i_state[0] & FB1_i_state[1] & (!FB1_i_state[2]);
FB1_i_state[1] = DFFEAS(FB1_i_state[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1L125 is std_1s10:inst|sdram:the_sdram|i_cmd[0]~636
--operation mode is normal
FB1L125 = FB1_i_state[0] & FB1_i_state[1] # !FB1_i_state[2];
--FB1_refresh_counter[3] is std_1s10:inst|sdram:the_sdram|refresh_counter[3]
--operation mode is normal
FB1_refresh_counter[3]_lut_out = !FB1L74;
FB1_refresh_counter[3] = DFFEAS(FB1_refresh_counter[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_refresh_counter[0] is std_1s10:inst|sdram:the_sdram|refresh_counter[0]
--operation mode is normal
FB1_refresh_counter[0]_lut_out = FB1L76;
FB1_refresh_counter[0] = DFFEAS(FB1_refresh_counter[0]_lut_out, DE1__clk0, VCC, , , A1L275, !E1_data_out, , );
--FB1_refresh_counter[1] is std_1s10:inst|sdram:the_sdram|refresh_counter[1]
--operation mode is normal
FB1_refresh_counter[1]_lut_out = FB1L78 & (!FB1L103);
FB1_refresh_counter[1] = DFFEAS(FB1_refresh_counter[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_refresh_counter[2] is std_1s10:inst|sdram:the_sdram|refresh_counter[2]
--operation mode is normal
FB1_refresh_counter[2]_lut_out = FB1L80;
FB1_refresh_counter[2] = DFFEAS(FB1_refresh_counter[2]_lut_out, DE1__clk0, VCC, , , A1L275, !E1_data_out, , );
--FB1L100 is std_1s10:inst|sdram:the_sdram|Equal1~166
--operation mode is normal
FB1L100 = FB1_refresh_counter[3] & !FB1_refresh_counter[0] & !FB1_refresh_counter[1] & !FB1_refresh_counter[2];
--FB1_refresh_counter[7] is std_1s10:inst|sdram:the_sdram|refresh_counter[7]
--operation mode is normal
FB1_refresh_counter[7]_lut_out = FB1L103 # !FB1L82;
FB1_refresh_counter[7] = DFFEAS(FB1_refresh_counter[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_refresh_counter[4] is std_1s10:inst|sdram:the_sdram|refresh_counter[4]
--operation mode is normal
FB1_refresh_counter[4]_lut_out = FB1L84 & (!FB1L103);
FB1_refresh_counter[4] = DFFEAS(FB1_refresh_counter[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_refresh_counter[5] is std_1s10:inst|sdram:the_sdram|refresh_counter[5]
--operation mode is normal
FB1_refresh_counter[5]_lut_out = FB1L86 & (!FB1L103);
FB1_refresh_counter[5] = DFFEAS(FB1_refresh_counter[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_refresh_counter[6] is std_1s10:inst|sdram:the_sdram|refresh_counter[6]
--operation mode is normal
FB1_refresh_counter[6]_lut_out = FB1L88 & (!FB1L103);
FB1_refresh_counter[6] = DFFEAS(FB1_refresh_counter[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1L101 is std_1s10:inst|sdram:the_sdram|Equal1~167
--operation mode is normal
FB1L101 = FB1_refresh_counter[7] & !FB1_refresh_counter[4] & !FB1_refresh_counter[5] & !FB1_refresh_counter[6];
--FB1_refresh_counter[12] is std_1s10:inst|sdram:the_sdram|refresh_counter[12]
--operation mode is normal
FB1_refresh_counter[12]_lut_out = FB1L103 # !FB1L90;
FB1_refresh_counter[12] = DFFEAS(FB1_refresh_counter[12]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_refresh_counter[8] is std_1s10:inst|sdram:the_sdram|refresh_counter[8]
--operation mode is normal
FB1_refresh_counter[8]_lut_out = !FB1L91;
FB1_refresh_counter[8] = DFFEAS(FB1_refresh_counter[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_refresh_counter[9] is std_1s10:inst|sdram:the_sdram|refresh_counter[9]
--operation mode is normal
FB1_refresh_counter[9]_lut_out = !FB1L93;
FB1_refresh_counter[9] = DFFEAS(FB1_refresh_counter[9]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_refresh_counter[10] is std_1s10:inst|sdram:the_sdram|refresh_counter[10]
--operation mode is normal
FB1_refresh_counter[10]_lut_out = FB1L95 & (!FB1L103);
FB1_refresh_counter[10] = DFFEAS(FB1_refresh_counter[10]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_refresh_counter[11] is std_1s10:inst|sdram:the_sdram|refresh_counter[11]
--operation mode is normal
FB1_refresh_counter[11]_lut_out = FB1L97 & (!FB1L103);
FB1_refresh_counter[11] = DFFEAS(FB1_refresh_counter[11]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1L102 is std_1s10:inst|sdram:the_sdram|Equal1~168
--operation mode is normal
FB1L102 = FB1_refresh_counter[8] & FB1_refresh_counter[9] & !FB1_refresh_counter[10] & !FB1_refresh_counter[11];
--FB1L103 is std_1s10:inst|sdram:the_sdram|Equal1~169
--operation mode is normal
FB1L103 = FB1L100 & FB1L101 & FB1_refresh_counter[12] & FB1L102;
--FB1_ack_refresh_request is std_1s10:inst|sdram:the_sdram|ack_refresh_request
--operation mode is normal
FB1_ack_refresh_request_lut_out = FB1L271 & (FB1_m_state[7] # FB1_ack_refresh_request & !FB1_init_done) # !FB1L271 & (FB1_ack_refresh_request);
FB1_ack_refresh_request = DFFEAS(FB1_ack_refresh_request_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1L341 is std_1s10:inst|sdram:the_sdram|Mux39~1227
--operation mode is normal
FB1L341 = FB1L306 & (FB1_refresh_request # EE1L127 & FB1L554);
--FB1L316 is std_1s10:inst|sdram:the_sdram|Mux32~1273
--operation mode is normal
FB1L316 = FB1L306 & FB1_init_done & (FB1_m_next[7] # FB1_refresh_request) # !FB1L306 & (FB1_m_next[7]);
--FB1L317 is std_1s10:inst|sdram:the_sdram|Mux32~1274
--operation mode is normal
FB1L317 = FB1_m_next[7] & (FB1_m_state[4] # FB1_m_state[1] # !FB1L221);
--FB1L318 is std_1s10:inst|sdram:the_sdram|Mux32~1275
--operation mode is normal
FB1L318 = FB1_m_state[4] & (FB1_m_state[7] # !FB1_m_state[1] & FB1L221) # !FB1_m_state[4] & FB1_m_state[1];
--FB1L319 is std_1s10:inst|sdram:the_sdram|Mux32~1276
--operation mode is normal
FB1L319 = FB1_m_state[3] & (FB1_m_state[7]) # !FB1_m_state[3] & FB1_m_next[7] & (FB1_m_state[7] $ !FB1L318);
--FB1L320 is std_1s10:inst|sdram:the_sdram|Mux32~1277
--operation mode is normal
FB1L320 = FB1_m_state[3] & (FB1L319 & (FB1_m_next[7]) # !FB1L319 & FB1L317) # !FB1_m_state[3] & (FB1L319);
--FB1L321 is std_1s10:inst|sdram:the_sdram|Mux32~1278
--operation mode is normal
FB1L321 = FB1_m_state[8] & (!FB1_m_state[0]) # !FB1_m_state[8] & (FB1_m_state[0] & (FB1L320) # !FB1_m_state[0] & FB1L316);
--FB1L342 is std_1s10:inst|sdram:the_sdram|Mux39~1228
--operation mode is normal
FB1L342 = !FB1_m_state[5] & !FB1_m_state[2] & !FB1_m_state[6];
--FB1L343 is std_1s10:inst|sdram:the_sdram|Mux39~1229
--operation mode is normal
FB1L343 = FB1L306 & (!FB1_refresh_request & !FB1_m_next[0] # !FB1_init_done) # !FB1L306 & (!FB1_m_next[0]);
--FB1L344 is std_1s10:inst|sdram:the_sdram|Mux39~1230
--operation mode is normal
FB1L344 = FB1_m_state[7] # FB1_m_state[1] & (FB1_m_state[4] # FB1_m_state[3]);
--FB1L345 is std_1s10:inst|sdram:the_sdram|Mux39~1231
--operation mode is normal
FB1L345 = FB1L344 & (FB1L348) # !FB1L344 & FB1L264 & FB1L221;
--FB1L346 is std_1s10:inst|sdram:the_sdram|Mux39~1232
--operation mode is normal
FB1L346 = FB1_m_next[0] & !FB1_m_state[1] & (FB1L345) # !FB1_m_next[0] & (FB1L344 # !FB1_m_state[1]);
--FB1L347 is std_1s10:inst|sdram:the_sdram|Mux39~1233
--operation mode is normal
FB1L347 = FB1_m_state[8] & (!FB1_m_state[0]) # !FB1_m_state[8] & (FB1_m_state[0] & (FB1L346) # !FB1_m_state[0] & FB1L343);
--FB1L336 is std_1s10:inst|sdram:the_sdram|Mux38~1199
--operation mode is normal
FB1L336 = FB1_m_next[1] & (FB1_init_done & !FB1_refresh_request # !FB1L306);
--FB1L337 is std_1s10:inst|sdram:the_sdram|Mux38~1200
--operation mode is normal
FB1L337 = FB1_m_next[1] & (FB1_m_state[4] # FB1_m_state[1] # !FB1L221);
--FB1L338 is std_1s10:inst|sdram:the_sdram|Mux38~1201
--operation mode is normal
FB1L338 = FB1_m_state[3] & (FB1_m_state[7]) # !FB1_m_state[3] & FB1_m_next[1] & (FB1_m_state[7] $ !FB1L318);
--FB1L339 is std_1s10:inst|sdram:the_sdram|Mux38~1202
--operation mode is normal
FB1L339 = FB1_m_state[3] & (FB1L338 & (FB1_m_next[1]) # !FB1L338 & FB1L337) # !FB1_m_state[3] & (FB1L338);
--FB1L340 is std_1s10:inst|sdram:the_sdram|Mux38~1203
--operation mode is normal
FB1L340 = FB1_m_state[8] & (!FB1_m_state[0]) # !FB1_m_state[8] & (FB1_m_state[0] & (FB1L339) # !FB1_m_state[0] & FB1L336);
--FB1L329 is std_1s10:inst|sdram:the_sdram|Mux36~1263
--operation mode is normal
FB1L329 = FB1_m_next[3] & (!FB1L222 # !FB1L448);
--FB1L330 is std_1s10:inst|sdram:the_sdram|Mux36~1264
--operation mode is normal
FB1L330 = FB1_m_state[4] & FB1_m_next[3] # !FB1_m_state[4] & (FB1_m_state[3] & FB1_m_next[3] # !FB1_m_state[3] & (FB1_active_rnw));
--FB1L331 is std_1s10:inst|sdram:the_sdram|Mux36~1265
--operation mode is normal
FB1L331 = FB1_m_next[3] & (FB1_init_done & !FB1_refresh_request # !FB1L348);
--FB1L332 is std_1s10:inst|sdram:the_sdram|Mux36~1266
--operation mode is normal
FB1L332 = FB1_m_state[1] & (!FB1_m_state[0]) # !FB1_m_state[1] & (FB1_m_state[0] & (FB1L335) # !FB1_m_state[0] & FB1L331);
--FB1L333 is std_1s10:inst|sdram:the_sdram|Mux36~1267
--operation mode is normal
FB1L333 = FB1_m_state[1] & (FB1L332 & (FB1_m_next[3]) # !FB1L332 & FB1L330) # !FB1_m_state[1] & (FB1L332);
--FB1L334 is std_1s10:inst|sdram:the_sdram|Mux36~1268
--operation mode is normal
FB1L334 = FB1_m_state[7] & (FB1_m_state[8]) # !FB1_m_state[7] & (FB1_m_state[8] & FB1L329 # !FB1_m_state[8] & (FB1L333));
--FB1L322 is std_1s10:inst|sdram:the_sdram|Mux35~1193
--operation mode is normal
FB1L322 = FB1_m_next[4] & (!FB1L222 # !FB1L448);
--FB1L323 is std_1s10:inst|sdram:the_sdram|Mux35~1194
--operation mode is normal
FB1L323 = FB1_m_state[4] & FB1_m_next[4] # !FB1_m_state[4] & (FB1_m_state[3] & FB1_m_next[4] # !FB1_m_state[3] & (!FB1_active_rnw));
--FB1L324 is std_1s10:inst|sdram:the_sdram|Mux35~1195
--operation mode is normal
FB1L324 = FB1_m_next[4] & (FB1_init_done & !FB1_refresh_request # !FB1L348);
--FB1L325 is std_1s10:inst|sdram:the_sdram|Mux35~1196
--operation mode is normal
FB1L325 = FB1_m_state[1] & (!FB1_m_state[0]) # !FB1_m_state[1] & (FB1_m_state[0] & (FB1L328) # !FB1_m_state[0] & FB1L324);
--FB1L326 is std_1s10:inst|sdram:the_sdram|Mux35~1197
--operation mode is normal
FB1L326 = FB1_m_state[1] & (FB1L325 & (FB1_m_next[4]) # !FB1L325 & FB1L323) # !FB1_m_state[1] & (FB1L325);
--FB1L327 is std_1s10:inst|sdram:the_sdram|Mux35~1198
--operation mode is normal
FB1L327 = FB1_m_state[7] & (FB1_m_state[8]) # !FB1_m_state[7] & (FB1_m_state[8] & FB1L322 # !FB1_m_state[8] & (FB1L326));
--L1_M_ipending_reg[2] is std_1s10:inst|cpu:the_cpu|M_ipending_reg[2]
--operation mode is normal
L1_M_ipending_reg[2] = AMPP_FUNCTION(DE1__clk0, L1_M_ienable_reg[2], T1L49, M1L304, SC1_internal_oci_ienable1[2], E1_data_out);
--L1_M_ienable_reg[2] is std_1s10:inst|cpu:the_cpu|M_ienable_reg[2]
--operation mode is normal
L1_M_ienable_reg[2] = AMPP_FUNCTION(DE1__clk0, L1L410, E1_data_out, L1L1150);
--L1_D_iw[8] is std_1s10:inst|cpu:the_cpu|D_iw[8]
--operation mode is normal
L1_D_iw[8] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[8], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[7] is std_1s10:inst|cpu:the_cpu|D_iw[7]
--operation mode is normal
L1_D_iw[7] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[7], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[6] is std_1s10:inst|cpu:the_cpu|D_iw[6]
--operation mode is normal
L1_D_iw[6] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[6], L1L1095, E1_data_out, L1_W_stall);
--L1L186 is std_1s10:inst|cpu:the_cpu|D_control_rd_data_without_mmu_regs[2]~418
--operation mode is normal
L1L186 = AMPP_FUNCTION(L1_D_iw[8], L1_D_iw[7], L1_D_iw[6]);
--L1_D_iw[4] is std_1s10:inst|cpu:the_cpu|D_iw[4]
--operation mode is normal
L1_D_iw[4] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[4], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[15] is std_1s10:inst|cpu:the_cpu|D_iw[15]
--operation mode is normal
L1_D_iw[15] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[15], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[5] is std_1s10:inst|cpu:the_cpu|D_iw[5]
--operation mode is normal
L1_D_iw[5] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[5], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[0] is std_1s10:inst|cpu:the_cpu|D_iw[0]
--operation mode is normal
L1_D_iw[0] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[0], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[1] is std_1s10:inst|cpu:the_cpu|D_iw[1]
--operation mode is normal
L1_D_iw[1] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[1], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[2] is std_1s10:inst|cpu:the_cpu|D_iw[2]
--operation mode is normal
L1_D_iw[2] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[2], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[3] is std_1s10:inst|cpu:the_cpu|D_iw[3]
--operation mode is normal
L1_D_iw[3] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[3], L1L1095, E1_data_out, L1_W_stall);
--L1L808 is std_1s10:inst|cpu:the_cpu|Equal53~781
--operation mode is normal
L1L808 = AMPP_FUNCTION(L1_D_iw[0], L1_D_iw[1], L1_D_iw[2], L1_D_iw[3]);
--MC1_q_b[2] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[2] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1346, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[2] is std_1s10:inst|cpu:the_cpu|W_wr_data[2]
--operation mode is normal
L1_W_wr_data[2] = AMPP_FUNCTION(DE1__clk0, L1L1346, E1_data_out, L1_W_stall);
--L1_D_iw[29] is std_1s10:inst|cpu:the_cpu|D_iw[29]
--operation mode is normal
L1_D_iw[29] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[29], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[28] is std_1s10:inst|cpu:the_cpu|D_iw[28]
--operation mode is normal
L1_D_iw[28] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[28], L1L1095, E1_data_out, L1_W_stall);
--L1_W_dst_regnum[1] is std_1s10:inst|cpu:the_cpu|W_dst_regnum[1]
--operation mode is normal
L1_W_dst_regnum[1] = AMPP_FUNCTION(DE1__clk0, L1_M_dst_regnum[1], E1_data_out, L1_W_stall);
--L1_W_dst_regnum[2] is std_1s10:inst|cpu:the_cpu|W_dst_regnum[2]
--operation mode is normal
L1_W_dst_regnum[2] = AMPP_FUNCTION(DE1__clk0, L1_M_dst_regnum[2], E1_data_out, L1_W_stall);
--L1L371 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_W~37
--operation mode is normal
L1L371 = AMPP_FUNCTION(L1_D_iw[29], L1_D_iw[28], L1_W_dst_regnum[1], L1_W_dst_regnum[2]);
--L1_D_iw[30] is std_1s10:inst|cpu:the_cpu|D_iw[30]
--operation mode is normal
L1_D_iw[30] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[30], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[27] is std_1s10:inst|cpu:the_cpu|D_iw[27]
--operation mode is normal
L1_D_iw[27] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[27], L1L1095, E1_data_out, L1_W_stall);
--L1_W_dst_regnum[0] is std_1s10:inst|cpu:the_cpu|W_dst_regnum[0]
--operation mode is normal
L1_W_dst_regnum[0] = AMPP_FUNCTION(DE1__clk0, L1_M_dst_regnum[0], E1_data_out, L1_W_stall);
--L1_W_dst_regnum[3] is std_1s10:inst|cpu:the_cpu|W_dst_regnum[3]
--operation mode is normal
L1_W_dst_regnum[3] = AMPP_FUNCTION(DE1__clk0, L1_M_dst_regnum[3], E1_data_out, L1_W_stall);
--L1L372 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_W~38
--operation mode is normal
L1L372 = AMPP_FUNCTION(L1_D_iw[30], L1_D_iw[27], L1_W_dst_regnum[0], L1_W_dst_regnum[3]);
--L1_W_wr_dst_reg is std_1s10:inst|cpu:the_cpu|W_wr_dst_reg
--operation mode is normal
L1_W_wr_dst_reg = AMPP_FUNCTION(DE1__clk0, L1_M_wr_dst_reg, E1_data_out, L1_W_stall);
--L1_D_iw[31] is std_1s10:inst|cpu:the_cpu|D_iw[31]
--operation mode is normal
L1_D_iw[31] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[31], L1L1095, E1_data_out, L1_W_stall);
--L1_W_dst_regnum[4] is std_1s10:inst|cpu:the_cpu|W_dst_regnum[4]
--operation mode is normal
L1_W_dst_regnum[4] = AMPP_FUNCTION(DE1__clk0, L1_M_dst_regnum[4], E1_data_out, L1_W_stall);
--L1L373 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_W~39
--operation mode is normal
L1L373 = AMPP_FUNCTION(L1_W_wr_dst_reg, L1_D_iw[31], L1_W_dst_regnum[4]);
--L1L187 is std_1s10:inst|cpu:the_cpu|D_ctrl_a_not_src~70
--operation mode is normal
L1L187 = AMPP_FUNCTION(L1_D_iw[4], L1_D_iw[5]);
--L1L188 is std_1s10:inst|cpu:the_cpu|D_ctrl_a_not_src~71
--operation mode is normal
L1L188 = AMPP_FUNCTION(L1L187, L1_D_iw[1], L1_D_iw[2], L1_D_iw[3]);
--L1_D_src1_hazard_W is std_1s10:inst|cpu:the_cpu|D_src1_hazard_W
--operation mode is normal
L1_D_src1_hazard_W = AMPP_FUNCTION(L1L371, L1L372, L1L373, L1L188);
--L1_M_dst_regnum[1] is std_1s10:inst|cpu:the_cpu|M_dst_regnum[1]
--operation mode is normal
L1_M_dst_regnum[1] = AMPP_FUNCTION(DE1__clk0, L1_E_dst_regnum[1], E1_data_out, L1_W_stall);
--L1_M_dst_regnum[2] is std_1s10:inst|cpu:the_cpu|M_dst_regnum[2]
--operation mode is normal
L1_M_dst_regnum[2] = AMPP_FUNCTION(DE1__clk0, L1_E_dst_regnum[2], E1_data_out, L1_W_stall);
--L1L367 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_M~37
--operation mode is normal
L1L367 = AMPP_FUNCTION(L1_D_iw[29], L1_D_iw[28], L1_M_dst_regnum[1], L1_M_dst_regnum[2]);
--L1_M_dst_regnum[0] is std_1s10:inst|cpu:the_cpu|M_dst_regnum[0]
--operation mode is normal
L1_M_dst_regnum[0] = AMPP_FUNCTION(DE1__clk0, L1_E_dst_regnum[0], E1_data_out, L1_W_stall);
--L1_M_dst_regnum[3] is std_1s10:inst|cpu:the_cpu|M_dst_regnum[3]
--operation mode is normal
L1_M_dst_regnum[3] = AMPP_FUNCTION(DE1__clk0, L1_E_dst_regnum[3], E1_data_out, L1_W_stall);
--L1L368 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_M~38
--operation mode is normal
L1L368 = AMPP_FUNCTION(L1_D_iw[30], L1_D_iw[27], L1_M_dst_regnum[0], L1_M_dst_regnum[3]);
--L1_M_dst_regnum[4] is std_1s10:inst|cpu:the_cpu|M_dst_regnum[4]
--operation mode is normal
L1_M_dst_regnum[4] = AMPP_FUNCTION(DE1__clk0, L1_E_dst_regnum[4], E1_data_out, L1_W_stall);
--L1_M_wr_dst_reg is std_1s10:inst|cpu:the_cpu|M_wr_dst_reg
--operation mode is normal
L1_M_wr_dst_reg = AMPP_FUNCTION(DE1__clk0, L1L803, E1_data_out, L1_W_stall);
--L1L369 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_M~39
--operation mode is normal
L1L369 = AMPP_FUNCTION(L1_D_iw[31], L1_M_dst_regnum[4], L1_M_wr_dst_reg);
--L1_D_src1_hazard_M is std_1s10:inst|cpu:the_cpu|D_src1_hazard_M
--operation mode is normal
L1_D_src1_hazard_M = AMPP_FUNCTION(L1L367, L1L368, L1L369, L1L188);
--L1_E_wr_dst_reg_from_D is std_1s10:inst|cpu:the_cpu|E_wr_dst_reg_from_D
--operation mode is normal
L1_E_wr_dst_reg_from_D = AMPP_FUNCTION(DE1__clk0, L1L401, L1L232, L1L236, L1L829, E1_data_out, L1_W_stall);
--L1L802 is std_1s10:inst|cpu:the_cpu|E_wr_dst_reg~35
--operation mode is normal
L1L802 = AMPP_FUNCTION(L1_M_pipe_flush, L1_E_wr_dst_reg_from_D);
--L1L803 is std_1s10:inst|cpu:the_cpu|E_wr_dst_reg~36
--operation mode is normal
L1L803 = AMPP_FUNCTION(L1L802, L1L483, L1L484, L1L968);
--L1_E_dst_regnum[4] is std_1s10:inst|cpu:the_cpu|E_dst_regnum[4]
--operation mode is normal
L1_E_dst_regnum[4] = AMPP_FUNCTION(DE1__clk0, L1L236, E1_data_out, L1_W_stall);
--L1_E_dst_regnum[1] is std_1s10:inst|cpu:the_cpu|E_dst_regnum[1]
--operation mode is normal
L1_E_dst_regnum[1] = AMPP_FUNCTION(DE1__clk0, L1L232, E1_data_out, L1_W_stall);
--L1L363 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_E~52
--operation mode is normal
L1L363 = AMPP_FUNCTION(L1_D_iw[28], L1_D_iw[31], L1_E_dst_regnum[4], L1_E_dst_regnum[1]);
--L1_E_dst_regnum[2] is std_1s10:inst|cpu:the_cpu|E_dst_regnum[2]
--operation mode is normal
L1_E_dst_regnum[2] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[24], L1_D_iw[19], L1_D_ctrl_b_not_src, L1L235, E1_data_out, L1_W_stall);
--L1L364 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_E~53
--operation mode is normal
L1L364 = AMPP_FUNCTION(L1L363, L1_D_iw[29], L1_E_dst_regnum[2]);
--L1_E_dst_regnum[3] is std_1s10:inst|cpu:the_cpu|E_dst_regnum[3]
--operation mode is normal
L1_E_dst_regnum[3] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[25], L1_D_iw[20], L1_D_ctrl_b_not_src, L1L235, E1_data_out, L1_W_stall);
--L1_E_dst_regnum[0] is std_1s10:inst|cpu:the_cpu|E_dst_regnum[0]
--operation mode is normal
L1_E_dst_regnum[0] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[22], L1_D_iw[17], L1_D_ctrl_b_not_src, L1L235, E1_data_out, L1_W_stall);
--L1L365 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_E~54
--operation mode is normal
L1L365 = AMPP_FUNCTION(L1_D_iw[30], L1_E_dst_regnum[3], L1_D_iw[27], L1_E_dst_regnum[0]);
--QC1_result[0] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[0]
--DSP Block Operation Mode: Simple Multiplier (36-bit)
QC1_result[0] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[1] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[1]
QC1_result[1] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[2] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[2]
QC1_result[2] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[3] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[3]
QC1_result[3] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[4] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[4]
QC1_result[4] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[5] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[5]
QC1_result[5] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[6] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[6]
QC1_result[6] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[7] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[7]
QC1_result[7] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[8] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[8]
QC1_result[8] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[9] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[9]
QC1_result[9] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[10] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[10]
QC1_result[10] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[11] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[11]
QC1_result[11] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[12] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[12]
QC1_result[12] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[13] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[13]
QC1_result[13] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[14] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[14]
QC1_result[14] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[15] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[15]
QC1_result[15] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[16] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[16]
QC1_result[16] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[17] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[17]
QC1_result[17] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[18] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[18]
QC1_result[18] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[19] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[19]
QC1_result[19] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[20] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[20]
QC1_result[20] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[21] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[21]
QC1_result[21] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[22] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[22]
QC1_result[22] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[23] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[23]
QC1_result[23] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[24] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[24]
QC1_result[24] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[25] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[25]
QC1_result[25] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[26] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[26]
QC1_result[26] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[27] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[27]
QC1_result[27] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[28] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[28]
QC1_result[28] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[29] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[29]
QC1_result[29] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[30] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[30]
QC1_result[30] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[31] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[31]
QC1_result[31] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[32] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[32]
QC1_result[32] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[33] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[33]
QC1_result[33] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[34] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[34]
QC1_result[34] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[35] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[35]
QC1_result[35] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[36] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[36]
QC1_result[36] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[37] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[37]
QC1_result[37] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[38] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[38]
QC1_result[38] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[39] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[39]
QC1_result[39] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[40] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[40]
QC1_result[40] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[41] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[41]
QC1_result[41] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[42] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[42]
QC1_result[42] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[43] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[43]
QC1_result[43] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[44] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[44]
QC1_result[44] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[45] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[45]
QC1_result[45] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[46] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[46]
QC1_result[46] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[47] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[47]
QC1_result[47] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[48] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[48]
QC1_result[48] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[49] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[49]
QC1_result[49] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[50] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[50]
QC1_result[50] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[51] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[51]
QC1_result[51] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[52] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[52]
QC1_result[52] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[53] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[53]
QC1_result[53] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[54] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[54]
QC1_result[54] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[55] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[55]
QC1_result[55] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[56] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[56]
QC1_result[56] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[57] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[57]
QC1_result[57] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[58] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[58]
QC1_result[58] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[59] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[59]
QC1_result[59] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[60] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[60]
QC1_result[60] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[61] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[61]
QC1_result[61] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[62] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[62]
QC1_result[62] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[63] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[63]
QC1_result[63] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--L1L1218 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[2]~1344
--operation mode is normal
L1L1218 = AMPP_FUNCTION(QC1_result[2], QC1_result[34]);
--L1_M_ctrl_mulx is std_1s10:inst|cpu:the_cpu|M_ctrl_mulx
--operation mode is normal
L1_M_ctrl_mulx = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_mulx, E1_data_out, L1_W_stall);
--L1_M_ctrl_shift_right is std_1s10:inst|cpu:the_cpu|M_ctrl_shift_right
--operation mode is normal
L1_M_ctrl_shift_right = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_shift_right, E1_data_out, L1_W_stall);
--L1_M_shift_rot_by_zero is std_1s10:inst|cpu:the_cpu|M_shift_rot_by_zero
--operation mode is normal
L1_M_shift_rot_by_zero = AMPP_FUNCTION(DE1__clk0, L1L830, L1L653, L1L654, E1_data_out, L1_W_stall);
--L1L1247 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[31]~1345
--operation mode is normal
L1L1247 = AMPP_FUNCTION(L1_M_ctrl_mulx, L1_M_ctrl_shift_right, L1_M_shift_rot_by_zero);
--L1_M_ctrl_rot is std_1s10:inst|cpu:the_cpu|M_ctrl_rot
--operation mode is normal
L1_M_ctrl_rot = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_rot, E1_data_out, L1_W_stall);
--L1_E_ctrl_mul_shift_rot is std_1s10:inst|cpu:the_cpu|E_ctrl_mul_shift_rot
--operation mode is normal
L1_E_ctrl_mul_shift_rot = AMPP_FUNCTION(DE1__clk0, L1L229, L1L203, L1L221, L1L222, E1_data_out, L1_W_stall);
--L1_d_readdata_d1[2] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[2]
--operation mode is normal
L1_d_readdata_d1[2] = AMPP_FUNCTION(DE1__clk0, M1L44, FC1L5, FC1L6, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1_d_readdata_d1[18] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[18]
--operation mode is normal
L1_d_readdata_d1[18] = AMPP_FUNCTION(DE1__clk0, M1L160, FC1L21, FC1L22, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1_M_iw[4] is std_1s10:inst|cpu:the_cpu|M_iw[4]
--operation mode is normal
L1_M_iw[4] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[4], E1_data_out, L1_W_stall);
--L1_M_ld_align_sh16 is std_1s10:inst|cpu:the_cpu|M_ld_align_sh16
--operation mode is normal
L1_M_ld_align_sh16 = AMPP_FUNCTION(L1_M_alu_result[1], L1_M_iw[4]);
--L1_M_iw[3] is std_1s10:inst|cpu:the_cpu|M_iw[3]
--operation mode is normal
L1_M_iw[3] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[3], E1_data_out, L1_W_stall);
--L1_M_ld_align_sh8 is std_1s10:inst|cpu:the_cpu|M_ld_align_sh8
--operation mode is normal
L1_M_ld_align_sh8 = AMPP_FUNCTION(L1_M_alu_result[0], L1_M_iw[4], L1_M_iw[3]);
--L1_av_ld_aligning_data is std_1s10:inst|cpu:the_cpu|av_ld_aligning_data
--operation mode is normal
L1_av_ld_aligning_data = AMPP_FUNCTION(DE1__clk0, L1_internal_d_read, M1_internal_cpu_data_master_waitrequest, E1_data_out);
--L1L216 is std_1s10:inst|cpu:the_cpu|D_ctrl_hi_imm~98
--operation mode is normal
L1L216 = AMPP_FUNCTION(L1_D_iw[0], L1_D_iw[1], L1_D_iw[4], L1_D_iw[3]);
--L1_E_src2_prelim[2] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[2]
--operation mode is normal
L1_E_src2_prelim[2] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[2], L1_W_wr_data[2], L1L1346, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1L826 is std_1s10:inst|cpu:the_cpu|Equal143~6
--operation mode is normal
L1L826 = AMPP_FUNCTION(L1_E_iw[4], L1_E_iw[3]);
--L1L195 is std_1s10:inst|cpu:the_cpu|D_ctrl_b_is_dst~79
--operation mode is normal
L1L195 = AMPP_FUNCTION(L1_D_iw[4], L1_D_iw[5], L1_D_iw[0], L1_D_iw[1]);
--L1L197 is std_1s10:inst|cpu:the_cpu|D_ctrl_b_not_src~56
--operation mode is normal
L1L197 = AMPP_FUNCTION(L1_D_iw[2], L1_D_iw[0], L1_D_iw[1], L1L195);
--L1L809 is std_1s10:inst|cpu:the_cpu|Equal53~782
--operation mode is normal
L1L809 = AMPP_FUNCTION(L1_D_iw[0], L1_D_iw[1], L1_D_iw[2], L1_D_iw[3]);
--L1L810 is std_1s10:inst|cpu:the_cpu|Equal53~783
--operation mode is normal
L1L810 = AMPP_FUNCTION(L1_D_iw[4], L1L809, L1_D_iw[5]);
--L1_D_iw[12] is std_1s10:inst|cpu:the_cpu|D_iw[12]
--operation mode is normal
L1_D_iw[12] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[12], L1L1095, E1_data_out, L1_W_stall);
--L1L811 is std_1s10:inst|cpu:the_cpu|Equal53~784
--operation mode is normal
L1L811 = AMPP_FUNCTION(L1_D_iw[4], L1_D_iw[5]);
--L1_D_iw[11] is std_1s10:inst|cpu:the_cpu|D_iw[11]
--operation mode is normal
L1_D_iw[11] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[11], L1L1095, E1_data_out, L1_W_stall);
--L1L228 is std_1s10:inst|cpu:the_cpu|D_ctrl_wrctl_inst~23
--operation mode is normal
L1L228 = AMPP_FUNCTION(L1_D_iw[12], L1L811, L1L808, L1_D_iw[11]);
--L1_D_iw[16] is std_1s10:inst|cpu:the_cpu|D_iw[16]
--operation mode is normal
L1_D_iw[16] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[16], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[14] is std_1s10:inst|cpu:the_cpu|D_iw[14]
--operation mode is normal
L1_D_iw[14] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[14], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[13] is std_1s10:inst|cpu:the_cpu|D_iw[13]
--operation mode is normal
L1_D_iw[13] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[13], L1L1095, E1_data_out, L1_W_stall);
--L1L819 is std_1s10:inst|cpu:the_cpu|Equal77~562
--operation mode is normal
L1L819 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[15], L1_D_iw[14], L1_D_iw[13]);
--L1L820 is std_1s10:inst|cpu:the_cpu|Equal77~563
--operation mode is normal
L1L820 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[15], L1_D_iw[14], L1_D_iw[13]);
--L1L821 is std_1s10:inst|cpu:the_cpu|Equal77~564
--operation mode is normal
L1L821 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[15], L1_D_iw[14], L1_D_iw[13]);
--L1L203 is std_1s10:inst|cpu:the_cpu|D_ctrl_dst_data_sel_cmp~271
--operation mode is normal
L1L203 = AMPP_FUNCTION(L1L193, L1L206);
--L1L812 is std_1s10:inst|cpu:the_cpu|Equal53~785
--operation mode is normal
L1L812 = AMPP_FUNCTION(L1_D_iw[0], L1_D_iw[1], L1_D_iw[2], L1_D_iw[3]);
--L1_D_pc_plus_one[0] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[0]
--operation mode is normal
L1_D_pc_plus_one[0] = AMPP_FUNCTION(DE1__clk0, L1L914, E1_data_out, L1_W_stall);
--L1_D_br_taken_waddr_partial[0] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[0]
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[0] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[8], L1L914, E1_data_out, L1_W_stall);
--L1L164 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[0]~55
--operation mode is arithmetic
L1L164 = AMPP_FUNCTION(KC1_q_b[8], L1L914);
--L1L198 is std_1s10:inst|cpu:the_cpu|D_ctrl_br_cond~92
--operation mode is normal
L1L198 = AMPP_FUNCTION(L1_D_iw[4], L1_D_iw[5], L1_D_iw[2], L1_D_iw[3]);
--L1L199 is std_1s10:inst|cpu:the_cpu|D_ctrl_br_cond~93
--operation mode is normal
L1L199 = AMPP_FUNCTION(L1_D_iw[1], L1L198, L1_D_iw[0]);
--L1_D_iw[21] is std_1s10:inst|cpu:the_cpu|D_iw[21]
--operation mode is normal
L1_D_iw[21] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[21], L1L1095, E1_data_out, L1_W_stall);
--L1_E_ctrl_alu_subtract is std_1s10:inst|cpu:the_cpu|E_ctrl_alu_subtract
--operation mode is normal
L1_E_ctrl_alu_subtract = AMPP_FUNCTION(DE1__clk0, L1L191, L1L219, L1L192, E1_data_out, L1_W_stall);
--L1L822 is std_1s10:inst|cpu:the_cpu|Equal77~565
--operation mode is normal
L1L822 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[15], L1_D_iw[14], L1_D_iw[13]);
--L1L823 is std_1s10:inst|cpu:the_cpu|Equal77~566
--operation mode is normal
L1L823 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[15], L1_D_iw[14], L1_D_iw[13]);
--L1L824 is std_1s10:inst|cpu:the_cpu|Equal77~567
--operation mode is normal
L1L824 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[15], L1_D_iw[14], L1_D_iw[13]);
--L1L825 is std_1s10:inst|cpu:the_cpu|Equal77~568
--operation mode is normal
L1L825 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[15], L1_D_iw[14], L1_D_iw[13]);
--L1L813 is std_1s10:inst|cpu:the_cpu|Equal53~786
--operation mode is normal
L1L813 = AMPP_FUNCTION(L1_D_iw[0], L1_D_iw[1], L1_D_iw[2], L1_D_iw[3]);
--L1L814 is std_1s10:inst|cpu:the_cpu|Equal53~787
--operation mode is normal
L1L814 = AMPP_FUNCTION(L1_D_iw[0], L1_D_iw[1], L1_D_iw[2], L1_D_iw[3]);
--L1L207 is std_1s10:inst|cpu:the_cpu|D_ctrl_dst_data_sel_logic_result~47
--operation mode is normal
L1L207 = AMPP_FUNCTION(L1_D_iw[4], L1L813, L1L814);
--L1L815 is std_1s10:inst|cpu:the_cpu|Equal53~788
--operation mode is normal
L1L815 = AMPP_FUNCTION(L1_D_iw[0], L1_D_iw[1], L1_D_iw[2], L1_D_iw[3]);
--L1L204 is std_1s10:inst|cpu:the_cpu|D_ctrl_dst_data_sel_cmp~272
--operation mode is normal
L1L204 = AMPP_FUNCTION(L1L815, L1L818, L1_D_iw[4], L1_D_iw[5]);
--L1L205 is std_1s10:inst|cpu:the_cpu|D_ctrl_dst_data_sel_cmp~273
--operation mode is normal
L1L205 = AMPP_FUNCTION(L1L811, L1L808, L1_D_iw[11], L1_D_iw[12]);
--L1_M_valid_mul_shift_rot_entered_M is std_1s10:inst|cpu:the_cpu|M_valid_mul_shift_rot_entered_M
--operation mode is normal
L1_M_valid_mul_shift_rot_entered_M = AMPP_FUNCTION(DE1__clk0, L1L800, L1_E_ctrl_mul_shift_rot, L1_W_stall, E1_data_out);
--L1_M_ipending_reg[3] is std_1s10:inst|cpu:the_cpu|M_ipending_reg[3]
--operation mode is normal
L1_M_ipending_reg[3] = AMPP_FUNCTION(DE1__clk0, L1_M_ienable_reg[3], HE1_irq, SC1_internal_oci_ienable1[3], E1_data_out);
--L1_M_ienable_reg[3] is std_1s10:inst|cpu:the_cpu|M_ienable_reg[3]
--operation mode is normal
L1_M_ienable_reg[3] = AMPP_FUNCTION(DE1__clk0, L1L411, E1_data_out, L1L1150);
--MC1_q_b[3] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[3] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1349, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[3] is std_1s10:inst|cpu:the_cpu|W_wr_data[3]
--operation mode is normal
L1_W_wr_data[3] = AMPP_FUNCTION(DE1__clk0, L1L1349, E1_data_out, L1_W_stall);
--L1L1219 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[3]~1346
--operation mode is normal
L1L1219 = AMPP_FUNCTION(QC1_result[3], QC1_result[35]);
--L1_d_readdata_d1[3] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[3]
--operation mode is normal
L1_d_readdata_d1[3] = AMPP_FUNCTION(DE1__clk0, M1L53, FC1L7, FC1L8, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1_d_readdata_d1[19] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[19]
--operation mode is normal
L1_d_readdata_d1[19] = AMPP_FUNCTION(DE1__clk0, M1L165, FC1L21, FC1L23, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1_D_iw[9] is std_1s10:inst|cpu:the_cpu|D_iw[9]
--operation mode is normal
L1_D_iw[9] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[9], L1L1095, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[3] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[3]
--operation mode is normal
L1_E_src2_prelim[3] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[3], L1_W_wr_data[3], L1L1349, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_D_pc_plus_one[1] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[1]
--operation mode is normal
L1_D_pc_plus_one[1] = AMPP_FUNCTION(DE1__clk0, L1L916, E1_data_out, L1_W_stall);
--L1_D_br_taken_waddr_partial[1] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[1]
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[1] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[9], L1L916, E1_data_out, L1_W_stall, L1L164);
--L1L166 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[1]~56
--operation mode is arithmetic
L1L166 = AMPP_FUNCTION(KC1_q_b[9], L1L916, L1L164);
--L1_D_pc_plus_one[5] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[5]
--operation mode is normal
L1_D_pc_plus_one[5] = AMPP_FUNCTION(DE1__clk0, L1L924, E1_data_out, L1_W_stall);
--L1_D_br_taken_waddr_partial[5] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[5]
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[5] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[13], L1L924, E1_data_out, L1_W_stall, L1L172);
--L1L174 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[5]~57
--operation mode is arithmetic
L1L174 = AMPP_FUNCTION(KC1_q_b[13], L1L924, L1L172);
--MC1_q_b[7] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[7] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1361, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[7] is std_1s10:inst|cpu:the_cpu|W_wr_data[7]
--operation mode is normal
L1_W_wr_data[7] = AMPP_FUNCTION(DE1__clk0, L1L1361, E1_data_out, L1_W_stall);
--L1L1223 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[7]~1347
--operation mode is normal
L1L1223 = AMPP_FUNCTION(QC1_result[7], QC1_result[39]);
--L1_d_readdata_d1[7] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[7]
--operation mode is normal
L1_d_readdata_d1[7] = AMPP_FUNCTION(DE1__clk0, M1L87, FC1L21, FC1L10, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1_d_readdata_d1[23] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[23]
--operation mode is normal
L1_d_readdata_d1[23] = AMPP_FUNCTION(DE1__clk0, M1L185, FC1L21, FC1L27, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1_E_src2_prelim[7] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[7]
--operation mode is normal
L1_E_src2_prelim[7] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[7], L1_W_wr_data[7], L1L1361, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_D_issue is std_1s10:inst|cpu:the_cpu|D_issue
--operation mode is normal
L1_D_issue = AMPP_FUNCTION(DE1__clk0, L1L857, L1L862, L1L861, L1_F_kill, E1_data_out, L1_W_stall);
--L1_E_ctrl_flush_pipe_always is std_1s10:inst|cpu:the_cpu|E_ctrl_flush_pipe_always
--operation mode is normal
L1_E_ctrl_flush_pipe_always = AMPP_FUNCTION(DE1__clk0, L1L210, L1L817, L1L213, E1_data_out, L1_W_stall);
--L1_E_ctrl_br_cond is std_1s10:inst|cpu:the_cpu|E_ctrl_br_cond
--operation mode is normal
L1_E_ctrl_br_cond = AMPP_FUNCTION(DE1__clk0, L1L199, E1_data_out, L1_W_stall);
--L1_E_iw[21] is std_1s10:inst|cpu:the_cpu|E_iw[21]
--operation mode is normal
L1_E_iw[21] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[21], E1_data_out, L1_W_stall);
--GC1L1 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~558
--operation mode is normal
--HC1_result[32] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[32]
--operation mode is normal
HC1_result[32] = AMPP_FUNCTION(GND, HC1L65, L1_E_ctrl_alu_subtract);
--L1L416 is std_1s10:inst|cpu:the_cpu|E_br_actually_taken~243
--operation mode is normal
L1L416 = AMPP_FUNCTION(GC1L1, L1_E_logic_op[1], HC1_result[32], L1_E_logic_op[0]);
--L1L1251 is std_1s10:inst|cpu:the_cpu|M_pipe_flush_nxt~105
--operation mode is normal
L1L1251 = AMPP_FUNCTION(L1_E_ctrl_br_cond, L1_E_iw[21], L1L416);
--VC1_probepresent is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|probepresent
--operation mode is normal
VC1_probepresent = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[19], VC1_probepresent, DD1_internal_jdo1[18], !C1_CLR_SIGNAL, DD1L190);
--DD1_internal_jdo1[21] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[21]
--operation mode is normal
DD1_internal_jdo1[21] = AMPP_FUNCTION(!A1L9, DD1_sr[21], VCC, DD1L144);
--DD1_internal_jdo1[20] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[20]
--operation mode is normal
DD1_internal_jdo1[20] = AMPP_FUNCTION(!A1L9, DD1_sr[20], VCC, DD1L144);
--VC1L1 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|A_WE_StdLogicVector~9
--operation mode is normal
VC1L1 = AMPP_FUNCTION(DD1_internal_jdo1[21], VC1_jtag_break, DD1_internal_jdo1[20]);
--C1_CLR_SIGNAL is sld_hub:sld_hub_inst|CLR_SIGNAL
--operation mode is normal
C1_CLR_SIGNAL = AMPP_FUNCTION(!A1L6, RE1_state[1], ME1_Q[0], VCC);
--DD1_internal_jdo1[34] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[34]
--operation mode is normal
DD1_internal_jdo1[34] = AMPP_FUNCTION(!A1L9, DD1_sr[34], VCC, DD1L144);
--DD1_jxdr is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|jxdr
--operation mode is normal
DD1_jxdr = AMPP_FUNCTION(DE1__clk0, DD1_dr_update2, DD1_dr_update1, VCC);
--DD1_internal_jdo1[35] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[35]
--operation mode is normal
DD1_internal_jdo1[35] = AMPP_FUNCTION(!A1L9, DD1_sr[35], VCC, DD1L144);
--DD1_ir[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0]
--operation mode is normal
DD1_ir[0] = AMPP_FUNCTION(!A1L6, ME5_Q[0], VCC, DD1L116);
--DD1_ir[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[1]
--operation mode is normal
DD1_ir[1] = AMPP_FUNCTION(!A1L6, ME5_Q[1], VCC, DD1L116);
--DD1L189 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_a~42
--operation mode is normal
DD1L189 = AMPP_FUNCTION(DD1_jxdr, DD1_internal_jdo1[35], DD1_ir[0], DD1_ir[1]);
--DD1L190 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_a~43
--operation mode is normal
DD1L190 = AMPP_FUNCTION(DD1_internal_jdo1[34], DD1L189);
--L1_M_iw[5] is std_1s10:inst|cpu:the_cpu|M_iw[5]
--operation mode is normal
L1_M_iw[5] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[5], E1_data_out, L1_W_stall);
--L1_M_ctrl_break is std_1s10:inst|cpu:the_cpu|M_ctrl_break
--operation mode is normal
L1_M_ctrl_break = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_break, E1_data_out, L1_W_stall);
--L1L962 is std_1s10:inst|cpu:the_cpu|hbreak_enabled~268
--operation mode is normal
L1L962 = AMPP_FUNCTION(L1_M_iw[4], L1_M_iw[3], L1_M_iw[5], L1_M_ctrl_break);
--L1L963 is std_1s10:inst|cpu:the_cpu|hbreak_enabled~269
--operation mode is normal
L1L963 = AMPP_FUNCTION(L1_M_valid_from_E, L1L962, L1L1443, KB1L7);
--L1_M_iw[1] is std_1s10:inst|cpu:the_cpu|M_iw[1]
--operation mode is normal
L1_M_iw[1] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[1], E1_data_out, L1_W_stall);
--L1_M_iw[2] is std_1s10:inst|cpu:the_cpu|M_iw[2]
--operation mode is normal
L1_M_iw[2] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[2], E1_data_out, L1_W_stall);
--L1_M_iw[0] is std_1s10:inst|cpu:the_cpu|M_iw[0]
--operation mode is normal
L1_M_iw[0] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[0], E1_data_out, L1_W_stall);
--L1_M_iw[16] is std_1s10:inst|cpu:the_cpu|M_iw[16]
--operation mode is normal
L1_M_iw[16] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[16], E1_data_out, L1_W_stall);
--L1L964 is std_1s10:inst|cpu:the_cpu|hbreak_enabled~270
--operation mode is normal
L1L964 = AMPP_FUNCTION(L1_M_iw[1], L1_M_iw[2], L1_M_iw[0], L1_M_iw[16]);
--L1_M_iw[11] is std_1s10:inst|cpu:the_cpu|M_iw[11]
--operation mode is normal
L1_M_iw[11] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[11], E1_data_out, L1_W_stall);
--L1_M_iw[14] is std_1s10:inst|cpu:the_cpu|M_iw[14]
--operation mode is normal
L1_M_iw[14] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[14], E1_data_out, L1_W_stall);
--L1_M_iw[15] is std_1s10:inst|cpu:the_cpu|M_iw[15]
--operation mode is normal
L1_M_iw[15] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[15], E1_data_out, L1_W_stall);
--L1_M_iw[13] is std_1s10:inst|cpu:the_cpu|M_iw[13]
--operation mode is normal
L1_M_iw[13] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[13], E1_data_out, L1_W_stall);
--L1_M_iw[12] is std_1s10:inst|cpu:the_cpu|M_iw[12]
--operation mode is normal
L1_M_iw[12] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[12], E1_data_out, L1_W_stall);
--L1L965 is std_1s10:inst|cpu:the_cpu|hbreak_enabled~271
--operation mode is normal
L1L965 = AMPP_FUNCTION(L1_M_iw[14], L1_M_iw[15], L1_M_iw[13], L1_M_iw[12]);
--L1L966 is std_1s10:inst|cpu:the_cpu|hbreak_enabled~272
--operation mode is normal
L1L966 = AMPP_FUNCTION(L1L964, L1_M_iw[11], L1L965);
--L1L967 is std_1s10:inst|cpu:the_cpu|hbreak_enabled~273
--operation mode is normal
L1L967 = AMPP_FUNCTION(L1L1443, KB1L7, L1_M_valid_from_E, L1_M_ctrl_break);
--SC1_internal_oci_single_step_mode1 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_single_step_mode1
--operation mode is normal
SC1_internal_oci_single_step_mode1 = AMPP_FUNCTION(DE1__clk0, L1_M_st_data[3], SC1_internal_oci_single_step_mode1, SC1L13, E1_data_out);
--L1_E_ctrl_ld_signed is std_1s10:inst|cpu:the_cpu|E_ctrl_ld_signed
--operation mode is normal
L1_E_ctrl_ld_signed = AMPP_FUNCTION(DE1__clk0, L1_D_iw[0], L1_D_iw[1], L1_D_iw[2], E1_data_out, L1_W_stall);
--L1_M_ipending_reg[4] is std_1s10:inst|cpu:the_cpu|M_ipending_reg[4]
--operation mode is normal
L1_M_ipending_reg[4] = AMPP_FUNCTION(DE1__clk0, L1_M_ienable_reg[4], R1_control_register[0], R1_timeout_occurred, SC1_internal_oci_ienable1[4], E1_data_out);
--L1_M_ienable_reg[4] is std_1s10:inst|cpu:the_cpu|M_ienable_reg[4]
--operation mode is normal
L1_M_ienable_reg[4] = AMPP_FUNCTION(DE1__clk0, L1L412, E1_data_out, L1L1150);
--MC1_q_b[4] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[4] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1352, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[4] is std_1s10:inst|cpu:the_cpu|W_wr_data[4]
--operation mode is normal
L1_W_wr_data[4] = AMPP_FUNCTION(DE1__clk0, L1L1352, E1_data_out, L1_W_stall);
--L1L1220 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[4]~1348
--operation mode is normal
L1L1220 = AMPP_FUNCTION(QC1_result[4], QC1_result[36]);
--L1_d_readdata_d1[4] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[4]
--operation mode is normal
L1_d_readdata_d1[4] = AMPP_FUNCTION(DE1__clk0, M1L61, P1_cpu_data_master_requests_cpu_jtag_debug_module, N1L105, E1_data_out);
--L1_d_readdata_d1[20] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[20]
--operation mode is normal
L1_d_readdata_d1[20] = AMPP_FUNCTION(DE1__clk0, M1L170, FC1L21, FC1L24, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1_D_iw[10] is std_1s10:inst|cpu:the_cpu|D_iw[10]
--operation mode is normal
L1_D_iw[10] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[10], L1L1095, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[4] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[4]
--operation mode is normal
L1_E_src2_prelim[4] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[4], L1_W_wr_data[4], L1L1352, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_D_pc_plus_one[2] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[2]
--operation mode is normal
L1_D_pc_plus_one[2] = AMPP_FUNCTION(DE1__clk0, L1L918, E1_data_out, L1_W_stall);
--L1_D_br_taken_waddr_partial[2] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[2]
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[2] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[10], L1L918, E1_data_out, L1_W_stall, L1L166);
--L1L168 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[2]~58
--operation mode is arithmetic
L1L168 = AMPP_FUNCTION(KC1_q_b[10], L1L918, L1L166);
--L1_D_pc_plus_one[20] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[20]
--operation mode is normal
L1_D_pc_plus_one[20] = AMPP_FUNCTION(DE1__clk0, L1L954, E1_data_out, L1_W_stall);
--L1L81 is std_1s10:inst|cpu:the_cpu|Add1~250
--operation mode is arithmetic
L1L81 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[20], L1L84);
--L1L82 is std_1s10:inst|cpu:the_cpu|Add1~251
--operation mode is arithmetic
L1L82 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[20], L1L84);
--MC1_q_b[22] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[22]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[22] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1406, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[22] is std_1s10:inst|cpu:the_cpu|W_wr_data[22]
--operation mode is normal
L1_W_wr_data[22] = AMPP_FUNCTION(DE1__clk0, L1L1406, E1_data_out, L1_W_stall);
--L1L1238 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[22]~1349
--operation mode is normal
L1L1238 = AMPP_FUNCTION(QC1_result[22], QC1_result[54]);
--L1_d_readdata_d1[22] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[22]
--operation mode is normal
L1_d_readdata_d1[22] = AMPP_FUNCTION(DE1__clk0, M1L179, FC1L21, FC1L26, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1_M_ctrl_ld_signed is std_1s10:inst|cpu:the_cpu|M_ctrl_ld_signed
--operation mode is normal
L1_M_ctrl_ld_signed = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_ld_signed, E1_data_out, L1_W_stall);
--L1_d_readdata_d1[15] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[15]
--operation mode is normal
L1_d_readdata_d1[15] = AMPP_FUNCTION(DE1__clk0, M1L144, FC1L21, FC1L18, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1L158 is std_1s10:inst|cpu:the_cpu|av_sign_bit~0
--operation mode is normal
L1L158 = AMPP_FUNCTION(L1_M_alu_result[0], L1_M_iw[3], L1_M_iw[4]);
--L1L159 is std_1s10:inst|cpu:the_cpu|av_sign_bit~9
--operation mode is normal
L1L159 = AMPP_FUNCTION(L1L158, L1_d_readdata_d1[23], L1_M_alu_result[1], L1_d_readdata_d1[7]);
--L1_d_readdata_d1[31] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[31]
--operation mode is normal
L1_d_readdata_d1[31] = AMPP_FUNCTION(DE1__clk0, M1L225, FC1L21, FC1L35, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1L160 is std_1s10:inst|cpu:the_cpu|av_sign_bit~10
--operation mode is normal
L1L160 = AMPP_FUNCTION(L1_d_readdata_d1[15], L1L158, L1L159, L1_d_readdata_d1[31]);
--L1L217 is std_1s10:inst|cpu:the_cpu|D_ctrl_hi_imm~99
--operation mode is normal
L1L217 = AMPP_FUNCTION(L1_D_iw[5], L1_D_iw[2], L1L216);
--L1L391 is std_1s10:inst|cpu:the_cpu|D_src2_imm[22]~2231
--operation mode is normal
L1L391 = AMPP_FUNCTION(L1_D_iw[12], L1_D_iw[21], L1L217);
--L1_E_src2_prelim[22] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[22]
--operation mode is normal
L1_E_src2_prelim[22] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[22], L1_W_wr_data[22], L1L1406, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_D_pc_plus_one[19] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[19]
--operation mode is normal
L1_D_pc_plus_one[19] = AMPP_FUNCTION(DE1__clk0, L1L952, E1_data_out, L1_W_stall);
--L1L83 is std_1s10:inst|cpu:the_cpu|Add1~252
--operation mode is arithmetic
L1L83 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[19], L1L99);
--L1L84 is std_1s10:inst|cpu:the_cpu|Add1~253
--operation mode is arithmetic
L1L84 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[19], L1L99);
--MC1_q_b[21] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[21]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[21] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1403, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[21] is std_1s10:inst|cpu:the_cpu|W_wr_data[21]
--operation mode is normal
L1_W_wr_data[21] = AMPP_FUNCTION(DE1__clk0, L1L1403, E1_data_out, L1_W_stall);
--L1L1237 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[21]~1350
--operation mode is normal
L1L1237 = AMPP_FUNCTION(QC1_result[21], QC1_result[53]);
--L1_d_readdata_d1[21] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[21]
--operation mode is normal
L1_d_readdata_d1[21] = AMPP_FUNCTION(DE1__clk0, M1L175, FC1L21, FC1L25, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1L390 is std_1s10:inst|cpu:the_cpu|D_src2_imm[21]~2233
--operation mode is normal
L1L390 = AMPP_FUNCTION(L1_D_iw[11], L1_D_iw[21], L1L217);
--L1_E_src2_prelim[21] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[21]
--operation mode is normal
L1_E_src2_prelim[21] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[21], L1_W_wr_data[21], L1L1403, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_D_pc_plus_one[22] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[22]
--operation mode is normal
L1_D_pc_plus_one[22] = AMPP_FUNCTION(DE1__clk0, L1L958, E1_data_out, L1_W_stall);
--L1L85 is std_1s10:inst|cpu:the_cpu|Add1~254
--operation mode is arithmetic
L1L85 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[22], L1L96);
--L1L86 is std_1s10:inst|cpu:the_cpu|Add1~255
--operation mode is arithmetic
L1L86 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[22], L1L96);
--L1L393 is std_1s10:inst|cpu:the_cpu|D_src2_imm[24]~2235
--operation mode is normal
L1L393 = AMPP_FUNCTION(L1_D_iw[14], L1_D_iw[21], L1L217);
--NC1_q_b[24] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[24]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[24] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1412, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1_W_wr_data[24] is std_1s10:inst|cpu:the_cpu|W_wr_data[24]
--operation mode is normal
L1_W_wr_data[24] = AMPP_FUNCTION(DE1__clk0, L1L1412, E1_data_out, L1_W_stall);
--L1_D_iw[25] is std_1s10:inst|cpu:the_cpu|D_iw[25]
--operation mode is normal
L1_D_iw[25] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[25], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[26] is std_1s10:inst|cpu:the_cpu|D_iw[26]
--operation mode is normal
L1_D_iw[26] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[26], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[24] is std_1s10:inst|cpu:the_cpu|D_iw[24]
--operation mode is normal
L1_D_iw[24] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[24], L1L1095, E1_data_out, L1_W_stall);
--L1L381 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_W~56
--operation mode is normal
L1L381 = AMPP_FUNCTION(L1_W_dst_regnum[2], L1_W_dst_regnum[4], L1_D_iw[26], L1_D_iw[24]);
--L1_D_iw[22] is std_1s10:inst|cpu:the_cpu|D_iw[22]
--operation mode is normal
L1_D_iw[22] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[22], L1L1095, E1_data_out, L1_W_stall);
--L1_D_iw[23] is std_1s10:inst|cpu:the_cpu|D_iw[23]
--operation mode is normal
L1_D_iw[23] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[23], L1L1095, E1_data_out, L1_W_stall);
--L1L382 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_W~57
--operation mode is normal
L1L382 = AMPP_FUNCTION(L1_W_dst_regnum[0], L1_D_iw[22], L1_W_dst_regnum[1], L1_D_iw[23]);
--L1L383 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_W~58
--operation mode is normal
L1L383 = AMPP_FUNCTION(L1_W_dst_regnum[3], L1_D_iw[25], L1L381, L1L382);
--L1L384 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_W~59
--operation mode is normal
L1L384 = AMPP_FUNCTION(L1_W_wr_dst_reg, L1L197, L1L810, L1L383);
--L1L377 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_M~40
--operation mode is normal
L1L377 = AMPP_FUNCTION(L1_M_dst_regnum[2], L1_M_dst_regnum[4], L1_D_iw[26], L1_D_iw[24]);
--L1L378 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_M~41
--operation mode is normal
L1L378 = AMPP_FUNCTION(L1_M_dst_regnum[0], L1_D_iw[22], L1_M_dst_regnum[1], L1_D_iw[23]);
--L1L379 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_M~42
--operation mode is normal
L1L379 = AMPP_FUNCTION(L1_M_dst_regnum[3], L1_D_iw[25], L1L377, L1L378);
--L1L380 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_M~43
--operation mode is normal
L1L380 = AMPP_FUNCTION(L1_M_wr_dst_reg, L1L197, L1L810, L1L379);
--L1L374 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_E~39
--operation mode is normal
L1L374 = AMPP_FUNCTION(L1_E_dst_regnum[1], L1_E_dst_regnum[4], L1_D_iw[26], L1_D_iw[23]);
--L1L375 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_E~40
--operation mode is normal
L1L375 = AMPP_FUNCTION(L1_E_dst_regnum[3], L1_E_dst_regnum[0], L1_D_iw[22], L1_D_iw[25]);
--L1L376 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_E~41
--operation mode is normal
L1L376 = AMPP_FUNCTION(L1L374, L1L375, L1L197, L1L810);
--L1L1240 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[24]~1351
--operation mode is normal
L1L1240 = AMPP_FUNCTION(QC1_result[24], QC1_result[56]);
--L1_d_readdata_d1[24] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[24]
--operation mode is normal
L1_d_readdata_d1[24] = AMPP_FUNCTION(DE1__clk0, M1L190, FC1L21, FC1L28, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--MC1_q_b[24] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[24]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[24] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1412, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_D_pc_plus_one[17] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[17]
--operation mode is normal
L1_D_pc_plus_one[17] = AMPP_FUNCTION(DE1__clk0, L1L948, E1_data_out, L1_W_stall);
--L1L87 is std_1s10:inst|cpu:the_cpu|Add1~256
--operation mode is arithmetic
L1L87 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[17], L1L90);
--L1L88 is std_1s10:inst|cpu:the_cpu|Add1~257
--operation mode is arithmetic
L1L88 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[17], L1L90);
--MC1_q_b[19] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[19]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[19] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1397, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[19] is std_1s10:inst|cpu:the_cpu|W_wr_data[19]
--operation mode is normal
L1_W_wr_data[19] = AMPP_FUNCTION(DE1__clk0, L1L1397, E1_data_out, L1_W_stall);
--L1L1235 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[19]~1352
--operation mode is normal
L1L1235 = AMPP_FUNCTION(QC1_result[19], QC1_result[51]);
--L1L388 is std_1s10:inst|cpu:the_cpu|D_src2_imm[19]~2237
--operation mode is normal
L1L388 = AMPP_FUNCTION(L1_D_iw[9], L1_D_iw[21], L1L217);
--L1_E_src2_prelim[19] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[19]
--operation mode is normal
L1_E_src2_prelim[19] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[19], L1_W_wr_data[19], L1L1397, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_D_pc_plus_one[16] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[16]
--operation mode is normal
L1_D_pc_plus_one[16] = AMPP_FUNCTION(DE1__clk0, L1L946, E1_data_out, L1_W_stall);
--L1L89 is std_1s10:inst|cpu:the_cpu|Add1~258
--operation mode is arithmetic
L1L89 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[16], L1L92);
--L1L90 is std_1s10:inst|cpu:the_cpu|Add1~259
--operation mode is arithmetic
L1L90 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[16], L1L92);
--MC1_q_b[18] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[18]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[18] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1394, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[18] is std_1s10:inst|cpu:the_cpu|W_wr_data[18]
--operation mode is normal
L1_W_wr_data[18] = AMPP_FUNCTION(DE1__clk0, L1L1394, E1_data_out, L1_W_stall);
--L1L1234 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[18]~1353
--operation mode is normal
L1L1234 = AMPP_FUNCTION(QC1_result[18], QC1_result[50]);
--L1L387 is std_1s10:inst|cpu:the_cpu|D_src2_imm[18]~2239
--operation mode is normal
L1L387 = AMPP_FUNCTION(L1_D_iw[8], L1_D_iw[21], L1L217);
--L1_E_src2_prelim[18] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[18]
--operation mode is normal
L1_E_src2_prelim[18] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[18], L1_W_wr_data[18], L1L1394, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_D_pc_plus_one[15] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[15]
--operation mode is normal
L1_D_pc_plus_one[15] = AMPP_FUNCTION(DE1__clk0, L1L944, E1_data_out, L1_W_stall);
--L1L91 is std_1s10:inst|cpu:the_cpu|Add1~260
--operation mode is arithmetic
L1L91 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[15], L1L94);
--L1L92 is std_1s10:inst|cpu:the_cpu|Add1~261
--operation mode is arithmetic
L1L92 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[15], L1L94);
--MC1_q_b[17] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[17]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[17] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1391, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[17] is std_1s10:inst|cpu:the_cpu|W_wr_data[17]
--operation mode is normal
L1_W_wr_data[17] = AMPP_FUNCTION(DE1__clk0, L1L1391, E1_data_out, L1_W_stall);
--L1L1233 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[17]~1354
--operation mode is normal
L1L1233 = AMPP_FUNCTION(QC1_result[17], QC1_result[49]);
--L1_d_readdata_d1[17] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[17]
--operation mode is normal
L1_d_readdata_d1[17] = AMPP_FUNCTION(DE1__clk0, M1L155, FC1L21, FC1L20, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1L386 is std_1s10:inst|cpu:the_cpu|D_src2_imm[17]~2241
--operation mode is normal
L1L386 = AMPP_FUNCTION(L1_D_iw[7], L1_D_iw[21], L1L217);
--L1_E_src2_prelim[17] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[17]
--operation mode is normal
L1_E_src2_prelim[17] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[17], L1_W_wr_data[17], L1L1391, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_D_pc_plus_one[14] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[14]
--operation mode is normal
L1_D_pc_plus_one[14] = AMPP_FUNCTION(DE1__clk0, L1L942, E1_data_out, L1_W_stall);
--L1L93 is std_1s10:inst|cpu:the_cpu|Add1~262
--operation mode is arithmetic
L1L93 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[14], L1L101);
--L1L94 is std_1s10:inst|cpu:the_cpu|Add1~263
--operation mode is arithmetic
L1L94 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[14], L1L101);
--MC1_q_b[16] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[16]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[16] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1388, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[16] is std_1s10:inst|cpu:the_cpu|W_wr_data[16]
--operation mode is normal
L1_W_wr_data[16] = AMPP_FUNCTION(DE1__clk0, L1L1388, E1_data_out, L1_W_stall);
--L1L1232 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[16]~1355
--operation mode is normal
L1L1232 = AMPP_FUNCTION(QC1_result[16], QC1_result[48]);
--L1_d_readdata_d1[16] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[16]
--operation mode is normal
L1_d_readdata_d1[16] = AMPP_FUNCTION(DE1__clk0, M1L150, FC1L21, FC1L19, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1L385 is std_1s10:inst|cpu:the_cpu|D_src2_imm[16]~2243
--operation mode is normal
L1L385 = AMPP_FUNCTION(L1_D_iw[6], L1_D_iw[21], L1L217);
--L1_E_src2_prelim[16] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[16]
--operation mode is normal
L1_E_src2_prelim[16] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[16], L1_W_wr_data[16], L1L1388, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_D_pc_plus_one[21] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[21]
--operation mode is normal
L1_D_pc_plus_one[21] = AMPP_FUNCTION(DE1__clk0, L1L956, E1_data_out, L1_W_stall);
--L1L95 is std_1s10:inst|cpu:the_cpu|Add1~264
--operation mode is arithmetic
L1L95 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[21], L1L82);
--L1L96 is std_1s10:inst|cpu:the_cpu|Add1~265
--operation mode is arithmetic
L1L96 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[21], L1L82);
--MC1_q_b[23] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[23]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[23] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1409, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[23] is std_1s10:inst|cpu:the_cpu|W_wr_data[23]
--operation mode is normal
L1_W_wr_data[23] = AMPP_FUNCTION(DE1__clk0, L1L1409, E1_data_out, L1_W_stall);
--L1L1239 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[23]~1356
--operation mode is normal
L1L1239 = AMPP_FUNCTION(QC1_result[23], QC1_result[55]);
--L1L392 is std_1s10:inst|cpu:the_cpu|D_src2_imm[23]~2245
--operation mode is normal
L1L392 = AMPP_FUNCTION(L1_D_iw[13], L1_D_iw[21], L1L217);
--L1_E_src2_prelim[23] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[23]
--operation mode is normal
L1_E_src2_prelim[23] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[23], L1_W_wr_data[23], L1L1409, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_D_pc_plus_one[23] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[23]
--operation mode is normal
L1_D_pc_plus_one[23] = AMPP_FUNCTION(DE1__clk0, L1L960, E1_data_out, L1_W_stall);
--L1L97 is std_1s10:inst|cpu:the_cpu|Add1~266
--operation mode is normal
L1L97 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[23], L1L86);
--L1L394 is std_1s10:inst|cpu:the_cpu|D_src2_imm[25]~2247
--operation mode is normal
L1L394 = AMPP_FUNCTION(L1_D_iw[15], L1_D_iw[21], L1L217);
--NC1_q_b[25] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[25]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[25] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1415, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1_W_wr_data[25] is std_1s10:inst|cpu:the_cpu|W_wr_data[25]
--operation mode is normal
L1_W_wr_data[25] = AMPP_FUNCTION(DE1__clk0, L1L1415, E1_data_out, L1_W_stall);
--L1L1241 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[25]~1357
--operation mode is normal
L1L1241 = AMPP_FUNCTION(QC1_result[25], QC1_result[57]);
--L1_d_readdata_d1[25] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[25]
--operation mode is normal
L1_d_readdata_d1[25] = AMPP_FUNCTION(DE1__clk0, M1L195, FC1L21, FC1L29, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--MC1_q_b[25] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[25]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[25] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1415, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_D_pc_plus_one[18] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[18]
--operation mode is normal
L1_D_pc_plus_one[18] = AMPP_FUNCTION(DE1__clk0, L1L950, E1_data_out, L1_W_stall);
--L1L98 is std_1s10:inst|cpu:the_cpu|Add1~268
--operation mode is arithmetic
L1L98 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[18], L1L88);
--L1L99 is std_1s10:inst|cpu:the_cpu|Add1~269
--operation mode is arithmetic
L1L99 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[18], L1L88);
--MC1_q_b[20] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[20]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[20] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1400, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[20] is std_1s10:inst|cpu:the_cpu|W_wr_data[20]
--operation mode is normal
L1_W_wr_data[20] = AMPP_FUNCTION(DE1__clk0, L1L1400, E1_data_out, L1_W_stall);
--L1L1236 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[20]~1358
--operation mode is normal
L1L1236 = AMPP_FUNCTION(QC1_result[20], QC1_result[52]);
--L1L389 is std_1s10:inst|cpu:the_cpu|D_src2_imm[20]~2249
--operation mode is normal
L1L389 = AMPP_FUNCTION(L1_D_iw[10], L1_D_iw[21], L1L217);
--L1_E_src2_prelim[20] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[20]
--operation mode is normal
L1_E_src2_prelim[20] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[20], L1_W_wr_data[20], L1L1400, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_D_pc_plus_one[13] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[13]
--operation mode is normal
L1_D_pc_plus_one[13] = AMPP_FUNCTION(DE1__clk0, L1L940, E1_data_out, L1_W_stall);
--L1L100 is std_1s10:inst|cpu:the_cpu|Add1~270
--operation mode is arithmetic
L1L100 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[13], L1L103);
--L1L101 is std_1s10:inst|cpu:the_cpu|Add1~271
--operation mode is arithmetic
L1L101 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[13], L1L103);
--NC1_q_b[15] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[15]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[15] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1385, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1_W_wr_data[15] is std_1s10:inst|cpu:the_cpu|W_wr_data[15]
--operation mode is normal
L1_W_wr_data[15] = AMPP_FUNCTION(DE1__clk0, L1L1385, E1_data_out, L1_W_stall);
--L1L1231 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[15]~1359
--operation mode is normal
L1L1231 = AMPP_FUNCTION(QC1_result[15], QC1_result[47]);
--L1_av_fill_bit is std_1s10:inst|cpu:the_cpu|av_fill_bit
--operation mode is normal
L1_av_fill_bit = AMPP_FUNCTION(L1_M_ctrl_ld_signed, L1L160);
--L1L827 is std_1s10:inst|cpu:the_cpu|Equal145~6
--operation mode is normal
L1L827 = AMPP_FUNCTION(L1_M_iw[4], L1_M_iw[3]);
--MC1_q_b[15] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[15]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[15] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1385, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_D_pc_plus_one[12] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[12]
--operation mode is normal
L1_D_pc_plus_one[12] = AMPP_FUNCTION(DE1__clk0, L1L938, E1_data_out, L1_W_stall);
--L1L102 is std_1s10:inst|cpu:the_cpu|Add1~272
--operation mode is arithmetic
L1L102 = AMPP_FUNCTION(L1_D_iw[20], L1_D_pc_plus_one[12], L1L105);
--L1L103 is std_1s10:inst|cpu:the_cpu|Add1~273
--operation mode is arithmetic
L1L103 = AMPP_FUNCTION(L1_D_iw[20], L1_D_pc_plus_one[12], L1L105);
--L1_D_iw[20] is std_1s10:inst|cpu:the_cpu|D_iw[20]
--operation mode is normal
L1_D_iw[20] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[20], L1L1095, E1_data_out, L1_W_stall);
--NC1_q_b[14] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[14]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[14] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1382, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1_W_wr_data[14] is std_1s10:inst|cpu:the_cpu|W_wr_data[14]
--operation mode is normal
L1_W_wr_data[14] = AMPP_FUNCTION(DE1__clk0, L1L1382, E1_data_out, L1_W_stall);
--L1L1230 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[14]~1360
--operation mode is normal
L1L1230 = AMPP_FUNCTION(QC1_result[14], QC1_result[46]);
--L1_d_readdata_d1[14] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[14]
--operation mode is normal
L1_d_readdata_d1[14] = AMPP_FUNCTION(DE1__clk0, M1L137, FC1L21, FC1L17, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1_d_readdata_d1[30] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[30]
--operation mode is normal
L1_d_readdata_d1[30] = AMPP_FUNCTION(DE1__clk0, M1L219, FC1L21, FC1L34, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--MC1_q_b[14] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[14]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[14] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1382, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_D_pc_plus_one[11] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[11]
--operation mode is normal
L1_D_pc_plus_one[11] = AMPP_FUNCTION(DE1__clk0, L1L936, E1_data_out, L1_W_stall);
--L1L104 is std_1s10:inst|cpu:the_cpu|Add1~274
--operation mode is arithmetic
L1L104 = AMPP_FUNCTION(L1_D_iw[19], L1_D_pc_plus_one[11], L1L107);
--L1L105 is std_1s10:inst|cpu:the_cpu|Add1~275
--operation mode is arithmetic
L1L105 = AMPP_FUNCTION(L1_D_iw[19], L1_D_pc_plus_one[11], L1L107);
--L1_D_iw[19] is std_1s10:inst|cpu:the_cpu|D_iw[19]
--operation mode is normal
L1_D_iw[19] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[19], L1L1095, E1_data_out, L1_W_stall);
--NC1_q_b[13] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[13]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[13] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1379, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1_W_wr_data[13] is std_1s10:inst|cpu:the_cpu|W_wr_data[13]
--operation mode is normal
L1_W_wr_data[13] = AMPP_FUNCTION(DE1__clk0, L1L1379, E1_data_out, L1_W_stall);
--L1L1229 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[13]~1361
--operation mode is normal
L1L1229 = AMPP_FUNCTION(QC1_result[13], QC1_result[45]);
--L1_d_readdata_d1[13] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[13]
--operation mode is normal
L1_d_readdata_d1[13] = AMPP_FUNCTION(DE1__clk0, M1L131, FC1L21, FC1L16, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1_d_readdata_d1[29] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[29]
--operation mode is normal
L1_d_readdata_d1[29] = AMPP_FUNCTION(DE1__clk0, M1L215, FC1L21, FC1L33, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--MC1_q_b[13] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[13]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[13] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1379, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_D_pc_plus_one[10] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[10]
--operation mode is normal
L1_D_pc_plus_one[10] = AMPP_FUNCTION(DE1__clk0, L1L934, E1_data_out, L1_W_stall);
--L1L106 is std_1s10:inst|cpu:the_cpu|Add1~276
--operation mode is arithmetic
L1L106 = AMPP_FUNCTION(L1_D_iw[18], L1_D_pc_plus_one[10], L1L109);
--L1L107 is std_1s10:inst|cpu:the_cpu|Add1~277
--operation mode is arithmetic
L1L107 = AMPP_FUNCTION(L1_D_iw[18], L1_D_pc_plus_one[10], L1L109);
--L1_D_iw[18] is std_1s10:inst|cpu:the_cpu|D_iw[18]
--operation mode is normal
L1_D_iw[18] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[18], L1L1095, E1_data_out, L1_W_stall);
--NC1_q_b[12] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[12]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[12] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1376, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1_W_wr_data[12] is std_1s10:inst|cpu:the_cpu|W_wr_data[12]
--operation mode is normal
L1_W_wr_data[12] = AMPP_FUNCTION(DE1__clk0, L1L1376, E1_data_out, L1_W_stall);
--L1L1228 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[12]~1362
--operation mode is normal
L1L1228 = AMPP_FUNCTION(QC1_result[12], QC1_result[44]);
--L1_d_readdata_d1[12] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[12]
--operation mode is normal
L1_d_readdata_d1[12] = AMPP_FUNCTION(DE1__clk0, M1L125, FC1L21, FC1L15, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1_d_readdata_d1[28] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[28]
--operation mode is normal
L1_d_readdata_d1[28] = AMPP_FUNCTION(DE1__clk0, M1L210, FC1L21, FC1L32, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--MC1_q_b[12] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[12]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[12] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1376, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_D_pc_plus_one[9] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[9]
--operation mode is normal
L1_D_pc_plus_one[9] = AMPP_FUNCTION(DE1__clk0, L1L932, E1_data_out, L1_W_stall);
--L1_D_br_taken_waddr_partial[9] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[9]
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[9] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[17], L1L932, E1_data_out, L1_W_stall, L1L180);
--L1L182 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[9]~59
--operation mode is arithmetic
L1L182 = AMPP_FUNCTION(KC1_q_b[17], L1L932, L1L180);
--L1_D_iw[17] is std_1s10:inst|cpu:the_cpu|D_iw[17]
--operation mode is normal
L1_D_iw[17] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, KC1_q_b[17], L1L1095, E1_data_out, L1_W_stall);
--NC1_q_b[11] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[11]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[11] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1373, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1_W_wr_data[11] is std_1s10:inst|cpu:the_cpu|W_wr_data[11]
--operation mode is normal
L1_W_wr_data[11] = AMPP_FUNCTION(DE1__clk0, L1L1373, E1_data_out, L1_W_stall);
--L1L1227 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[11]~1363
--operation mode is normal
L1L1227 = AMPP_FUNCTION(QC1_result[11], QC1_result[43]);
--L1_d_readdata_d1[11] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[11]
--operation mode is normal
L1_d_readdata_d1[11] = AMPP_FUNCTION(DE1__clk0, M1L118, FC1L21, FC1L14, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1_d_readdata_d1[27] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[27]
--operation mode is normal
L1_d_readdata_d1[27] = AMPP_FUNCTION(DE1__clk0, M1L205, FC1L21, FC1L31, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--MC1_q_b[11] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[11]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[11] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1373, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_D_pc_plus_one[8] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[8]
--operation mode is normal
L1_D_pc_plus_one[8] = AMPP_FUNCTION(DE1__clk0, L1L930, E1_data_out, L1_W_stall);
--L1_D_br_taken_waddr_partial[8] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[8]
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[8] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[16], L1L930, E1_data_out, L1_W_stall, L1L178);
--L1L180 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[8]~60
--operation mode is arithmetic
L1L180 = AMPP_FUNCTION(KC1_q_b[16], L1L930, L1L178);
--NC1_q_b[10] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[10]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[10] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1370, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1_W_wr_data[10] is std_1s10:inst|cpu:the_cpu|W_wr_data[10]
--operation mode is normal
L1_W_wr_data[10] = AMPP_FUNCTION(DE1__clk0, L1L1370, E1_data_out, L1_W_stall);
--L1L1226 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[10]~1364
--operation mode is normal
L1L1226 = AMPP_FUNCTION(QC1_result[10], QC1_result[42]);
--L1_d_readdata_d1[10] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[10]
--operation mode is normal
L1_d_readdata_d1[10] = AMPP_FUNCTION(DE1__clk0, M1L111, FC1L21, FC1L13, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1_d_readdata_d1[26] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[26]
--operation mode is normal
L1_d_readdata_d1[26] = AMPP_FUNCTION(DE1__clk0, M1L200, FC1L21, FC1L30, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--MC1_q_b[10] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[10]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[10] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1370, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_D_pc_plus_one[7] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[7]
--operation mode is normal
L1_D_pc_plus_one[7] = AMPP_FUNCTION(DE1__clk0, L1L928, E1_data_out, L1_W_stall);
--L1_D_br_taken_waddr_partial[7] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[7]
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[7] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[15], L1L928, E1_data_out, L1_W_stall, L1L176);
--L1L178 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[7]~61
--operation mode is arithmetic
L1L178 = AMPP_FUNCTION(KC1_q_b[15], L1L928, L1L176);
--NC1_q_b[9] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[9] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1367, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1_W_wr_data[9] is std_1s10:inst|cpu:the_cpu|W_wr_data[9]
--operation mode is normal
L1_W_wr_data[9] = AMPP_FUNCTION(DE1__clk0, L1L1367, E1_data_out, L1_W_stall);
--L1L1225 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[9]~1365
--operation mode is normal
L1L1225 = AMPP_FUNCTION(QC1_result[9], QC1_result[41]);
--L1_d_readdata_d1[9] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[9]
--operation mode is normal
L1_d_readdata_d1[9] = AMPP_FUNCTION(DE1__clk0, M1L103, FC1L21, FC1L12, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--MC1_q_b[9] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[9] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1367, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_D_pc_plus_one[6] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[6]
--operation mode is normal
L1_D_pc_plus_one[6] = AMPP_FUNCTION(DE1__clk0, L1L926, E1_data_out, L1_W_stall);
--L1_D_br_taken_waddr_partial[6] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[6]
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[6] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[14], L1L926, E1_data_out, L1_W_stall, L1L174);
--L1L176 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[6]~62
--operation mode is arithmetic
L1L176 = AMPP_FUNCTION(KC1_q_b[14], L1L926, L1L174);
--NC1_q_b[8] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[8] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1364, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1_W_wr_data[8] is std_1s10:inst|cpu:the_cpu|W_wr_data[8]
--operation mode is normal
L1_W_wr_data[8] = AMPP_FUNCTION(DE1__clk0, L1L1364, E1_data_out, L1_W_stall);
--L1L1224 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[8]~1366
--operation mode is normal
L1L1224 = AMPP_FUNCTION(QC1_result[8], QC1_result[40]);
--L1_d_readdata_d1[8] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[8]
--operation mode is normal
L1_d_readdata_d1[8] = AMPP_FUNCTION(DE1__clk0, M1L94, FC1L21, FC1L11, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--MC1_q_b[8] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[8] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1364, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_M_ipending_reg[5] is std_1s10:inst|cpu:the_cpu|M_ipending_reg[5]
--operation mode is normal
L1_M_ipending_reg[5] = AMPP_FUNCTION(DE1__clk0, L1_M_ienable_reg[5], L1L1161, L1L1162, SC1_internal_oci_ienable1[5], E1_data_out);
--L1_M_ienable_reg[5] is std_1s10:inst|cpu:the_cpu|M_ienable_reg[5]
--operation mode is normal
L1_M_ienable_reg[5] = AMPP_FUNCTION(DE1__clk0, L1L413, E1_data_out, L1L1150);
--MC1_q_b[5] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[5] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1355, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[5] is std_1s10:inst|cpu:the_cpu|W_wr_data[5]
--operation mode is normal
L1_W_wr_data[5] = AMPP_FUNCTION(DE1__clk0, L1L1355, E1_data_out, L1_W_stall);
--L1L1221 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[5]~1367
--operation mode is normal
L1L1221 = AMPP_FUNCTION(QC1_result[5], QC1_result[37]);
--L1_d_readdata_d1[5] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[5]
--operation mode is normal
L1_d_readdata_d1[5] = AMPP_FUNCTION(DE1__clk0, M1L70, P1_cpu_data_master_requests_cpu_jtag_debug_module, N1L106, E1_data_out);
--L1_E_src2_prelim[5] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[5]
--operation mode is normal
L1_E_src2_prelim[5] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[5], L1_W_wr_data[5], L1L1355, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_D_pc_plus_one[3] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[3]
--operation mode is normal
L1_D_pc_plus_one[3] = AMPP_FUNCTION(DE1__clk0, L1L920, E1_data_out, L1_W_stall);
--L1_D_br_taken_waddr_partial[3] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[3]
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[3] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[11], L1L920, E1_data_out, L1_W_stall, L1L168);
--L1L170 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[3]~63
--operation mode is arithmetic
L1L170 = AMPP_FUNCTION(KC1_q_b[11], L1L920, L1L168);
--L1_D_pc_plus_one[4] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[4]
--operation mode is normal
L1_D_pc_plus_one[4] = AMPP_FUNCTION(DE1__clk0, L1L922, E1_data_out, L1_W_stall);
--L1_D_br_taken_waddr_partial[4] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[4]
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[4] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[12], L1L922, E1_data_out, L1_W_stall, L1L170);
--L1L172 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[4]~64
--operation mode is arithmetic
L1L172 = AMPP_FUNCTION(KC1_q_b[12], L1L922, L1L170);
--MC1_q_b[6] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[6] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1358, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[6] is std_1s10:inst|cpu:the_cpu|W_wr_data[6]
--operation mode is normal
L1_W_wr_data[6] = AMPP_FUNCTION(DE1__clk0, L1L1358, E1_data_out, L1_W_stall);
--L1L1222 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[6]~1368
--operation mode is normal
L1L1222 = AMPP_FUNCTION(QC1_result[6], QC1_result[38]);
--L1_d_readdata_d1[6] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[6]
--operation mode is normal
L1_d_readdata_d1[6] = AMPP_FUNCTION(DE1__clk0, M1L78, FC1L21, FC1L9, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1_E_src2_prelim[6] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[6]
--operation mode is normal
L1_E_src2_prelim[6] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[6], L1_W_wr_data[6], L1L1358, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_E_src2_imm[0] is std_1s10:inst|cpu:the_cpu|E_src2_imm[0]
--operation mode is normal
L1_E_src2_imm[0] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[6], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1L650 is std_1s10:inst|cpu:the_cpu|E_src2[0]~1515
--operation mode is normal
L1L650 = AMPP_FUNCTION(L1_E_src2_imm[0], L1L1288, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[0] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[0]
--operation mode is normal
L1_E_src1_prelim[0] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[0], L1_W_wr_data[0], L1L1340, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[0] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[0]
--operation mode is normal
L1_M_mul_shift_rot_result[0] = AMPP_FUNCTION(DE1__clk0, QC1_result[0], QC1_result[32], L1L1216, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1338 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[0]~3693
--operation mode is normal
L1L1338 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[0], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[0] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[0]
--operation mode is normal
L1_av_ld_data_aligned_or_div[0] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[0], L1_d_readdata_d1[16], L1L126, L1_M_ld_align_sh16, E1_data_out, L1_M_ld_align_sh8);
--L1L1339 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[0]~3694
--operation mode is normal
L1L1339 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[0], L1_M_alu_result[0], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L584 is std_1s10:inst|cpu:the_cpu|E_src1[0]~1989
--operation mode is normal
L1L584 = AMPP_FUNCTION(L1_E_src1_prelim[0], L1_E_src1_hazard_M, L1L1338, L1L1339);
--L1_E_src2_imm[1] is std_1s10:inst|cpu:the_cpu|E_src2_imm[1]
--operation mode is normal
L1_E_src2_imm[1] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[7], L1_D_iw[5], L1_D_iw[2], L1L216, E1_data_out, L1_W_stall);
--L1L651 is std_1s10:inst|cpu:the_cpu|E_src2[1]~1516
--operation mode is normal
L1L651 = AMPP_FUNCTION(L1_E_src2_imm[1], L1L1290, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[1] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[1]
--operation mode is normal
L1_E_src1_prelim[1] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[1], L1_W_wr_data[1], L1L1343, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[1] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[1]
--operation mode is normal
L1_M_mul_shift_rot_result[1] = AMPP_FUNCTION(DE1__clk0, QC1_result[1], QC1_result[33], L1L1217, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1341 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[1]~3695
--operation mode is normal
L1L1341 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[1], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[1] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[1]
--operation mode is normal
L1_av_ld_data_aligned_or_div[1] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[1], L1_d_readdata_d1[17], L1L128, L1_M_ld_align_sh16, E1_data_out, L1_M_ld_align_sh8);
--L1L1342 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[1]~3696
--operation mode is normal
L1L1342 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[1], L1_M_alu_result[1], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L585 is std_1s10:inst|cpu:the_cpu|E_src1[1]~1990
--operation mode is normal
L1L585 = AMPP_FUNCTION(L1_E_src1_prelim[1], L1_E_src1_hazard_M, L1L1341, L1L1342);
--HE1L15 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~99
--operation mode is normal
HE1L15 = L1_M_alu_result[2] & L1_M_alu_result[3] & (!L1_M_alu_result[4]);
--LB1L2 is std_1s10:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~149
--operation mode is normal
LB1L2 = P1L7 & NB1L2 & QB1L4 & !L1_M_alu_result[7];
--QB1L2 is std_1s10:inst|uart1_s1_arbitrator:the_uart1_s1|cpu_data_master_granted_uart1_s1~102
--operation mode is normal
QB1L2 = L1_M_alu_result[6] & (!L1_M_alu_result[5]);
--HE1L13 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_wr_strobe~20
--operation mode is normal
HE1L13 = L1_internal_d_write & HE1L15 & LB1L2 & QB1L2;
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0]
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0]_lut_out = KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] & (!KE1_do_load_shifter);
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0]_lut_out, DE1__clk0, E1_data_out, , KE1L39, , , , );
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]_lut_out = KE1_do_load_shifter & HE1_internal_tx_data[2] # !KE1_do_load_shifter & (KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4]);
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]_lut_out, DE1__clk0, E1_data_out, , KE1L39, , , , );
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]_lut_out = KE1_do_load_shifter & HE1_internal_tx_data[1] # !KE1_do_load_shifter & (KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]);
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]_lut_out, DE1__clk0, E1_data_out, , KE1L39, , , , );
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1]
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1]_lut_out = KE1_do_load_shifter & HE1_internal_tx_data[0] # !KE1_do_load_shifter & (KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]);
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1]_lut_out, DE1__clk0, E1_data_out, , KE1L39, , , , );
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4]
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4]_lut_out = KE1_do_load_shifter & HE1_internal_tx_data[3] # !KE1_do_load_shifter & (KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5]);
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4]_lut_out, DE1__clk0, E1_data_out, , KE1L39, , , , );
--KE1L26 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd~61
--operation mode is normal
KE1L26 = !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] & !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] & !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] & !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4];
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5]
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5]_lut_out = KE1_do_load_shifter & HE1_internal_tx_data[4] # !KE1_do_load_shifter & (KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6]);
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5]_lut_out, DE1__clk0, E1_data_out, , KE1L39, , , , );
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6]
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6]_lut_out = KE1_do_load_shifter & HE1_internal_tx_data[5] # !KE1_do_load_shifter & (KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7]);
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6]_lut_out, DE1__clk0, E1_data_out, , KE1L39, , , , );
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7]
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7]_lut_out = KE1_do_load_shifter & HE1_internal_tx_data[6] # !KE1_do_load_shifter & (KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8]);
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7]_lut_out, DE1__clk0, E1_data_out, , KE1L39, , , , );
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8]
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8]_lut_out = KE1_do_load_shifter & HE1_internal_tx_data[7] # !KE1_do_load_shifter & (KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]);
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8]_lut_out, DE1__clk0, E1_data_out, , KE1L39, , , , );
--KE1L27 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd~62
--operation mode is normal
KE1L27 = !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] & !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] & !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] & !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8];
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]_lut_out = KE1_do_load_shifter;
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]_lut_out, DE1__clk0, E1_data_out, , KE1L39, , , , );
--KE1L28 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd~63
--operation mode is normal
KE1L28 = KE1L26 & KE1L27 & (!KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]);
--L1_D_pc[13] is std_1s10:inst|cpu:the_cpu|D_pc[13]
--operation mode is normal
L1_D_pc[13] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[13], E1_data_out, L1_W_stall);
--L1_D_pc[12] is std_1s10:inst|cpu:the_cpu|D_pc[12]
--operation mode is normal
L1_D_pc[12] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[12], E1_data_out, L1_W_stall);
--L1_D_pc[11] is std_1s10:inst|cpu:the_cpu|D_pc[11]
--operation mode is normal
L1_D_pc[11] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[11], E1_data_out, L1_W_stall);
--L1_D_pc[10] is std_1s10:inst|cpu:the_cpu|D_pc[10]
--operation mode is normal
L1_D_pc[10] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[10], E1_data_out, L1_W_stall);
--L1L1089 is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[6]~COMBOUT
--operation mode is normal
L1L1089 = AMPP_FUNCTION(L1_D_pc[9], L1_ic_fill_line[6], L1_D_ic_fill_starting);
--L1_ic_tag_wraddress[6] is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[6]
--operation mode is normal
L1_ic_tag_wraddress[6] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[9], L1_ic_fill_line[6], L1_M_alu_result[11], L1_D_ic_fill_starting, E1_data_out, !L1_reset_d1, L1L1040);
--L1L1087 is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[5]~COMBOUT
--operation mode is normal
L1L1087 = AMPP_FUNCTION(L1_D_pc[8], L1_ic_fill_line[5], L1_D_ic_fill_starting);
--L1_ic_tag_wraddress[5] is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[5]
--operation mode is normal
L1_ic_tag_wraddress[5] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[8], L1_ic_fill_line[5], L1_M_alu_result[10], L1_D_ic_fill_starting, E1_data_out, !L1_reset_d1, L1L1040);
--L1L1085 is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[4]~COMBOUT
--operation mode is normal
L1L1085 = AMPP_FUNCTION(L1_D_pc[7], L1_ic_fill_line[4], L1_D_ic_fill_starting);
--L1_ic_tag_wraddress[4] is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[4]
--operation mode is normal
L1_ic_tag_wraddress[4] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[7], L1_ic_fill_line[4], L1_M_alu_result[9], L1_D_ic_fill_starting, E1_data_out, !L1_reset_d1, L1L1040);
--L1L1083 is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[3]~COMBOUT
--operation mode is normal
L1L1083 = AMPP_FUNCTION(L1_D_pc[6], L1_ic_fill_line[3], L1_D_ic_fill_starting);
--L1_ic_tag_wraddress[3] is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[3]
--operation mode is normal
L1_ic_tag_wraddress[3] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[6], L1_ic_fill_line[3], L1_M_alu_result[8], L1_D_ic_fill_starting, E1_data_out, !L1_reset_d1, L1L1040);
--L1L1081 is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[2]~COMBOUT
--operation mode is normal
L1L1081 = AMPP_FUNCTION(L1_D_pc[5], L1_ic_fill_line[2], L1_D_ic_fill_starting);
--L1_ic_tag_wraddress[2] is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[2]
--operation mode is normal
L1_ic_tag_wraddress[2] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[5], L1_ic_fill_line[2], L1_M_alu_result[7], L1_D_ic_fill_starting, E1_data_out, !L1_reset_d1, L1L1040);
--L1L1079 is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[1]~COMBOUT
--operation mode is normal
L1L1079 = AMPP_FUNCTION(L1_D_pc[4], L1_ic_fill_line[1], L1_D_ic_fill_starting);
--L1_ic_tag_wraddress[1] is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[1]
--operation mode is normal
L1_ic_tag_wraddress[1] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[4], L1_ic_fill_line[1], L1_M_alu_result[6], L1_D_ic_fill_starting, E1_data_out, !L1_reset_d1, L1L1040);
--L1_D_pc[3] is std_1s10:inst|cpu:the_cpu|D_pc[3]
--operation mode is normal
L1_D_pc[3] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[3], E1_data_out, L1_W_stall);
--L1L1038 is std_1s10:inst|cpu:the_cpu|ic_fill_line~121
--operation mode is normal
L1L1038 = AMPP_FUNCTION(L1_ic_fill_line[0], L1_D_pc[3], L1L240, L1L241);
--L1_D_pc[2] is std_1s10:inst|cpu:the_cpu|D_pc[2]
--operation mode is normal
L1_D_pc[2] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[2], E1_data_out, L1_W_stall);
--L1L110 is std_1s10:inst|cpu:the_cpu|Add5~37
--operation mode is normal
L1L110 = AMPP_FUNCTION(L1_ic_fill_ap_offset[2], L1_ic_fill_ap_offset[1], L1_ic_fill_ap_offset[0]);
--L1_D_pc[1] is std_1s10:inst|cpu:the_cpu|D_pc[1]
--operation mode is normal
L1_D_pc[1] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[1], E1_data_out, L1_W_stall);
--L1L111 is std_1s10:inst|cpu:the_cpu|Add5~38
--operation mode is normal
L1L111 = AMPP_FUNCTION(L1_ic_fill_ap_offset[1], L1_ic_fill_ap_offset[0]);
--L1_D_pc[0] is std_1s10:inst|cpu:the_cpu|D_pc[0]
--operation mode is normal
L1_D_pc[0] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[0], E1_data_out, L1_W_stall);
--L1_E_control_rd_data_without_mmu_regs[1] is std_1s10:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[1]
--operation mode is normal
L1_E_control_rd_data_without_mmu_regs[1] = AMPP_FUNCTION(DE1__clk0, L1_M_ipending_reg[1], L1_M_ienable_reg[1], L1_D_iw[8], L1L186, E1_data_out, L1_W_stall);
--L1L407 is std_1s10:inst|cpu:the_cpu|E_alu_result[1]~2250
--operation mode is normal
L1L407 = AMPP_FUNCTION(L1_E_logic_op[1], L1L651, L1L585, L1_E_logic_op[0]);
--L1L408 is std_1s10:inst|cpu:the_cpu|E_alu_result[1]~2251
--operation mode is normal
L1L408 = AMPP_FUNCTION(L1L407, L1_E_ctrl_dst_data_sel_logic_result, HC1_result[1], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1L409 is std_1s10:inst|cpu:the_cpu|E_alu_result[1]~2252
--operation mode is normal
L1L409 = AMPP_FUNCTION(L1_E_control_rd_data_without_mmu_regs[1], L1L408, L1_E_ctrl_rdctl_inst, L1_E_ctrl_dst_data_sel_cmp);
--L1_E_control_rd_data_without_mmu_regs[0] is std_1s10:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[0]
--operation mode is normal
L1_E_control_rd_data_without_mmu_regs[0] = AMPP_FUNCTION(DE1__clk0, L1_M_bstatus_reg, L1_D_iw[6], L1L184, L1L185, E1_data_out, L1_W_stall);
--L1L403 is std_1s10:inst|cpu:the_cpu|E_alu_result[0]~2253
--operation mode is normal
L1L403 = AMPP_FUNCTION(L1_E_logic_op[1], L1L650, L1L584, L1_E_logic_op[0]);
--L1L404 is std_1s10:inst|cpu:the_cpu|E_alu_result[0]~2254
--operation mode is normal
L1L404 = AMPP_FUNCTION(L1L403, L1_E_ctrl_dst_data_sel_logic_result, HC1_result[0], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1L405 is std_1s10:inst|cpu:the_cpu|E_alu_result[0]~2255
--operation mode is normal
L1L405 = AMPP_FUNCTION(L1_E_control_rd_data_without_mmu_regs[0], L1L404, L1_E_ctrl_rdctl_inst);
--L1L406 is std_1s10:inst|cpu:the_cpu|E_alu_result[0]~2256
--operation mode is normal
L1L406 = AMPP_FUNCTION(L1L416, L1L405, L1_E_ctrl_dst_data_sel_cmp);
--L1_E_src2_prelim[1] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[1]
--operation mode is normal
L1_E_src2_prelim[1] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[1], L1_W_wr_data[1], L1L1343, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1_E_src2_prelim[0] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[0]
--operation mode is normal
L1_E_src2_prelim[0] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[0], L1_W_wr_data[0], L1L1340, L1L384, E1_data_out, L1L380, L1_W_stall);
--GB1L37 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[7]~168
--operation mode is normal
GB1L37 = GB1L14 & L1_M_alu_result[9] # !GB1L14 & (L1_ic_fill_line[4]);
--GB1L36 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[6]~169
--operation mode is normal
GB1L36 = GB1L14 & L1_M_alu_result[8] # !GB1L14 & (L1_ic_fill_line[3]);
--GB1L35 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[5]~170
--operation mode is normal
GB1L35 = GB1L14 & L1_M_alu_result[7] # !GB1L14 & (L1_ic_fill_line[2]);
--GB1L34 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[4]~171
--operation mode is normal
GB1L34 = GB1L14 & L1_M_alu_result[6] # !GB1L14 & (L1_ic_fill_line[1]);
--GB1L33 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[3]~172
--operation mode is normal
GB1L33 = GB1L14 & L1_M_alu_result[5] # !GB1L14 & (L1_ic_fill_line[0]);
--GB1L32 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[2]~173
--operation mode is normal
GB1L32 = GB1L14 & L1_M_alu_result[4] # !GB1L14 & (L1_ic_fill_ap_offset[2]);
--GB1L31 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[1]~174
--operation mode is normal
GB1L31 = GB1L14 & L1_M_alu_result[3] # !GB1L14 & (L1_ic_fill_ap_offset[1]);
--GB1L30 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[0]~175
--operation mode is normal
GB1L30 = GB1L14 & L1_M_alu_result[2] # !GB1L14 & (L1_ic_fill_ap_offset[0]);
--FB1L236 is std_1s10:inst|sdram:the_sdram|module_input1[35]~36
--operation mode is normal
FB1L236 = L1_internal_d_write & GB1L14 & (!L1_M_mem_byte_en[3]);
--FB1L235 is std_1s10:inst|sdram:the_sdram|module_input1[34]~37
--operation mode is normal
FB1L235 = L1_internal_d_write & GB1L14 & (!L1_M_mem_byte_en[2]);
--FB1L234 is std_1s10:inst|sdram:the_sdram|module_input1[33]~38
--operation mode is normal
FB1L234 = L1_internal_d_write & GB1L14 & (!L1_M_mem_byte_en[1]);
--FB1L233 is std_1s10:inst|sdram:the_sdram|module_input1[32]~39
--operation mode is normal
FB1L233 = L1_internal_d_write & GB1L14 & (!L1_M_mem_byte_en[0]);
--ME3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]
--operation mode is normal
ME3_Q[0] = AMPP_FUNCTION(!A1L6, DD1L118Q, C1L17, ME3_Q[1], ME3L3, !C1_CLR_SIGNAL, RE1_state[4], ME3L4);
--ME9_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
--operation mode is normal
ME9_Q[0] = AMPP_FUNCTION(!A1L6, altera_internal_jtag, ME3_Q[6], VCC, C1L18);
--NE1_WORD_SR[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]
--operation mode is normal
NE1_WORD_SR[0] = AMPP_FUNCTION(!A1L6, NE1_WORD_SR[1], NE1L19, RE1_state[4], NE1_clear_signal, VCC, NE1L20);
--C1_HUB_BYPASS_REG is sld_hub:sld_hub_inst|HUB_BYPASS_REG
--operation mode is normal
C1_HUB_BYPASS_REG = AMPP_FUNCTION(!A1L6, C1L11, VCC);
--SE1_dffe1a[0] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0]
--operation mode is normal
SE1_dffe1a[0] = AMPP_FUNCTION(!A1L6, C1L26, ME3_Q[1], ME3_Q[3], ME3_Q[2], !C1_CLR_SIGNAL, C1L5);
--C1L13 is sld_hub:sld_hub_inst|hub_tdo~543
--operation mode is normal
C1L13 = AMPP_FUNCTION(ME9_Q[0], NE1_WORD_SR[0], C1_HUB_BYPASS_REG, SE1_dffe1a[0]);
--QD1_td_shift[0] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[0]
--operation mode is normal
QD1_td_shift[0] = AMPP_FUNCTION(!A1L6, QD1L65, QD1L67, ME4_Q[0], !C1_CLR_SIGNAL, !RE1_state[4], QD1L52);
--ME8_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
--operation mode is normal
ME8_Q[0] = AMPP_FUNCTION(!A1L6, altera_internal_jtag, ME3_Q[6], !C1_CLR_SIGNAL, C1L18);
--DD1_sr[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[0]
--operation mode is normal
DD1_sr[0] = AMPP_FUNCTION(!A1L6, DD1L140, DD1L5, DD1L141, DD1L143, !C1_CLR_SIGNAL, DD1L6);
--ME8_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1]
--operation mode is normal
ME8_Q[1] = AMPP_FUNCTION(!A1L6, altera_internal_jtag, ME3_Q[6], !C1_CLR_SIGNAL, C1L18);
--C1L14 is sld_hub:sld_hub_inst|hub_tdo~544
--operation mode is normal
C1L14 = AMPP_FUNCTION(QD1_td_shift[0], ME8_Q[0], DD1_sr[0], ME8_Q[1]);
--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1
--operation mode is normal
C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(!A1L6, QE1_dffs[1], C1L6, C1L7, QE1_dffs[0], RE1_state[0], RE1_state[12]);
--C1L15 is sld_hub:sld_hub_inst|hub_tdo~545
--operation mode is normal
C1L15 = AMPP_FUNCTION(ME3_Q[0], C1L13, C1L14, C1_jtag_debug_mode_usr1);
--RE1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]
--operation mode is normal
RE1_state[4] = AMPP_FUNCTION(!A1L6, RE1_state[7], RE1_state[3], RE1_state[4], VCC, !A1L8);
--RE1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]
--operation mode is normal
RE1_state[3] = AMPP_FUNCTION(!A1L6, A1L8, RE1_state[2], VCC);
--RE1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8]
--operation mode is normal
RE1_state[8] = AMPP_FUNCTION(!A1L6, RE1_state[5], RE1_state[7], VCC, A1L8);
--DB1_data_out is std_1s10:inst|reconfig_request_pio:the_reconfig_request_pio|data_out
--operation mode is normal
DB1_data_out_lut_out = HE1L14 & (DB1L3 & L1_M_st_data[0] # !DB1L3 & (DB1_data_out)) # !HE1L14 & (DB1_data_out);
DB1_data_out = DFFEAS(DB1_data_out_lut_out, DE1__clk0, E1_data_out, , , , , , );
--DB1_data_dir is std_1s10:inst|reconfig_request_pio:the_reconfig_request_pio|data_dir
--operation mode is normal
DB1_data_dir_lut_out = DB1L3 & (HE1L16 & L1_M_st_data[0] # !HE1L16 & (DB1_data_dir)) # !DB1L3 & (DB1_data_dir);
DB1_data_dir = DFFEAS(DB1_data_dir_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[31] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[31]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[31]_lut_out = L1_M_st_data[31] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[31] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[31]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_in_a_write_cycle is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle
--operation mode is normal
Q1_d1_in_a_write_cycle_lut_out = L1_internal_d_write & (!Q1L190 & !Q1L297);
Q1_d1_in_a_write_cycle = DFFEAS(Q1_d1_in_a_write_cycle_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[30] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[30]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[30]_lut_out = L1_M_st_data[30] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[30] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[30]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[29] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[29]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[29]_lut_out = L1_M_st_data[29] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[29] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[29]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[28] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[28]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[28]_lut_out = L1_M_st_data[28] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[28] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[28]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[27] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[27]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[27]_lut_out = L1_M_st_data[27] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[27] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[27]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[26] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[26]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[26]_lut_out = L1_M_st_data[26] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[26] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[26]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[25] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[25]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[25]_lut_out = L1_M_st_data[25] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[25] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[25]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[24] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[24]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[24]_lut_out = L1_M_st_data[24] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[24] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[24]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[23] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[23]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[23]_lut_out = L1_M_st_data[23] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[23] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[23]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[22] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[22]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[22]_lut_out = L1_M_st_data[22] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[22] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[22]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[21] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[21]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[21]_lut_out = L1_M_st_data[21] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[21] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[21]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[20] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[20]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[20]_lut_out = L1_M_st_data[20] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[20] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[20]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[19] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[19]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[19]_lut_out = L1_M_st_data[19] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[19] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[19]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[18] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[18]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[18]_lut_out = L1_M_st_data[18] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[18] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[18]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[17] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[17]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[17]_lut_out = L1_M_st_data[17] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[17] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[17]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[16] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[16]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[16]_lut_out = L1_M_st_data[16] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[16] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[16]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[15] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[15]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[15]_lut_out = L1_M_st_data[15] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[15] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[15]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[14] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[14]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[14]_lut_out = L1_M_st_data[14] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[14] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[14]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[13] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[13]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[13]_lut_out = L1_M_st_data[13] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[13] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[13]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[12] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[12]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[12]_lut_out = L1_M_st_data[12] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[12] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[12]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[11] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[11]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[11]_lut_out = L1_M_st_data[11] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[11] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[11]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[10] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[10]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[10]_lut_out = L1_M_st_data[10] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[10] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[10]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[9] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[9]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[9]_lut_out = L1_M_st_data[9] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[9] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[9]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[8] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[8]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[8]_lut_out = L1_M_st_data[8] & (Q1L48 # !Q1L46);
Q1_d1_outgoing_ext_ram_bus_data[8] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[7] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[7]_lut_out = M1L260 & (Q1L273 & Q1L272 # !Q1L273 & (L1_M_st_data[7])) # !M1L260 & (L1_M_st_data[7]);
Q1_d1_outgoing_ext_ram_bus_data[7] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[6] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[6]_lut_out = M1L260 & (Q1L273 & Q1L270 # !Q1L273 & (L1_M_st_data[6])) # !M1L260 & (L1_M_st_data[6]);
Q1_d1_outgoing_ext_ram_bus_data[6] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[5] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[5]_lut_out = M1L260 & (Q1L273 & Q1L268 # !Q1L273 & (L1_M_st_data[5])) # !M1L260 & (L1_M_st_data[5]);
Q1_d1_outgoing_ext_ram_bus_data[5] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[4] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[4]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[4]_lut_out = M1L260 & (Q1L273 & Q1L266 # !Q1L273 & (L1_M_st_data[4])) # !M1L260 & (L1_M_st_data[4]);
Q1_d1_outgoing_ext_ram_bus_data[4] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[3]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[3]_lut_out = M1L260 & (Q1L273 & Q1L264 # !Q1L273 & (L1_M_st_data[3])) # !M1L260 & (L1_M_st_data[3]);
Q1_d1_outgoing_ext_ram_bus_data[3] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[2]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[2]_lut_out = M1L260 & (Q1L273 & Q1L262 # !Q1L273 & (L1_M_st_data[2])) # !M1L260 & (L1_M_st_data[2]);
Q1_d1_outgoing_ext_ram_bus_data[2] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[1]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[1]_lut_out = M1L260 & (Q1L273 & Q1L260 # !Q1L273 & (L1_M_st_data[1])) # !M1L260 & (L1_M_st_data[1]);
Q1_d1_outgoing_ext_ram_bus_data[1] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_d1_outgoing_ext_ram_bus_data[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[0]
--operation mode is normal
Q1_d1_outgoing_ext_ram_bus_data[0]_lut_out = M1L260 & (Q1L273 & Q1L258 # !Q1L273 & (L1_M_st_data[0])) # !M1L260 & (L1_M_st_data[0]);
Q1_d1_outgoing_ext_ram_bus_data[0] = DFFEAS(Q1_d1_outgoing_ext_ram_bus_data[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[31] is std_1s10:inst|sdram:the_sdram|m_data[31]
--operation mode is normal
FB1_m_data[31]_lut_out = FB1L511 & (FB1L510 & FB1L509 # !FB1L510 & (FB1_m_data[31])) # !FB1L511 & (FB1_m_data[31]);
FB1_m_data[31] = DFFEAS(FB1_m_data[31]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_oe is std_1s10:inst|sdram:the_sdram|oe
--operation mode is normal
FB1_oe_lut_out = FB1L548 & (EE1L127 & !FB1L554 # !FB1_f_pop);
FB1_oe = DFFEAS(FB1_oe_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[30] is std_1s10:inst|sdram:the_sdram|m_data[30]
--operation mode is normal
FB1_m_data[30]_lut_out = FB1L511 & (FB1L510 & FB1L512 # !FB1L510 & (FB1_m_data[30])) # !FB1L511 & (FB1_m_data[30]);
FB1_m_data[30] = DFFEAS(FB1_m_data[30]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[29] is std_1s10:inst|sdram:the_sdram|m_data[29]
--operation mode is normal
FB1_m_data[29]_lut_out = FB1L511 & (FB1L510 & FB1L513 # !FB1L510 & (FB1_m_data[29])) # !FB1L511 & (FB1_m_data[29]);
FB1_m_data[29] = DFFEAS(FB1_m_data[29]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[28] is std_1s10:inst|sdram:the_sdram|m_data[28]
--operation mode is normal
FB1_m_data[28]_lut_out = FB1L511 & (FB1L510 & FB1L514 # !FB1L510 & (FB1_m_data[28])) # !FB1L511 & (FB1_m_data[28]);
FB1_m_data[28] = DFFEAS(FB1_m_data[28]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[27] is std_1s10:inst|sdram:the_sdram|m_data[27]
--operation mode is normal
FB1_m_data[27]_lut_out = FB1L511 & (FB1L510 & FB1L515 # !FB1L510 & (FB1_m_data[27])) # !FB1L511 & (FB1_m_data[27]);
FB1_m_data[27] = DFFEAS(FB1_m_data[27]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[26] is std_1s10:inst|sdram:the_sdram|m_data[26]
--operation mode is normal
FB1_m_data[26]_lut_out = FB1L511 & (FB1L510 & FB1L516 # !FB1L510 & (FB1_m_data[26])) # !FB1L511 & (FB1_m_data[26]);
FB1_m_data[26] = DFFEAS(FB1_m_data[26]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[25] is std_1s10:inst|sdram:the_sdram|m_data[25]
--operation mode is normal
FB1_m_data[25]_lut_out = FB1L511 & (FB1L510 & FB1L517 # !FB1L510 & (FB1_m_data[25])) # !FB1L511 & (FB1_m_data[25]);
FB1_m_data[25] = DFFEAS(FB1_m_data[25]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[24] is std_1s10:inst|sdram:the_sdram|m_data[24]
--operation mode is normal
FB1_m_data[24]_lut_out = FB1L511 & (FB1L510 & FB1L518 # !FB1L510 & (FB1_m_data[24])) # !FB1L511 & (FB1_m_data[24]);
FB1_m_data[24] = DFFEAS(FB1_m_data[24]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[23] is std_1s10:inst|sdram:the_sdram|m_data[23]
--operation mode is normal
FB1_m_data[23]_lut_out = FB1L511 & (FB1L510 & FB1L519 # !FB1L510 & (FB1_m_data[23])) # !FB1L511 & (FB1_m_data[23]);
FB1_m_data[23] = DFFEAS(FB1_m_data[23]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[22] is std_1s10:inst|sdram:the_sdram|m_data[22]
--operation mode is normal
FB1_m_data[22]_lut_out = FB1L511 & (FB1L510 & FB1L520 # !FB1L510 & (FB1_m_data[22])) # !FB1L511 & (FB1_m_data[22]);
FB1_m_data[22] = DFFEAS(FB1_m_data[22]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[21] is std_1s10:inst|sdram:the_sdram|m_data[21]
--operation mode is normal
FB1_m_data[21]_lut_out = FB1L511 & (FB1L510 & FB1L521 # !FB1L510 & (FB1_m_data[21])) # !FB1L511 & (FB1_m_data[21]);
FB1_m_data[21] = DFFEAS(FB1_m_data[21]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[20] is std_1s10:inst|sdram:the_sdram|m_data[20]
--operation mode is normal
FB1_m_data[20]_lut_out = FB1L511 & (FB1L510 & FB1L522 # !FB1L510 & (FB1_m_data[20])) # !FB1L511 & (FB1_m_data[20]);
FB1_m_data[20] = DFFEAS(FB1_m_data[20]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[19] is std_1s10:inst|sdram:the_sdram|m_data[19]
--operation mode is normal
FB1_m_data[19]_lut_out = FB1L511 & (FB1L510 & FB1L523 # !FB1L510 & (FB1_m_data[19])) # !FB1L511 & (FB1_m_data[19]);
FB1_m_data[19] = DFFEAS(FB1_m_data[19]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[18] is std_1s10:inst|sdram:the_sdram|m_data[18]
--operation mode is normal
FB1_m_data[18]_lut_out = FB1L511 & (FB1L510 & FB1L524 # !FB1L510 & (FB1_m_data[18])) # !FB1L511 & (FB1_m_data[18]);
FB1_m_data[18] = DFFEAS(FB1_m_data[18]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[17] is std_1s10:inst|sdram:the_sdram|m_data[17]
--operation mode is normal
FB1_m_data[17]_lut_out = FB1L511 & (FB1L510 & FB1L525 # !FB1L510 & (FB1_m_data[17])) # !FB1L511 & (FB1_m_data[17]);
FB1_m_data[17] = DFFEAS(FB1_m_data[17]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[16] is std_1s10:inst|sdram:the_sdram|m_data[16]
--operation mode is normal
FB1_m_data[16]_lut_out = FB1L511 & (FB1L510 & FB1L526 # !FB1L510 & (FB1_m_data[16])) # !FB1L511 & (FB1_m_data[16]);
FB1_m_data[16] = DFFEAS(FB1_m_data[16]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[15] is std_1s10:inst|sdram:the_sdram|m_data[15]
--operation mode is normal
FB1_m_data[15]_lut_out = FB1L511 & (FB1L510 & FB1L527 # !FB1L510 & (FB1_m_data[15])) # !FB1L511 & (FB1_m_data[15]);
FB1_m_data[15] = DFFEAS(FB1_m_data[15]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[14] is std_1s10:inst|sdram:the_sdram|m_data[14]
--operation mode is normal
FB1_m_data[14]_lut_out = FB1L511 & (FB1L510 & FB1L528 # !FB1L510 & (FB1_m_data[14])) # !FB1L511 & (FB1_m_data[14]);
FB1_m_data[14] = DFFEAS(FB1_m_data[14]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[13] is std_1s10:inst|sdram:the_sdram|m_data[13]
--operation mode is normal
FB1_m_data[13]_lut_out = FB1L511 & (FB1L510 & FB1L529 # !FB1L510 & (FB1_m_data[13])) # !FB1L511 & (FB1_m_data[13]);
FB1_m_data[13] = DFFEAS(FB1_m_data[13]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[12] is std_1s10:inst|sdram:the_sdram|m_data[12]
--operation mode is normal
FB1_m_data[12]_lut_out = FB1L511 & (FB1L510 & FB1L530 # !FB1L510 & (FB1_m_data[12])) # !FB1L511 & (FB1_m_data[12]);
FB1_m_data[12] = DFFEAS(FB1_m_data[12]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[11] is std_1s10:inst|sdram:the_sdram|m_data[11]
--operation mode is normal
FB1_m_data[11]_lut_out = FB1L511 & (FB1L510 & FB1L531 # !FB1L510 & (FB1_m_data[11])) # !FB1L511 & (FB1_m_data[11]);
FB1_m_data[11] = DFFEAS(FB1_m_data[11]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[10] is std_1s10:inst|sdram:the_sdram|m_data[10]
--operation mode is normal
FB1_m_data[10]_lut_out = FB1L511 & (FB1L510 & FB1L532 # !FB1L510 & (FB1_m_data[10])) # !FB1L511 & (FB1_m_data[10]);
FB1_m_data[10] = DFFEAS(FB1_m_data[10]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[9] is std_1s10:inst|sdram:the_sdram|m_data[9]
--operation mode is normal
FB1_m_data[9]_lut_out = FB1L511 & (FB1L510 & FB1L533 # !FB1L510 & (FB1_m_data[9])) # !FB1L511 & (FB1_m_data[9]);
FB1_m_data[9] = DFFEAS(FB1_m_data[9]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[8] is std_1s10:inst|sdram:the_sdram|m_data[8]
--operation mode is normal
FB1_m_data[8]_lut_out = FB1L511 & (FB1L510 & FB1L534 # !FB1L510 & (FB1_m_data[8])) # !FB1L511 & (FB1_m_data[8]);
FB1_m_data[8] = DFFEAS(FB1_m_data[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[7] is std_1s10:inst|sdram:the_sdram|m_data[7]
--operation mode is normal
FB1_m_data[7]_lut_out = FB1L511 & (FB1L510 & FB1L535 # !FB1L510 & (FB1_m_data[7])) # !FB1L511 & (FB1_m_data[7]);
FB1_m_data[7] = DFFEAS(FB1_m_data[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[6] is std_1s10:inst|sdram:the_sdram|m_data[6]
--operation mode is normal
FB1_m_data[6]_lut_out = FB1L511 & (FB1L510 & FB1L536 # !FB1L510 & (FB1_m_data[6])) # !FB1L511 & (FB1_m_data[6]);
FB1_m_data[6] = DFFEAS(FB1_m_data[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[5] is std_1s10:inst|sdram:the_sdram|m_data[5]
--operation mode is normal
FB1_m_data[5]_lut_out = FB1L511 & (FB1L510 & FB1L537 # !FB1L510 & (FB1_m_data[5])) # !FB1L511 & (FB1_m_data[5]);
FB1_m_data[5] = DFFEAS(FB1_m_data[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[4] is std_1s10:inst|sdram:the_sdram|m_data[4]
--operation mode is normal
FB1_m_data[4]_lut_out = FB1L511 & (FB1L510 & FB1L538 # !FB1L510 & (FB1_m_data[4])) # !FB1L511 & (FB1_m_data[4]);
FB1_m_data[4] = DFFEAS(FB1_m_data[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[3] is std_1s10:inst|sdram:the_sdram|m_data[3]
--operation mode is normal
FB1_m_data[3]_lut_out = FB1L511 & (FB1L510 & FB1L539 # !FB1L510 & (FB1_m_data[3])) # !FB1L511 & (FB1_m_data[3]);
FB1_m_data[3] = DFFEAS(FB1_m_data[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[2] is std_1s10:inst|sdram:the_sdram|m_data[2]
--operation mode is normal
FB1_m_data[2]_lut_out = FB1L511 & (FB1L510 & FB1L540 # !FB1L510 & (FB1_m_data[2])) # !FB1L511 & (FB1_m_data[2]);
FB1_m_data[2] = DFFEAS(FB1_m_data[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[1] is std_1s10:inst|sdram:the_sdram|m_data[1]
--operation mode is normal
FB1_m_data[1]_lut_out = FB1L511 & (FB1L510 & FB1L541 # !FB1L510 & (FB1_m_data[1])) # !FB1L511 & (FB1_m_data[1]);
FB1_m_data[1] = DFFEAS(FB1_m_data[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_m_data[0] is std_1s10:inst|sdram:the_sdram|m_data[0]
--operation mode is normal
FB1_m_data[0]_lut_out = FB1L511 & (FB1L510 & FB1L542 # !FB1L510 & (FB1_m_data[0])) # !FB1L511 & (FB1_m_data[0]);
FB1_m_data[0] = DFFEAS(FB1_m_data[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--L1_ic_fill_ap_cnt[2] is std_1s10:inst|cpu:the_cpu|ic_fill_ap_cnt[2]
--operation mode is normal
L1_ic_fill_ap_cnt[2] = AMPP_FUNCTION(DE1__clk0, L1_internal_i_read, N1L114, L1_ic_fill_ap_cnt[2], L1L113, E1_data_out, L1L1027);
--L1_ic_fill_ap_cnt[1] is std_1s10:inst|cpu:the_cpu|ic_fill_ap_cnt[1]
--operation mode is normal
L1_ic_fill_ap_cnt[1] = AMPP_FUNCTION(DE1__clk0, L1_internal_i_read, N1L114, L1_ic_fill_ap_cnt[1], L1_ic_fill_ap_cnt[0], E1_data_out, L1L1027);
--L1_ic_fill_ap_cnt[0] is std_1s10:inst|cpu:the_cpu|ic_fill_ap_cnt[0]
--operation mode is normal
L1_ic_fill_ap_cnt[0] = AMPP_FUNCTION(DE1__clk0, L1_D_ic_fill_starting, L1_ic_fill_ap_cnt[0], L1_internal_i_read, N1L114, E1_data_out);
--L1L112 is std_1s10:inst|cpu:the_cpu|Add6~103
--operation mode is normal
L1L112 = AMPP_FUNCTION(L1_ic_fill_ap_cnt[2], L1_ic_fill_ap_cnt[1], L1_ic_fill_ap_cnt[0]);
--L1L1027 is std_1s10:inst|cpu:the_cpu|ic_fill_initial_offset[0]~801
--operation mode is normal
L1L1027 = AMPP_FUNCTION(L1_internal_i_read, N1L114, L1_D_ic_fill_starting);
--GB1_sdram_s1_saved_chosen_master_vector[0] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_saved_chosen_master_vector[0]
--operation mode is normal
GB1_sdram_s1_saved_chosen_master_vector[0]_lut_out = GB1L19;
GB1_sdram_s1_saved_chosen_master_vector[0] = DFFEAS(GB1_sdram_s1_saved_chosen_master_vector[0]_lut_out, DE1__clk0, E1_data_out, , GB1L73, , , , );
--GB1L71 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[5]~541
--operation mode is normal
GB1L71 = GB1_sdram_s1_slavearbiterlockenable & (GB1L13 # GB1L70);
--GB1L72 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_winner[0]~30
--operation mode is normal
GB1L72 = GB1L71 & GB1_sdram_s1_saved_chosen_master_vector[0] # !GB1L71 & (GB1L19 # GB1_sdram_s1_saved_chosen_master_vector[0] & !GB1L14);
--GB1L56 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[1]~733
--operation mode is normal
GB1L56 = EE1L126 & (FB1L237 & GB1L14 # !FB1L237 & (GB1L72)) # !EE1L126 & (GB1L72);
--GB1_WideOr1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|WideOr1
--operation mode is normal
GB1_WideOr1 = GB1_sdram_s1_arb_addend[1] & (GB1L20 # GB1L17) # !GB1_sdram_s1_arb_addend[1] & !GB1_sdram_s1_arb_addend[0] & (GB1L20 # GB1L17);
--FE1_how_many_ones[3] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[3]
--operation mode is normal
FE1_how_many_ones[3]_lut_out = FE1L2;
FE1_how_many_ones[3] = DFFEAS(FE1_how_many_ones[3]_lut_out, DE1__clk0, E1_data_out, , GE1L27, , , , );
--FE1L21 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|updated_one_count~62
--operation mode is normal
FE1L21 = GB1L14 & !EE1L126 & (L1_internal_d_read # GB1L19);
--FE1_how_many_ones[2] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[2]
--operation mode is normal
FE1_how_many_ones[2]_lut_out = FE1L3;
FE1_how_many_ones[2] = DFFEAS(FE1_how_many_ones[2]_lut_out, DE1__clk0, E1_data_out, , GE1L27, , , , );
--FE1_how_many_ones[1] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[1]
--operation mode is normal
FE1_how_many_ones[1]_lut_out = FE1L4;
FE1_how_many_ones[1] = DFFEAS(FE1_how_many_ones[1]_lut_out, DE1__clk0, E1_data_out, , GE1L27, , , , );
--FE1_how_many_ones[0] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[0]
--operation mode is normal
FE1_how_many_ones[0]_lut_out = FE1L6;
FE1_how_many_ones[0] = DFFEAS(FE1_how_many_ones[0]_lut_out, DE1__clk0, E1_data_out, , GE1L27, , , , );
--FE1L22 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|updated_one_count~63
--operation mode is normal
FE1L22 = FB1_za_valid & FE1_stage_0;
--FE1L1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1192
--operation mode is normal
FE1L1 = FE1_how_many_ones[2] & FE1_how_many_ones[1] & FE1_how_many_ones[0] & !FE1L22 # !FE1_how_many_ones[2] & !FE1_how_many_ones[1] & !FE1_how_many_ones[0] & FE1L22;
--FE1L2 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1193
--operation mode is normal
FE1L2 = FE1_how_many_ones[3] $ (FE1L1 & (FE1L21 $ !FE1_how_many_ones[2]));
--FE1L3 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1194
--operation mode is normal
FE1L3 = FE1_how_many_ones[2] $ (FE1L5 & (FE1L21 $ !FE1_how_many_ones[1]));
--FE1L4 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1195
--operation mode is normal
FE1L4 = FE1_how_many_ones[1] $ (FE1L22 & !FE1L21 & !FE1_how_many_ones[0] # !FE1L22 & FE1L21 & FE1_how_many_ones[0]);
--GB1L2 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~99
--operation mode is arithmetic
GB1L2 = !GB1_sdram_s1_arb_share_counter[0];
--GB1L3 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~100
--operation mode is arithmetic
GB1L3 = CARRY(GB1_sdram_s1_arb_share_counter[0]);
--GB1_sdram_s1_arb_share_counter[0] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[0]
--operation mode is normal
GB1_sdram_s1_arb_share_counter[0]_lut_out = GB1L66;
GB1_sdram_s1_arb_share_counter[0] = DFFEAS(GB1_sdram_s1_arb_share_counter[0]_lut_out, DE1__clk0, E1_data_out, , GB1L58, , , , );
--GB1_sdram_s1_arb_share_counter[1] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[1]
--operation mode is normal
GB1_sdram_s1_arb_share_counter[1]_lut_out = GB1L68;
GB1_sdram_s1_arb_share_counter[1] = DFFEAS(GB1_sdram_s1_arb_share_counter[1]_lut_out, DE1__clk0, E1_data_out, , GB1L58, , , , );
--GB1_sdram_s1_arb_share_counter[2] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[2]
--operation mode is normal
GB1_sdram_s1_arb_share_counter[2]_lut_out = GB1L69;
GB1_sdram_s1_arb_share_counter[2] = DFFEAS(GB1_sdram_s1_arb_share_counter[2]_lut_out, DE1__clk0, E1_data_out, , GB1L58, , , , );
--GB1_sdram_s1_arb_share_counter[3] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[3]
--operation mode is normal
GB1_sdram_s1_arb_share_counter[3]_lut_out = GB1L10 & GB1L67;
GB1_sdram_s1_arb_share_counter[3] = DFFEAS(GB1_sdram_s1_arb_share_counter[3]_lut_out, DE1__clk0, E1_data_out, , GB1L58, , , , );
--GB1L84 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|WideOr0~28
--operation mode is normal
GB1L84 = GB1_sdram_s1_arb_share_counter[0] # GB1_sdram_s1_arb_share_counter[1] # GB1_sdram_s1_arb_share_counter[2] # GB1_sdram_s1_arb_share_counter[3];
--GB1_sdram_s1_arb_share_counter[4] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[4]
--operation mode is normal
GB1_sdram_s1_arb_share_counter[4]_lut_out = GB1L8 & GB1L67;
GB1_sdram_s1_arb_share_counter[4] = DFFEAS(GB1_sdram_s1_arb_share_counter[4]_lut_out, DE1__clk0, E1_data_out, , GB1L58, , , , );
--GB1_sdram_s1_arb_share_counter[5] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[5]
--operation mode is normal
GB1_sdram_s1_arb_share_counter[5]_lut_out = GB1L12 & GB1L67;
GB1_sdram_s1_arb_share_counter[5] = DFFEAS(GB1_sdram_s1_arb_share_counter[5]_lut_out, DE1__clk0, E1_data_out, , GB1L58, , , , );
--GB1_WideOr0 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|WideOr0
--operation mode is normal
GB1_WideOr0 = GB1L84 # GB1_sdram_s1_arb_share_counter[4] # GB1_sdram_s1_arb_share_counter[5];
--GB1L66 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[0]~542
--operation mode is normal
GB1L66 = GB1L71 & GB1L2 & GB1_WideOr0 # !GB1L71 & (GB1L19);
--GB1L4 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~101
--operation mode is arithmetic
GB1L4 = GB1_sdram_s1_arb_share_counter[1] $ (!GB1L4_carry_eqn);
--GB1L5 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~102
--operation mode is arithmetic
GB1L5 = CARRY(!GB1_sdram_s1_arb_share_counter[1] & (!GB1L3));
--GB1L68 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[1]~543
--operation mode is normal
GB1L68 = GB1L71 & GB1L4 & GB1_WideOr0 # !GB1L71 & (GB1L19);
--GB1L6 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~103
--operation mode is arithmetic
GB1L6 = GB1_sdram_s1_arb_share_counter[2] $ (GB1L6_carry_eqn);
--GB1L7 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~104
--operation mode is arithmetic
GB1L7 = CARRY(GB1_sdram_s1_arb_share_counter[2] # !GB1L5);
--GB1L69 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[2]~544
--operation mode is normal
GB1L69 = GB1L71 & GB1L6 & GB1_WideOr0 # !GB1L71 & (GB1L19);
--GB1L67 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[0]~545
--operation mode is normal
GB1L67 = GB1_sdram_s1_slavearbiterlockenable & GB1_WideOr0 & (GB1L13 # GB1L70);
--GB1L8 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~105
--operation mode is arithmetic
GB1L8 = GB1_sdram_s1_arb_share_counter[4] $ (GB1L8_carry_eqn);
--GB1L9 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~106
--operation mode is arithmetic
GB1L9 = CARRY(GB1_sdram_s1_arb_share_counter[4] # !GB1L11);
--GB1L10 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~107
--operation mode is arithmetic
GB1L10 = GB1_sdram_s1_arb_share_counter[3] $ (!GB1L10_carry_eqn);
--GB1L11 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~108
--operation mode is arithmetic
GB1L11 = CARRY(!GB1_sdram_s1_arb_share_counter[3] & (!GB1L7));
--GB1L12 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~109
--operation mode is normal
GB1L12 = GB1_sdram_s1_arb_share_counter[5] $ (!GB1L12_carry_eqn);
--GB1L81 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable~154
--operation mode is normal
GB1L81 = GB1L67 & (GB1L8 # GB1L10 # GB1L12);
--GB1L82 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable~155
--operation mode is normal
GB1L82 = GB1L66 # GB1L68 # GB1L69 # GB1L81;
--GB1L29 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|process2~43
--operation mode is normal
GB1L29 = GB1L17 # GB1L22 & (!GB1L25) # !GB1L22 & !GB1L18;
--GB1_d1_reasons_to_wait is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|d1_reasons_to_wait
--operation mode is normal
GB1_d1_reasons_to_wait_lut_out = GB1L75;
GB1_d1_reasons_to_wait = DFFEAS(GB1_d1_reasons_to_wait_lut_out, DE1__clk0, E1_data_out, , , , , , );
--GB1L74 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arbitration_holdoff_internal~150
--operation mode is normal
GB1L74 = !GB1L71 & !GB1_d1_reasons_to_wait & (GB1L20 # GB1L17);
--GB1_sdram_s1_saved_chosen_master_vector[1] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_saved_chosen_master_vector[1]
--operation mode is normal
GB1_sdram_s1_saved_chosen_master_vector[1]_lut_out = GB1L14;
GB1_sdram_s1_saved_chosen_master_vector[1] = DFFEAS(GB1_sdram_s1_saved_chosen_master_vector[1]_lut_out, DE1__clk0, E1_data_out, , GB1L73, , , , );
--GB1L1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|A_WE_StdLogicVector~128
--operation mode is normal
GB1L1 = GB1L71 & GB1_sdram_s1_saved_chosen_master_vector[1] # !GB1L71 & (GB1L14 # GB1_sdram_s1_saved_chosen_master_vector[1] & !GB1L19);
--GB1L54 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[0]~735
--operation mode is normal
GB1L54 = EE1L126 & (FB1L237 & GB1L19 # !FB1L237 & (!GB1L72)) # !EE1L126 & (!GB1L72);
--P1L9 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_granted_cpu_jtag_debug_module~83
--operation mode is normal
P1L9 = P1L10 & (P1L2 # !P1_cpu_jtag_debug_module_arb_addend[0]);
--P1L3 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_granted_cpu_jtag_debug_module~54
--operation mode is normal
P1L3 = P1_cpu_data_master_requests_cpu_jtag_debug_module & (P1_cpu_jtag_debug_module_arb_addend[1] # !P1L10 & !P1_cpu_jtag_debug_module_arb_addend[0]);
--P1L30 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_begintransfer~56
--operation mode is normal
P1L30 = !P1_d1_reasons_to_wait & (P1L10 # P1L7 & P1L8);
--P1L35 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_end_xfer~38
--operation mode is normal
P1L35 = P1L30 & (P1L9 # QB1L4 & P1L3);
--P1L28 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]~737
--operation mode is normal
P1L28 = P1L9 & (!P1L35) # !P1L9 & P1_cpu_jtag_debug_module_arb_addend[1] & !P1L3;
--P1_cpu_jtag_debug_module_saved_chosen_master_vector[0] is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_saved_chosen_master_vector[0]
--operation mode is normal
P1_cpu_jtag_debug_module_saved_chosen_master_vector[0]_lut_out = P1L29;
P1_cpu_jtag_debug_module_saved_chosen_master_vector[0] = DFFEAS(P1_cpu_jtag_debug_module_saved_chosen_master_vector[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--P1L29 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_winner[0]~20
--operation mode is normal
P1L29 = P1L9 # P1_cpu_jtag_debug_module_saved_chosen_master_vector[0] & (!P1L3);
--P1L26 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]~739
--operation mode is normal
P1L26 = P1L9 & P1L35 # !P1L9 & (!P1_cpu_jtag_debug_module_arb_addend[0] & !P1L3);
--L1L816 is std_1s10:inst|cpu:the_cpu|Equal53~789
--operation mode is normal
L1L816 = AMPP_FUNCTION(L1_D_iw[0], L1_D_iw[1], L1_D_iw[2], L1_D_iw[3]);
--L1L161 is std_1s10:inst|cpu:the_cpu|D_br_pred_taken~34
--operation mode is normal
L1L161 = AMPP_FUNCTION(L1L202, L1_D_iw[21], L1L187, L1L816);
--L1_D_refetch is std_1s10:inst|cpu:the_cpu|D_refetch
--operation mode is normal
L1_D_refetch = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit);
--L1_F_kill is std_1s10:inst|cpu:the_cpu|F_kill
--operation mode is normal
L1_F_kill = AMPP_FUNCTION(L1_D_issue, L1L161, L1_M_pipe_flush, L1_D_refetch);
--L1_F_pc[12] is std_1s10:inst|cpu:the_cpu|F_pc[12]
--operation mode is normal
L1_F_pc[12] = AMPP_FUNCTION(DE1__clk0, L1L33, L1_D_pc[12], L1_M_pipe_flush_waddr[12], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1_F_pc[16] is std_1s10:inst|cpu:the_cpu|F_pc[16]
--operation mode is normal
L1_F_pc[16] = AMPP_FUNCTION(DE1__clk0, L1L34, L1_D_pc[16], L1_M_pipe_flush_waddr[16], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--LC1_q_b[14] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[14]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[14] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--LC1_q_b[10] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[10]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[10] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[2], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1L853 is std_1s10:inst|cpu:the_cpu|F_ic_hit~116
--operation mode is normal
L1L853 = AMPP_FUNCTION(L1_F_pc[12], L1_F_pc[16], LC1_q_b[14], LC1_q_b[10]);
--L1_F_pc[20] is std_1s10:inst|cpu:the_cpu|F_pc[20]
--operation mode is normal
L1_F_pc[20] = AMPP_FUNCTION(DE1__clk0, L1L35, L1_D_pc[20], L1_M_pipe_flush_waddr[20], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1_F_pc[19] is std_1s10:inst|cpu:the_cpu|F_pc[19]
--operation mode is normal
L1_F_pc[19] = AMPP_FUNCTION(DE1__clk0, L1L36, L1_D_pc[19], L1_M_pipe_flush_waddr[19], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--LC1_q_b[17] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[17]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[17] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[9], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--LC1_q_b[18] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[18]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[18] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[10], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1L854 is std_1s10:inst|cpu:the_cpu|F_ic_hit~117
--operation mode is normal
L1L854 = AMPP_FUNCTION(L1_F_pc[20], L1_F_pc[19], LC1_q_b[17], LC1_q_b[18]);
--L1_F_pc[18] is std_1s10:inst|cpu:the_cpu|F_pc[18]
--operation mode is normal
L1_F_pc[18] = AMPP_FUNCTION(DE1__clk0, L1L37, L1_D_pc[18], L1_M_pipe_flush_waddr[18], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1_F_pc[17] is std_1s10:inst|cpu:the_cpu|F_pc[17]
--operation mode is normal
L1_F_pc[17] = AMPP_FUNCTION(DE1__clk0, L1L38, L1_D_pc[17], L1_M_pipe_flush_waddr[17], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--LC1_q_b[15] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[15]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[15] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[7], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--LC1_q_b[16] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[16]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[16] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[8], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1L855 is std_1s10:inst|cpu:the_cpu|F_ic_hit~118
--operation mode is normal
L1L855 = AMPP_FUNCTION(L1_F_pc[18], L1_F_pc[17], LC1_q_b[15], LC1_q_b[16]);
--L1_F_pc[21] is std_1s10:inst|cpu:the_cpu|F_pc[21]
--operation mode is normal
L1_F_pc[21] = AMPP_FUNCTION(DE1__clk0, L1L39, L1_D_pc[21], L1_M_pipe_flush_waddr[21], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1_F_pc[14] is std_1s10:inst|cpu:the_cpu|F_pc[14]
--operation mode is normal
L1_F_pc[14] = AMPP_FUNCTION(DE1__clk0, L1L40, L1_D_pc[14], L1_M_pipe_flush_waddr[14], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--LC1_q_b[12] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[12]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[12] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[4], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--LC1_q_b[19] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[19]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[19] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[11], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1L856 is std_1s10:inst|cpu:the_cpu|F_ic_hit~119
--operation mode is normal
L1L856 = AMPP_FUNCTION(L1_F_pc[21], L1_F_pc[14], LC1_q_b[12], LC1_q_b[19]);
--L1L857 is std_1s10:inst|cpu:the_cpu|F_ic_hit~120
--operation mode is normal
L1L857 = AMPP_FUNCTION(L1L853, L1L854, L1L855, L1L856);
--L1_F_pc[11] is std_1s10:inst|cpu:the_cpu|F_pc[11]
--operation mode is normal
L1_F_pc[11] = AMPP_FUNCTION(DE1__clk0, L1L41, L1_D_pc[11], L1_M_pipe_flush_waddr[11], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1_F_pc[22] is std_1s10:inst|cpu:the_cpu|F_pc[22]
--operation mode is normal
L1_F_pc[22] = AMPP_FUNCTION(DE1__clk0, L1L42, L1_D_pc[22], L1_M_pipe_flush_waddr[22], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--LC1_q_b[20] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[20]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[20] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[12], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--LC1_q_b[9] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[9] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[1], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1L858 is std_1s10:inst|cpu:the_cpu|F_ic_hit~121
--operation mode is normal
L1L858 = AMPP_FUNCTION(L1_F_pc[11], L1_F_pc[22], LC1_q_b[20], LC1_q_b[9]);
--L1_F_pc[23] is std_1s10:inst|cpu:the_cpu|F_pc[23]
--operation mode is normal
L1_F_pc[23] = AMPP_FUNCTION(DE1__clk0, L1L43, L1_D_pc[23], L1_M_pipe_flush_waddr[23], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1_F_pc[15] is std_1s10:inst|cpu:the_cpu|F_pc[15]
--operation mode is normal
L1_F_pc[15] = AMPP_FUNCTION(DE1__clk0, L1L44, L1_D_pc[15], L1_M_pipe_flush_waddr[15], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--LC1_q_b[13] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[13]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[13] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[5], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--LC1_q_b[21] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[21]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[21] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[13], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1L859 is std_1s10:inst|cpu:the_cpu|F_ic_hit~122
--operation mode is normal
L1L859 = AMPP_FUNCTION(L1_F_pc[23], L1_F_pc[15], LC1_q_b[13], LC1_q_b[21]);
--L1_F_pc[13] is std_1s10:inst|cpu:the_cpu|F_pc[13]
--operation mode is normal
L1_F_pc[13] = AMPP_FUNCTION(DE1__clk0, L1L45, L1_D_pc[13], L1_M_pipe_flush_waddr[13], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1_F_pc[10] is std_1s10:inst|cpu:the_cpu|F_pc[10]
--operation mode is normal
L1_F_pc[10] = AMPP_FUNCTION(DE1__clk0, L1L46, L1_D_pc[10], L1_M_pipe_flush_waddr[10], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--LC1_q_b[8] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[8] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[0], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--LC1_q_b[11] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[11]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[11] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[3], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1L860 is std_1s10:inst|cpu:the_cpu|F_ic_hit~123
--operation mode is normal
L1L860 = AMPP_FUNCTION(L1_F_pc[13], L1_F_pc[10], LC1_q_b[8], LC1_q_b[11]);
--LC1_q_b[5] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[5] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_valid_bits[5], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1_F_pc[2] is std_1s10:inst|cpu:the_cpu|F_pc[2]
--operation mode is normal
L1_F_pc[2] = AMPP_FUNCTION(DE1__clk0, L1L838, E1_data_out, L1_W_stall);
--LC1_q_b[3] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[3] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_valid_bits[3], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1_F_pc[1] is std_1s10:inst|cpu:the_cpu|F_pc[1]
--operation mode is normal
L1_F_pc[1] = AMPP_FUNCTION(DE1__clk0, L1L835, E1_data_out, L1_W_stall);
--LC1_q_b[1] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[1] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_valid_bits[1], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1L884 is std_1s10:inst|cpu:the_cpu|F_ic_valid~23
--operation mode is normal
L1L884 = AMPP_FUNCTION(L1_F_pc[2], LC1_q_b[3], L1_F_pc[1], LC1_q_b[1]);
--LC1_q_b[7] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[7] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_valid_bits[7], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1L885 is std_1s10:inst|cpu:the_cpu|F_ic_valid~24
--operation mode is normal
L1L885 = AMPP_FUNCTION(LC1_q_b[5], L1_F_pc[2], L1L884, LC1_q_b[7]);
--LC1_q_b[2] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[2] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_valid_bits[2], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--LC1_q_b[4] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[4] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_valid_bits[4], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--LC1_q_b[0] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[0] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_valid_bits[0], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1L886 is std_1s10:inst|cpu:the_cpu|F_ic_valid~25
--operation mode is normal
L1L886 = AMPP_FUNCTION(L1_F_pc[1], LC1_q_b[4], L1_F_pc[2], LC1_q_b[0]);
--LC1_q_b[6] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 1, Port B Depth: 128, Port B Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[6] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_valid_bits[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1L887 is std_1s10:inst|cpu:the_cpu|F_ic_valid~26
--operation mode is normal
L1L887 = AMPP_FUNCTION(LC1_q_b[2], L1_F_pc[1], L1L886, LC1_q_b[6]);
--L1_F_pc[0] is std_1s10:inst|cpu:the_cpu|F_pc[0]
--operation mode is normal
L1_F_pc[0] = AMPP_FUNCTION(DE1__clk0, L1L832, E1_data_out, L1_W_stall);
--L1L861 is std_1s10:inst|cpu:the_cpu|F_ic_hit~124
--operation mode is normal
L1L861 = AMPP_FUNCTION(L1L860, L1L885, L1L887, L1_F_pc[0]);
--L1_M_ctrl_invalidate_i is std_1s10:inst|cpu:the_cpu|M_ctrl_invalidate_i
--operation mode is normal
L1_M_ctrl_invalidate_i = AMPP_FUNCTION(DE1__clk0, L1_E_iw[14], L1L545, L1L546, L1L433, E1_data_out, L1_W_stall);
--L1L1040 is std_1s10:inst|cpu:the_cpu|ic_fill_prevent_refill_nxt~0
--operation mode is normal
L1L1040 = AMPP_FUNCTION(L1_M_valid_from_E, L1_M_ctrl_invalidate_i);
--L1L840 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~195
--operation mode is normal
L1L840 = AMPP_FUNCTION(L1_F_pc[19], L1_F_pc[17], L1_ic_fill_tag[7], L1_ic_fill_tag[9]);
--L1_F_pc[9] is std_1s10:inst|cpu:the_cpu|F_pc[9]
--operation mode is normal
L1_F_pc[9] = AMPP_FUNCTION(DE1__clk0, L1L882, E1_data_out, L1_W_stall);
--L1L841 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~196
--operation mode is normal
L1L841 = AMPP_FUNCTION(L1_F_pc[13], L1_ic_fill_line[6], L1_F_pc[9], L1_ic_fill_tag[3]);
--L1_F_pc[7] is std_1s10:inst|cpu:the_cpu|F_pc[7]
--operation mode is normal
L1_F_pc[7] = AMPP_FUNCTION(DE1__clk0, L1L876, E1_data_out, L1_W_stall);
--L1L842 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~197
--operation mode is normal
L1L842 = AMPP_FUNCTION(L1_F_pc[21], L1_ic_fill_line[4], L1_F_pc[7], L1_ic_fill_tag[11]);
--L1_F_pc[5] is std_1s10:inst|cpu:the_cpu|F_pc[5]
--operation mode is normal
L1_F_pc[5] = AMPP_FUNCTION(DE1__clk0, L1L870, E1_data_out, L1_W_stall);
--L1L843 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~198
--operation mode is normal
L1L843 = AMPP_FUNCTION(L1_F_pc[11], L1_ic_fill_line[2], L1_F_pc[5], L1_ic_fill_tag[1]);
--L1L844 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~199
--operation mode is normal
L1L844 = AMPP_FUNCTION(L1L840, L1L841, L1L842, L1L843);
--L1_F_pc[3] is std_1s10:inst|cpu:the_cpu|F_pc[3]
--operation mode is normal
L1_F_pc[3] = AMPP_FUNCTION(DE1__clk0, L1L864, E1_data_out, L1_W_stall);
--L1L845 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~200
--operation mode is normal
L1L845 = AMPP_FUNCTION(L1_F_pc[14], L1_ic_fill_line[0], L1_F_pc[3], L1_ic_fill_tag[4]);
--L1_F_pc[8] is std_1s10:inst|cpu:the_cpu|F_pc[8]
--operation mode is normal
L1_F_pc[8] = AMPP_FUNCTION(DE1__clk0, L1L879, E1_data_out, L1_W_stall);
--L1L846 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~201
--operation mode is normal
L1L846 = AMPP_FUNCTION(L1_F_pc[18], L1_ic_fill_line[5], L1_F_pc[8], L1_ic_fill_tag[8]);
--L1L847 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~202
--operation mode is normal
L1L847 = AMPP_FUNCTION(L1_F_pc[20], L1_F_pc[10], L1_ic_fill_tag[0], L1_ic_fill_tag[10]);
--L1_F_pc[4] is std_1s10:inst|cpu:the_cpu|F_pc[4]
--operation mode is normal
L1_F_pc[4] = AMPP_FUNCTION(DE1__clk0, L1L867, E1_data_out, L1_W_stall);
--L1L848 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~203
--operation mode is normal
L1L848 = AMPP_FUNCTION(L1_F_pc[15], L1_ic_fill_line[1], L1_F_pc[4], L1_ic_fill_tag[5]);
--L1L849 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~204
--operation mode is normal
L1L849 = AMPP_FUNCTION(L1L845, L1L846, L1L847, L1L848);
--L1L850 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~205
--operation mode is normal
L1L850 = AMPP_FUNCTION(L1_F_pc[16], L1_F_pc[23], L1_ic_fill_tag[13], L1_ic_fill_tag[6]);
--L1_F_pc[6] is std_1s10:inst|cpu:the_cpu|F_pc[6]
--operation mode is normal
L1_F_pc[6] = AMPP_FUNCTION(DE1__clk0, L1L873, E1_data_out, L1_W_stall);
--L1L851 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~206
--operation mode is normal
L1L851 = AMPP_FUNCTION(L1_F_pc[12], L1_ic_fill_line[3], L1_F_pc[6], L1_ic_fill_tag[2]);
--L1L852 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~207
--operation mode is normal
L1L852 = AMPP_FUNCTION(L1L851, L1_F_pc[22], L1_ic_fill_tag[12]);
--L1_i_readdatavalid_d1 is std_1s10:inst|cpu:the_cpu|i_readdatavalid_d1
--operation mode is normal
L1_i_readdatavalid_d1 = AMPP_FUNCTION(DE1__clk0, N1_cpu_instruction_master_read_but_no_slave_selected, P1L9, P1L30, N1L104, E1_data_out);
--L1_D_ic_fill_starting_d1 is std_1s10:inst|cpu:the_cpu|D_ic_fill_starting_d1
--operation mode is normal
L1_D_ic_fill_starting_d1 = AMPP_FUNCTION(DE1__clk0, L1_D_ic_fill_starting, E1_data_out);
--L1_ic_fill_dp_offset[2] is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset[2]
--operation mode is normal
L1_ic_fill_dp_offset[2] = AMPP_FUNCTION(DE1__clk0, L1_ic_fill_initial_offset[2], L1_D_ic_fill_starting_d1, L1L1023, E1_data_out, L1L1020);
--L1_ic_fill_dp_offset[0] is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset[0]
--operation mode is normal
L1_ic_fill_dp_offset[0] = AMPP_FUNCTION(DE1__clk0, L1L1021, E1_data_out, L1L1020);
--L1_ic_fill_dp_offset[1] is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset[1]
--operation mode is normal
L1_ic_fill_dp_offset[1] = AMPP_FUNCTION(DE1__clk0, L1L1022, E1_data_out, L1L1020);
--L1L1023 is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[2]~152
--operation mode is normal
L1L1023 = AMPP_FUNCTION(L1_ic_fill_dp_offset[2], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_D_ic_fill_starting_d1);
--L1_ic_fill_initial_offset[2] is std_1s10:inst|cpu:the_cpu|ic_fill_initial_offset[2]
--operation mode is normal
L1_ic_fill_initial_offset[2] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[2], E1_data_out, L1_D_ic_fill_starting);
--L1_ic_fill_initial_offset[1] is std_1s10:inst|cpu:the_cpu|ic_fill_initial_offset[1]
--operation mode is normal
L1_ic_fill_initial_offset[1] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[1], E1_data_out, L1_D_ic_fill_starting);
--L1_ic_fill_initial_offset[0] is std_1s10:inst|cpu:the_cpu|ic_fill_initial_offset[0]
--operation mode is normal
L1_ic_fill_initial_offset[0] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[0], E1_data_out, L1_D_ic_fill_starting);
--L1L1004 is std_1s10:inst|cpu:the_cpu|ic_fill_active_nxt~270
--operation mode is normal
L1L1004 = AMPP_FUNCTION(L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_initial_offset[1], L1_ic_fill_initial_offset[0]);
--L1L1005 is std_1s10:inst|cpu:the_cpu|ic_fill_active_nxt~271
--operation mode is normal
L1L1005 = AMPP_FUNCTION(L1_D_ic_fill_starting_d1, L1L1023, L1_ic_fill_initial_offset[2], L1L1004);
--Q1_ext_ram_bus_avalon_slave_arb_share_counter[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0]
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_share_counter[0]_lut_out = Q1L185 # !Q1L194 & (Q1L46 # Q1L80);
Q1_ext_ram_bus_avalon_slave_arb_share_counter[0] = DFFEAS(Q1_ext_ram_bus_avalon_slave_arb_share_counter[0]_lut_out, DE1__clk0, E1_data_out, , Q1L181, , , , );
--Q1L186 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter_next_value[1]~81
--operation mode is normal
Q1L186 = Q1L194 & Q1_ext_ram_bus_avalon_slave_arb_share_counter[0] & Q1_ext_ram_bus_avalon_slave_arb_share_counter[1];
--Q1L297 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|WideOr6~14
--operation mode is normal
Q1L297 = !Q1L48 & !Q1L46 & !Q1L47;
--Q1L181 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_counter_enable~18
--operation mode is normal
Q1L181 = !Q1L192 & (Q1L290 # !N1L5 # !Q1L297);
--Q1L187 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_winner~0
--operation mode is normal
Q1L187 = !Q1L194 & (!N1L5 # !Q1L297);
--Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]_lut_out = Q1L46;
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[3] = DFFEAS(Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[3]_lut_out, DE1__clk0, E1_data_out, , Q1L187, , , , );
--Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]_lut_out = Q1L48;
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[1] = DFFEAS(Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[1]_lut_out, DE1__clk0, E1_data_out, , Q1L187, , , , );
--FB1_rd_valid[2] is std_1s10:inst|sdram:the_sdram|rd_valid[2]
--operation mode is normal
FB1_rd_valid[2]_lut_out = FB1_rd_valid[1];
FB1_rd_valid[2] = DFFEAS(FB1_rd_valid[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--GE1_stage_1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_1
--operation mode is normal
GE1_stage_1_lut_out = GE1_full_2 & GE1_stage_2 # !GE1_full_2 & (GB1L19);
GE1_stage_1 = DFFEAS(GE1_stage_1_lut_out, DE1__clk0, VCC, , GE1L25, , , , );
--GE1_full_1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_1
--operation mode is normal
GE1_full_1_lut_out = FB1_za_valid & (GB1L28 & GE1_full_0 # !GB1L28 & (GE1_full_2)) # !FB1_za_valid & GE1_full_0;
GE1_full_1 = DFFEAS(GE1_full_1_lut_out, DE1__clk0, E1_data_out, , FE1L13, , , , );
--GE1_full_0 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_0
--operation mode is normal
GE1_full_0_lut_out = GB1L28 # GE1_full_1 # !FB1_za_valid;
GE1_full_0 = DFFEAS(GE1_full_0_lut_out, DE1__clk0, E1_data_out, , FE1L13, , , , );
--GE1L26 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process12~3
--operation mode is normal
GE1L26 = FB1_za_valid # GB1L28 & (!GE1_full_0);
--Q1L3 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4230
--operation mode is normal
Q1L3 = !Q1L174 & !Q1L178 & !Q1L172 & !Q1L176;
--Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[4] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]_lut_out = Q1L81;
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[4] = DFFEAS(Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[4]_lut_out, DE1__clk0, E1_data_out, , Q1L187, , , , );
--Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]_lut_out = Q1L82;
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[0] = DFFEAS(Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]_lut_out, DE1__clk0, E1_data_out, , Q1L187, , , , );
--Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]_lut_out = Q1L80;
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[2] = DFFEAS(Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[2]_lut_out, DE1__clk0, E1_data_out, , Q1L187, , , , );
--FE1_stage_1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_1
--operation mode is normal
FE1_stage_1_lut_out = GE1_full_2 & FE1_stage_2 # !GE1_full_2 & (GB1L14);
FE1_stage_1 = DFFEAS(FE1_stage_1_lut_out, DE1__clk0, VCC, , GE1L25, , , , );
--YB1L8 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux2~229
--operation mode is normal
YB1L8 = YB1L7 # YB1_slave_state[2] & (!M1L13);
--YB1L9 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux2~230
--operation mode is normal
YB1L9 = !YB1_slave_state[1] & (M1_internal_cpu_data_master_waitrequest # !J1_cpu_data_master_requests_clock_0_in # !QB1L4);
--SB1_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync|data_in_d1
--operation mode is normal
SB1_data_in_d1_lut_out = WB1_internal_master_write_done;
SB1_data_in_d1 = DFFEAS(SB1_data_in_d1_lut_out, DE1__clk0, E1_data_out, , , , , , );
--J1L1 is std_1s10:inst|clock_0_in_arbitrator:the_clock_0_in|clock_0_in_read~25
--operation mode is normal
J1L1 = L1_internal_d_read & J1_cpu_data_master_requests_clock_0_in & (!M1_internal_cpu_data_master_waitrequest);
--YB1L6 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux1~130
--operation mode is normal
YB1L6 = YB1_slave_state[2] # YB1_slave_state[0] & (XB1_data_in_d1 $ RB1_data_out);
--YB1L5 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux0~139
--operation mode is normal
YB1L5 = YB1_slave_state[2] & (XB2_data_in_d1 $ SB1_data_out # !YB1_slave_state[0]) # !YB1_slave_state[2] & YB1_slave_state[0];
--YB1L4 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_write_request~32
--operation mode is normal
YB1L4 = L1_internal_d_write & J1_cpu_data_master_requests_clock_0_in & !L1_internal_d_read & !M1_internal_cpu_data_master_waitrequest;
--RB1_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_in_d1
--operation mode is normal
RB1_data_in_d1_lut_out = WB1_internal_master_read_done;
RB1_data_in_d1 = DFFEAS(RB1_data_in_d1_lut_out, DE1__clk0, E1_data_out, , , , , , );
--DD1_internal_jdo1[22] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[22]
--operation mode is normal
DD1_internal_jdo1[22] = AMPP_FUNCTION(!A1L9, DD1_sr[22], VCC, DD1L144);
--BB1_countup[4] is std_1s10:inst|pll:the_pll|countup[4]
--operation mode is arithmetic
BB1_countup[4]_carry_eqn = BB1L27;
BB1_countup[4]_lut_out = BB1_countup[4] $ (BB1_countup[4]_carry_eqn);
BB1_countup[4] = DFFEAS(BB1_countup[4]_lut_out, PLD_CLOCKINPUT, BB1_not_areset, , !BB1_count_done, , , , );
--BB1L29 is std_1s10:inst|pll:the_pll|countup[4]~594
--operation mode is arithmetic
BB1L29 = CARRY(!BB1L27 # !BB1_countup[4]);
--BB1_countup[5] is std_1s10:inst|pll:the_pll|countup[5]
--operation mode is normal
BB1_countup[5]_carry_eqn = BB1L29;
BB1_countup[5]_lut_out = BB1_countup[5] $ (!BB1_countup[5]_carry_eqn);
BB1_countup[5] = DFFEAS(BB1_countup[5]_lut_out, PLD_CLOCKINPUT, BB1_not_areset, , !BB1_count_done, , , , );
--BB1_countup[1] is std_1s10:inst|pll:the_pll|countup[1]
--operation mode is arithmetic
BB1_countup[1]_lut_out = BB1_countup[1] $ BB1_countup[0];
BB1_countup[1] = DFFEAS(BB1_countup[1]_lut_out, PLD_CLOCKINPUT, BB1_not_areset, , !BB1_count_done, , , , );
--BB1L23 is std_1s10:inst|pll:the_pll|countup[1]~596
--operation mode is arithmetic
BB1L23 = CARRY(BB1_countup[1] & BB1_countup[0]);
--BB1_countup[2] is std_1s10:inst|pll:the_pll|countup[2]
--operation mode is arithmetic
BB1_countup[2]_carry_eqn = BB1L23;
BB1_countup[2]_lut_out = BB1_countup[2] $ (BB1_countup[2]_carry_eqn);
BB1_countup[2] = DFFEAS(BB1_countup[2]_lut_out, PLD_CLOCKINPUT, BB1_not_areset, , !BB1_count_done, , , , );
--BB1L25 is std_1s10:inst|pll:the_pll|countup[2]~597
--operation mode is arithmetic
BB1L25 = CARRY(!BB1L23 # !BB1_countup[2]);
--BB1_countup[3] is std_1s10:inst|pll:the_pll|countup[3]
--operation mode is arithmetic
BB1_countup[3]_carry_eqn = BB1L25;
BB1_countup[3]_lut_out = BB1_countup[3] $ (!BB1_countup[3]_carry_eqn);
BB1_countup[3] = DFFEAS(BB1_countup[3]_lut_out, PLD_CLOCKINPUT, BB1_not_areset, , !BB1_count_done, , , , );
--BB1L27 is std_1s10:inst|pll:the_pll|countup[3]~598
--operation mode is arithmetic
BB1L27 = CARRY(BB1_countup[3] & (!BB1L25));
--BB1_countup[0] is std_1s10:inst|pll:the_pll|countup[0]
--operation mode is normal
BB1_countup[0]_lut_out = BB1_count_done $ !BB1_countup[0];
BB1_countup[0] = DFFEAS(BB1_countup[0]_lut_out, PLD_CLOCKINPUT, BB1_not_areset, , , , , , );
--BB1L31 is std_1s10:inst|pll:the_pll|Equal0~41
--operation mode is normal
BB1L31 = BB1_countup[1] & BB1_countup[2] & BB1_countup[3] & BB1_countup[0];
--BB1_not_areset is std_1s10:inst|pll:the_pll|not_areset
--operation mode is normal
BB1_not_areset_lut_out = VCC;
BB1_not_areset = DFFEAS(BB1_not_areset_lut_out, PLD_CLOCKINPUT, VCC, , , , , , );
--FB1L350 is std_1s10:inst|sdram:the_sdram|Mux40~1437
--operation mode is normal
FB1L350 = !FB1_m_state[7] & !FB1_m_state[5] & !FB1_m_state[2] & !FB1_m_state[1];
--FB1L351 is std_1s10:inst|sdram:the_sdram|Mux40~1438
--operation mode is normal
FB1L351 = !FB1_refresh_request & (!FB1L554 # !EE1L127) # !FB1L364;
--FB1L352 is std_1s10:inst|sdram:the_sdram|Mux40~1439
--operation mode is normal
FB1L352 = FB1_m_count[2] & (!FB1L350 # !FB1L176 # !FB1L348);
--FB1L353 is std_1s10:inst|sdram:the_sdram|Mux40~1440
--operation mode is normal
FB1L353 = !FB1_m_state[3] & !FB1_m_state[7] & !FB1_m_state[2] & !FB1_m_state[1];
--FB1L354 is std_1s10:inst|sdram:the_sdram|Mux40~1441
--operation mode is normal
FB1L354 = FB1L554 # !FB1L353 # !FB1_refresh_request # !EE1L127;
--FB1_m_count[0] is std_1s10:inst|sdram:the_sdram|m_count[0]
--operation mode is normal
FB1_m_count[0]_lut_out = FB1_m_state[5] & (FB1L388 & (FB1_m_count[0]) # !FB1L388 & FB1L380) # !FB1_m_state[5] & (FB1L388);
FB1_m_count[0] = DFFEAS(FB1_m_count[0]_lut_out, DE1__clk0, E1_data_out, , !FB1_m_state[6], , , , );
--FB1L355 is std_1s10:inst|sdram:the_sdram|Mux40~1442
--operation mode is normal
FB1L355 = FB1_m_count[2] & (FB1_m_count[1] # FB1_m_count[0] # !FB1L353);
--FB1L356 is std_1s10:inst|sdram:the_sdram|Mux40~1443
--operation mode is normal
FB1L356 = FB1L554 # !FB1L299 # !FB1_refresh_request # !EE1L127;
--FB1L357 is std_1s10:inst|sdram:the_sdram|Mux40~1444
--operation mode is normal
FB1L357 = FB1_m_count[2] & (FB1_m_count[1] # FB1_m_count[0] # !FB1L299);
--FB1L358 is std_1s10:inst|sdram:the_sdram|Mux40~1445
--operation mode is normal
FB1L358 = FB1_m_count[2] & (FB1_m_state[7] $ !FB1_m_state[1]);
--FB1L359 is std_1s10:inst|sdram:the_sdram|Mux40~1446
--operation mode is normal
FB1L359 = FB1_m_state[3] & (FB1_m_state[2]) # !FB1_m_state[3] & (FB1_m_state[2] & FB1L357 # !FB1_m_state[2] & (FB1L358));
--FB1L360 is std_1s10:inst|sdram:the_sdram|Mux40~1447
--operation mode is normal
FB1L360 = FB1_m_state[3] & FB1_m_count[2] & (FB1L356 # FB1L359) # !FB1_m_state[3] & (FB1L359);
--FB1L361 is std_1s10:inst|sdram:the_sdram|Mux40~1448
--operation mode is normal
FB1L361 = FB1_m_state[4] & (FB1_m_state[5]) # !FB1_m_state[4] & (FB1_m_state[5] & FB1L355 # !FB1_m_state[5] & (FB1L360));
--FB1L362 is std_1s10:inst|sdram:the_sdram|Mux40~1449
--operation mode is normal
FB1L362 = FB1_m_state[4] & FB1_m_count[2] & (FB1L354 # FB1L361) # !FB1_m_state[4] & (FB1L361);
--FB1L363 is std_1s10:inst|sdram:the_sdram|Mux40~1450
--operation mode is normal
FB1L363 = FB1_m_state[8] & (!FB1_m_state[0]) # !FB1_m_state[8] & (FB1_m_state[0] & (FB1L362) # !FB1_m_state[0] & FB1L352);
--FB1L366 is std_1s10:inst|sdram:the_sdram|Mux41~1449
--operation mode is normal
FB1L366 = FB1L554 # !FB1L377 # !FB1_refresh_request # !EE1L127;
--FB1L367 is std_1s10:inst|sdram:the_sdram|Mux41~1450
--operation mode is normal
FB1L367 = FB1_m_count[1] & (!FB1L222 # !FB1L350 # !FB1L365);
--FB1L368 is std_1s10:inst|sdram:the_sdram|Mux41~1451
--operation mode is normal
FB1L368 = EE1L127 & FB1_refresh_request & FB1L350 & !FB1L554;
--FB1L369 is std_1s10:inst|sdram:the_sdram|Mux41~1452
--operation mode is normal
FB1L369 = !FB1_m_state[5] & !FB1_m_state[2];
--FB1L370 is std_1s10:inst|sdram:the_sdram|Mux41~1453
--operation mode is normal
FB1L370 = FB1_m_state[1] & (FB1_m_state[5] # FB1_m_state[2]) # !FB1_m_state[1] & !FB1_m_count[0] & (FB1_m_state[5] $ FB1_m_state[2]);
--FB1L371 is std_1s10:inst|sdram:the_sdram|Mux41~1454
--operation mode is normal
FB1L371 = FB1L370 & (FB1_m_count[1] # FB1_m_count[2]);
--FB1L372 is std_1s10:inst|sdram:the_sdram|Mux41~1455
--operation mode is normal
FB1L372 = FB1_m_state[7] & FB1_m_state[1] # !FB1_m_state[7] & (FB1_m_state[1] & FB1_m_count[1] & FB1L371 # !FB1_m_state[1] & (FB1_m_count[1] $ FB1L371));
--FB1L373 is std_1s10:inst|sdram:the_sdram|Mux41~1456
--operation mode is normal
FB1L373 = FB1_m_state[7] & (FB1_m_count[1] # FB1L369 & !FB1L372) # !FB1_m_state[7] & (FB1L372);
--FB1L374 is std_1s10:inst|sdram:the_sdram|Mux41~1457
--operation mode is normal
FB1L374 = FB1_m_state[3] & (!FB1_m_state[0]) # !FB1_m_state[3] & (FB1_m_state[0] & (FB1L373) # !FB1_m_state[0] & FB1L378);
--FB1L375 is std_1s10:inst|sdram:the_sdram|Mux41~1458
--operation mode is normal
FB1L375 = FB1_m_state[3] & (FB1_m_count[1] # FB1L368 & !FB1L374) # !FB1_m_state[3] & (FB1L374);
--FB1L376 is std_1s10:inst|sdram:the_sdram|Mux41~1459
--operation mode is normal
FB1L376 = FB1_m_state[4] & (FB1_m_state[8]) # !FB1_m_state[4] & (FB1_m_state[8] & FB1L367 # !FB1_m_state[8] & (FB1L375));
--FB1_i_next[0] is std_1s10:inst|sdram:the_sdram|i_next[0]
--operation mode is normal
FB1_i_next[0]_lut_out = FB1_i_state[2] # CD1L26 & !FB1_i_refs[1] & !FB1_i_refs[2];
FB1_i_next[0] = DFFEAS(FB1_i_next[0]_lut_out, DE1__clk0, E1_data_out, , CD1L27, , , , );
--FB1_i_count[2] is std_1s10:inst|sdram:the_sdram|i_count[2]
--operation mode is normal
FB1_i_count[2]_lut_out = FB1_i_state[0] & FB1_i_state[1] & (FB1_i_state[2] # FB1L242);
FB1_i_count[2] = DFFEAS(FB1_i_count[2]_lut_out, DE1__clk0, E1_data_out, , FB1L243, , , , );
--FB1_i_count[1] is std_1s10:inst|sdram:the_sdram|i_count[1]
--operation mode is normal
FB1_i_count[1]_lut_out = FB1_i_state[1] & !FB1_i_state[2] & (FB1L244 # !FB1_i_state[0]);
FB1_i_count[1] = DFFEAS(FB1_i_count[1]_lut_out, DE1__clk0, E1_data_out, , FB1L243, , , , );
--FB1L148 is std_1s10:inst|sdram:the_sdram|LessThan0~41
--operation mode is normal
FB1L148 = FB1_i_count[2] # FB1_i_count[1];
--FB1L240 is std_1s10:inst|sdram:the_sdram|Mux9~221
--operation mode is normal
FB1L240 = FB1_i_state[1] & (!FB1_i_state[2]);
--FB1L241 is std_1s10:inst|sdram:the_sdram|Mux9~222
--operation mode is normal
FB1L241 = FB1_i_state[0] & (FB1_i_next[0] # FB1L148 # !FB1L240);
--FB1L138 is std_1s10:inst|sdram:the_sdram|i_refs[0]~278
--operation mode is normal
FB1L138 = !FB1_i_state[0] & !FB1_i_state[2];
--FB1L238 is std_1s10:inst|sdram:the_sdram|Mux7~95
--operation mode is normal
FB1L238 = FB1_i_next[0] & (!FB1_i_count[2] & !FB1_i_count[1]);
--FB1_i_next[1] is std_1s10:inst|sdram:the_sdram|i_next[1]
--operation mode is normal
FB1_i_next[1]_lut_out = !FB1_i_state[2];
FB1_i_next[1] = DFFEAS(FB1_i_next[1]_lut_out, DE1__clk0, E1_data_out, , CD1L27, , , , );
--FB1L239 is std_1s10:inst|sdram:the_sdram|Mux8~208
--operation mode is normal
FB1L239 = FB1_i_count[2] # FB1_i_count[1] # FB1_i_next[1];
--FB1L74 is std_1s10:inst|sdram:the_sdram|Add0~218
--operation mode is arithmetic
FB1L74 = FB1_refresh_counter[3] $ (FB1L74_carry_eqn);
--FB1L75 is std_1s10:inst|sdram:the_sdram|Add0~219
--operation mode is arithmetic
FB1L75 = CARRY(FB1_refresh_counter[3] & (!FB1L81));
--FB1L76 is std_1s10:inst|sdram:the_sdram|Add0~220
--operation mode is arithmetic
FB1L76 = !FB1_refresh_counter[0];
--FB1L77 is std_1s10:inst|sdram:the_sdram|Add0~221
--operation mode is arithmetic
FB1L77 = CARRY(FB1_refresh_counter[0]);
--FB1L78 is std_1s10:inst|sdram:the_sdram|Add0~222
--operation mode is arithmetic
FB1L78 = FB1_refresh_counter[1] $ (!FB1L78_carry_eqn);
--FB1L79 is std_1s10:inst|sdram:the_sdram|Add0~223
--operation mode is arithmetic
FB1L79 = CARRY(!FB1_refresh_counter[1] & (!FB1L77));
--FB1L80 is std_1s10:inst|sdram:the_sdram|Add0~224
--operation mode is arithmetic
FB1L80 = FB1_refresh_counter[2] $ (FB1L80_carry_eqn);
--FB1L81 is std_1s10:inst|sdram:the_sdram|Add0~225
--operation mode is arithmetic
FB1L81 = CARRY(FB1_refresh_counter[2] # !FB1L79);
--FB1L82 is std_1s10:inst|sdram:the_sdram|Add0~226
--operation mode is arithmetic
FB1L82 = FB1_refresh_counter[7] $ (FB1L82_carry_eqn);
--FB1L83 is std_1s10:inst|sdram:the_sdram|Add0~227
--operation mode is arithmetic
FB1L83 = CARRY(FB1_refresh_counter[7] & (!FB1L89));
--FB1L84 is std_1s10:inst|sdram:the_sdram|Add0~228
--operation mode is arithmetic
FB1L84 = FB1_refresh_counter[4] $ (FB1L84_carry_eqn);
--FB1L85 is std_1s10:inst|sdram:the_sdram|Add0~229
--operation mode is arithmetic
FB1L85 = CARRY(FB1_refresh_counter[4] # !FB1L75);
--FB1L86 is std_1s10:inst|sdram:the_sdram|Add0~230
--operation mode is arithmetic
FB1L86 = FB1_refresh_counter[5] $ (!FB1L86_carry_eqn);
--FB1L87 is std_1s10:inst|sdram:the_sdram|Add0~231
--operation mode is arithmetic
FB1L87 = CARRY(!FB1_refresh_counter[5] & (!FB1L85));
--FB1L88 is std_1s10:inst|sdram:the_sdram|Add0~232
--operation mode is arithmetic
FB1L88 = FB1_refresh_counter[6] $ (FB1L88_carry_eqn);
--FB1L89 is std_1s10:inst|sdram:the_sdram|Add0~233
--operation mode is arithmetic
FB1L89 = CARRY(FB1_refresh_counter[6] # !FB1L87);
--FB1L90 is std_1s10:inst|sdram:the_sdram|Add0~234
--operation mode is normal
FB1L90 = FB1_refresh_counter[12] $ (!FB1L90_carry_eqn);
--FB1L91 is std_1s10:inst|sdram:the_sdram|Add0~236
--operation mode is arithmetic
FB1L91 = FB1_refresh_counter[8] $ (!FB1L91_carry_eqn);
--FB1L92 is std_1s10:inst|sdram:the_sdram|Add0~237
--operation mode is arithmetic
FB1L92 = CARRY(!FB1L83 # !FB1_refresh_counter[8]);
--FB1L93 is std_1s10:inst|sdram:the_sdram|Add0~238
--operation mode is arithmetic
FB1L93 = FB1_refresh_counter[9] $ (FB1L93_carry_eqn);
--FB1L94 is std_1s10:inst|sdram:the_sdram|Add0~239
--operation mode is arithmetic
FB1L94 = CARRY(FB1_refresh_counter[9] & (!FB1L92));
--FB1L95 is std_1s10:inst|sdram:the_sdram|Add0~240
--operation mode is arithmetic
FB1L95 = FB1_refresh_counter[10] $ (FB1L95_carry_eqn);
--FB1L96 is std_1s10:inst|sdram:the_sdram|Add0~241
--operation mode is arithmetic
FB1L96 = CARRY(FB1_refresh_counter[10] # !FB1L94);
--FB1L97 is std_1s10:inst|sdram:the_sdram|Add0~242
--operation mode is arithmetic
FB1L97 = FB1_refresh_counter[11] $ (!FB1L97_carry_eqn);
--FB1L98 is std_1s10:inst|sdram:the_sdram|Add0~243
--operation mode is arithmetic
FB1L98 = CARRY(!FB1_refresh_counter[11] & (!FB1L96));
--FB1L270 is std_1s10:inst|sdram:the_sdram|Mux21~1080
--operation mode is normal
FB1L270 = !FB1_m_state[2] & (FB1_m_state[7] $ !FB1_m_state[0]);
--FB1L271 is std_1s10:inst|sdram:the_sdram|Mux21~1081
--operation mode is normal
FB1L271 = FB1L246 & FB1L270 & !FB1_m_state[4] & !FB1_m_state[6];
--T1_ien_AE is std_1s10:inst|jtag_uart:the_jtag_uart|ien_AE
--operation mode is normal
T1_ien_AE_lut_out = L1_M_st_data[1];
T1_ien_AE = DFFEAS(T1_ien_AE_lut_out, DE1__clk0, E1_data_out, , T1L46, , , , );
--T1_fifo_AE is std_1s10:inst|jtag_uart:the_jtag_uart|fifo_AE
--operation mode is normal
T1_fifo_AE_lut_out = !ZD1_safe_q[5] & !ZD1_safe_q[4] & !T1L50 & !WD1_b_full;
T1_fifo_AE = DFFEAS(T1_fifo_AE_lut_out, DE1__clk0, E1_data_out, , , , , , );
--T1L49 is std_1s10:inst|jtag_uart:the_jtag_uart|ipen_AE~11
--operation mode is normal
T1L49 = T1_ien_AE & T1_fifo_AE;
--T1_ien_AF is std_1s10:inst|jtag_uart:the_jtag_uart|ien_AF
--operation mode is normal
T1_ien_AF_lut_out = L1_M_st_data[0];
T1_ien_AF = DFFEAS(T1_ien_AF_lut_out, DE1__clk0, E1_data_out, , T1L46, , , , );
--T1_fifo_AF is std_1s10:inst|jtag_uart:the_jtag_uart|fifo_AF
--operation mode is normal
T1_fifo_AF_lut_out = !T1L3 & !T1L51 & !T1L52 & T1L15;
T1_fifo_AF = DFFEAS(T1_fifo_AF_lut_out, DE1__clk0, E1_data_out, , , , , , );
--T1_pause_irq is std_1s10:inst|jtag_uart:the_jtag_uart|pause_irq
--operation mode is normal
T1_pause_irq_lut_out = WD2_b_non_empty & (QD1L39Q # T1_pause_irq & !T1_read_0) # !WD2_b_non_empty & (T1_pause_irq & !T1_read_0);
T1_pause_irq = DFFEAS(T1_pause_irq_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L304 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~2077
--operation mode is normal
M1L304 = T1_ien_AF & (T1_fifo_AF # T1_pause_irq);
--SC1_internal_oci_ienable1[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[2]
--operation mode is normal
SC1_internal_oci_ienable1[2] = AMPP_FUNCTION(DE1__clk0, L1_M_st_data[2], E1_data_out, SC1L12);
--L1_E_iw[6] is std_1s10:inst|cpu:the_cpu|E_iw[6]
--operation mode is normal
L1_E_iw[6] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[6], E1_data_out, L1_W_stall);
--L1_E_iw[7] is std_1s10:inst|cpu:the_cpu|E_iw[7]
--operation mode is normal
L1_E_iw[7] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[7], E1_data_out, L1_W_stall);
--L1_E_ctrl_wrctl_inst is std_1s10:inst|cpu:the_cpu|E_ctrl_wrctl_inst
--operation mode is normal
L1_E_ctrl_wrctl_inst = AMPP_FUNCTION(DE1__clk0, L1L228, L1L824, E1_data_out, L1_W_stall);
--L1_E_iw[8] is std_1s10:inst|cpu:the_cpu|E_iw[8]
--operation mode is normal
L1_E_iw[8] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[8], E1_data_out, L1_W_stall);
--L1L805 is std_1s10:inst|cpu:the_cpu|E_wrctl_bstatus~9
--operation mode is normal
L1L805 = AMPP_FUNCTION(L1_E_iw[7], L1_E_ctrl_wrctl_inst, L1_E_iw[8]);
--L1L1150 is std_1s10:inst|cpu:the_cpu|M_ienable_reg[2]~3
--operation mode is normal
L1L1150 = AMPP_FUNCTION(L1L800, L1_E_iw[6], L1L805, L1_W_stall);
--KC1_q_b[8] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[8]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[8] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[8], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1_M_status_reg_pie is std_1s10:inst|cpu:the_cpu|M_status_reg_pie
--operation mode is normal
L1_M_status_reg_pie = AMPP_FUNCTION(DE1__clk0, L1L1329, L1L1334, L1L1331, L1L1332, E1_data_out);
--L1L1094 is std_1s10:inst|cpu:the_cpu|intr_req~66
--operation mode is normal
L1L1094 = AMPP_FUNCTION(L1_M_ipending_reg[2], L1_M_ipending_reg[3], L1_M_ipending_reg[4], L1_M_ipending_reg[5]);
--L1_M_ipending_reg[1] is std_1s10:inst|cpu:the_cpu|M_ipending_reg[1]
--operation mode is normal
L1_M_ipending_reg[1] = AMPP_FUNCTION(DE1__clk0, L1_M_ienable_reg[1], KB1_control_register[0], KB1_timeout_occurred, SC1_internal_oci_ienable1[1], E1_data_out);
--L1_M_ipending_reg[0] is std_1s10:inst|cpu:the_cpu|M_ipending_reg[0]
--operation mode is normal
L1_M_ipending_reg[0] = AMPP_FUNCTION(DE1__clk0, L1_M_ienable_reg[0], Q1_d1_irq_from_the_lan91c111, SC1_internal_oci_ienable1[0], E1_data_out);
--L1L1095 is std_1s10:inst|cpu:the_cpu|intr_req~67
--operation mode is normal
L1L1095 = AMPP_FUNCTION(L1_M_status_reg_pie, L1L1094, L1_M_ipending_reg[1], L1_M_ipending_reg[0]);
--KC1_q_b[7] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[7] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[7], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[6] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[6] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[6], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[4] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[4] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[4], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[15] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[15]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[15] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[15], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[5] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[5] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[5], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[0] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[0] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[0], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[1] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[1] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[1], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[2] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[2] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[2], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[3] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[3] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[3], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[27] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[27]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[27] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[27], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[28] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[28]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[28] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[28], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[29] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[29]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[29] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[29], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[30] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[30]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[30] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[30], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[31] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[31]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[31] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[31], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1L231 is std_1s10:inst|cpu:the_cpu|D_dst_regnum[1]~573
--operation mode is normal
L1L231 = AMPP_FUNCTION(L1_D_iw[23], L1_D_iw[18], L1L197, L1L810);
--L1L200 is std_1s10:inst|cpu:the_cpu|D_ctrl_break~35
--operation mode is normal
L1L200 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[13], L1_D_iw[14]);
--L1L201 is std_1s10:inst|cpu:the_cpu|D_ctrl_break~36
--operation mode is normal
L1L201 = AMPP_FUNCTION(L1L811, L1L808, L1L200, L1_D_iw[12]);
--L1L232 is std_1s10:inst|cpu:the_cpu|D_dst_regnum[1]~574
--operation mode is normal
L1L232 = AMPP_FUNCTION(L1L188, L1L231, L1_D_iw[15], L1L201);
--L1L235 is std_1s10:inst|cpu:the_cpu|D_dst_regnum[4]~575
--operation mode is normal
L1L235 = AMPP_FUNCTION(L1_D_iw[15], L1L201, L1L188);
--L1L236 is std_1s10:inst|cpu:the_cpu|D_dst_regnum[4]~576
--operation mode is normal
L1L236 = AMPP_FUNCTION(L1_D_iw[26], L1_D_iw[21], L1_D_ctrl_b_not_src, L1L235);
--L1L233 is std_1s10:inst|cpu:the_cpu|D_dst_regnum[2]~577
--operation mode is normal
L1L233 = AMPP_FUNCTION(L1_D_iw[24], L1_D_iw[19], L1L197, L1L810);
--L1L230 is std_1s10:inst|cpu:the_cpu|D_dst_regnum[0]~578
--operation mode is normal
L1L230 = AMPP_FUNCTION(L1_D_iw[22], L1_D_iw[17], L1L197, L1L810);
--L1L234 is std_1s10:inst|cpu:the_cpu|D_dst_regnum[3]~579
--operation mode is normal
L1L234 = AMPP_FUNCTION(L1_D_iw[25], L1_D_iw[20], L1L197, L1L810);
--L1L829 is std_1s10:inst|cpu:the_cpu|Equal171~117
--operation mode is normal
L1L829 = AMPP_FUNCTION(L1L235, L1L233, L1L230, L1L234);
--QC1_mac_mult1 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1
--DSP Block Multiplier Base Width: 18-bits
QC1_mac_mult1 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L2 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT1
QC1L2 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L3 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT2
QC1L3 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L4 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT3
QC1L4 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L5 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT4
QC1L5 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L6 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT5
QC1L6 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L7 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT6
QC1L7 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L8 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT7
QC1L8 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L9 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT8
QC1L9 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L10 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT9
QC1L10 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L11 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT10
QC1L11 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L12 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT11
QC1L12 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L13 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT12
QC1L13 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L14 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT13
QC1L14 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L15 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT14
QC1L15 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L16 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT15
QC1L16 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L17 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT16
QC1L17 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L18 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT17
QC1L18 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L19 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT18
QC1L19 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L20 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT19
QC1L20 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L21 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT20
QC1L21 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L22 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT21
QC1L22 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L23 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT22
QC1L23 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L24 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT23
QC1L24 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L25 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT24
QC1L25 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L26 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT25
QC1L26 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L27 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT26
QC1L27 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L28 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT27
QC1L28 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L29 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT28
QC1L29 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L30 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT29
QC1L30 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L31 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT30
QC1L31 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L32 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT31
QC1L32 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L33 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT32
QC1L33 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L34 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT33
QC1L34 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L35 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT34
QC1L35 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L36 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT35
QC1L36 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1_mac_mult2 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2
--DSP Block Multiplier Base Width: 18-bits
QC1_mac_mult2 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L110 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT1
QC1L110 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L111 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT2
QC1L111 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L112 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT3
QC1L112 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L113 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT4
QC1L113 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L114 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT5
QC1L114 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L115 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT6
QC1L115 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L116 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT7
QC1L116 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L117 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT8
QC1L117 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L118 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT9
QC1L118 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L119 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT10
QC1L119 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L120 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT11
QC1L120 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L121 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT12
QC1L121 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L122 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT13
QC1L122 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L123 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT14
QC1L123 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L124 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT15
QC1L124 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L125 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT16
QC1L125 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L126 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT17
QC1L126 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L127 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT18
QC1L127 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L128 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT19
QC1L128 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L129 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT20
QC1L129 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L130 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT21
QC1L130 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L131 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT22
QC1L131 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L132 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT23
QC1L132 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L133 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT24
QC1L133 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L134 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT25
QC1L134 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L135 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT26
QC1L135 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L136 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT27
QC1L136 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L137 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT28
QC1L137 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L138 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT29
QC1L138 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L139 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT30
QC1L139 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L140 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT31
QC1L140 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L141 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT32
QC1L141 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L142 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT33
QC1L142 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L143 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT34
QC1L143 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L144 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT35
QC1L144 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1_mac_mult3 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3
--DSP Block Multiplier Base Width: 18-bits
QC1_mac_mult3 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L218 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT1
QC1L218 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L219 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT2
QC1L219 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L220 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT3
QC1L220 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L221 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT4
QC1L221 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L222 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT5
QC1L222 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L223 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT6
QC1L223 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L224 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT7
QC1L224 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L225 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT8
QC1L225 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L226 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT9
QC1L226 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L227 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT10
QC1L227 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L228 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT11
QC1L228 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L229 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT12
QC1L229 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L230 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT13
QC1L230 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L231 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT14
QC1L231 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L232 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT15
QC1L232 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L233 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT16
QC1L233 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L234 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT17
QC1L234 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L235 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT18
QC1L235 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L236 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT19
QC1L236 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L237 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT20
QC1L237 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L238 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT21
QC1L238 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L239 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT22
QC1L239 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L240 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT23
QC1L240 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L241 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT24
QC1L241 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L242 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT25
QC1L242 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L243 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT26
QC1L243 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L244 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT27
QC1L244 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L245 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT28
QC1L245 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L246 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT29
QC1L246 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L247 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT30
QC1L247 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L248 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT31
QC1L248 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L249 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT32
QC1L249 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L250 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT33
QC1L250 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L251 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT34
QC1L251 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1L252 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT35
QC1L252 = AMPP_FUNCTION(GND, GND, L1L599, L1L600, L1L601, L1L602, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, QC1_w7w[32], VCC, VCC, VCC, L1L716, L1L717, L1L718, L1L719, L1L720, L1L721, L1L722, L1L723, L1L724, L1L725, L1L726, L1L727, L1L728, L1L729, L1L730, DE1__clk0, E1_data_out, GND);
--QC1_mac_mult4 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4
--DSP Block Multiplier Base Width: 18-bits
QC1_mac_mult4 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L326 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT1
QC1L326 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L327 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT2
QC1L327 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L328 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT3
QC1L328 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L329 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT4
QC1L329 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L330 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT5
QC1L330 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L331 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT6
QC1L331 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L332 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT7
QC1L332 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L333 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT8
QC1L333 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L334 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT9
QC1L334 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L335 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT10
QC1L335 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L336 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT11
QC1L336 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L337 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT12
QC1L337 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L338 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT13
QC1L338 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L339 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT14
QC1L339 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L340 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT15
QC1L340 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L341 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT16
QC1L341 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L342 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT17
QC1L342 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L343 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT18
QC1L343 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L344 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT19
QC1L344 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L345 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT20
QC1L345 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L346 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT21
QC1L346 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L347 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT22
QC1L347 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L348 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT23
QC1L348 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L349 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT24
QC1L349 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L350 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT25
QC1L350 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L351 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT26
QC1L351 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L352 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT27
QC1L352 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L353 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT28
QC1L353 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L354 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT29
QC1L354 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L355 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT30
QC1L355 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L356 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT31
QC1L356 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L357 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT32
QC1L357 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L358 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT33
QC1L358 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L359 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT34
QC1L359 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L360 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT35
QC1L360 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L584, L1L585, L1L586, L1L587, L1L588, L1L589, L1L590, L1L591, L1L592, L1L593, L1L594, L1L595, L1L596, L1L597, L1L598, L1L731, L1L732, L1L733, L1L734, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L745, L1L746, L1L747, L1L748, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--L1_E_ctrl_mulx is std_1s10:inst|cpu:the_cpu|E_ctrl_mulx
--operation mode is normal
L1_E_ctrl_mulx = AMPP_FUNCTION(DE1__clk0, L1_D_iw[12], L1L811, L1L808, L1L223, E1_data_out, L1_W_stall);
--L1_E_ctrl_shift_right is std_1s10:inst|cpu:the_cpu|E_ctrl_shift_right
--operation mode is normal
L1_E_ctrl_shift_right = AMPP_FUNCTION(DE1__clk0, L1_D_iw[12], L1L811, L1L808, L1L225, E1_data_out, L1_W_stall);
--L1L830 is std_1s10:inst|cpu:the_cpu|Equal230~89
--operation mode is normal
L1L830 = AMPP_FUNCTION(L1L652, L1L651, L1L650);
--L1_E_ctrl_rot is std_1s10:inst|cpu:the_cpu|E_ctrl_rot
--operation mode is normal
L1_E_ctrl_rot = AMPP_FUNCTION(DE1__clk0, L1L224, L1_D_iw[15], E1_data_out, L1_W_stall);
--L1L221 is std_1s10:inst|cpu:the_cpu|D_ctrl_mul_shift_rot~227
--operation mode is normal
L1L221 = AMPP_FUNCTION(L1_D_iw[5], L1L813, L1_D_iw[4]);
--F1_readdata[2] is std_1s10:inst|button_pio:the_button_pio|readdata[2]
--operation mode is normal
F1_readdata[2]_lut_out = L1_M_alu_result[3] & F1L26 # !L1_M_alu_result[3] & (in_port_to_the_button_pio[2] & !L1_M_alu_result[2]);
F1_readdata[2] = DFFEAS(F1_readdata[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L37 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4830
--operation mode is normal
M1L37 = L1_M_alu_result[7] & A1L141 # !L1_M_alu_result[7] & (F1_readdata[2]) # !G1L1;
--M1_registered_cpu_data_master_readdata[2] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[2]
--operation mode is normal
M1_registered_cpu_data_master_readdata[2]_lut_out = M1L298 & M1L270 & (FB1_za_data[2] # !GB1L18);
M1_registered_cpu_data_master_readdata[2] = DFFEAS(M1_registered_cpu_data_master_readdata[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L38 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4831
--operation mode is normal
M1L38 = M1L37 & (M1_registered_cpu_data_master_readdata[2] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--KB1_readdata[2] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[2]
--operation mode is normal
KB1_readdata[2]_lut_out = KB1L164 # KB1L165 # HE1L20 & !KB1_period_l_register[2];
KB1_readdata[2] = DFFEAS(KB1_readdata[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--LB1L3 is std_1s10:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~150
--operation mode is normal
LB1L3 = !L1_M_alu_result[6] & !L1_M_alu_result[5];
--NB1L3 is std_1s10:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~59
--operation mode is normal
NB1L3 = L1_M_alu_result[3] & (!L1_M_alu_result[4]);
--NB1L4 is std_1s10:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~60
--operation mode is normal
NB1L4 = L1_M_alu_result[5] & L1_internal_d_read & NB1L3 & !L1_M_alu_result[6];
--NB1_cpu_data_master_granted_sysid_control_slave is std_1s10:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave
--operation mode is normal
NB1_cpu_data_master_granted_sysid_control_slave = P1L7 & NB1L2 & NB1L4 & !L1_M_alu_result[7];
--M1L39 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4832
--operation mode is normal
M1L39 = !NB1_cpu_data_master_granted_sysid_control_slave & (KB1_readdata[2] # !LB1L3 # !LB1L2);
--BE1_q_a[0] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[0]
--RAM Block Operation Mode: Single Port
--Port A Depth: 16384, Port A Width: 8
--Port A Logical Depth: 16384, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_B_address_reg = DFFE(BE1_q_a[0]_PORT_B_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = AB1L34;
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = DE1__clk0;
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, BE1_q_a[0]_PORT_B_address_reg, BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[0] = BE1_q_a[0]_PORT_A_data_out[0];
--BE1_q_a[1] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[1]
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_B_address_reg = DFFE(BE1_q_a[0]_PORT_B_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = AB1L34;
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = DE1__clk0;
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, BE1_q_a[0]_PORT_B_address_reg, BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[1] = BE1_q_a[0]_PORT_A_data_out[1];
--BE1_q_a[2] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[2]
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_B_address_reg = DFFE(BE1_q_a[0]_PORT_B_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = AB1L34;
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = DE1__clk0;
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, BE1_q_a[0]_PORT_B_address_reg, BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[2] = BE1_q_a[0]_PORT_A_data_out[2];
--BE1_q_a[3] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[3]
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_B_address_reg = DFFE(BE1_q_a[0]_PORT_B_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = AB1L34;
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = DE1__clk0;
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, BE1_q_a[0]_PORT_B_address_reg, BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[3] = BE1_q_a[0]_PORT_A_data_out[3];
--BE1_q_a[4] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[4]
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_B_address_reg = DFFE(BE1_q_a[0]_PORT_B_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = AB1L34;
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = DE1__clk0;
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, BE1_q_a[0]_PORT_B_address_reg, BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[4] = BE1_q_a[0]_PORT_A_data_out[4];
--BE1_q_a[5] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[5]
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_B_address_reg = DFFE(BE1_q_a[0]_PORT_B_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = AB1L34;
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = DE1__clk0;
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, BE1_q_a[0]_PORT_B_address_reg, BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[5] = BE1_q_a[0]_PORT_A_data_out[5];
--BE1_q_a[6] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[6]
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_B_address_reg = DFFE(BE1_q_a[0]_PORT_B_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = AB1L34;
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = DE1__clk0;
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, BE1_q_a[0]_PORT_B_address_reg, BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[6] = BE1_q_a[0]_PORT_A_data_out[6];
--BE1_q_a[7] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[7]
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_B_address_reg = DFFE(BE1_q_a[0]_PORT_B_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = AB1L34;
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = DE1__clk0;
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, BE1_q_a[0]_PORT_B_address_reg, BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[7] = BE1_q_a[0]_PORT_A_data_out[7];
--Q1_internal_incoming_ext_ram_bus_data[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[2]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[2]_lut_out = A1L116;
Q1_internal_incoming_ext_ram_bus_data[2] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L40 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4833
--operation mode is normal
M1L40 = BE1_q_a[2] & (Q1_internal_incoming_ext_ram_bus_data[2] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[2] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[2] # !Q1_cpu_data_master_requests_lan91c111_s1);
--R1_readdata[2] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[2]
--operation mode is normal
R1_readdata[2]_lut_out = R1L163 # R1L164 # HE1L20 & !R1_period_l_register[2];
R1_readdata[2] = DFFEAS(R1_readdata[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--S1L2 is std_1s10:inst|high_res_timer_s1_arbitrator:the_high_res_timer_s1|cpu_data_master_requests_high_res_timer_s1~144
--operation mode is normal
S1L2 = L1_M_alu_result[6] & L1_M_alu_result[5];
--M1L41 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4834
--operation mode is normal
M1L41 = M1L39 & M1L40 & (R1_readdata[2] # !S1_cpu_data_master_requests_high_res_timer_s1);
--M1_dbs_8_reg_segment_0[2] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[2]
--operation mode is normal
M1_dbs_8_reg_segment_0[2]_lut_out = Q1_internal_incoming_ext_ram_bus_data[2];
M1_dbs_8_reg_segment_0[2] = DFFEAS(M1_dbs_8_reg_segment_0[2]_lut_out, DE1__clk0, E1_data_out, , M1L308, , , , );
--M1L42 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4835
--operation mode is normal
M1L42 = M1_registered_cpu_data_master_readdata[2] & (M1_dbs_8_reg_segment_0[2] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[2] & !GB1L18 & (M1_dbs_8_reg_segment_0[2] # !Q1_cpu_data_master_requests_ext_flash_s1);
--HE1_readdata[2] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[2]
--operation mode is normal
HE1_readdata[2]_lut_out = !L1_M_alu_result[4] & (L1_M_alu_result[2] & HE1L51 # !L1_M_alu_result[2] & (HE1L52));
HE1_readdata[2] = DFFEAS(HE1_readdata[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--EB1_cpu_data_master_requests_reconfig_request_pio_s1 is std_1s10:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1
--operation mode is normal
EB1_cpu_data_master_requests_reconfig_request_pio_s1 = L1_M_alu_result[7] & EB1L2;
--M1L43 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4836
--operation mode is normal
M1L43 = M1L45 & !EB1_cpu_data_master_requests_reconfig_request_pio_s1 & (HE1_readdata[2] # !QB1_cpu_data_master_granted_uart1_s1);
--M1L44 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4837
--operation mode is normal
M1L44 = M1L38 & M1L41 & M1L43;
--P1L15 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[0]~90
--operation mode is normal
P1L15 = P1L3 & L1_M_alu_result[2] # !P1L3 & (L1_ic_fill_ap_offset[0]);
--P1L23 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[8]~91
--operation mode is normal
P1L23 = P1L3 & L1_M_alu_result[10] # !P1L3 & (L1_ic_fill_line[5]);
--P1L16 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[1]~92
--operation mode is normal
P1L16 = P1L3 & L1_M_alu_result[3] # !P1L3 & (L1_ic_fill_ap_offset[1]);
--P1L22 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[7]~93
--operation mode is normal
P1L22 = P1L3 & L1_M_alu_result[9] # !P1L3 & (L1_ic_fill_line[4]);
--P1L20 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[5]~94
--operation mode is normal
P1L20 = P1L3 & L1_M_alu_result[7] # !P1L3 & (L1_ic_fill_line[2]);
--SC1L1 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~67
--operation mode is normal
SC1L1 = AMPP_FUNCTION(P1L23, P1L16, P1L22, P1L20);
--P1L18 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[3]~95
--operation mode is normal
P1L18 = P1L3 & L1_M_alu_result[5] # !P1L3 & (L1_ic_fill_line[0]);
--P1L19 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[4]~96
--operation mode is normal
P1L19 = P1L3 & L1_M_alu_result[6] # !P1L3 & (L1_ic_fill_line[1]);
--P1L21 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[6]~97
--operation mode is normal
P1L21 = P1L3 & L1_M_alu_result[8] # !P1L3 & (L1_ic_fill_line[3]);
--P1L17 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[2]~98
--operation mode is normal
P1L17 = P1L3 & L1_M_alu_result[4] # !P1L3 & (L1_ic_fill_ap_offset[2]);
--SC1L2 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~68
--operation mode is normal
SC1L2 = AMPP_FUNCTION(P1L18, P1L19, P1L21, P1L17);
--FC1L21 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[18]~1195
--operation mode is normal
FC1L21 = AMPP_FUNCTION(P1L15, P1L23, SC1L1, SC1L2);
--SC1L3 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~69
--operation mode is normal
SC1L3 = AMPP_FUNCTION(SC1L1, SC1L2, P1L15);
--FC1L5 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[2]~1196
--operation mode is normal
FC1L5 = AMPP_FUNCTION(FC1L21, SC1_internal_oci_ienable1[2], SC1L3);
--VC1_internal_monitor_go is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_go
--operation mode is normal
VC1_internal_monitor_go = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[23], SC1L13, VC1_internal_monitor_go, VC1L5, VCC);
--PD1_q_a[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 8, Port B Depth: 256, Port B Width: 8
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
PD1_q_a[0] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[1]
PD1_q_a[1] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[2]
PD1_q_a[2] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[3]
PD1_q_a[3] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[4]
PD1_q_a[4] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[5]
PD1_q_a[5] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[6] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[6]
PD1_q_a[6] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[7] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[7]
PD1_q_a[7] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[0]
PD1_q_b[0] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[1]
PD1_q_b[1] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[2]
PD1_q_b[2] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[3]
PD1_q_b[3] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[4]
PD1_q_b[4] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[5]
PD1_q_b[5] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[6] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[6]
PD1_q_b[6] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[7] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[7]
PD1_q_b[7] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--FC1L6 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[2]~1197
--operation mode is normal
FC1L6 = AMPP_FUNCTION(SC1L3, VC1_internal_monitor_go, PD1_q_a[2], P1L23);
--EB1L3 is std_1s10:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1~45
--operation mode is normal
--M1L97 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~4838
--operation mode is normal
M1L97 = !L1_M_alu_result[7] & !L1_M_alu_result[4] # !EB1L3;
--M1L145 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~4839
--operation mode is normal
M1L145 = M1L97 & (L1_M_alu_result[5] & !L1_M_alu_result[6] # !LB1L2);
--BE1_q_a[16] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[16]
--RAM Block Operation Mode: Single Port
--Port A Depth: 16384, Port A Width: 8
--Port A Logical Depth: 16384, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
BE1_q_a[16]_PORT_A_data_in = BUS(L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23]);
BE1_q_a[16]_PORT_A_data_in_reg = DFFE(BE1_q_a[16]_PORT_A_data_in, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_A_address_reg = DFFE(BE1_q_a[16]_PORT_A_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_B_address_reg = DFFE(BE1_q_a[16]_PORT_B_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_write_enable = Z1L1;
BE1_q_a[16]_PORT_A_write_enable_reg = DFFE(BE1_q_a[16]_PORT_A_write_enable, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_byte_mask = AB1L36;
BE1_q_a[16]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[16]_PORT_A_byte_mask, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_clock_0 = DE1__clk0;
BE1_q_a[16]_PORT_A_data_out = MEMORY(BE1_q_a[16]_PORT_A_data_in_reg, , BE1_q_a[16]_PORT_A_address_reg, BE1_q_a[16]_PORT_B_address_reg, BE1_q_a[16]_PORT_A_write_enable_reg, , BE1_q_a[16]_PORT_A_byte_mask_reg, , BE1_q_a[16]_clock_0, , , , , );
BE1_q_a[16] = BE1_q_a[16]_PORT_A_data_out[0];
--BE1_q_a[17] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[17]
BE1_q_a[16]_PORT_A_data_in = BUS(L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23]);
BE1_q_a[16]_PORT_A_data_in_reg = DFFE(BE1_q_a[16]_PORT_A_data_in, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_A_address_reg = DFFE(BE1_q_a[16]_PORT_A_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_B_address_reg = DFFE(BE1_q_a[16]_PORT_B_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_write_enable = Z1L1;
BE1_q_a[16]_PORT_A_write_enable_reg = DFFE(BE1_q_a[16]_PORT_A_write_enable, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_byte_mask = AB1L36;
BE1_q_a[16]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[16]_PORT_A_byte_mask, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_clock_0 = DE1__clk0;
BE1_q_a[16]_PORT_A_data_out = MEMORY(BE1_q_a[16]_PORT_A_data_in_reg, , BE1_q_a[16]_PORT_A_address_reg, BE1_q_a[16]_PORT_B_address_reg, BE1_q_a[16]_PORT_A_write_enable_reg, , BE1_q_a[16]_PORT_A_byte_mask_reg, , BE1_q_a[16]_clock_0, , , , , );
BE1_q_a[17] = BE1_q_a[16]_PORT_A_data_out[1];
--BE1_q_a[18] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[18]
BE1_q_a[16]_PORT_A_data_in = BUS(L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23]);
BE1_q_a[16]_PORT_A_data_in_reg = DFFE(BE1_q_a[16]_PORT_A_data_in, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_A_address_reg = DFFE(BE1_q_a[16]_PORT_A_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_B_address_reg = DFFE(BE1_q_a[16]_PORT_B_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_write_enable = Z1L1;
BE1_q_a[16]_PORT_A_write_enable_reg = DFFE(BE1_q_a[16]_PORT_A_write_enable, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_byte_mask = AB1L36;
BE1_q_a[16]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[16]_PORT_A_byte_mask, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_clock_0 = DE1__clk0;
BE1_q_a[16]_PORT_A_data_out = MEMORY(BE1_q_a[16]_PORT_A_data_in_reg, , BE1_q_a[16]_PORT_A_address_reg, BE1_q_a[16]_PORT_B_address_reg, BE1_q_a[16]_PORT_A_write_enable_reg, , BE1_q_a[16]_PORT_A_byte_mask_reg, , BE1_q_a[16]_clock_0, , , , , );
BE1_q_a[18] = BE1_q_a[16]_PORT_A_data_out[2];
--BE1_q_a[19] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[19]
BE1_q_a[16]_PORT_A_data_in = BUS(L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23]);
BE1_q_a[16]_PORT_A_data_in_reg = DFFE(BE1_q_a[16]_PORT_A_data_in, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_A_address_reg = DFFE(BE1_q_a[16]_PORT_A_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_B_address_reg = DFFE(BE1_q_a[16]_PORT_B_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_write_enable = Z1L1;
BE1_q_a[16]_PORT_A_write_enable_reg = DFFE(BE1_q_a[16]_PORT_A_write_enable, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_byte_mask = AB1L36;
BE1_q_a[16]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[16]_PORT_A_byte_mask, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_clock_0 = DE1__clk0;
BE1_q_a[16]_PORT_A_data_out = MEMORY(BE1_q_a[16]_PORT_A_data_in_reg, , BE1_q_a[16]_PORT_A_address_reg, BE1_q_a[16]_PORT_B_address_reg, BE1_q_a[16]_PORT_A_write_enable_reg, , BE1_q_a[16]_PORT_A_byte_mask_reg, , BE1_q_a[16]_clock_0, , , , , );
BE1_q_a[19] = BE1_q_a[16]_PORT_A_data_out[3];
--BE1_q_a[20] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[20]
BE1_q_a[16]_PORT_A_data_in = BUS(L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23]);
BE1_q_a[16]_PORT_A_data_in_reg = DFFE(BE1_q_a[16]_PORT_A_data_in, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_A_address_reg = DFFE(BE1_q_a[16]_PORT_A_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_B_address_reg = DFFE(BE1_q_a[16]_PORT_B_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_write_enable = Z1L1;
BE1_q_a[16]_PORT_A_write_enable_reg = DFFE(BE1_q_a[16]_PORT_A_write_enable, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_byte_mask = AB1L36;
BE1_q_a[16]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[16]_PORT_A_byte_mask, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_clock_0 = DE1__clk0;
BE1_q_a[16]_PORT_A_data_out = MEMORY(BE1_q_a[16]_PORT_A_data_in_reg, , BE1_q_a[16]_PORT_A_address_reg, BE1_q_a[16]_PORT_B_address_reg, BE1_q_a[16]_PORT_A_write_enable_reg, , BE1_q_a[16]_PORT_A_byte_mask_reg, , BE1_q_a[16]_clock_0, , , , , );
BE1_q_a[20] = BE1_q_a[16]_PORT_A_data_out[4];
--BE1_q_a[21] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[21]
BE1_q_a[16]_PORT_A_data_in = BUS(L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23]);
BE1_q_a[16]_PORT_A_data_in_reg = DFFE(BE1_q_a[16]_PORT_A_data_in, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_A_address_reg = DFFE(BE1_q_a[16]_PORT_A_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_B_address_reg = DFFE(BE1_q_a[16]_PORT_B_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_write_enable = Z1L1;
BE1_q_a[16]_PORT_A_write_enable_reg = DFFE(BE1_q_a[16]_PORT_A_write_enable, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_byte_mask = AB1L36;
BE1_q_a[16]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[16]_PORT_A_byte_mask, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_clock_0 = DE1__clk0;
BE1_q_a[16]_PORT_A_data_out = MEMORY(BE1_q_a[16]_PORT_A_data_in_reg, , BE1_q_a[16]_PORT_A_address_reg, BE1_q_a[16]_PORT_B_address_reg, BE1_q_a[16]_PORT_A_write_enable_reg, , BE1_q_a[16]_PORT_A_byte_mask_reg, , BE1_q_a[16]_clock_0, , , , , );
BE1_q_a[21] = BE1_q_a[16]_PORT_A_data_out[5];
--BE1_q_a[22] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[22]
BE1_q_a[16]_PORT_A_data_in = BUS(L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23]);
BE1_q_a[16]_PORT_A_data_in_reg = DFFE(BE1_q_a[16]_PORT_A_data_in, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_A_address_reg = DFFE(BE1_q_a[16]_PORT_A_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_B_address_reg = DFFE(BE1_q_a[16]_PORT_B_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_write_enable = Z1L1;
BE1_q_a[16]_PORT_A_write_enable_reg = DFFE(BE1_q_a[16]_PORT_A_write_enable, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_byte_mask = AB1L36;
BE1_q_a[16]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[16]_PORT_A_byte_mask, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_clock_0 = DE1__clk0;
BE1_q_a[16]_PORT_A_data_out = MEMORY(BE1_q_a[16]_PORT_A_data_in_reg, , BE1_q_a[16]_PORT_A_address_reg, BE1_q_a[16]_PORT_B_address_reg, BE1_q_a[16]_PORT_A_write_enable_reg, , BE1_q_a[16]_PORT_A_byte_mask_reg, , BE1_q_a[16]_clock_0, , , , , );
BE1_q_a[22] = BE1_q_a[16]_PORT_A_data_out[6];
--BE1_q_a[23] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[23]
BE1_q_a[16]_PORT_A_data_in = BUS(L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23]);
BE1_q_a[16]_PORT_A_data_in_reg = DFFE(BE1_q_a[16]_PORT_A_data_in, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_A_address_reg = DFFE(BE1_q_a[16]_PORT_A_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[16]_PORT_B_address_reg = DFFE(BE1_q_a[16]_PORT_B_address, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_write_enable = Z1L1;
BE1_q_a[16]_PORT_A_write_enable_reg = DFFE(BE1_q_a[16]_PORT_A_write_enable, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_PORT_A_byte_mask = AB1L36;
BE1_q_a[16]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[16]_PORT_A_byte_mask, BE1_q_a[16]_clock_0, , , );
BE1_q_a[16]_clock_0 = DE1__clk0;
BE1_q_a[16]_PORT_A_data_out = MEMORY(BE1_q_a[16]_PORT_A_data_in_reg, , BE1_q_a[16]_PORT_A_address_reg, BE1_q_a[16]_PORT_B_address_reg, BE1_q_a[16]_PORT_A_write_enable_reg, , BE1_q_a[16]_PORT_A_byte_mask_reg, , BE1_q_a[16]_clock_0, , , , , );
BE1_q_a[23] = BE1_q_a[16]_PORT_A_data_out[7];
--Q1_internal_incoming_ext_ram_bus_data[18] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[18]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[18]_lut_out = A1L100;
Q1_internal_incoming_ext_ram_bus_data[18] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[18]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L156 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~4840
--operation mode is normal
M1L156 = BE1_q_a[18] & (Q1_internal_incoming_ext_ram_bus_data[18] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[18] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[18] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[18] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[18]
--operation mode is normal
M1_registered_cpu_data_master_readdata[18]_lut_out = M1L284 & !J1_cpu_data_master_requests_clock_0_in & (T1L18 # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
M1_registered_cpu_data_master_readdata[18] = DFFEAS(M1_registered_cpu_data_master_readdata[18]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1_dbs_8_reg_segment_2[2] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[2]
--operation mode is normal
M1_dbs_8_reg_segment_2[2]_lut_out = Q1_internal_incoming_ext_ram_bus_data[2];
M1_dbs_8_reg_segment_2[2] = DFFEAS(M1_dbs_8_reg_segment_2[2]_lut_out, DE1__clk0, E1_data_out, , M1L310, , , , );
--M1L157 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~4841
--operation mode is normal
M1L157 = M1_registered_cpu_data_master_readdata[18] & (M1_dbs_8_reg_segment_2[2] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[18] & !GB1L18 & (M1_dbs_8_reg_segment_2[2] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L158 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~4842
--operation mode is normal
M1L158 = M1L156 & M1L157 & (Q1_internal_incoming_ext_ram_bus_data[18] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L159 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~4843
--operation mode is normal
M1L159 = M1L158 & (M1_registered_cpu_data_master_readdata[18] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L160 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~4844
--operation mode is normal
M1L160 = M1L145 & M1L159 & (!NB1_cpu_data_master_granted_sysid_control_slave);
--PD1_q_a[16] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[16]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 8, Port B Depth: 256, Port B Width: 8
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
PD1_q_a[16] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[17] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[17]
PD1_q_a[17] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[18] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[18]
PD1_q_a[18] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[19] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[19]
PD1_q_a[19] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[20] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[20]
PD1_q_a[20] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[21] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[21]
PD1_q_a[21] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[22] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[22]
PD1_q_a[22] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[23] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[23]
PD1_q_a[23] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[16] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[16]
PD1_q_b[16] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[17] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[17]
PD1_q_b[17] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[18] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[18]
PD1_q_b[18] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[19] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[19]
PD1_q_b[19] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[20] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[20]
PD1_q_b[20] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[21] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[21]
PD1_q_b[21] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[22] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[22]
PD1_q_b[22] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[23] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[23]
PD1_q_b[23] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L33, CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--FC1L22 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[18]~1198
--operation mode is normal
FC1L22 = AMPP_FUNCTION(PD1_q_a[18], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--NC1_q_b[2] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[2] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1346, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--KC1_q_b[12] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[12]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[12] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[12], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[11] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[11]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[11] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[11], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[16] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[16]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[16] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[16], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[14] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[14]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[14] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[14], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[13] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[13]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[13] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[13], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1L914 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[0]~48
--operation mode is arithmetic
L1L914 = AMPP_FUNCTION(L1_F_pc[0]);
--L1L915 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[0]~49
--operation mode is arithmetic
L1L915 = AMPP_FUNCTION(L1_F_pc[0]);
--KC1_q_b[21] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[21]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[21] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[21], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--L1L189 is std_1s10:inst|cpu:the_cpu|D_ctrl_alu_signed_cmp~318
--operation mode is normal
L1L189 = AMPP_FUNCTION(L1L815, L1L816);
--L1L191 is std_1s10:inst|cpu:the_cpu|D_ctrl_alu_subtract~408
--operation mode is normal
L1L191 = AMPP_FUNCTION(L1L189, L1L808, L1L194, L1_D_iw[4]);
--L1L225 is std_1s10:inst|cpu:the_cpu|D_ctrl_shift_right~48
--operation mode is normal
L1L225 = AMPP_FUNCTION(L1_D_iw[15], L1_D_iw[14], L1_D_iw[13]);
--L1L192 is std_1s10:inst|cpu:the_cpu|D_ctrl_alu_subtract~409
--operation mode is normal
L1L192 = AMPP_FUNCTION(L1L225, L1_D_iw[11], L1L193);
--HE1_irq is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|irq
--operation mode is normal
HE1_irq_lut_out = HE1L35 # HE1L36 # HE1_control_reg[7] & JE1_internal_rx_char_ready;
HE1_irq = DFFEAS(HE1_irq_lut_out, DE1__clk0, E1_data_out, , , , , , );
--SC1_internal_oci_ienable1[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[3]
--operation mode is normal
SC1_internal_oci_ienable1[3] = AMPP_FUNCTION(DE1__clk0, L1_M_st_data[3], E1_data_out, SC1L12);
--F1_readdata[3] is std_1s10:inst|button_pio:the_button_pio|readdata[3]
--operation mode is normal
F1_readdata[3]_lut_out = L1_M_alu_result[3] & F1L27 # !L1_M_alu_result[3] & (in_port_to_the_button_pio[3] & !L1_M_alu_result[2]);
F1_readdata[3] = DFFEAS(F1_readdata[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L46 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4845
--operation mode is normal
M1L46 = L1_M_alu_result[7] & A1L140 # !L1_M_alu_result[7] & (F1_readdata[3]) # !G1L1;
--M1_registered_cpu_data_master_readdata[3] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[3]
--operation mode is normal
M1_registered_cpu_data_master_readdata[3]_lut_out = M1L299 & M1L271 & (FB1_za_data[3] # !GB1L18);
M1_registered_cpu_data_master_readdata[3] = DFFEAS(M1_registered_cpu_data_master_readdata[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L47 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4846
--operation mode is normal
M1L47 = M1L46 & !EB1_cpu_data_master_requests_reconfig_request_pio_s1 & (M1_registered_cpu_data_master_readdata[3] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
--M1L48 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4847
--operation mode is normal
M1L48 = M1_registered_cpu_data_master_readdata[3] & (!NB1_cpu_data_master_granted_sysid_control_slave # !L1_M_alu_result[2]) # !M1_registered_cpu_data_master_readdata[3] & !J1_cpu_data_master_requests_clock_0_in & (!NB1_cpu_data_master_granted_sysid_control_slave # !L1_M_alu_result[2]);
--Q1_internal_incoming_ext_ram_bus_data[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[3]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[3]_lut_out = A1L115;
Q1_internal_incoming_ext_ram_bus_data[3] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L49 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4848
--operation mode is normal
M1L49 = BE1_q_a[3] & (Q1_internal_incoming_ext_ram_bus_data[3] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[3] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[3] # !Q1_cpu_data_master_requests_lan91c111_s1);
--KB1_readdata[3] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[3]
--operation mode is normal
KB1_readdata[3]_lut_out = KB1L166 # KB1L167 # HE1L20 & !KB1_period_l_register[3];
KB1_readdata[3] = DFFEAS(KB1_readdata[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L50 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4849
--operation mode is normal
M1L50 = M1L48 & M1L49 & (KB1_readdata[3] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--R1_readdata[3] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[3]
--operation mode is normal
R1_readdata[3]_lut_out = R1L165 # R1L166 # HE1L20 & !R1_period_l_register[3];
R1_readdata[3] = DFFEAS(R1_readdata[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1_dbs_8_reg_segment_0[3] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[3]
--operation mode is normal
M1_dbs_8_reg_segment_0[3]_lut_out = Q1_internal_incoming_ext_ram_bus_data[3];
M1_dbs_8_reg_segment_0[3] = DFFEAS(M1_dbs_8_reg_segment_0[3]_lut_out, DE1__clk0, E1_data_out, , M1L308, , , , );
--M1L51 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4850
--operation mode is normal
M1L51 = M1_registered_cpu_data_master_readdata[3] & (M1_dbs_8_reg_segment_0[3] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[3] & !GB1L18 & (M1_dbs_8_reg_segment_0[3] # !Q1_cpu_data_master_requests_ext_flash_s1);
--HE1_readdata[3] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[3]
--operation mode is normal
HE1_readdata[3]_lut_out = !L1_M_alu_result[4] & (L1_M_alu_result[2] & HE1L53 # !L1_M_alu_result[2] & (HE1L54));
HE1_readdata[3] = DFFEAS(HE1_readdata[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L52 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4851
--operation mode is normal
M1L52 = M1L226 & M1L54 & (HE1_readdata[3] # !QB1_cpu_data_master_granted_uart1_s1);
--M1L53 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4852
--operation mode is normal
M1L53 = M1L47 & M1L50 & M1L52;
--FC1L7 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[3]~1199
--operation mode is normal
FC1L7 = AMPP_FUNCTION(FC1L21, SC1L3, SC1_internal_oci_ienable1[3]);
--FC1L8 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[3]~1200
--operation mode is normal
FC1L8 = AMPP_FUNCTION(SC1_internal_oci_single_step_mode1, SC1L3, PD1_q_a[3], P1L23);
--Q1_internal_incoming_ext_ram_bus_data[19] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[19]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[19]_lut_out = A1L99;
Q1_internal_incoming_ext_ram_bus_data[19] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[19]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L161 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~4853
--operation mode is normal
M1L161 = BE1_q_a[19] & (Q1_internal_incoming_ext_ram_bus_data[19] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[19] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[19] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[19] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[19]
--operation mode is normal
M1_registered_cpu_data_master_readdata[19]_lut_out = M1L285 & !J1_cpu_data_master_requests_clock_0_in & (T1L21 # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
M1_registered_cpu_data_master_readdata[19] = DFFEAS(M1_registered_cpu_data_master_readdata[19]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1_dbs_8_reg_segment_2[3] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[3]
--operation mode is normal
M1_dbs_8_reg_segment_2[3]_lut_out = Q1_internal_incoming_ext_ram_bus_data[3];
M1_dbs_8_reg_segment_2[3] = DFFEAS(M1_dbs_8_reg_segment_2[3]_lut_out, DE1__clk0, E1_data_out, , M1L310, , , , );
--M1L162 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~4854
--operation mode is normal
M1L162 = M1_registered_cpu_data_master_readdata[19] & (M1_dbs_8_reg_segment_2[3] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[19] & !GB1L18 & (M1_dbs_8_reg_segment_2[3] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L163 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~4855
--operation mode is normal
M1L163 = M1L161 & M1L162 & (Q1_internal_incoming_ext_ram_bus_data[19] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L164 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~4856
--operation mode is normal
M1L164 = M1L163 & (M1_registered_cpu_data_master_readdata[19] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L165 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~4857
--operation mode is normal
M1L165 = M1L145 & M1L164 & (L1_M_alu_result[2] # !NB1_cpu_data_master_granted_sysid_control_slave);
--FC1L23 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[19]~1201
--operation mode is normal
FC1L23 = AMPP_FUNCTION(PD1_q_a[19], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--KC1_q_b[9] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[9]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[9] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[9], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--NC1_q_b[3] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[3] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1349, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L916 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[1]~50
--operation mode is arithmetic
L1L916 = AMPP_FUNCTION(L1_F_pc[1], L1L915);
--L1L917 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[1]~51
--operation mode is arithmetic
L1L917 = AMPP_FUNCTION(L1_F_pc[1], L1L915);
--L1L924 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[5]~52
--operation mode is arithmetic
L1L924 = AMPP_FUNCTION(L1_F_pc[5], L1L923);
--L1L925 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[5]~53
--operation mode is arithmetic
L1L925 = AMPP_FUNCTION(L1_F_pc[5], L1L923);
--M1L63 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4858
--operation mode is normal
M1L63 = L1_M_alu_result[7] $ !L1_M_alu_result[4] # !EB1L3;
--M1L80 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4859
--operation mode is normal
M1L80 = M1L63 & (L1_M_alu_result[2] # !NB1_cpu_data_master_granted_sysid_control_slave);
--M1_registered_cpu_data_master_readdata[7] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[7]
--operation mode is normal
M1_registered_cpu_data_master_readdata[7]_lut_out = M1L303 & M1L275 & (FB1_za_data[7] # !GB1L18);
M1_registered_cpu_data_master_readdata[7] = DFFEAS(M1_registered_cpu_data_master_readdata[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L81 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4860
--operation mode is normal
M1L81 = M1_registered_cpu_data_master_readdata[7] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--Q1_internal_incoming_ext_ram_bus_data[7] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[7]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[7]_lut_out = A1L111;
Q1_internal_incoming_ext_ram_bus_data[7] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L82 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4861
--operation mode is normal
M1L82 = BE1_q_a[7] & (Q1_internal_incoming_ext_ram_bus_data[7] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[7] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[7] # !Q1_cpu_data_master_requests_lan91c111_s1);
--HE1_readdata[7] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[7]
--operation mode is normal
HE1_readdata[7]_lut_out = !L1_M_alu_result[4] & (L1_M_alu_result[2] & HE1L61 # !L1_M_alu_result[2] & (HE1L62));
HE1_readdata[7] = DFFEAS(HE1_readdata[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L83 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4862
--operation mode is normal
M1L83 = M1L81 & M1L82 & (HE1_readdata[7] # !QB1_cpu_data_master_granted_uart1_s1);
--M1_dbs_8_reg_segment_0[7] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[7]
--operation mode is normal
M1_dbs_8_reg_segment_0[7]_lut_out = Q1_internal_incoming_ext_ram_bus_data[7];
M1_dbs_8_reg_segment_0[7] = DFFEAS(M1_dbs_8_reg_segment_0[7]_lut_out, DE1__clk0, E1_data_out, , M1L308, , , , );
--M1L84 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4863
--operation mode is normal
M1L84 = M1_registered_cpu_data_master_readdata[7] & (M1_dbs_8_reg_segment_0[7] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[7] & !GB1L18 & (M1_dbs_8_reg_segment_0[7] # !Q1_cpu_data_master_requests_ext_flash_s1);
--R1_readdata[7] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[7]
--operation mode is normal
R1_readdata[7]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (R1L174) # !L1_M_alu_result[3] & L1_M_alu_result[4] & R1L173;
R1_readdata[7] = DFFEAS(R1_readdata[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L85 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4864
--operation mode is normal
M1L85 = M1L88 & (R1_readdata[7] # !S1L2 # !LB1L2);
--KB1_readdata[7] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[7]
--operation mode is normal
KB1_readdata[7]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (KB1L175) # !L1_M_alu_result[3] & L1_M_alu_result[4] & KB1L174;
KB1_readdata[7] = DFFEAS(KB1_readdata[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L86 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4865
--operation mode is normal
M1L86 = KB1_readdata[7] & (A1L136 # !W1L12) # !KB1_readdata[7] & !LB1_cpu_data_master_requests_sys_clk_timer_s1 & (A1L136 # !W1L12);
--M1L87 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4866
--operation mode is normal
M1L87 = M1L80 & M1L83 & M1L85 & M1L86;
--FC1L10 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[7]~1202
--operation mode is normal
FC1L10 = AMPP_FUNCTION(PD1_q_a[7], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--Q1_internal_incoming_ext_ram_bus_data[23] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[23]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[23]_lut_out = A1L95;
Q1_internal_incoming_ext_ram_bus_data[23] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[23]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L181 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~4867
--operation mode is normal
M1L181 = BE1_q_a[23] & (Q1_internal_incoming_ext_ram_bus_data[23] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[23] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[23] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[23] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[23]
--operation mode is normal
M1_registered_cpu_data_master_readdata[23]_lut_out = M1L289 & !J1_cpu_data_master_requests_clock_0_in & (FB1_za_data[23] # !GB1L18);
M1_registered_cpu_data_master_readdata[23] = DFFEAS(M1_registered_cpu_data_master_readdata[23]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1_dbs_8_reg_segment_2[7] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[7]
--operation mode is normal
M1_dbs_8_reg_segment_2[7]_lut_out = Q1_internal_incoming_ext_ram_bus_data[7];
M1_dbs_8_reg_segment_2[7] = DFFEAS(M1_dbs_8_reg_segment_2[7]_lut_out, DE1__clk0, E1_data_out, , M1L310, , , , );
--M1L182 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~4868
--operation mode is normal
M1L182 = M1_registered_cpu_data_master_readdata[23] & (M1_dbs_8_reg_segment_2[7] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[23] & !GB1L18 & (M1_dbs_8_reg_segment_2[7] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L183 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~4869
--operation mode is normal
M1L183 = M1L181 & M1L182 & (Q1_internal_incoming_ext_ram_bus_data[23] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L184 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~4870
--operation mode is normal
M1L184 = M1L183 & (M1_registered_cpu_data_master_readdata[23] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L185 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~4871
--operation mode is normal
M1L185 = M1L145 & M1L184 & (!NB1_cpu_data_master_granted_sysid_control_slave);
--FC1L27 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[23]~1203
--operation mode is normal
FC1L27 = AMPP_FUNCTION(PD1_q_a[23], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--NC1_q_b[7] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[7] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1361, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L862 is std_1s10:inst|cpu:the_cpu|F_ic_hit~125
--operation mode is normal
L1L862 = AMPP_FUNCTION(L1L858, L1L859);
--L1L210 is std_1s10:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~729
--operation mode is normal
L1L210 = AMPP_FUNCTION(L1L214, L1L228, L1L824);
--L1L211 is std_1s10:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~730
--operation mode is normal
L1L211 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[11], L1_D_iw[14], L1_D_iw[13]);
--L1L212 is std_1s10:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~731
--operation mode is normal
L1L212 = AMPP_FUNCTION(L1L211, L1_D_iw[15], L1L215, L1L208);
--L1L213 is std_1s10:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~732
--operation mode is normal
L1L213 = AMPP_FUNCTION(L1L825, L1_D_iw[11], L1_D_iw[12], L1L212);
--GC1L3 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~561
--operation mode is arithmetic
GC1L3 = AMPP_FUNCTION(L1L615, L1L681, GC1L5);
--HC1_result[31] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[31]
--operation mode is arithmetic
HC1_result[31] = AMPP_FUNCTION(L1L415, L1L414, HC1L63, L1_E_ctrl_alu_subtract);
--HC1L65 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[31]~COUT
--operation mode is arithmetic
HC1L65 = AMPP_FUNCTION(L1L415, L1L414, HC1L63, L1_E_ctrl_alu_subtract);
--DD1_internal_jdo1[19] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[19]
--operation mode is normal
DD1_internal_jdo1[19] = AMPP_FUNCTION(!A1L9, DD1_sr[19], VCC, DD1L144);
--DD1_internal_jdo1[18] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[18]
--operation mode is normal
DD1_internal_jdo1[18] = AMPP_FUNCTION(!A1L9, DD1_sr[18], VCC, DD1L144);
--DD1_sr[21] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[21]
--operation mode is normal
DD1_sr[21] = AMPP_FUNCTION(!A1L6, DD1L8, DD1_sr[22], DD1L9, DD1L10, !C1_CLR_SIGNAL, DD1L12);
--C1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode
--operation mode is normal
C1_jtag_debug_mode = AMPP_FUNCTION(!A1L6, C1L26, C1_jtag_debug_mode, C1L27, RE1_state[15], RE1_state[0]);
--ME2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
--operation mode is normal
ME2_Q[0] = AMPP_FUNCTION(!A1L6, SE1_dffe1a[1], ME2_Q[0], ME9_Q[0], C1L1, !C1_CLR_SIGNAL);
--DD1L144 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process3~12
--operation mode is normal
DD1L144 = AMPP_FUNCTION(ME8_Q[0], C1_jtag_debug_mode, C1_jtag_debug_mode_usr1, ME2_Q[0]);
--DD1_sr[20] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[20]
--operation mode is normal
DD1_sr[20] = AMPP_FUNCTION(!A1L6, DD1L14, DD1_sr[21], DD1L9, DD1L15, !C1_CLR_SIGNAL, DD1L12);
--RE1_state[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1]
--operation mode is normal
RE1_state[1] = AMPP_FUNCTION(!A1L6, RE1_state[0], RE1_state[8], RE1_state[1], RE1_state[15], VCC, !A1L8);
--ME1_Q[0] is sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0]
--operation mode is normal
ME1_Q[0] = AMPP_FUNCTION(!A1L6, ME1_Q[0], SE1_dffe1a[7], C1L2, ME2_Q[0], C1_jtag_debug_mode_usr1);
--DD1_sr[34] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[34]
--operation mode is normal
DD1_sr[34] = AMPP_FUNCTION(!A1L6, DD1_sr[35], DD1L16, DD1L141, DD1L17, !C1_CLR_SIGNAL, DD1L12);
--DD1_dr_update2 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|dr_update2
--operation mode is normal
DD1_dr_update2 = AMPP_FUNCTION(DE1__clk0, DD1_dr_update1, VCC);
--DD1_dr_update1 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|dr_update1
--operation mode is normal
DD1_dr_update1 = AMPP_FUNCTION(DE1__clk0, DD1_st_updatedr, VCC);
--DD1_sr[35] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[35]
--operation mode is normal
DD1_sr[35] = AMPP_FUNCTION(!A1L6, DD1L18, DD1L133, DD1L19, DD1_ir[1], !C1_CLR_SIGNAL, !DD1_ir[0], DD1L12);
--ME5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0]
--operation mode is normal
ME5_Q[0] = AMPP_FUNCTION(!A1L6, ME7_Q[0], ME3_Q[0], ME2_Q[0], !C1_CLR_SIGNAL, C1L20);
--DD1_st_updateir is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updateir
--operation mode is normal
DD1_st_updateir = AMPP_FUNCTION(!A1L6, DD1L145, VCC, !A1L9);
--DD1L116 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0]~0
--operation mode is normal
DD1L116 = AMPP_FUNCTION(DD1_st_updateir, C1_CLR_SIGNAL);
--ME5_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]
--operation mode is normal
ME5_Q[1] = AMPP_FUNCTION(!A1L6, ME7_Q[1], ME3_Q[1], ME2_Q[0], !C1_CLR_SIGNAL, C1L20);
--L1_E_ctrl_break is std_1s10:inst|cpu:the_cpu|E_ctrl_break
--operation mode is normal
L1_E_ctrl_break = AMPP_FUNCTION(DE1__clk0, L1_D_iw[15], L1L201, E1_data_out, L1_W_stall);
--CD1L61 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|module_input6~22
--operation mode is normal
CD1L61 = AMPP_FUNCTION(L1_internal_d_write, L1_hbreak_enabled, P1L3);
--SC1L13 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|take_action_ocireg~11
--operation mode is normal
SC1L13 = AMPP_FUNCTION(SC1L1, SC1L2, CD1L61, P1L15);
--R1_control_register[0] is std_1s10:inst|high_res_timer:the_high_res_timer|control_register[0]
--operation mode is normal
R1_control_register[0]_lut_out = L1_M_st_data[0];
R1_control_register[0] = DFFEAS(R1_control_register[0]_lut_out, DE1__clk0, E1_data_out, , R1_control_wr_strobe, , , , );
--R1_timeout_occurred is std_1s10:inst|high_res_timer:the_high_res_timer|timeout_occurred
--operation mode is normal
R1_timeout_occurred_lut_out = R1L210 & (!HE1L21 # !S1_cpu_data_master_requests_high_res_timer_s1 # !KB1L7);
R1_timeout_occurred = DFFEAS(R1_timeout_occurred_lut_out, DE1__clk0, E1_data_out, , , , , , );
--SC1_internal_oci_ienable1[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[4]
--operation mode is normal
SC1_internal_oci_ienable1[4] = AMPP_FUNCTION(DE1__clk0, L1_M_st_data[4], E1_data_out, SC1L12);
--M1_registered_cpu_data_master_readdata[4] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[4]
--operation mode is normal
M1_registered_cpu_data_master_readdata[4]_lut_out = M1L300 & M1L272 & (FB1_za_data[4] # !GB1L18);
M1_registered_cpu_data_master_readdata[4] = DFFEAS(M1_registered_cpu_data_master_readdata[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L55 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4872
--operation mode is normal
M1L55 = M1_registered_cpu_data_master_readdata[4] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--Q1_internal_incoming_ext_ram_bus_data[4] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[4]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[4]_lut_out = A1L114;
Q1_internal_incoming_ext_ram_bus_data[4] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L56 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4873
--operation mode is normal
M1L56 = BE1_q_a[4] & (Q1_internal_incoming_ext_ram_bus_data[4] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[4] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[4] # !Q1_cpu_data_master_requests_lan91c111_s1);
--HE1_readdata[4] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[4]
--operation mode is normal
HE1_readdata[4]_lut_out = !L1_M_alu_result[4] & (L1_M_alu_result[2] & HE1L55 # !L1_M_alu_result[2] & (HE1L56));
HE1_readdata[4] = DFFEAS(HE1_readdata[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L57 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4874
--operation mode is normal
M1L57 = M1L55 & M1L56 & (HE1_readdata[4] # !QB1_cpu_data_master_granted_uart1_s1);
--M1_dbs_8_reg_segment_0[4] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[4]
--operation mode is normal
M1_dbs_8_reg_segment_0[4]_lut_out = Q1_internal_incoming_ext_ram_bus_data[4];
M1_dbs_8_reg_segment_0[4] = DFFEAS(M1_dbs_8_reg_segment_0[4]_lut_out, DE1__clk0, E1_data_out, , M1L308, , , , );
--M1L58 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4875
--operation mode is normal
M1L58 = M1_registered_cpu_data_master_readdata[4] & (M1_dbs_8_reg_segment_0[4] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[4] & !GB1L18 & (M1_dbs_8_reg_segment_0[4] # !Q1_cpu_data_master_requests_ext_flash_s1);
--R1_readdata[4] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[4]
--operation mode is normal
R1_readdata[4]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (R1L168) # !L1_M_alu_result[3] & L1_M_alu_result[4] & R1L167;
R1_readdata[4] = DFFEAS(R1_readdata[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L59 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4876
--operation mode is normal
M1L59 = M1L62 & (R1_readdata[4] # !S1L2 # !LB1L2);
--KB1_readdata[4] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[4]
--operation mode is normal
KB1_readdata[4]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (KB1L169) # !L1_M_alu_result[3] & L1_M_alu_result[4] & KB1L168;
KB1_readdata[4] = DFFEAS(KB1_readdata[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L60 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4877
--operation mode is normal
M1L60 = KB1_readdata[4] & (A1L139 # !W1L12) # !KB1_readdata[4] & !LB1_cpu_data_master_requests_sys_clk_timer_s1 & (A1L139 # !W1L12);
--M1L61 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4878
--operation mode is normal
M1L61 = M1L80 & M1L57 & M1L59 & M1L60;
--N1L105 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~1862
--operation mode is normal
N1L105 = P1L23 & (SC1_internal_oci_ienable1[4] # !FC1L21) # !P1L23 & !PD1_q_a[4] & (SC1_internal_oci_ienable1[4] # !FC1L21);
--Q1_internal_incoming_ext_ram_bus_data[20] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[20]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[20]_lut_out = A1L98;
Q1_internal_incoming_ext_ram_bus_data[20] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[20]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L166 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~4879
--operation mode is normal
M1L166 = BE1_q_a[20] & (Q1_internal_incoming_ext_ram_bus_data[20] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[20] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[20] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[20] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[20]
--operation mode is normal
M1_registered_cpu_data_master_readdata[20]_lut_out = M1L286 & !J1_cpu_data_master_requests_clock_0_in & (T1L25 # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
M1_registered_cpu_data_master_readdata[20] = DFFEAS(M1_registered_cpu_data_master_readdata[20]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1_dbs_8_reg_segment_2[4] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[4]
--operation mode is normal
M1_dbs_8_reg_segment_2[4]_lut_out = Q1_internal_incoming_ext_ram_bus_data[4];
M1_dbs_8_reg_segment_2[4] = DFFEAS(M1_dbs_8_reg_segment_2[4]_lut_out, DE1__clk0, E1_data_out, , M1L310, , , , );
--M1L167 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~4880
--operation mode is normal
M1L167 = M1_registered_cpu_data_master_readdata[20] & (M1_dbs_8_reg_segment_2[4] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[20] & !GB1L18 & (M1_dbs_8_reg_segment_2[4] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L168 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~4881
--operation mode is normal
M1L168 = M1L166 & M1L167 & (Q1_internal_incoming_ext_ram_bus_data[20] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L169 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~4882
--operation mode is normal
M1L169 = M1L168 & (M1_registered_cpu_data_master_readdata[20] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L170 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~4883
--operation mode is normal
M1L170 = M1L145 & M1L169 & (!NB1_cpu_data_master_granted_sysid_control_slave);
--FC1L24 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[20]~1204
--operation mode is normal
FC1L24 = AMPP_FUNCTION(PD1_q_a[20], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--KC1_q_b[10] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[10]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[10] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[10], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--NC1_q_b[4] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[4] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1352, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L918 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[2]~54
--operation mode is arithmetic
L1L918 = AMPP_FUNCTION(L1_F_pc[2], L1L917);
--L1L919 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[2]~55
--operation mode is arithmetic
L1L919 = AMPP_FUNCTION(L1_F_pc[2], L1L917);
--L1L954 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[20]~56
--operation mode is arithmetic
L1L954 = AMPP_FUNCTION(L1_F_pc[20], L1L953);
--L1L955 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[20]~57
--operation mode is arithmetic
L1L955 = AMPP_FUNCTION(L1_F_pc[20], L1L953);
--M1_registered_cpu_data_master_readdata[22] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[22]
--operation mode is normal
M1_registered_cpu_data_master_readdata[22]_lut_out = M1L288 & !J1_cpu_data_master_requests_clock_0_in & (T1L28 # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
M1_registered_cpu_data_master_readdata[22] = DFFEAS(M1_registered_cpu_data_master_readdata[22]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L176 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~4884
--operation mode is normal
M1L176 = M1_registered_cpu_data_master_readdata[22] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--Q1_internal_incoming_ext_ram_bus_data[22] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[22]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[22]_lut_out = A1L96;
Q1_internal_incoming_ext_ram_bus_data[22] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[22]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L177 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~4885
--operation mode is normal
M1L177 = BE1_q_a[22] & (Q1_internal_incoming_ext_ram_bus_data[22] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[22] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[22] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_dbs_8_reg_segment_2[6] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[6]
--operation mode is normal
M1_dbs_8_reg_segment_2[6]_lut_out = Q1_internal_incoming_ext_ram_bus_data[6];
M1_dbs_8_reg_segment_2[6] = DFFEAS(M1_dbs_8_reg_segment_2[6]_lut_out, DE1__clk0, E1_data_out, , M1L310, , , , );
--M1L178 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~4886
--operation mode is normal
M1L178 = M1_registered_cpu_data_master_readdata[22] & (M1_dbs_8_reg_segment_2[6] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[22] & !GB1L18 & (M1_dbs_8_reg_segment_2[6] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L179 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~4887
--operation mode is normal
M1L179 = M1L145 & M1L176 & M1L177 & M1L180;
--FC1L26 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[22]~1205
--operation mode is normal
FC1L26 = AMPP_FUNCTION(PD1_q_a[22], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--M1_registered_cpu_data_master_readdata[15] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[15]
--operation mode is normal
M1_registered_cpu_data_master_readdata[15]_lut_out = !M1L283 & (T1_rvalid # !U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[15] = DFFEAS(M1_registered_cpu_data_master_readdata[15]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L139 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~4888
--operation mode is normal
M1L139 = M1_registered_cpu_data_master_readdata[15] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--BE1_q_a[8] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[8]
--RAM Block Operation Mode: Single Port
--Port A Depth: 16384, Port A Width: 8
--Port A Logical Depth: 16384, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
BE1_q_a[8]_PORT_A_data_in = BUS(L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15]);
BE1_q_a[8]_PORT_A_data_in_reg = DFFE(BE1_q_a[8]_PORT_A_data_in, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_A_address_reg = DFFE(BE1_q_a[8]_PORT_A_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_B_address_reg = DFFE(BE1_q_a[8]_PORT_B_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_write_enable = Z1L1;
BE1_q_a[8]_PORT_A_write_enable_reg = DFFE(BE1_q_a[8]_PORT_A_write_enable, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_byte_mask = AB1L35;
BE1_q_a[8]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[8]_PORT_A_byte_mask, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_clock_0 = DE1__clk0;
BE1_q_a[8]_PORT_A_data_out = MEMORY(BE1_q_a[8]_PORT_A_data_in_reg, , BE1_q_a[8]_PORT_A_address_reg, BE1_q_a[8]_PORT_B_address_reg, BE1_q_a[8]_PORT_A_write_enable_reg, , BE1_q_a[8]_PORT_A_byte_mask_reg, , BE1_q_a[8]_clock_0, , , , , );
BE1_q_a[8] = BE1_q_a[8]_PORT_A_data_out[0];
--BE1_q_a[9] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[9]
BE1_q_a[8]_PORT_A_data_in = BUS(L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15]);
BE1_q_a[8]_PORT_A_data_in_reg = DFFE(BE1_q_a[8]_PORT_A_data_in, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_A_address_reg = DFFE(BE1_q_a[8]_PORT_A_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_B_address_reg = DFFE(BE1_q_a[8]_PORT_B_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_write_enable = Z1L1;
BE1_q_a[8]_PORT_A_write_enable_reg = DFFE(BE1_q_a[8]_PORT_A_write_enable, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_byte_mask = AB1L35;
BE1_q_a[8]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[8]_PORT_A_byte_mask, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_clock_0 = DE1__clk0;
BE1_q_a[8]_PORT_A_data_out = MEMORY(BE1_q_a[8]_PORT_A_data_in_reg, , BE1_q_a[8]_PORT_A_address_reg, BE1_q_a[8]_PORT_B_address_reg, BE1_q_a[8]_PORT_A_write_enable_reg, , BE1_q_a[8]_PORT_A_byte_mask_reg, , BE1_q_a[8]_clock_0, , , , , );
BE1_q_a[9] = BE1_q_a[8]_PORT_A_data_out[1];
--BE1_q_a[10] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[10]
BE1_q_a[8]_PORT_A_data_in = BUS(L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15]);
BE1_q_a[8]_PORT_A_data_in_reg = DFFE(BE1_q_a[8]_PORT_A_data_in, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_A_address_reg = DFFE(BE1_q_a[8]_PORT_A_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_B_address_reg = DFFE(BE1_q_a[8]_PORT_B_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_write_enable = Z1L1;
BE1_q_a[8]_PORT_A_write_enable_reg = DFFE(BE1_q_a[8]_PORT_A_write_enable, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_byte_mask = AB1L35;
BE1_q_a[8]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[8]_PORT_A_byte_mask, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_clock_0 = DE1__clk0;
BE1_q_a[8]_PORT_A_data_out = MEMORY(BE1_q_a[8]_PORT_A_data_in_reg, , BE1_q_a[8]_PORT_A_address_reg, BE1_q_a[8]_PORT_B_address_reg, BE1_q_a[8]_PORT_A_write_enable_reg, , BE1_q_a[8]_PORT_A_byte_mask_reg, , BE1_q_a[8]_clock_0, , , , , );
BE1_q_a[10] = BE1_q_a[8]_PORT_A_data_out[2];
--BE1_q_a[11] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[11]
BE1_q_a[8]_PORT_A_data_in = BUS(L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15]);
BE1_q_a[8]_PORT_A_data_in_reg = DFFE(BE1_q_a[8]_PORT_A_data_in, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_A_address_reg = DFFE(BE1_q_a[8]_PORT_A_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_B_address_reg = DFFE(BE1_q_a[8]_PORT_B_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_write_enable = Z1L1;
BE1_q_a[8]_PORT_A_write_enable_reg = DFFE(BE1_q_a[8]_PORT_A_write_enable, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_byte_mask = AB1L35;
BE1_q_a[8]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[8]_PORT_A_byte_mask, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_clock_0 = DE1__clk0;
BE1_q_a[8]_PORT_A_data_out = MEMORY(BE1_q_a[8]_PORT_A_data_in_reg, , BE1_q_a[8]_PORT_A_address_reg, BE1_q_a[8]_PORT_B_address_reg, BE1_q_a[8]_PORT_A_write_enable_reg, , BE1_q_a[8]_PORT_A_byte_mask_reg, , BE1_q_a[8]_clock_0, , , , , );
BE1_q_a[11] = BE1_q_a[8]_PORT_A_data_out[3];
--BE1_q_a[12] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[12]
BE1_q_a[8]_PORT_A_data_in = BUS(L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15]);
BE1_q_a[8]_PORT_A_data_in_reg = DFFE(BE1_q_a[8]_PORT_A_data_in, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_A_address_reg = DFFE(BE1_q_a[8]_PORT_A_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_B_address_reg = DFFE(BE1_q_a[8]_PORT_B_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_write_enable = Z1L1;
BE1_q_a[8]_PORT_A_write_enable_reg = DFFE(BE1_q_a[8]_PORT_A_write_enable, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_byte_mask = AB1L35;
BE1_q_a[8]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[8]_PORT_A_byte_mask, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_clock_0 = DE1__clk0;
BE1_q_a[8]_PORT_A_data_out = MEMORY(BE1_q_a[8]_PORT_A_data_in_reg, , BE1_q_a[8]_PORT_A_address_reg, BE1_q_a[8]_PORT_B_address_reg, BE1_q_a[8]_PORT_A_write_enable_reg, , BE1_q_a[8]_PORT_A_byte_mask_reg, , BE1_q_a[8]_clock_0, , , , , );
BE1_q_a[12] = BE1_q_a[8]_PORT_A_data_out[4];
--BE1_q_a[13] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[13]
BE1_q_a[8]_PORT_A_data_in = BUS(L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15]);
BE1_q_a[8]_PORT_A_data_in_reg = DFFE(BE1_q_a[8]_PORT_A_data_in, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_A_address_reg = DFFE(BE1_q_a[8]_PORT_A_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_B_address_reg = DFFE(BE1_q_a[8]_PORT_B_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_write_enable = Z1L1;
BE1_q_a[8]_PORT_A_write_enable_reg = DFFE(BE1_q_a[8]_PORT_A_write_enable, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_byte_mask = AB1L35;
BE1_q_a[8]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[8]_PORT_A_byte_mask, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_clock_0 = DE1__clk0;
BE1_q_a[8]_PORT_A_data_out = MEMORY(BE1_q_a[8]_PORT_A_data_in_reg, , BE1_q_a[8]_PORT_A_address_reg, BE1_q_a[8]_PORT_B_address_reg, BE1_q_a[8]_PORT_A_write_enable_reg, , BE1_q_a[8]_PORT_A_byte_mask_reg, , BE1_q_a[8]_clock_0, , , , , );
BE1_q_a[13] = BE1_q_a[8]_PORT_A_data_out[5];
--BE1_q_a[14] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[14]
BE1_q_a[8]_PORT_A_data_in = BUS(L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15]);
BE1_q_a[8]_PORT_A_data_in_reg = DFFE(BE1_q_a[8]_PORT_A_data_in, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_A_address_reg = DFFE(BE1_q_a[8]_PORT_A_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_B_address_reg = DFFE(BE1_q_a[8]_PORT_B_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_write_enable = Z1L1;
BE1_q_a[8]_PORT_A_write_enable_reg = DFFE(BE1_q_a[8]_PORT_A_write_enable, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_byte_mask = AB1L35;
BE1_q_a[8]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[8]_PORT_A_byte_mask, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_clock_0 = DE1__clk0;
BE1_q_a[8]_PORT_A_data_out = MEMORY(BE1_q_a[8]_PORT_A_data_in_reg, , BE1_q_a[8]_PORT_A_address_reg, BE1_q_a[8]_PORT_B_address_reg, BE1_q_a[8]_PORT_A_write_enable_reg, , BE1_q_a[8]_PORT_A_byte_mask_reg, , BE1_q_a[8]_clock_0, , , , , );
BE1_q_a[14] = BE1_q_a[8]_PORT_A_data_out[6];
--BE1_q_a[15] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[15]
BE1_q_a[8]_PORT_A_data_in = BUS(L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15]);
BE1_q_a[8]_PORT_A_data_in_reg = DFFE(BE1_q_a[8]_PORT_A_data_in, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_A_address_reg = DFFE(BE1_q_a[8]_PORT_A_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[8]_PORT_B_address_reg = DFFE(BE1_q_a[8]_PORT_B_address, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_write_enable = Z1L1;
BE1_q_a[8]_PORT_A_write_enable_reg = DFFE(BE1_q_a[8]_PORT_A_write_enable, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_PORT_A_byte_mask = AB1L35;
BE1_q_a[8]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[8]_PORT_A_byte_mask, BE1_q_a[8]_clock_0, , , );
BE1_q_a[8]_clock_0 = DE1__clk0;
BE1_q_a[8]_PORT_A_data_out = MEMORY(BE1_q_a[8]_PORT_A_data_in_reg, , BE1_q_a[8]_PORT_A_address_reg, BE1_q_a[8]_PORT_B_address_reg, BE1_q_a[8]_PORT_A_write_enable_reg, , BE1_q_a[8]_PORT_A_byte_mask_reg, , BE1_q_a[8]_clock_0, , , , , );
BE1_q_a[15] = BE1_q_a[8]_PORT_A_data_out[7];
--Q1_internal_incoming_ext_ram_bus_data[15] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[15]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[15]_lut_out = A1L103;
Q1_internal_incoming_ext_ram_bus_data[15] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[15]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L140 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~4889
--operation mode is normal
M1L140 = BE1_q_a[15] & (Q1_internal_incoming_ext_ram_bus_data[15] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[15] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[15] # !Q1_cpu_data_master_requests_lan91c111_s1);
--KB1_readdata[15] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[15]
--operation mode is normal
KB1_readdata[15]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (KB1L191) # !L1_M_alu_result[3] & L1_M_alu_result[4] & KB1L190;
KB1_readdata[15] = DFFEAS(KB1_readdata[15]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L141 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~4890
--operation mode is normal
M1L141 = M1L139 & M1L140 & (KB1_readdata[15] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--R1_readdata[15] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[15]
--operation mode is normal
R1_readdata[15]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (R1L190) # !L1_M_alu_result[3] & L1_M_alu_result[4] & R1L189;
R1_readdata[15] = DFFEAS(R1_readdata[15]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1_dbs_8_reg_segment_1[7] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[7]
--operation mode is normal
M1_dbs_8_reg_segment_1[7]_lut_out = Q1_internal_incoming_ext_ram_bus_data[7];
M1_dbs_8_reg_segment_1[7] = DFFEAS(M1_dbs_8_reg_segment_1[7]_lut_out, DE1__clk0, E1_data_out, , M1L309, , , , );
--M1L142 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~4891
--operation mode is normal
M1L142 = M1_dbs_8_reg_segment_1[7] & (!M1_registered_cpu_data_master_readdata[15] & GB1L18) # !M1_dbs_8_reg_segment_1[7] & (Q1_cpu_data_master_requests_ext_flash_s1 # !M1_registered_cpu_data_master_readdata[15] & GB1L18);
--M1L143 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~4892
--operation mode is normal
M1L143 = !M1L142 & (Q1_internal_incoming_ext_ram_bus_data[15] # !Q1L73 # !Q1L71);
--M1L144 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~4893
--operation mode is normal
M1L144 = M1L112 & M1L141 & M1L230 & M1L143;
--PD1_q_a[8] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[8]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 8, Port B Depth: 256, Port B Width: 8
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
PD1_q_a[8] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[9] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[9]
PD1_q_a[9] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[10] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[10]
PD1_q_a[10] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[11] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[11]
PD1_q_a[11] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[12] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[12]
PD1_q_a[12] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[13] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[13]
PD1_q_a[13] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[14] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[14]
PD1_q_a[14] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[15] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[15]
PD1_q_a[15] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[8] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[8]
PD1_q_b[8] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[9] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[9]
PD1_q_b[9] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[10] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[10]
PD1_q_b[10] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[11] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[11]
PD1_q_b[11] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[12] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[12]
PD1_q_b[12] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[13] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[13]
PD1_q_b[13] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[14] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[14]
PD1_q_b[14] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[15] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[15]
PD1_q_b[15] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--FC1L18 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[15]~1206
--operation mode is normal
FC1L18 = AMPP_FUNCTION(PD1_q_a[15], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--BE1_q_a[24] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[24]
--RAM Block Operation Mode: Single Port
--Port A Depth: 16384, Port A Width: 8
--Port A Logical Depth: 16384, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
BE1_q_a[24]_PORT_A_data_in = BUS(L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[24]_PORT_A_data_in_reg = DFFE(BE1_q_a[24]_PORT_A_data_in, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_A_address_reg = DFFE(BE1_q_a[24]_PORT_A_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_B_address_reg = DFFE(BE1_q_a[24]_PORT_B_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_write_enable = Z1L1;
BE1_q_a[24]_PORT_A_write_enable_reg = DFFE(BE1_q_a[24]_PORT_A_write_enable, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_byte_mask = AB1L37;
BE1_q_a[24]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[24]_PORT_A_byte_mask, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_clock_0 = DE1__clk0;
BE1_q_a[24]_PORT_A_data_out = MEMORY(BE1_q_a[24]_PORT_A_data_in_reg, , BE1_q_a[24]_PORT_A_address_reg, BE1_q_a[24]_PORT_B_address_reg, BE1_q_a[24]_PORT_A_write_enable_reg, , BE1_q_a[24]_PORT_A_byte_mask_reg, , BE1_q_a[24]_clock_0, , , , , );
BE1_q_a[24] = BE1_q_a[24]_PORT_A_data_out[0];
--BE1_q_a[25] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[25]
BE1_q_a[24]_PORT_A_data_in = BUS(L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[24]_PORT_A_data_in_reg = DFFE(BE1_q_a[24]_PORT_A_data_in, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_A_address_reg = DFFE(BE1_q_a[24]_PORT_A_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_B_address_reg = DFFE(BE1_q_a[24]_PORT_B_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_write_enable = Z1L1;
BE1_q_a[24]_PORT_A_write_enable_reg = DFFE(BE1_q_a[24]_PORT_A_write_enable, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_byte_mask = AB1L37;
BE1_q_a[24]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[24]_PORT_A_byte_mask, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_clock_0 = DE1__clk0;
BE1_q_a[24]_PORT_A_data_out = MEMORY(BE1_q_a[24]_PORT_A_data_in_reg, , BE1_q_a[24]_PORT_A_address_reg, BE1_q_a[24]_PORT_B_address_reg, BE1_q_a[24]_PORT_A_write_enable_reg, , BE1_q_a[24]_PORT_A_byte_mask_reg, , BE1_q_a[24]_clock_0, , , , , );
BE1_q_a[25] = BE1_q_a[24]_PORT_A_data_out[1];
--BE1_q_a[26] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[26]
BE1_q_a[24]_PORT_A_data_in = BUS(L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[24]_PORT_A_data_in_reg = DFFE(BE1_q_a[24]_PORT_A_data_in, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_A_address_reg = DFFE(BE1_q_a[24]_PORT_A_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_B_address_reg = DFFE(BE1_q_a[24]_PORT_B_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_write_enable = Z1L1;
BE1_q_a[24]_PORT_A_write_enable_reg = DFFE(BE1_q_a[24]_PORT_A_write_enable, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_byte_mask = AB1L37;
BE1_q_a[24]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[24]_PORT_A_byte_mask, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_clock_0 = DE1__clk0;
BE1_q_a[24]_PORT_A_data_out = MEMORY(BE1_q_a[24]_PORT_A_data_in_reg, , BE1_q_a[24]_PORT_A_address_reg, BE1_q_a[24]_PORT_B_address_reg, BE1_q_a[24]_PORT_A_write_enable_reg, , BE1_q_a[24]_PORT_A_byte_mask_reg, , BE1_q_a[24]_clock_0, , , , , );
BE1_q_a[26] = BE1_q_a[24]_PORT_A_data_out[2];
--BE1_q_a[27] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[27]
BE1_q_a[24]_PORT_A_data_in = BUS(L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[24]_PORT_A_data_in_reg = DFFE(BE1_q_a[24]_PORT_A_data_in, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_A_address_reg = DFFE(BE1_q_a[24]_PORT_A_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_B_address_reg = DFFE(BE1_q_a[24]_PORT_B_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_write_enable = Z1L1;
BE1_q_a[24]_PORT_A_write_enable_reg = DFFE(BE1_q_a[24]_PORT_A_write_enable, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_byte_mask = AB1L37;
BE1_q_a[24]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[24]_PORT_A_byte_mask, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_clock_0 = DE1__clk0;
BE1_q_a[24]_PORT_A_data_out = MEMORY(BE1_q_a[24]_PORT_A_data_in_reg, , BE1_q_a[24]_PORT_A_address_reg, BE1_q_a[24]_PORT_B_address_reg, BE1_q_a[24]_PORT_A_write_enable_reg, , BE1_q_a[24]_PORT_A_byte_mask_reg, , BE1_q_a[24]_clock_0, , , , , );
BE1_q_a[27] = BE1_q_a[24]_PORT_A_data_out[3];
--BE1_q_a[28] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[28]
BE1_q_a[24]_PORT_A_data_in = BUS(L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[24]_PORT_A_data_in_reg = DFFE(BE1_q_a[24]_PORT_A_data_in, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_A_address_reg = DFFE(BE1_q_a[24]_PORT_A_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_B_address_reg = DFFE(BE1_q_a[24]_PORT_B_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_write_enable = Z1L1;
BE1_q_a[24]_PORT_A_write_enable_reg = DFFE(BE1_q_a[24]_PORT_A_write_enable, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_byte_mask = AB1L37;
BE1_q_a[24]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[24]_PORT_A_byte_mask, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_clock_0 = DE1__clk0;
BE1_q_a[24]_PORT_A_data_out = MEMORY(BE1_q_a[24]_PORT_A_data_in_reg, , BE1_q_a[24]_PORT_A_address_reg, BE1_q_a[24]_PORT_B_address_reg, BE1_q_a[24]_PORT_A_write_enable_reg, , BE1_q_a[24]_PORT_A_byte_mask_reg, , BE1_q_a[24]_clock_0, , , , , );
BE1_q_a[28] = BE1_q_a[24]_PORT_A_data_out[4];
--BE1_q_a[29] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[29]
BE1_q_a[24]_PORT_A_data_in = BUS(L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[24]_PORT_A_data_in_reg = DFFE(BE1_q_a[24]_PORT_A_data_in, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_A_address_reg = DFFE(BE1_q_a[24]_PORT_A_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_B_address_reg = DFFE(BE1_q_a[24]_PORT_B_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_write_enable = Z1L1;
BE1_q_a[24]_PORT_A_write_enable_reg = DFFE(BE1_q_a[24]_PORT_A_write_enable, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_byte_mask = AB1L37;
BE1_q_a[24]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[24]_PORT_A_byte_mask, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_clock_0 = DE1__clk0;
BE1_q_a[24]_PORT_A_data_out = MEMORY(BE1_q_a[24]_PORT_A_data_in_reg, , BE1_q_a[24]_PORT_A_address_reg, BE1_q_a[24]_PORT_B_address_reg, BE1_q_a[24]_PORT_A_write_enable_reg, , BE1_q_a[24]_PORT_A_byte_mask_reg, , BE1_q_a[24]_clock_0, , , , , );
BE1_q_a[29] = BE1_q_a[24]_PORT_A_data_out[5];
--BE1_q_a[30] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[30]
BE1_q_a[24]_PORT_A_data_in = BUS(L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[24]_PORT_A_data_in_reg = DFFE(BE1_q_a[24]_PORT_A_data_in, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_A_address_reg = DFFE(BE1_q_a[24]_PORT_A_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_B_address_reg = DFFE(BE1_q_a[24]_PORT_B_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_write_enable = Z1L1;
BE1_q_a[24]_PORT_A_write_enable_reg = DFFE(BE1_q_a[24]_PORT_A_write_enable, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_byte_mask = AB1L37;
BE1_q_a[24]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[24]_PORT_A_byte_mask, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_clock_0 = DE1__clk0;
BE1_q_a[24]_PORT_A_data_out = MEMORY(BE1_q_a[24]_PORT_A_data_in_reg, , BE1_q_a[24]_PORT_A_address_reg, BE1_q_a[24]_PORT_B_address_reg, BE1_q_a[24]_PORT_A_write_enable_reg, , BE1_q_a[24]_PORT_A_byte_mask_reg, , BE1_q_a[24]_clock_0, , , , , );
BE1_q_a[30] = BE1_q_a[24]_PORT_A_data_out[6];
--BE1_q_a[31] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[31]
BE1_q_a[24]_PORT_A_data_in = BUS(L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[24]_PORT_A_data_in_reg = DFFE(BE1_q_a[24]_PORT_A_data_in, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_A_address_reg = DFFE(BE1_q_a[24]_PORT_A_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_B_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[24]_PORT_B_address_reg = DFFE(BE1_q_a[24]_PORT_B_address, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_write_enable = Z1L1;
BE1_q_a[24]_PORT_A_write_enable_reg = DFFE(BE1_q_a[24]_PORT_A_write_enable, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_PORT_A_byte_mask = AB1L37;
BE1_q_a[24]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[24]_PORT_A_byte_mask, BE1_q_a[24]_clock_0, , , );
BE1_q_a[24]_clock_0 = DE1__clk0;
BE1_q_a[24]_PORT_A_data_out = MEMORY(BE1_q_a[24]_PORT_A_data_in_reg, , BE1_q_a[24]_PORT_A_address_reg, BE1_q_a[24]_PORT_B_address_reg, BE1_q_a[24]_PORT_A_write_enable_reg, , BE1_q_a[24]_PORT_A_byte_mask_reg, , BE1_q_a[24]_clock_0, , , , , );
BE1_q_a[31] = BE1_q_a[24]_PORT_A_data_out[7];
--Q1_internal_incoming_ext_ram_bus_data[31] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[31]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[31]_lut_out = A1L87;
Q1_internal_incoming_ext_ram_bus_data[31] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[31]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L221 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~4894
--operation mode is normal
M1L221 = BE1_q_a[31] & (Q1_internal_incoming_ext_ram_bus_data[31] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[31] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[31] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[31] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[31]
--operation mode is normal
M1_registered_cpu_data_master_readdata[31]_lut_out = M1L297 & !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[31] = DFFEAS(M1_registered_cpu_data_master_readdata[31]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L222 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~4895
--operation mode is normal
M1L222 = M1_registered_cpu_data_master_readdata[31] & (Q1_internal_incoming_ext_ram_bus_data[7] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[31] & !GB1L18 & (Q1_internal_incoming_ext_ram_bus_data[7] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L223 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~4896
--operation mode is normal
M1L223 = M1L221 & M1L222 & (Q1_internal_incoming_ext_ram_bus_data[31] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L224 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~4897
--operation mode is normal
M1L224 = M1L223 & (M1_registered_cpu_data_master_readdata[31] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L225 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~4898
--operation mode is normal
M1L225 = M1L145 & M1L224 & (!NB1_cpu_data_master_granted_sysid_control_slave);
--PD1_q_a[24] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[24]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 8, Port B Depth: 256, Port B Width: 8
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
PD1_q_a[24] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[25] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[25]
PD1_q_a[25] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[26] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[26]
PD1_q_a[26] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[27] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[27]
PD1_q_a[27] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[28] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[28]
PD1_q_a[28] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[29] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[29]
PD1_q_a[29] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[30] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[30]
PD1_q_a[30] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_a[31] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[31]
PD1_q_a[31] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[24] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[24]
PD1_q_b[24] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[25] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[25]
PD1_q_b[25] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[26] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[26]
PD1_q_b[26] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[27] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[27]
PD1_q_b[27] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[28] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[28]
PD1_q_b[28] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[29] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[29]
PD1_q_b[29] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[30] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[30]
PD1_q_b[30] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--PD1_q_b[31] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[31]
PD1_q_b[31] = AMPP_FUNCTION(CD1L62, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L34, CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9]);
--FC1L35 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[31]~1207
--operation mode is normal
FC1L35 = AMPP_FUNCTION(PD1_q_a[31], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--NC1_q_b[22] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[22]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[22] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1406, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L952 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[19]~58
--operation mode is arithmetic
L1L952 = AMPP_FUNCTION(L1_F_pc[19], L1L951);
--L1L953 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[19]~59
--operation mode is arithmetic
L1L953 = AMPP_FUNCTION(L1_F_pc[19], L1L951);
--M1L232 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~714
--operation mode is normal
M1L232 = !NB1_cpu_data_master_granted_sysid_control_slave # !L1_M_alu_result[2];
--Q1_internal_incoming_ext_ram_bus_data[21] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[21]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[21]_lut_out = A1L97;
Q1_internal_incoming_ext_ram_bus_data[21] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[21]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L171 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~4899
--operation mode is normal
M1L171 = BE1_q_a[21] & (Q1_internal_incoming_ext_ram_bus_data[21] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[21] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[21] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[21] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[21]
--operation mode is normal
M1_registered_cpu_data_master_readdata[21]_lut_out = M1L287 & !J1_cpu_data_master_requests_clock_0_in & (T1L31 # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
M1_registered_cpu_data_master_readdata[21] = DFFEAS(M1_registered_cpu_data_master_readdata[21]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1_dbs_8_reg_segment_2[5] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[5]
--operation mode is normal
M1_dbs_8_reg_segment_2[5]_lut_out = Q1_internal_incoming_ext_ram_bus_data[5];
M1_dbs_8_reg_segment_2[5] = DFFEAS(M1_dbs_8_reg_segment_2[5]_lut_out, DE1__clk0, E1_data_out, , M1L310, , , , );
--M1L172 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~4900
--operation mode is normal
M1L172 = M1_registered_cpu_data_master_readdata[21] & (M1_dbs_8_reg_segment_2[5] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[21] & !GB1L18 & (M1_dbs_8_reg_segment_2[5] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L173 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~4901
--operation mode is normal
M1L173 = M1L171 & M1L172 & (Q1_internal_incoming_ext_ram_bus_data[21] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L174 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~4902
--operation mode is normal
M1L174 = M1L173 & (M1_registered_cpu_data_master_readdata[21] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--FC1L25 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[21]~1208
--operation mode is normal
FC1L25 = AMPP_FUNCTION(PD1_q_a[21], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--NC1_q_b[21] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[21]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[21] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1403, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L958 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[22]~60
--operation mode is arithmetic
L1L958 = AMPP_FUNCTION(L1_F_pc[22], L1L957);
--L1L959 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[22]~61
--operation mode is arithmetic
L1L959 = AMPP_FUNCTION(L1_F_pc[22], L1L957);
--KC1_q_b[22] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[22]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[22] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[22], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[23] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[23]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[23] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[23], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[24] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[24]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[24] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[24], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[25] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[25]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[25] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[25], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--KC1_q_b[26] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[26]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[26] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[26], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--Q1_internal_incoming_ext_ram_bus_data[24] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[24]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[24]_lut_out = A1L94;
Q1_internal_incoming_ext_ram_bus_data[24] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[24]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L186 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~4903
--operation mode is normal
M1L186 = BE1_q_a[24] & (Q1_internal_incoming_ext_ram_bus_data[24] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[24] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[24] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[24] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[24]
--operation mode is normal
M1_registered_cpu_data_master_readdata[24]_lut_out = M1L290 & !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[24] = DFFEAS(M1_registered_cpu_data_master_readdata[24]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_internal_incoming_ext_ram_bus_data[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[0]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[0]_lut_out = A1L118;
Q1_internal_incoming_ext_ram_bus_data[0] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L187 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~4904
--operation mode is normal
M1L187 = M1_registered_cpu_data_master_readdata[24] & (Q1_internal_incoming_ext_ram_bus_data[0] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[24] & !GB1L18 & (Q1_internal_incoming_ext_ram_bus_data[0] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L188 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~4905
--operation mode is normal
M1L188 = M1L186 & M1L187 & (Q1_internal_incoming_ext_ram_bus_data[24] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L189 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~4906
--operation mode is normal
M1L189 = M1L188 & (M1_registered_cpu_data_master_readdata[24] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L190 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~4907
--operation mode is normal
M1L190 = M1L145 & M1L189 & (!NB1_cpu_data_master_granted_sysid_control_slave);
--FC1L28 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[24]~1209
--operation mode is normal
FC1L28 = AMPP_FUNCTION(PD1_q_a[24], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--L1L948 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[17]~62
--operation mode is arithmetic
L1L948 = AMPP_FUNCTION(L1_F_pc[17], L1L947);
--L1L949 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[17]~63
--operation mode is arithmetic
L1L949 = AMPP_FUNCTION(L1_F_pc[17], L1L947);
--NC1_q_b[19] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[19]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[19] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1397, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L946 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[16]~64
--operation mode is arithmetic
L1L946 = AMPP_FUNCTION(L1_F_pc[16], L1L945);
--L1L947 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[16]~65
--operation mode is arithmetic
L1L947 = AMPP_FUNCTION(L1_F_pc[16], L1L945);
--NC1_q_b[18] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[18]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[18] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1394, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L944 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[15]~66
--operation mode is arithmetic
L1L944 = AMPP_FUNCTION(L1_F_pc[15], L1L943);
--L1L945 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[15]~67
--operation mode is arithmetic
L1L945 = AMPP_FUNCTION(L1_F_pc[15], L1L943);
--Q1_internal_incoming_ext_ram_bus_data[17] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[17]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[17]_lut_out = A1L101;
Q1_internal_incoming_ext_ram_bus_data[17] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[17]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L151 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~4908
--operation mode is normal
M1L151 = BE1_q_a[17] & (Q1_internal_incoming_ext_ram_bus_data[17] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[17] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[17] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[17] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[17]
--operation mode is normal
M1_registered_cpu_data_master_readdata[17]_lut_out = T1L38 & !J1_cpu_data_master_requests_clock_0_in & (FB1_za_data[17] # !GB1L18);
M1_registered_cpu_data_master_readdata[17] = DFFEAS(M1_registered_cpu_data_master_readdata[17]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1_dbs_8_reg_segment_2[1] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[1]
--operation mode is normal
M1_dbs_8_reg_segment_2[1]_lut_out = Q1_internal_incoming_ext_ram_bus_data[1];
M1_dbs_8_reg_segment_2[1] = DFFEAS(M1_dbs_8_reg_segment_2[1]_lut_out, DE1__clk0, E1_data_out, , M1L310, , , , );
--M1L152 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~4909
--operation mode is normal
M1L152 = M1_registered_cpu_data_master_readdata[17] & (M1_dbs_8_reg_segment_2[1] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[17] & !GB1L18 & (M1_dbs_8_reg_segment_2[1] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L153 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~4910
--operation mode is normal
M1L153 = M1L151 & M1L152 & (Q1_internal_incoming_ext_ram_bus_data[17] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L154 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~4911
--operation mode is normal
M1L154 = M1L153 & (M1_registered_cpu_data_master_readdata[17] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L155 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~4912
--operation mode is normal
M1L155 = M1L145 & M1L154 & (!NB1_cpu_data_master_granted_sysid_control_slave);
--FC1L20 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[17]~1210
--operation mode is normal
FC1L20 = AMPP_FUNCTION(PD1_q_a[17], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--NC1_q_b[17] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[17]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[17] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1391, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L942 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[14]~68
--operation mode is arithmetic
L1L942 = AMPP_FUNCTION(L1_F_pc[14], L1L941);
--L1L943 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[14]~69
--operation mode is arithmetic
L1L943 = AMPP_FUNCTION(L1_F_pc[14], L1L941);
--Q1_internal_incoming_ext_ram_bus_data[16] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[16]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[16]_lut_out = A1L102;
Q1_internal_incoming_ext_ram_bus_data[16] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[16]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L146 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~4913
--operation mode is normal
M1L146 = BE1_q_a[16] & (Q1_internal_incoming_ext_ram_bus_data[16] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[16] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[16] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[16] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[16]
--operation mode is normal
M1_registered_cpu_data_master_readdata[16]_lut_out = T1L39 & !J1_cpu_data_master_requests_clock_0_in & (FB1_za_data[16] # !GB1L18);
M1_registered_cpu_data_master_readdata[16] = DFFEAS(M1_registered_cpu_data_master_readdata[16]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1_dbs_8_reg_segment_2[0] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[0]
--operation mode is normal
M1_dbs_8_reg_segment_2[0]_lut_out = Q1_internal_incoming_ext_ram_bus_data[0];
M1_dbs_8_reg_segment_2[0] = DFFEAS(M1_dbs_8_reg_segment_2[0]_lut_out, DE1__clk0, E1_data_out, , M1L310, , , , );
--M1L147 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~4914
--operation mode is normal
M1L147 = M1_registered_cpu_data_master_readdata[16] & (M1_dbs_8_reg_segment_2[0] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[16] & !GB1L18 & (M1_dbs_8_reg_segment_2[0] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L148 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~4915
--operation mode is normal
M1L148 = M1L146 & M1L147 & (Q1_internal_incoming_ext_ram_bus_data[16] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L149 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~4916
--operation mode is normal
M1L149 = M1L148 & (M1_registered_cpu_data_master_readdata[16] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--FC1L19 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[16]~1211
--operation mode is normal
FC1L19 = AMPP_FUNCTION(PD1_q_a[16], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--NC1_q_b[16] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[16]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[16] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1388, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L956 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[21]~70
--operation mode is arithmetic
L1L956 = AMPP_FUNCTION(L1_F_pc[21], L1L955);
--L1L957 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[21]~71
--operation mode is arithmetic
L1L957 = AMPP_FUNCTION(L1_F_pc[21], L1L955);
--NC1_q_b[23] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[23]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[23] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1409, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L960 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[23]~72
--operation mode is normal
L1L960 = AMPP_FUNCTION(L1_F_pc[23], L1L959);
--Q1_internal_incoming_ext_ram_bus_data[25] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[25]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[25]_lut_out = A1L93;
Q1_internal_incoming_ext_ram_bus_data[25] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[25]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L191 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~4917
--operation mode is normal
M1L191 = BE1_q_a[25] & (Q1_internal_incoming_ext_ram_bus_data[25] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[25] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[25] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[25] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[25]
--operation mode is normal
M1_registered_cpu_data_master_readdata[25]_lut_out = M1L291 & !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[25] = DFFEAS(M1_registered_cpu_data_master_readdata[25]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_internal_incoming_ext_ram_bus_data[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[1]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[1]_lut_out = A1L117;
Q1_internal_incoming_ext_ram_bus_data[1] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L192 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~4918
--operation mode is normal
M1L192 = M1_registered_cpu_data_master_readdata[25] & (Q1_internal_incoming_ext_ram_bus_data[1] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[25] & !GB1L18 & (Q1_internal_incoming_ext_ram_bus_data[1] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L193 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~4919
--operation mode is normal
M1L193 = M1L191 & M1L192 & (Q1_internal_incoming_ext_ram_bus_data[25] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L194 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~4920
--operation mode is normal
M1L194 = M1L193 & (M1_registered_cpu_data_master_readdata[25] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L195 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~4921
--operation mode is normal
M1L195 = M1L145 & M1L194 & (!NB1_cpu_data_master_granted_sysid_control_slave);
--FC1L29 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[25]~1212
--operation mode is normal
FC1L29 = AMPP_FUNCTION(PD1_q_a[25], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--L1L950 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[18]~74
--operation mode is arithmetic
L1L950 = AMPP_FUNCTION(L1_F_pc[18], L1L949);
--L1L951 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[18]~75
--operation mode is arithmetic
L1L951 = AMPP_FUNCTION(L1_F_pc[18], L1L949);
--NC1_q_b[20] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[20]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[20] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1400, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L940 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[13]~76
--operation mode is arithmetic
L1L940 = AMPP_FUNCTION(L1_F_pc[13], L1L939);
--L1L941 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[13]~77
--operation mode is arithmetic
L1L941 = AMPP_FUNCTION(L1_F_pc[13], L1L939);
--L1L938 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[12]~78
--operation mode is arithmetic
L1L938 = AMPP_FUNCTION(L1_F_pc[12], L1L937);
--L1L939 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[12]~79
--operation mode is arithmetic
L1L939 = AMPP_FUNCTION(L1_F_pc[12], L1L937);
--KC1_q_b[20] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[20]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[20] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[20], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--M1_registered_cpu_data_master_readdata[14] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[14]
--operation mode is normal
M1_registered_cpu_data_master_readdata[14]_lut_out = !M1L282 & (T1_woverflow # !U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[14] = DFFEAS(M1_registered_cpu_data_master_readdata[14]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L132 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~4922
--operation mode is normal
M1L132 = M1_registered_cpu_data_master_readdata[14] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--Q1_internal_incoming_ext_ram_bus_data[14] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[14]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[14]_lut_out = A1L104;
Q1_internal_incoming_ext_ram_bus_data[14] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[14]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L133 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~4923
--operation mode is normal
M1L133 = BE1_q_a[14] & (Q1_internal_incoming_ext_ram_bus_data[14] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[14] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[14] # !Q1_cpu_data_master_requests_lan91c111_s1);
--KB1_readdata[14] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[14]
--operation mode is normal
KB1_readdata[14]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (KB1L189) # !L1_M_alu_result[3] & L1_M_alu_result[4] & KB1L188;
KB1_readdata[14] = DFFEAS(KB1_readdata[14]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L134 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~4924
--operation mode is normal
M1L134 = M1L132 & M1L133 & (KB1_readdata[14] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--M1_dbs_8_reg_segment_1[6] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[6]
--operation mode is normal
M1_dbs_8_reg_segment_1[6]_lut_out = Q1_internal_incoming_ext_ram_bus_data[6];
M1_dbs_8_reg_segment_1[6] = DFFEAS(M1_dbs_8_reg_segment_1[6]_lut_out, DE1__clk0, E1_data_out, , M1L309, , , , );
--M1L135 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~4925
--operation mode is normal
M1L135 = M1_registered_cpu_data_master_readdata[14] & (M1_dbs_8_reg_segment_1[6] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[14] & !GB1L18 & (M1_dbs_8_reg_segment_1[6] # !Q1_cpu_data_master_requests_ext_flash_s1);
--R1_readdata[14] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[14]
--operation mode is normal
R1_readdata[14]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (R1L188) # !L1_M_alu_result[3] & L1_M_alu_result[4] & R1L187;
R1_readdata[14] = DFFEAS(R1_readdata[14]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L136 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~4926
--operation mode is normal
M1L136 = M1L232 & M1L138 & (R1_readdata[14] # !S1_cpu_data_master_requests_high_res_timer_s1);
--M1L137 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~4927
--operation mode is normal
M1L137 = M1L112 & M1L134 & M1L136;
--FC1L17 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[14]~1213
--operation mode is normal
FC1L17 = AMPP_FUNCTION(PD1_q_a[14], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--M1_registered_cpu_data_master_readdata[30] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[30]
--operation mode is normal
M1_registered_cpu_data_master_readdata[30]_lut_out = M1L296 & !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[30] = DFFEAS(M1_registered_cpu_data_master_readdata[30]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L216 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~4928
--operation mode is normal
M1L216 = M1_registered_cpu_data_master_readdata[30] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--Q1_internal_incoming_ext_ram_bus_data[30] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[30]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[30]_lut_out = A1L88;
Q1_internal_incoming_ext_ram_bus_data[30] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[30]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L217 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~4929
--operation mode is normal
M1L217 = BE1_q_a[30] & (Q1_internal_incoming_ext_ram_bus_data[30] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[30] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[30] # !Q1_cpu_data_master_requests_lan91c111_s1);
--Q1_internal_incoming_ext_ram_bus_data[6] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[6]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[6]_lut_out = A1L112;
Q1_internal_incoming_ext_ram_bus_data[6] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L218 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~4930
--operation mode is normal
M1L218 = M1_registered_cpu_data_master_readdata[30] & (Q1_internal_incoming_ext_ram_bus_data[6] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[30] & !GB1L18 & (Q1_internal_incoming_ext_ram_bus_data[6] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L219 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~4931
--operation mode is normal
M1L219 = M1L145 & M1L216 & M1L217 & M1L220;
--FC1L34 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[30]~1214
--operation mode is normal
FC1L34 = AMPP_FUNCTION(PD1_q_a[30], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--L1L936 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[11]~80
--operation mode is arithmetic
L1L936 = AMPP_FUNCTION(L1_F_pc[11], L1L935);
--L1L937 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[11]~81
--operation mode is arithmetic
L1L937 = AMPP_FUNCTION(L1_F_pc[11], L1L935);
--KC1_q_b[19] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[19]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[19] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[19], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--M1_registered_cpu_data_master_readdata[13] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[13]
--operation mode is normal
M1_registered_cpu_data_master_readdata[13]_lut_out = !M1L281 & (!WD1_b_full # !U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[13] = DFFEAS(M1_registered_cpu_data_master_readdata[13]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L126 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~4932
--operation mode is normal
M1L126 = M1_registered_cpu_data_master_readdata[13] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--Q1_internal_incoming_ext_ram_bus_data[13] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[13]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[13]_lut_out = A1L105;
Q1_internal_incoming_ext_ram_bus_data[13] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[13]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L127 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~4933
--operation mode is normal
M1L127 = BE1_q_a[13] & (Q1_internal_incoming_ext_ram_bus_data[13] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[13] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[13] # !Q1_cpu_data_master_requests_lan91c111_s1);
--KB1_readdata[13] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[13]
--operation mode is normal
KB1_readdata[13]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (KB1L187) # !L1_M_alu_result[3] & L1_M_alu_result[4] & KB1L186;
KB1_readdata[13] = DFFEAS(KB1_readdata[13]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L128 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~4934
--operation mode is normal
M1L128 = M1L126 & M1L127 & (KB1_readdata[13] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--R1_readdata[13] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[13]
--operation mode is normal
R1_readdata[13]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (R1L186) # !L1_M_alu_result[3] & L1_M_alu_result[4] & R1L185;
R1_readdata[13] = DFFEAS(R1_readdata[13]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1_dbs_8_reg_segment_1[5] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[5]
--operation mode is normal
M1_dbs_8_reg_segment_1[5]_lut_out = Q1_internal_incoming_ext_ram_bus_data[5];
M1_dbs_8_reg_segment_1[5] = DFFEAS(M1_dbs_8_reg_segment_1[5]_lut_out, DE1__clk0, E1_data_out, , M1L309, , , , );
--M1L129 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~4935
--operation mode is normal
M1L129 = M1_dbs_8_reg_segment_1[5] & (!M1_registered_cpu_data_master_readdata[13] & GB1L18) # !M1_dbs_8_reg_segment_1[5] & (Q1_cpu_data_master_requests_ext_flash_s1 # !M1_registered_cpu_data_master_readdata[13] & GB1L18);
--M1L130 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~4936
--operation mode is normal
M1L130 = !M1L129 & (Q1_internal_incoming_ext_ram_bus_data[13] # !Q1L73 # !Q1L71);
--M1L131 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~4937
--operation mode is normal
M1L131 = M1L112 & M1L128 & M1L229 & M1L130;
--FC1L16 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[13]~1215
--operation mode is normal
FC1L16 = AMPP_FUNCTION(PD1_q_a[13], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--Q1_internal_incoming_ext_ram_bus_data[29] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[29]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[29]_lut_out = A1L89;
Q1_internal_incoming_ext_ram_bus_data[29] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[29]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L211 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~4938
--operation mode is normal
M1L211 = BE1_q_a[29] & (Q1_internal_incoming_ext_ram_bus_data[29] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[29] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[29] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[29] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[29]
--operation mode is normal
M1_registered_cpu_data_master_readdata[29]_lut_out = M1L295 & !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[29] = DFFEAS(M1_registered_cpu_data_master_readdata[29]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_internal_incoming_ext_ram_bus_data[5] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[5]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[5]_lut_out = A1L113;
Q1_internal_incoming_ext_ram_bus_data[5] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L212 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~4939
--operation mode is normal
M1L212 = M1_registered_cpu_data_master_readdata[29] & (Q1_internal_incoming_ext_ram_bus_data[5] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[29] & !GB1L18 & (Q1_internal_incoming_ext_ram_bus_data[5] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L213 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~4940
--operation mode is normal
M1L213 = M1L211 & M1L212 & (Q1_internal_incoming_ext_ram_bus_data[29] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L214 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~4941
--operation mode is normal
M1L214 = M1L213 & (M1_registered_cpu_data_master_readdata[29] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--FC1L33 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[29]~1216
--operation mode is normal
FC1L33 = AMPP_FUNCTION(PD1_q_a[29], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--L1L934 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[10]~82
--operation mode is arithmetic
L1L934 = AMPP_FUNCTION(L1_F_pc[10], L1L933);
--L1L935 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[10]~83
--operation mode is arithmetic
L1L935 = AMPP_FUNCTION(L1_F_pc[10], L1L933);
--L1L109 is std_1s10:inst|cpu:the_cpu|Add1~279
--operation mode is arithmetic
L1L109 = AMPP_FUNCTION(L1_D_br_taken_waddr_partial[10]);
--KC1_q_b[18] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[18]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[18] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[18], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--M1_registered_cpu_data_master_readdata[12] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[12]
--operation mode is normal
M1_registered_cpu_data_master_readdata[12]_lut_out = !M1L280 & (WD2_b_non_empty # !U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[12] = DFFEAS(M1_registered_cpu_data_master_readdata[12]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L119 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~4942
--operation mode is normal
M1L119 = M1_registered_cpu_data_master_readdata[12] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--Q1_internal_incoming_ext_ram_bus_data[12] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[12]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[12]_lut_out = A1L106;
Q1_internal_incoming_ext_ram_bus_data[12] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[12]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L120 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~4943
--operation mode is normal
M1L120 = BE1_q_a[12] & (Q1_internal_incoming_ext_ram_bus_data[12] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[12] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[12] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_dbs_8_reg_segment_1[4] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[4]
--operation mode is normal
M1_dbs_8_reg_segment_1[4]_lut_out = Q1_internal_incoming_ext_ram_bus_data[4];
M1_dbs_8_reg_segment_1[4] = DFFEAS(M1_dbs_8_reg_segment_1[4]_lut_out, DE1__clk0, E1_data_out, , M1L309, , , , );
--M1L121 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~4944
--operation mode is normal
M1L121 = M1_dbs_8_reg_segment_1[4] & (!M1_registered_cpu_data_master_readdata[12] & GB1L18) # !M1_dbs_8_reg_segment_1[4] & (Q1_cpu_data_master_requests_ext_flash_s1 # !M1_registered_cpu_data_master_readdata[12] & GB1L18);
--M1L122 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~4945
--operation mode is normal
M1L122 = !M1L121 & (Q1_internal_incoming_ext_ram_bus_data[12] # !Q1L73 # !Q1L71);
--R1_readdata[12] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[12]
--operation mode is normal
R1_readdata[12]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (R1L184) # !L1_M_alu_result[3] & L1_M_alu_result[4] & R1L183;
R1_readdata[12] = DFFEAS(R1_readdata[12]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L123 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~4946
--operation mode is normal
M1L123 = M1L122 & (R1_readdata[12] # !S1L2 # !LB1L2);
--KB1_readdata[12] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[12]
--operation mode is normal
KB1_readdata[12]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (KB1L185) # !L1_M_alu_result[3] & L1_M_alu_result[4] & KB1L184;
KB1_readdata[12] = DFFEAS(KB1_readdata[12]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L124 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~4947
--operation mode is normal
M1L124 = M1L120 & M1L123 & (KB1_readdata[12] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--M1L125 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~4948
--operation mode is normal
M1L125 = M1L112 & M1L119 & M1L124 & !NB1_cpu_data_master_granted_sysid_control_slave;
--FC1L15 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[12]~1217
--operation mode is normal
FC1L15 = AMPP_FUNCTION(PD1_q_a[12], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--Q1_internal_incoming_ext_ram_bus_data[28] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[28]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[28]_lut_out = A1L90;
Q1_internal_incoming_ext_ram_bus_data[28] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[28]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L206 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~4949
--operation mode is normal
M1L206 = BE1_q_a[28] & (Q1_internal_incoming_ext_ram_bus_data[28] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[28] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[28] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[28] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[28]
--operation mode is normal
M1_registered_cpu_data_master_readdata[28]_lut_out = M1L294 & !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[28] = DFFEAS(M1_registered_cpu_data_master_readdata[28]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L207 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~4950
--operation mode is normal
M1L207 = M1_registered_cpu_data_master_readdata[28] & (Q1_internal_incoming_ext_ram_bus_data[4] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[28] & !GB1L18 & (Q1_internal_incoming_ext_ram_bus_data[4] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L208 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~4951
--operation mode is normal
M1L208 = M1L206 & M1L207 & (Q1_internal_incoming_ext_ram_bus_data[28] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L209 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~4952
--operation mode is normal
M1L209 = M1L208 & (M1_registered_cpu_data_master_readdata[28] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L210 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~4953
--operation mode is normal
M1L210 = M1L145 & M1L209 & (!NB1_cpu_data_master_granted_sysid_control_slave);
--FC1L32 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[28]~1218
--operation mode is normal
FC1L32 = AMPP_FUNCTION(PD1_q_a[28], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--L1L932 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[9]~84
--operation mode is arithmetic
L1L932 = AMPP_FUNCTION(L1_F_pc[9], L1L931);
--L1L933 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[9]~85
--operation mode is arithmetic
L1L933 = AMPP_FUNCTION(L1_F_pc[9], L1L931);
--KC1_q_b[17] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[17]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[17] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[17], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L832, L1L835, L1L838, L1L864, L1L867, L1L870, L1L873, L1L876, L1L879, L1L882);
--M1_registered_cpu_data_master_readdata[11] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[11]
--operation mode is normal
M1_registered_cpu_data_master_readdata[11]_lut_out = M1L279 & !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & (FB1_za_data[11] # !GB1L18);
M1_registered_cpu_data_master_readdata[11] = DFFEAS(M1_registered_cpu_data_master_readdata[11]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L113 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~4954
--operation mode is normal
M1L113 = M1_registered_cpu_data_master_readdata[11] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--Q1_internal_incoming_ext_ram_bus_data[11] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[11]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[11]_lut_out = A1L107;
Q1_internal_incoming_ext_ram_bus_data[11] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[11]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L114 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~4955
--operation mode is normal
M1L114 = BE1_q_a[11] & (Q1_internal_incoming_ext_ram_bus_data[11] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[11] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[11] # !Q1_cpu_data_master_requests_lan91c111_s1);
--KB1_readdata[11] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[11]
--operation mode is normal
KB1_readdata[11]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (KB1L183) # !L1_M_alu_result[3] & L1_M_alu_result[4] & KB1L182;
KB1_readdata[11] = DFFEAS(KB1_readdata[11]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L115 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~4956
--operation mode is normal
M1L115 = M1L113 & M1L114 & (KB1_readdata[11] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--R1_readdata[11] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[11]
--operation mode is normal
R1_readdata[11]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (R1L182) # !L1_M_alu_result[3] & L1_M_alu_result[4] & R1L181;
R1_readdata[11] = DFFEAS(R1_readdata[11]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1_dbs_8_reg_segment_1[3] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[3]
--operation mode is normal
M1_dbs_8_reg_segment_1[3]_lut_out = Q1_internal_incoming_ext_ram_bus_data[3];
M1_dbs_8_reg_segment_1[3] = DFFEAS(M1_dbs_8_reg_segment_1[3]_lut_out, DE1__clk0, E1_data_out, , M1L309, , , , );
--M1L116 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~4957
--operation mode is normal
M1L116 = M1_dbs_8_reg_segment_1[3] & (!M1_registered_cpu_data_master_readdata[11] & GB1L18) # !M1_dbs_8_reg_segment_1[3] & (Q1_cpu_data_master_requests_ext_flash_s1 # !M1_registered_cpu_data_master_readdata[11] & GB1L18);
--M1L117 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~4958
--operation mode is normal
M1L117 = !M1L116 & (Q1_internal_incoming_ext_ram_bus_data[11] # !Q1L73 # !Q1L71);
--M1L118 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~4959
--operation mode is normal
M1L118 = M1L112 & M1L115 & M1L228 & M1L117;
--FC1L14 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[11]~1219
--operation mode is normal
FC1L14 = AMPP_FUNCTION(PD1_q_a[11], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--Q1_internal_incoming_ext_ram_bus_data[27] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[27]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[27]_lut_out = A1L91;
Q1_internal_incoming_ext_ram_bus_data[27] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[27]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L201 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~4960
--operation mode is normal
M1L201 = BE1_q_a[27] & (Q1_internal_incoming_ext_ram_bus_data[27] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[27] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[27] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[27] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[27]
--operation mode is normal
M1_registered_cpu_data_master_readdata[27]_lut_out = M1L293 & !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[27] = DFFEAS(M1_registered_cpu_data_master_readdata[27]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L202 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~4961
--operation mode is normal
M1L202 = M1_registered_cpu_data_master_readdata[27] & (Q1_internal_incoming_ext_ram_bus_data[3] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[27] & !GB1L18 & (Q1_internal_incoming_ext_ram_bus_data[3] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L203 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~4962
--operation mode is normal
M1L203 = M1L201 & M1L202 & (Q1_internal_incoming_ext_ram_bus_data[27] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L204 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~4963
--operation mode is normal
M1L204 = M1L203 & (M1_registered_cpu_data_master_readdata[27] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--FC1L31 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[27]~1220
--operation mode is normal
FC1L31 = AMPP_FUNCTION(PD1_q_a[27], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--L1L930 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[8]~86
--operation mode is arithmetic
L1L930 = AMPP_FUNCTION(L1_F_pc[8], L1L929);
--L1L931 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[8]~87
--operation mode is arithmetic
L1L931 = AMPP_FUNCTION(L1_F_pc[8], L1L929);
--M1_registered_cpu_data_master_readdata[10] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[10]
--operation mode is normal
M1_registered_cpu_data_master_readdata[10]_lut_out = !M1L278 & (T1_ac # !U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[10] = DFFEAS(M1_registered_cpu_data_master_readdata[10]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L105 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~4964
--operation mode is normal
M1L105 = M1_registered_cpu_data_master_readdata[10] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--Q1_internal_incoming_ext_ram_bus_data[10] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[10]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[10]_lut_out = A1L108;
Q1_internal_incoming_ext_ram_bus_data[10] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[10]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L106 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~4965
--operation mode is normal
M1L106 = BE1_q_a[10] & (Q1_internal_incoming_ext_ram_bus_data[10] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[10] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[10] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_dbs_8_reg_segment_1[2] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[2]
--operation mode is normal
M1_dbs_8_reg_segment_1[2]_lut_out = Q1_internal_incoming_ext_ram_bus_data[2];
M1_dbs_8_reg_segment_1[2] = DFFEAS(M1_dbs_8_reg_segment_1[2]_lut_out, DE1__clk0, E1_data_out, , M1L309, , , , );
--M1L107 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~4966
--operation mode is normal
M1L107 = M1_dbs_8_reg_segment_1[2] & (!M1_registered_cpu_data_master_readdata[10] & GB1L18) # !M1_dbs_8_reg_segment_1[2] & (Q1_cpu_data_master_requests_ext_flash_s1 # !M1_registered_cpu_data_master_readdata[10] & GB1L18);
--M1L108 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~4967
--operation mode is normal
M1L108 = !M1L107 & (Q1_internal_incoming_ext_ram_bus_data[10] # !Q1L73 # !Q1L71);
--R1_readdata[10] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[10]
--operation mode is normal
R1_readdata[10]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (R1L180) # !L1_M_alu_result[3] & L1_M_alu_result[4] & R1L179;
R1_readdata[10] = DFFEAS(R1_readdata[10]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L109 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~4968
--operation mode is normal
M1L109 = M1L108 & (R1_readdata[10] # !S1L2 # !LB1L2);
--KB1_readdata[10] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[10]
--operation mode is normal
KB1_readdata[10]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (KB1L181) # !L1_M_alu_result[3] & L1_M_alu_result[4] & KB1L180;
KB1_readdata[10] = DFFEAS(KB1_readdata[10]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L110 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~4969
--operation mode is normal
M1L110 = M1L106 & M1L109 & (KB1_readdata[10] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--M1L111 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~4970
--operation mode is normal
M1L111 = M1L112 & M1L105 & M1L110 & !NB1_cpu_data_master_granted_sysid_control_slave;
--FC1L13 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[10]~1221
--operation mode is normal
FC1L13 = AMPP_FUNCTION(PD1_q_a[10], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--Q1_internal_incoming_ext_ram_bus_data[26] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[26]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[26]_lut_out = A1L92;
Q1_internal_incoming_ext_ram_bus_data[26] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[26]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L196 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~4971
--operation mode is normal
M1L196 = BE1_q_a[26] & (Q1_internal_incoming_ext_ram_bus_data[26] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[26] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[26] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[26] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[26]
--operation mode is normal
M1_registered_cpu_data_master_readdata[26]_lut_out = M1L292 & !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[26] = DFFEAS(M1_registered_cpu_data_master_readdata[26]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L197 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~4972
--operation mode is normal
M1L197 = M1_registered_cpu_data_master_readdata[26] & (Q1_internal_incoming_ext_ram_bus_data[2] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[26] & !GB1L18 & (Q1_internal_incoming_ext_ram_bus_data[2] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L198 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~4973
--operation mode is normal
M1L198 = M1L196 & M1L197 & (Q1_internal_incoming_ext_ram_bus_data[26] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L199 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~4974
--operation mode is normal
M1L199 = M1L198 & (M1_registered_cpu_data_master_readdata[26] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L200 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~4975
--operation mode is normal
M1L200 = M1L145 & M1L199 & (L1_M_alu_result[2] # !NB1_cpu_data_master_granted_sysid_control_slave);
--FC1L30 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[26]~1222
--operation mode is normal
FC1L30 = AMPP_FUNCTION(PD1_q_a[26], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--L1L928 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[7]~88
--operation mode is arithmetic
L1L928 = AMPP_FUNCTION(L1_F_pc[7], L1L927);
--L1L929 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[7]~89
--operation mode is arithmetic
L1L929 = AMPP_FUNCTION(L1_F_pc[7], L1L927);
--M1_registered_cpu_data_master_readdata[9] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[9]
--operation mode is normal
M1_registered_cpu_data_master_readdata[9]_lut_out = !M1L277 & (T1L49 # !U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[9] = DFFEAS(M1_registered_cpu_data_master_readdata[9]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L98 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~4976
--operation mode is normal
M1L98 = M1_registered_cpu_data_master_readdata[9] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--Q1_internal_incoming_ext_ram_bus_data[9] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[9]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[9]_lut_out = A1L109;
Q1_internal_incoming_ext_ram_bus_data[9] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[9]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L99 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~4977
--operation mode is normal
M1L99 = BE1_q_a[9] & (Q1_internal_incoming_ext_ram_bus_data[9] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[9] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[9] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1L100 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~4978
--operation mode is normal
M1L100 = M1L97 & M1L98 & M1L99;
--R1_readdata[9] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[9]
--operation mode is normal
R1_readdata[9]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (R1L178) # !L1_M_alu_result[3] & L1_M_alu_result[4] & R1L177;
R1_readdata[9] = DFFEAS(R1_readdata[9]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1_dbs_8_reg_segment_1[1] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[1]
--operation mode is normal
M1_dbs_8_reg_segment_1[1]_lut_out = Q1_internal_incoming_ext_ram_bus_data[1];
M1_dbs_8_reg_segment_1[1] = DFFEAS(M1_dbs_8_reg_segment_1[1]_lut_out, DE1__clk0, E1_data_out, , M1L309, , , , );
--M1L101 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~4979
--operation mode is normal
M1L101 = M1_registered_cpu_data_master_readdata[9] & (M1_dbs_8_reg_segment_1[1] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[9] & !GB1L18 & (M1_dbs_8_reg_segment_1[1] # !Q1_cpu_data_master_requests_ext_flash_s1);
--HE1_readdata[9] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[9]
--operation mode is normal
HE1_readdata[9]_lut_out = L1_M_alu_result[2] & L1_M_alu_result[3] & HE1_control_reg[9] & !L1_M_alu_result[4];
HE1_readdata[9] = DFFEAS(HE1_readdata[9]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L102 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~4980
--operation mode is normal
M1L102 = M1L227 & M1L104 & (HE1_readdata[9] # !QB1_cpu_data_master_granted_uart1_s1);
--KB1_readdata[9] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[9]
--operation mode is normal
KB1_readdata[9]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (KB1L179) # !L1_M_alu_result[3] & L1_M_alu_result[4] & KB1L178;
KB1_readdata[9] = DFFEAS(KB1_readdata[9]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L103 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~4981
--operation mode is normal
M1L103 = M1L100 & M1L102 & (KB1_readdata[9] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--FC1L12 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[9]~1223
--operation mode is normal
FC1L12 = AMPP_FUNCTION(PD1_q_a[9], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--L1L926 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[6]~90
--operation mode is arithmetic
L1L926 = AMPP_FUNCTION(L1_F_pc[6], L1L925);
--L1L927 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[6]~91
--operation mode is arithmetic
L1L927 = AMPP_FUNCTION(L1_F_pc[6], L1L925);
--M1_registered_cpu_data_master_readdata[8] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[8]
--operation mode is normal
M1_registered_cpu_data_master_readdata[8]_lut_out = !M1L276 & (M1L304 # !U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[8] = DFFEAS(M1_registered_cpu_data_master_readdata[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L89 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~4982
--operation mode is normal
M1L89 = M1_registered_cpu_data_master_readdata[8] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--Q1_internal_incoming_ext_ram_bus_data[8] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[8]
--operation mode is normal
Q1_internal_incoming_ext_ram_bus_data[8]_lut_out = A1L110;
Q1_internal_incoming_ext_ram_bus_data[8] = DFFEAS(Q1_internal_incoming_ext_ram_bus_data[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L90 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~4983
--operation mode is normal
M1L90 = BE1_q_a[8] & (Q1_internal_incoming_ext_ram_bus_data[8] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[8] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[8] # !Q1_cpu_data_master_requests_lan91c111_s1);
--R1_readdata[8] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[8]
--operation mode is normal
R1_readdata[8]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (R1L176) # !L1_M_alu_result[3] & L1_M_alu_result[4] & R1L175;
R1_readdata[8] = DFFEAS(R1_readdata[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L91 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~4984
--operation mode is normal
M1L91 = M1L89 & M1L90 & (R1_readdata[8] # !S1_cpu_data_master_requests_high_res_timer_s1);
--M1_dbs_8_reg_segment_1[0] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[0]
--operation mode is normal
M1_dbs_8_reg_segment_1[0]_lut_out = Q1_internal_incoming_ext_ram_bus_data[0];
M1_dbs_8_reg_segment_1[0] = DFFEAS(M1_dbs_8_reg_segment_1[0]_lut_out, DE1__clk0, E1_data_out, , M1L309, , , , );
--M1L92 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~4985
--operation mode is normal
M1L92 = M1_registered_cpu_data_master_readdata[8] & (M1_dbs_8_reg_segment_1[0] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[8] & !GB1L18 & (M1_dbs_8_reg_segment_1[0] # !Q1_cpu_data_master_requests_ext_flash_s1);
--KB1_readdata[8] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[8]
--operation mode is normal
KB1_readdata[8]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (KB1L177) # !L1_M_alu_result[3] & L1_M_alu_result[4] & KB1L176;
KB1_readdata[8] = DFFEAS(KB1_readdata[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L93 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~4986
--operation mode is normal
M1L93 = M1L95 & (KB1_readdata[8] # !LB1L3 # !LB1L2);
--HE1_readdata[8] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[8]
--operation mode is normal
HE1_readdata[8]_lut_out = NB1L3 & (L1_M_alu_result[2] & HE1_control_reg[8] # !L1_M_alu_result[2] & (HE1L1));
HE1_readdata[8] = DFFEAS(HE1_readdata[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L94 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~4987
--operation mode is normal
M1L94 = M1L80 & M1L91 & M1L93 & M1L96;
--FC1L11 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[8]~1224
--operation mode is normal
FC1L11 = AMPP_FUNCTION(PD1_q_a[8], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--F1_edge_capture[3] is std_1s10:inst|button_pio:the_button_pio|edge_capture[3]
--operation mode is normal
F1_edge_capture[3]_lut_out = !F1L17 & (F1_edge_capture[3] # F1_d2_data_in[3] $ F1_d1_data_in[3]);
F1_edge_capture[3] = DFFEAS(F1_edge_capture[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--F1_edge_capture[1] is std_1s10:inst|button_pio:the_button_pio|edge_capture[1]
--operation mode is normal
F1_edge_capture[1]_lut_out = !F1L17 & (F1_edge_capture[1] # F1_d2_data_in[1] $ F1_d1_data_in[1]);
F1_edge_capture[1] = DFFEAS(F1_edge_capture[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--F1_irq_mask[1] is std_1s10:inst|button_pio:the_button_pio|irq_mask[1]
--operation mode is normal
F1_irq_mask[1]_lut_out = L1_M_st_data[1];
F1_irq_mask[1] = DFFEAS(F1_irq_mask[1]_lut_out, DE1__clk0, E1_data_out, , F1L23, , , , );
--F1_irq_mask[3] is std_1s10:inst|button_pio:the_button_pio|irq_mask[3]
--operation mode is normal
F1_irq_mask[3]_lut_out = L1_M_st_data[3];
F1_irq_mask[3] = DFFEAS(F1_irq_mask[3]_lut_out, DE1__clk0, E1_data_out, , F1L23, , , , );
--L1L1161 is std_1s10:inst|cpu:the_cpu|M_ipending_reg_nxt[5]~169
--operation mode is normal
L1L1161 = AMPP_FUNCTION(F1_edge_capture[3], F1_edge_capture[1], F1_irq_mask[1], F1_irq_mask[3]);
--F1_edge_capture[2] is std_1s10:inst|button_pio:the_button_pio|edge_capture[2]
--operation mode is normal
F1_edge_capture[2]_lut_out = !F1L17 & (F1_edge_capture[2] # F1_d2_data_in[2] $ F1_d1_data_in[2]);
F1_edge_capture[2] = DFFEAS(F1_edge_capture[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--F1_edge_capture[0] is std_1s10:inst|button_pio:the_button_pio|edge_capture[0]
--operation mode is normal
F1_edge_capture[0]_lut_out = !F1L17 & (F1_edge_capture[0] # F1_d2_data_in[0] $ F1_d1_data_in[0]);
F1_edge_capture[0] = DFFEAS(F1_edge_capture[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--F1_irq_mask[0] is std_1s10:inst|button_pio:the_button_pio|irq_mask[0]
--operation mode is normal
F1_irq_mask[0]_lut_out = L1_M_st_data[0];
F1_irq_mask[0] = DFFEAS(F1_irq_mask[0]_lut_out, DE1__clk0, E1_data_out, , F1L23, , , , );
--F1_irq_mask[2] is std_1s10:inst|button_pio:the_button_pio|irq_mask[2]
--operation mode is normal
F1_irq_mask[2]_lut_out = L1_M_st_data[2];
F1_irq_mask[2] = DFFEAS(F1_irq_mask[2]_lut_out, DE1__clk0, E1_data_out, , F1L23, , , , );
--L1L1162 is std_1s10:inst|cpu:the_cpu|M_ipending_reg_nxt[5]~170
--operation mode is normal
L1L1162 = AMPP_FUNCTION(F1_edge_capture[2], F1_edge_capture[0], F1_irq_mask[0], F1_irq_mask[2]);
--SC1_internal_oci_ienable1[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[5]
--operation mode is normal
SC1_internal_oci_ienable1[5] = AMPP_FUNCTION(DE1__clk0, L1_M_st_data[5], E1_data_out, SC1L12);
--M1L64 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4988
--operation mode is normal
M1L64 = L1_M_alu_result[7] & A1L138 & L1_M_alu_result[4] # !L1_M_alu_result[7] & (!L1_M_alu_result[4]) # !EB1L3;
--M1_registered_cpu_data_master_readdata[5] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[5]
--operation mode is normal
M1_registered_cpu_data_master_readdata[5]_lut_out = M1L301 & M1L273 & (FB1_za_data[5] # !GB1L18);
M1_registered_cpu_data_master_readdata[5] = DFFEAS(M1_registered_cpu_data_master_readdata[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L65 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4989
--operation mode is normal
M1L65 = M1L64 & (M1_registered_cpu_data_master_readdata[5] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--R1_readdata[5] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[5]
--operation mode is normal
R1_readdata[5]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (R1L170) # !L1_M_alu_result[3] & L1_M_alu_result[4] & R1L169;
R1_readdata[5] = DFFEAS(R1_readdata[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L66 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4990
--operation mode is normal
M1L66 = !NB1_cpu_data_master_granted_sysid_control_slave & (R1_readdata[5] # !S1L2 # !LB1L2);
--M1L67 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4991
--operation mode is normal
M1L67 = BE1_q_a[5] & (Q1_internal_incoming_ext_ram_bus_data[5] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[5] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[5] # !Q1_cpu_data_master_requests_lan91c111_s1);
--HE1_readdata[5] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[5]
--operation mode is normal
HE1_readdata[5]_lut_out = !L1_M_alu_result[4] & (L1_M_alu_result[2] & HE1L57 # !L1_M_alu_result[2] & (HE1L58));
HE1_readdata[5] = DFFEAS(HE1_readdata[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L68 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4992
--operation mode is normal
M1L68 = M1L66 & M1L67 & (HE1_readdata[5] # !QB1_cpu_data_master_granted_uart1_s1);
--KB1_readdata[5] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[5]
--operation mode is normal
KB1_readdata[5]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (KB1L171) # !L1_M_alu_result[3] & L1_M_alu_result[4] & KB1L170;
KB1_readdata[5] = DFFEAS(KB1_readdata[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1_dbs_8_reg_segment_0[5] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[5]
--operation mode is normal
M1_dbs_8_reg_segment_0[5]_lut_out = Q1_internal_incoming_ext_ram_bus_data[5];
M1_dbs_8_reg_segment_0[5] = DFFEAS(M1_dbs_8_reg_segment_0[5]_lut_out, DE1__clk0, E1_data_out, , M1L308, , , , );
--M1L69 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4993
--operation mode is normal
M1L69 = M1_registered_cpu_data_master_readdata[5] & (M1_dbs_8_reg_segment_0[5] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[5] & !GB1L18 & (M1_dbs_8_reg_segment_0[5] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L70 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4994
--operation mode is normal
M1L70 = M1L65 & M1L68 & M1L231 & M1L71;
--N1L106 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~1863
--operation mode is normal
N1L106 = P1L23 & (SC1_internal_oci_ienable1[5] # !FC1L21) # !P1L23 & !PD1_q_a[5] & (SC1_internal_oci_ienable1[5] # !FC1L21);
--NC1_q_b[5] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[5] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1355, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L920 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[3]~92
--operation mode is arithmetic
L1L920 = AMPP_FUNCTION(L1_F_pc[3], L1L919);
--L1L921 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[3]~93
--operation mode is arithmetic
L1L921 = AMPP_FUNCTION(L1_F_pc[3], L1L919);
--L1L922 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[4]~94
--operation mode is arithmetic
L1L922 = AMPP_FUNCTION(L1_F_pc[4], L1L921);
--L1L923 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[4]~95
--operation mode is arithmetic
L1L923 = AMPP_FUNCTION(L1_F_pc[4], L1L921);
--M1L72 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~4995
--operation mode is normal
M1L72 = L1_M_alu_result[7] & A1L137 & L1_M_alu_result[4] # !L1_M_alu_result[7] & (!L1_M_alu_result[4]) # !EB1L3;
--M1_registered_cpu_data_master_readdata[6] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[6]
--operation mode is normal
M1_registered_cpu_data_master_readdata[6]_lut_out = M1L302 & M1L274 & (FB1_za_data[6] # !GB1L18);
M1_registered_cpu_data_master_readdata[6] = DFFEAS(M1_registered_cpu_data_master_readdata[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L73 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~4996
--operation mode is normal
M1L73 = M1L72 & (M1_registered_cpu_data_master_readdata[6] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L74 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~4997
--operation mode is normal
M1L74 = BE1_q_a[6] & (Q1_internal_incoming_ext_ram_bus_data[6] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[6] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[6] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_dbs_8_reg_segment_0[6] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[6]
--operation mode is normal
M1_dbs_8_reg_segment_0[6]_lut_out = Q1_internal_incoming_ext_ram_bus_data[6];
M1_dbs_8_reg_segment_0[6] = DFFEAS(M1_dbs_8_reg_segment_0[6]_lut_out, DE1__clk0, E1_data_out, , M1L308, , , , );
--M1L75 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~4998
--operation mode is normal
M1L75 = M1_registered_cpu_data_master_readdata[6] & (M1_dbs_8_reg_segment_0[6] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[6] & !GB1L18 & (M1_dbs_8_reg_segment_0[6] # !Q1_cpu_data_master_requests_ext_flash_s1);
--R1_readdata[6] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[6]
--operation mode is normal
R1_readdata[6]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (R1L172) # !L1_M_alu_result[3] & L1_M_alu_result[4] & R1L171;
R1_readdata[6] = DFFEAS(R1_readdata[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L76 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~4999
--operation mode is normal
M1L76 = M1L79 & (R1_readdata[6] # !S1L2 # !LB1L2);
--HE1_readdata[6] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[6]
--operation mode is normal
HE1_readdata[6]_lut_out = !L1_M_alu_result[4] & (L1_M_alu_result[2] & HE1L59 # !L1_M_alu_result[2] & (HE1L60));
HE1_readdata[6] = DFFEAS(HE1_readdata[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L77 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5000
--operation mode is normal
M1L77 = M1L74 & M1L76 & (HE1_readdata[6] # !QB1_cpu_data_master_granted_uart1_s1);
--KB1_readdata[6] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[6]
--operation mode is normal
KB1_readdata[6]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (KB1L173) # !L1_M_alu_result[3] & L1_M_alu_result[4] & KB1L172;
KB1_readdata[6] = DFFEAS(KB1_readdata[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L78 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5001
--operation mode is normal
M1L78 = M1L73 & M1L77 & (KB1_readdata[6] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--FC1L9 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[6]~1225
--operation mode is normal
FC1L9 = AMPP_FUNCTION(PD1_q_a[6], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--NC1_q_b[6] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[6] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1358, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--MC1_q_b[0] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[0] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1340, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[0] is std_1s10:inst|cpu:the_cpu|W_wr_data[0]
--operation mode is normal
L1_W_wr_data[0] = AMPP_FUNCTION(DE1__clk0, L1L1340, E1_data_out, L1_W_stall);
--L1L1216 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[0]~1369
--operation mode is normal
L1L1216 = AMPP_FUNCTION(QC1_result[0], QC1_result[32]);
--L1_d_readdata_d1[0] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[0]
--operation mode is normal
L1_d_readdata_d1[0] = AMPP_FUNCTION(DE1__clk0, M1L26, FC1L1, FC1L2, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--MC1_q_b[1] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[1] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1343, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[1] is std_1s10:inst|cpu:the_cpu|W_wr_data[1]
--operation mode is normal
L1_W_wr_data[1] = AMPP_FUNCTION(DE1__clk0, L1L1343, E1_data_out, L1_W_stall);
--L1L1217 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[1]~1370
--operation mode is normal
L1L1217 = AMPP_FUNCTION(QC1_result[1], QC1_result[33]);
--L1_d_readdata_d1[1] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[1]
--operation mode is normal
L1_d_readdata_d1[1] = AMPP_FUNCTION(DE1__clk0, M1L35, FC1L3, FC1L4, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--KE1_do_load_shifter is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|do_load_shifter
--operation mode is normal
KE1_do_load_shifter_lut_out = !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] & (KE1L28 & KE1_internal_tx_ready);
KE1_do_load_shifter = DFFEAS(KE1_do_load_shifter_lut_out, DE1__clk0, E1_data_out, , , , , , );
--KE1_baud_clk_en is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_clk_en
--operation mode is normal
KE1_baud_clk_en_lut_out = KE1L21 & KE1L22 & (!KE1_baud_rate_counter[8]);
KE1_baud_clk_en = DFFEAS(KE1_baud_clk_en_lut_out, DE1__clk0, E1_data_out, , , , , , );
--KE1L39 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]~2816
--operation mode is normal
KE1L39 = KE1_do_load_shifter # KE1_baud_clk_en & (KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] # !KE1L28);
--HE1_internal_tx_data[2] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[2]
--operation mode is normal
HE1_internal_tx_data[2]_lut_out = L1_M_st_data[2];
HE1_internal_tx_data[2] = DFFEAS(HE1_internal_tx_data[2]_lut_out, DE1__clk0, E1_data_out, , HE1L64, , , , );
--HE1_internal_tx_data[1] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[1]
--operation mode is normal
HE1_internal_tx_data[1]_lut_out = L1_M_st_data[1];
HE1_internal_tx_data[1] = DFFEAS(HE1_internal_tx_data[1]_lut_out, DE1__clk0, E1_data_out, , HE1L64, , , , );
--HE1_internal_tx_data[0] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[0]
--operation mode is normal
HE1_internal_tx_data[0]_lut_out = L1_M_st_data[0];
HE1_internal_tx_data[0] = DFFEAS(HE1_internal_tx_data[0]_lut_out, DE1__clk0, E1_data_out, , HE1L64, , , , );
--HE1_internal_tx_data[3] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[3]
--operation mode is normal
HE1_internal_tx_data[3]_lut_out = L1_M_st_data[3];
HE1_internal_tx_data[3] = DFFEAS(HE1_internal_tx_data[3]_lut_out, DE1__clk0, E1_data_out, , HE1L64, , , , );
--HE1_internal_tx_data[4] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[4]
--operation mode is normal
HE1_internal_tx_data[4]_lut_out = L1_M_st_data[4];
HE1_internal_tx_data[4] = DFFEAS(HE1_internal_tx_data[4]_lut_out, DE1__clk0, E1_data_out, , HE1L64, , , , );
--HE1_internal_tx_data[5] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[5]
--operation mode is normal
HE1_internal_tx_data[5]_lut_out = L1_M_st_data[5];
HE1_internal_tx_data[5] = DFFEAS(HE1_internal_tx_data[5]_lut_out, DE1__clk0, E1_data_out, , HE1L64, , , , );
--HE1_internal_tx_data[6] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[6]
--operation mode is normal
HE1_internal_tx_data[6]_lut_out = L1_M_st_data[6];
HE1_internal_tx_data[6] = DFFEAS(HE1_internal_tx_data[6]_lut_out, DE1__clk0, E1_data_out, , HE1L64, , , , );
--HE1_internal_tx_data[7] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[7]
--operation mode is normal
HE1_internal_tx_data[7]_lut_out = L1_M_st_data[7];
HE1_internal_tx_data[7] = DFFEAS(HE1_internal_tx_data[7]_lut_out, DE1__clk0, E1_data_out, , HE1L64, , , , );
--L1_D_pc[9] is std_1s10:inst|cpu:the_cpu|D_pc[9]
--operation mode is normal
L1_D_pc[9] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[9], E1_data_out, L1_W_stall);
--L1_reset_d1 is std_1s10:inst|cpu:the_cpu|reset_d1
--operation mode is normal
L1_reset_d1 = AMPP_FUNCTION(DE1__clk0, E1_data_out);
--L1_D_pc[8] is std_1s10:inst|cpu:the_cpu|D_pc[8]
--operation mode is normal
L1_D_pc[8] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[8], E1_data_out, L1_W_stall);
--L1_D_pc[7] is std_1s10:inst|cpu:the_cpu|D_pc[7]
--operation mode is normal
L1_D_pc[7] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[7], E1_data_out, L1_W_stall);
--L1_D_pc[6] is std_1s10:inst|cpu:the_cpu|D_pc[6]
--operation mode is normal
L1_D_pc[6] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[6], E1_data_out, L1_W_stall);
--L1_D_pc[5] is std_1s10:inst|cpu:the_cpu|D_pc[5]
--operation mode is normal
L1_D_pc[5] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[5], E1_data_out, L1_W_stall);
--L1_D_pc[4] is std_1s10:inst|cpu:the_cpu|D_pc[4]
--operation mode is normal
L1_D_pc[4] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[4], E1_data_out, L1_W_stall);
--L1_M_ienable_reg[1] is std_1s10:inst|cpu:the_cpu|M_ienable_reg[1]
--operation mode is normal
L1_M_ienable_reg[1] = AMPP_FUNCTION(DE1__clk0, L1L409, E1_data_out, L1L1150);
--L1_M_bstatus_reg is std_1s10:inst|cpu:the_cpu|M_bstatus_reg
--operation mode is normal
L1_M_bstatus_reg = AMPP_FUNCTION(DE1__clk0, L1_M_bstatus_reg, L1L406, L1_M_status_reg_pie, L1_E_wrctl_bstatus, E1_data_out, L1_E_ctrl_break, L1L1335);
--L1_M_estatus_reg is std_1s10:inst|cpu:the_cpu|M_estatus_reg
--operation mode is normal
L1_M_estatus_reg = AMPP_FUNCTION(DE1__clk0, L1_M_estatus_reg, L1L406, L1_M_status_reg_pie, L1_E_wrctl_estatus, E1_data_out, L1_E_ctrl_exception, L1L1335);
--L1_M_ienable_reg[0] is std_1s10:inst|cpu:the_cpu|M_ienable_reg[0]
--operation mode is normal
L1_M_ienable_reg[0] = AMPP_FUNCTION(DE1__clk0, L1L406, E1_data_out, L1L1150);
--L1L184 is std_1s10:inst|cpu:the_cpu|D_control_rd_data_without_mmu_regs[0]~424
--operation mode is normal
L1L184 = AMPP_FUNCTION(L1_D_iw[7], L1_M_estatus_reg, L1_D_iw[6], L1_M_ienable_reg[0]);
--L1L185 is std_1s10:inst|cpu:the_cpu|D_control_rd_data_without_mmu_regs[0]~425
--operation mode is normal
L1L185 = AMPP_FUNCTION(L1_M_status_reg_pie, L1_M_ipending_reg[0], L1_D_iw[8], L1L184);
--NC1_q_b[1] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[1] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1343, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--NC1_q_b[0] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[0] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1340, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--DD1L118Q is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir_out[0]~reg0
--operation mode is normal
DD1L118Q = AMPP_FUNCTION(!A1L6, VC1_internal_monitor_ready, !C1_CLR_SIGNAL);
--ME3_Q[4] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4]
--operation mode is normal
ME3_Q[4] = AMPP_FUNCTION(!A1L6, RE1_state[4], ME3_Q[5], !C1_CLR_SIGNAL, ME3L4);
--ME3_Q[6] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[6]
--operation mode is normal
ME3_Q[6] = AMPP_FUNCTION(!A1L6, A1L2, !C1_CLR_SIGNAL, RE1_state[4], C1_IRSR_ENA);
--SE1_dffe1a[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[3]
--operation mode is normal
SE1_dffe1a[3] = AMPP_FUNCTION(!A1L6, ME3_Q[1], ME3_Q[2], C1L26, ME3_Q[3], !C1_CLR_SIGNAL, C1L5);
--C1L17 is sld_hub:sld_hub_inst|IR_MUX_SEL[1]~26
--operation mode is normal
C1L17 = AMPP_FUNCTION(ME3_Q[4], ME3_Q[6], SE1_dffe1a[3]);
--ME3_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1]
--operation mode is normal
ME3_Q[1] = AMPP_FUNCTION(!A1L6, C1L17, DD1L119Q, ME3_Q[2], !C1_CLR_SIGNAL, RE1_state[4], ME3L4);
--ME4_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0]
--operation mode is normal
ME4_Q[0] = AMPP_FUNCTION(!A1L6, ME4L3, ME4_Q[0], C1L21, !C1_CLR_SIGNAL);
--ME3_Q[3] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3]
--operation mode is normal
ME3_Q[3] = AMPP_FUNCTION(!A1L6, RE1_state[4], ME3_Q[4], !C1_CLR_SIGNAL, ME3L4);
--ME3_Q[5] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5]
--operation mode is normal
ME3_Q[5] = AMPP_FUNCTION(!A1L6, ME3_Q[6], ME3_Q[5], RE1_state[4], C1_jtag_debug_mode_usr1, !C1_CLR_SIGNAL);
--C1L16 is sld_hub:sld_hub_inst|IR_MUX_SEL[0]~27
--operation mode is normal
C1L16 = AMPP_FUNCTION(ME3_Q[3], ME3_Q[5], SE1_dffe1a[3]);
--ME3L3 is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]~7772
--operation mode is normal
ME3L3 = AMPP_FUNCTION(C1L17, ME4_Q[0], C1L16);
--C1_IRSR_ENA is sld_hub:sld_hub_inst|IRSR_ENA
--operation mode is normal
C1_IRSR_ENA = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, RE1_state[4], RE1_state[3]);
--ME3L4 is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]~7773
--operation mode is normal
ME3L4 = AMPP_FUNCTION(C1_IRSR_ENA, RE1_state[4], C1L17, C1L16);
--C1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q
--operation mode is normal
C1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(!A1L6, C1_jtag_debug_mode_usr1, C1_OK_TO_UPDATE_IR_Q, RE1_state[4], RE1_state[8], VCC);
--C1L18 is sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21
--operation mode is normal
C1L18 = AMPP_FUNCTION(RE1_state[4], C1_jtag_debug_mode_usr1, C1_OK_TO_UPDATE_IR_Q, A1L8);
--NE1_WORD_SR[1] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[1]
--operation mode is normal
NE1_WORD_SR[1] = AMPP_FUNCTION(!A1L6, NE1_WORD_SR[2], NE1L15, RE1_state[4], NE1_clear_signal, VCC, NE1L20);
--NE1_word_counter[4] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[4]
--operation mode is normal
NE1_word_counter[4] = AMPP_FUNCTION(!A1L6, NE1L1, NE1_word_counter[3], NE1L11, NE1_clear_signal, VCC, NE1L21);
--NE1_word_counter[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]
--operation mode is normal
NE1_word_counter[0] = AMPP_FUNCTION(!A1L6, NE1L2, NE1_word_counter[3], NE1L11, NE1_clear_signal, VCC, NE1L21);
--NE1_word_counter[1] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[1]
--operation mode is normal
NE1_word_counter[1] = AMPP_FUNCTION(!A1L6, RE1_state[8], C1_jtag_debug_mode_usr1, NE1L4, VCC, NE1L21);
--NE1_word_counter[2] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[2]
--operation mode is normal
NE1_word_counter[2] = AMPP_FUNCTION(!A1L6, RE1_state[8], C1_jtag_debug_mode_usr1, NE1L6, VCC, NE1L21);
--NE1_word_counter[3] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[3]
--operation mode is normal
NE1_word_counter[3] = AMPP_FUNCTION(!A1L6, NE1L8, NE1_word_counter[3], NE1L11, NE1_clear_signal, VCC, NE1L21);
--NE1L16 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux3~33
--operation mode is normal
NE1L16 = AMPP_FUNCTION(NE1_word_counter[0], NE1_word_counter[1], NE1_word_counter[2], NE1_word_counter[3]);
--NE1L19 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1248
--operation mode is normal
NE1L19 = AMPP_FUNCTION(NE1_word_counter[4], NE1L16);
--NE1_clear_signal is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|clear_signal
--operation mode is normal
NE1_clear_signal = AMPP_FUNCTION(RE1_state[8], C1_jtag_debug_mode_usr1);
--C1_jtag_debug_mode_usr0 is sld_hub:sld_hub_inst|jtag_debug_mode_usr0
--operation mode is normal
C1_jtag_debug_mode_usr0 = AMPP_FUNCTION(!A1L6, C1L6, C1L7, QE1_dffs[1], QE1_dffs[0], RE1_state[0], RE1_state[12]);
--NE1L20 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1250
--operation mode is normal
NE1L20 = AMPP_FUNCTION(NE1_clear_signal, C1_jtag_debug_mode_usr0, RE1_state[4], RE1_state[3]);
--C1L11 is sld_hub:sld_hub_inst|HUB_BYPASS_REG~9
--operation mode is normal
C1L11 = AMPP_FUNCTION(altera_internal_jtag, RE1_state[4]);
--C1L26 is sld_hub:sld_hub_inst|jtag_debug_mode~2
--operation mode is normal
C1L26 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, C1_jtag_debug_mode_usr0);
--ME3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2]
--operation mode is normal
ME3_Q[2] = AMPP_FUNCTION(!A1L6, RE1_state[4], ME3_Q[3], !C1_CLR_SIGNAL, ME3L4);
--C1L4 is sld_hub:sld_hub_inst|comb~96
--operation mode is normal
C1L4 = AMPP_FUNCTION(RE1_state[4], RE1_state[3], C1_jtag_debug_mode_usr0, C1_jtag_debug_mode_usr1);
--QD1_rvalid is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rvalid
--operation mode is normal
QD1_rvalid = AMPP_FUNCTION(DE1__clk0, QD1_rvalid0, E1_data_out);
--QD1_td_shift[1] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[1]
--operation mode is normal
QD1_td_shift[1] = AMPP_FUNCTION(!A1L6, QD1L53, QD1L54, QD1L63, !C1_CLR_SIGNAL, QD1L52);
--QD1_count[9] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[9]
--operation mode is normal
QD1_count[9] = AMPP_FUNCTION(!A1L6, QD1L55, GND, VCC, C1_CLR_SIGNAL, QD1L52);
--QD1L65 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift~3494
--operation mode is normal
QD1L65 = AMPP_FUNCTION(QD1_rvalid, QD1_td_shift[1], QD1_count[9]);
--QD1_state is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|state
--operation mode is normal
QD1_state = AMPP_FUNCTION(!A1L6, QD1L1, C1L11, QD1_state, QD1L36, !C1_CLR_SIGNAL);
--QD1L66 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift~3495
--operation mode is normal
QD1L66 = AMPP_FUNCTION(altera_internal_jtag, QD1_state);
--QD1_count[1] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[1]
--operation mode is normal
QD1_count[1] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1_count[0], !C1_CLR_SIGNAL, QD1L52);
--QD1_td_shift[9] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]
--operation mode is normal
QD1_td_shift[9] = AMPP_FUNCTION(!A1L6, QD1_td_shift[10], QD1_rdata[7], QD1_count[9], !C1_CLR_SIGNAL, !RE1_state[4], QD1L52);
--QD1_user_saw_rvalid is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|user_saw_rvalid
--operation mode is normal
QD1_user_saw_rvalid = AMPP_FUNCTION(!A1L6, QD1_td_shift[0], QD1_user_saw_rvalid, QD1_count[0], QD1L69, !C1_CLR_SIGNAL);
--T1_t_dav is std_1s10:inst|jtag_uart:the_jtag_uart|t_dav
--operation mode is normal
T1_t_dav_lut_out = WD2_b_full;
T1_t_dav = DFFEAS(T1_t_dav_lut_out, DE1__clk0, E1_data_out, , , , , , );
--QD1L67 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift~3496
--operation mode is normal
QD1L67 = AMPP_FUNCTION(QD1L66, QD1L65, QD1L62, T1_t_dav);
--QD1L1 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|always0~50
--operation mode is normal
QD1L1 = AMPP_FUNCTION(ME8_Q[1], C1_jtag_debug_mode, C1_jtag_debug_mode_usr1, ME2_Q[0]);
--QD1L52 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3497
--operation mode is normal
QD1L52 = AMPP_FUNCTION(QD1L1, RE1_state[4], RE1_state[3]);
--DD1_sr[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[1]
--operation mode is normal
DD1_sr[1] = AMPP_FUNCTION(!A1L6, DD1L130, DD1_sr[2], DD1L143, DD1L141, !C1_CLR_SIGNAL, DD1L6);
--DD1_DRsize[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[1]
--operation mode is normal
DD1_DRsize[1] = AMPP_FUNCTION(!A1L6, DD1L121, !C1_CLR_SIGNAL, DD1_st_updateir);
--DD1_DRsize[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[2]
--operation mode is normal
DD1_DRsize[2] = AMPP_FUNCTION(!A1L6, DD1L121, !C1_CLR_SIGNAL, DD1_st_updateir);
--DD1_DRsize[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]
--operation mode is normal
DD1_DRsize[0] = AMPP_FUNCTION(!A1L6, ME5_Q[0], ME5_Q[1], !C1_CLR_SIGNAL, DD1_st_updateir);
--DD1L139 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux45~157
--operation mode is normal
DD1L139 = AMPP_FUNCTION(DD1_DRsize[1], DD1_DRsize[2], DD1_DRsize[0]);
--DD1L140 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux45~158
--operation mode is normal
DD1L140 = AMPP_FUNCTION(DD1_sr[1], DD1L139, altera_internal_jtag);
--VC1_internal_monitor_ready is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_ready
--operation mode is normal
VC1_internal_monitor_ready = AMPP_FUNCTION(DE1__clk0, VC1L7, L1_M_st_data[0], SC1L13, DD1L190, VCC);
--DD1L5 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19888
--operation mode is normal
DD1L5 = AMPP_FUNCTION(VC1_internal_monitor_ready, DD1_ir[0], DD1_ir[1]);
--DD1_in_between_shiftdr_and_updatedr is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|in_between_shiftdr_and_updatedr
--operation mode is normal
DD1_in_between_shiftdr_and_updatedr = AMPP_FUNCTION(!A1L6, DD1_st_shiftdr, DD1_in_between_shiftdr_and_updatedr, DD1_st_updatedr, !C1_CLR_SIGNAL);
--DD1L142 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process2~233
--operation mode is normal
DD1L142 = AMPP_FUNCTION(A1L5, DD1_in_between_shiftdr_and_updatedr);
--DD1L143 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process2~234
--operation mode is normal
DD1L143 = AMPP_FUNCTION(DD1L144, A1L5);
--DD1L6 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19890
--operation mode is normal
DD1L6 = AMPP_FUNCTION(DD1L144, A1L5, DD1_in_between_shiftdr_and_updatedr, DD1_st_updateir);
--QE1_dffs[1] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1]
--operation mode is normal
QE1_dffs[1] = AMPP_FUNCTION(!A1L6, QE1_dffs[2], RE1_state[0], RE1_state[11]);
--QE1_dffs[9] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]
--operation mode is normal
QE1_dffs[9] = AMPP_FUNCTION(!A1L6, altera_internal_jtag, RE1_state[0], RE1_state[11]);
--QE1_dffs[8] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8]
--operation mode is normal
QE1_dffs[8] = AMPP_FUNCTION(!A1L6, QE1_dffs[9], RE1_state[0], RE1_state[11]);
--QE1_dffs[7] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7]
--operation mode is normal
QE1_dffs[7] = AMPP_FUNCTION(!A1L6, QE1_dffs[8], RE1_state[0], RE1_state[11]);
--QE1_dffs[6] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6]
--operation mode is normal
QE1_dffs[6] = AMPP_FUNCTION(!A1L6, QE1_dffs[7], RE1_state[0], RE1_state[11]);
--C1L6 is sld_hub:sld_hub_inst|Equal0~83
--operation mode is normal
C1L6 = AMPP_FUNCTION(QE1_dffs[9], QE1_dffs[8], QE1_dffs[7], QE1_dffs[6]);
--QE1_dffs[3] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3]
--operation mode is normal
QE1_dffs[3] = AMPP_FUNCTION(!A1L6, QE1_dffs[4], RE1_state[0], RE1_state[11]);
--QE1_dffs[2] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2]
--operation mode is normal
QE1_dffs[2] = AMPP_FUNCTION(!A1L6, QE1_dffs[3], RE1_state[0], RE1_state[11]);
--QE1_dffs[5] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[5]
--operation mode is normal
QE1_dffs[5] = AMPP_FUNCTION(!A1L6, QE1_dffs[6], RE1_state[0], RE1_state[11]);
--QE1_dffs[4] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4]
--operation mode is normal
QE1_dffs[4] = AMPP_FUNCTION(!A1L6, QE1_dffs[5], RE1_state[0], RE1_state[11]);
--C1L7 is sld_hub:sld_hub_inst|Equal0~84
--operation mode is normal
C1L7 = AMPP_FUNCTION(QE1_dffs[3], QE1_dffs[2], QE1_dffs[5], QE1_dffs[4]);
--QE1_dffs[0] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0]
--operation mode is normal
QE1_dffs[0] = AMPP_FUNCTION(!A1L6, QE1_dffs[1], RE1_state[0], RE1_state[11]);
--RE1_state[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]
--operation mode is normal
RE1_state[0] = AMPP_FUNCTION(!A1L6, RE1_state[9], RE1L18, RE1_state[0], A1L8, VCC);
--RE1_state[12] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12]
--operation mode is normal
RE1_state[12] = AMPP_FUNCTION(!A1L6, RE1_state[10], RE1_state[11], VCC, A1L8);
--RE1_state[7] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[7]
--operation mode is normal
RE1_state[7] = AMPP_FUNCTION(!A1L6, RE1_state[6], A1L8, VCC);
--RE1_state[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2]
--operation mode is normal
RE1_state[2] = AMPP_FUNCTION(!A1L6, RE1_state[8], RE1_state[1], RE1_state[15], VCC, A1L8);
--RE1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
--operation mode is normal
RE1_state[5] = AMPP_FUNCTION(!A1L6, RE1_state[4], RE1_state[3], A1L8, VCC);
--HE1L16 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~100
--operation mode is normal
HE1L16 = L1_M_alu_result[2] & (!L1_M_alu_result[3]);
--L1_M_st_data[31] is std_1s10:inst|cpu:the_cpu|M_st_data[31]
--operation mode is normal
L1_M_st_data[31] = AMPP_FUNCTION(DE1__clk0, L1L1302, L1L797, L1L789, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--L1_M_st_data[30] is std_1s10:inst|cpu:the_cpu|M_st_data[30]
--operation mode is normal
L1_M_st_data[30] = AMPP_FUNCTION(DE1__clk0, L1L1300, L1L796, L1L788, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--L1_M_st_data[29] is std_1s10:inst|cpu:the_cpu|M_st_data[29]
--operation mode is normal
L1_M_st_data[29] = AMPP_FUNCTION(DE1__clk0, L1L1298, L1L795, L1L787, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--L1_M_st_data[28] is std_1s10:inst|cpu:the_cpu|M_st_data[28]
--operation mode is normal
L1_M_st_data[28] = AMPP_FUNCTION(DE1__clk0, L1L1296, L1L794, L1L786, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--L1_M_st_data[27] is std_1s10:inst|cpu:the_cpu|M_st_data[27]
--operation mode is normal
L1_M_st_data[27] = AMPP_FUNCTION(DE1__clk0, L1L1294, L1L793, L1L785, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--L1_M_st_data[26] is std_1s10:inst|cpu:the_cpu|M_st_data[26]
--operation mode is normal
L1_M_st_data[26] = AMPP_FUNCTION(DE1__clk0, L1L1292, L1L792, L1L784, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--L1_M_st_data[25] is std_1s10:inst|cpu:the_cpu|M_st_data[25]
--operation mode is normal
L1_M_st_data[25] = AMPP_FUNCTION(DE1__clk0, L1L1290, L1L791, L1L783, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--L1_M_st_data[24] is std_1s10:inst|cpu:the_cpu|M_st_data[24]
--operation mode is normal
L1_M_st_data[24] = AMPP_FUNCTION(DE1__clk0, L1L1288, L1L790, L1L782, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--Q1L271 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[7]~2841
--operation mode is normal
Q1L271 = M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & L1_M_st_data[31] # !M1_internal_cpu_data_master_dbs_address[0] & (L1_M_st_data[23])) # !M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[31] & (!M1_internal_cpu_data_master_dbs_address[0]);
--Q1L272 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[7]~2842
--operation mode is normal
Q1L272 = Q1L271 # L1_M_st_data[15] & M1_internal_cpu_data_master_dbs_address[0] & !M1_internal_cpu_data_master_dbs_address[1];
--M1L260 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|Equal1~40
--operation mode is normal
M1L260 = M1_internal_cpu_data_master_dbs_address[1] # M1_internal_cpu_data_master_dbs_address[0];
--Q1L273 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[31]~2843
--operation mode is normal
Q1L273 = Q1L52 & !Q1L48 & (Q1L12 # Q1L14);
--Q1L269 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[6]~2845
--operation mode is normal
Q1L269 = M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & L1_M_st_data[30] # !M1_internal_cpu_data_master_dbs_address[0] & (L1_M_st_data[22])) # !M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[30] & (!M1_internal_cpu_data_master_dbs_address[0]);
--Q1L270 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[6]~2846
--operation mode is normal
Q1L270 = Q1L269 # L1_M_st_data[14] & M1_internal_cpu_data_master_dbs_address[0] & !M1_internal_cpu_data_master_dbs_address[1];
--Q1L267 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[5]~2848
--operation mode is normal
Q1L267 = M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & L1_M_st_data[29] # !M1_internal_cpu_data_master_dbs_address[0] & (L1_M_st_data[21])) # !M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[29] & (!M1_internal_cpu_data_master_dbs_address[0]);
--Q1L268 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[5]~2849
--operation mode is normal
Q1L268 = Q1L267 # L1_M_st_data[13] & M1_internal_cpu_data_master_dbs_address[0] & !M1_internal_cpu_data_master_dbs_address[1];
--Q1L265 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[4]~2851
--operation mode is normal
Q1L265 = M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & L1_M_st_data[28] # !M1_internal_cpu_data_master_dbs_address[0] & (L1_M_st_data[20])) # !M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[28] & (!M1_internal_cpu_data_master_dbs_address[0]);
--Q1L266 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[4]~2852
--operation mode is normal
Q1L266 = Q1L265 # L1_M_st_data[12] & M1_internal_cpu_data_master_dbs_address[0] & !M1_internal_cpu_data_master_dbs_address[1];
--Q1L263 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[3]~2854
--operation mode is normal
Q1L263 = M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & L1_M_st_data[27] # !M1_internal_cpu_data_master_dbs_address[0] & (L1_M_st_data[19])) # !M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[27] & (!M1_internal_cpu_data_master_dbs_address[0]);
--Q1L264 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[3]~2855
--operation mode is normal
Q1L264 = Q1L263 # L1_M_st_data[11] & M1_internal_cpu_data_master_dbs_address[0] & !M1_internal_cpu_data_master_dbs_address[1];
--Q1L261 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[2]~2857
--operation mode is normal
Q1L261 = M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & L1_M_st_data[26] # !M1_internal_cpu_data_master_dbs_address[0] & (L1_M_st_data[18])) # !M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[26] & (!M1_internal_cpu_data_master_dbs_address[0]);
--Q1L262 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[2]~2858
--operation mode is normal
Q1L262 = Q1L261 # L1_M_st_data[10] & M1_internal_cpu_data_master_dbs_address[0] & !M1_internal_cpu_data_master_dbs_address[1];
--Q1L259 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[1]~2860
--operation mode is normal
Q1L259 = M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & L1_M_st_data[25] # !M1_internal_cpu_data_master_dbs_address[0] & (L1_M_st_data[17])) # !M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[25] & (!M1_internal_cpu_data_master_dbs_address[0]);
--Q1L260 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[1]~2861
--operation mode is normal
Q1L260 = Q1L259 # L1_M_st_data[9] & M1_internal_cpu_data_master_dbs_address[0] & !M1_internal_cpu_data_master_dbs_address[1];
--Q1L257 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[0]~2863
--operation mode is normal
Q1L257 = M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & L1_M_st_data[24] # !M1_internal_cpu_data_master_dbs_address[0] & (L1_M_st_data[16])) # !M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[24] & (!M1_internal_cpu_data_master_dbs_address[0]);
--Q1L258 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[0]~2864
--operation mode is normal
Q1L258 = Q1L257 # L1_M_st_data[8] & M1_internal_cpu_data_master_dbs_address[0] & !M1_internal_cpu_data_master_dbs_address[1];
--FB1_active_data[31] is std_1s10:inst|sdram:the_sdram|active_data[31]
--operation mode is normal
FB1_active_data[31]_lut_out = FB1L12 & (FB1L14 & (EE1L160) # !FB1L14 & FB1_active_data[31]) # !FB1L12 & FB1_active_data[31];
FB1_active_data[31] = DFFEAS(FB1_active_data[31]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[31] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[31]
--operation mode is normal
EE1_entry_1[31]_lut_out = L1_M_st_data[31];
EE1_entry_1[31] = DFFEAS(EE1_entry_1[31]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[31] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[31]
--operation mode is normal
EE1_entry_0[31]_lut_out = L1_M_st_data[31];
EE1_entry_0[31] = DFFEAS(EE1_entry_0[31]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L160 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[31]~510
--operation mode is normal
EE1L160 = EE1_rd_address & EE1_entry_1[31] # !EE1_rd_address & (EE1_entry_0[31]);
--FB1L509 is std_1s10:inst|sdram:the_sdram|Mux118~1212
--operation mode is normal
FB1L509 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[31] # !FB1_m_state[1] & (EE1L160)) # !FB1_f_select & FB1_active_data[31];
--FB1L510 is std_1s10:inst|sdram:the_sdram|Mux118~1213
--operation mode is normal
FB1L510 = !FB1_m_state[3] & (FB1_m_state[4] $ FB1_m_state[1]);
--FB1L548 is std_1s10:inst|sdram:the_sdram|Mux154~541
--operation mode is normal
FB1L548 = FB1_m_state[4] & FB1L298 & (!FB1_m_state[3]);
--FB1_active_data[30] is std_1s10:inst|sdram:the_sdram|active_data[30]
--operation mode is normal
FB1_active_data[30]_lut_out = FB1L65 & (FB1L66 & EE1L159 # !FB1L66 & (FB1_active_data[30])) # !FB1L65 & (FB1_active_data[30]);
FB1_active_data[30] = DFFEAS(FB1_active_data[30]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[30] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[30]
--operation mode is normal
EE1_entry_1[30]_lut_out = L1_M_st_data[30];
EE1_entry_1[30] = DFFEAS(EE1_entry_1[30]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[30] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[30]
--operation mode is normal
EE1_entry_0[30]_lut_out = L1_M_st_data[30];
EE1_entry_0[30] = DFFEAS(EE1_entry_0[30]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L159 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[30]~511
--operation mode is normal
EE1L159 = EE1_rd_address & EE1_entry_1[30] # !EE1_rd_address & (EE1_entry_0[30]);
--FB1L512 is std_1s10:inst|sdram:the_sdram|Mux119~1170
--operation mode is normal
FB1L512 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[30] # !FB1_m_state[1] & (EE1L159)) # !FB1_f_select & FB1_active_data[30];
--FB1_active_data[29] is std_1s10:inst|sdram:the_sdram|active_data[29]
--operation mode is normal
FB1_active_data[29]_lut_out = FB1L12 & (FB1L14 & (EE1L158) # !FB1L14 & FB1_active_data[29]) # !FB1L12 & FB1_active_data[29];
FB1_active_data[29] = DFFEAS(FB1_active_data[29]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[29] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[29]
--operation mode is normal
EE1_entry_1[29]_lut_out = L1_M_st_data[29];
EE1_entry_1[29] = DFFEAS(EE1_entry_1[29]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[29] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[29]
--operation mode is normal
EE1_entry_0[29]_lut_out = L1_M_st_data[29];
EE1_entry_0[29] = DFFEAS(EE1_entry_0[29]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L158 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[29]~512
--operation mode is normal
EE1L158 = EE1_rd_address & EE1_entry_1[29] # !EE1_rd_address & (EE1_entry_0[29]);
--FB1L513 is std_1s10:inst|sdram:the_sdram|Mux120~1170
--operation mode is normal
FB1L513 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[29] # !FB1_m_state[1] & (EE1L158)) # !FB1_f_select & FB1_active_data[29];
--FB1_active_data[28] is std_1s10:inst|sdram:the_sdram|active_data[28]
--operation mode is normal
FB1_active_data[28]_lut_out = FB1L65 & (FB1L66 & EE1L157 # !FB1L66 & (FB1_active_data[28])) # !FB1L65 & (FB1_active_data[28]);
FB1_active_data[28] = DFFEAS(FB1_active_data[28]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[28] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[28]
--operation mode is normal
EE1_entry_1[28]_lut_out = L1_M_st_data[28];
EE1_entry_1[28] = DFFEAS(EE1_entry_1[28]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[28] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[28]
--operation mode is normal
EE1_entry_0[28]_lut_out = L1_M_st_data[28];
EE1_entry_0[28] = DFFEAS(EE1_entry_0[28]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L157 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[28]~513
--operation mode is normal
EE1L157 = EE1_rd_address & EE1_entry_1[28] # !EE1_rd_address & (EE1_entry_0[28]);
--FB1L514 is std_1s10:inst|sdram:the_sdram|Mux121~1170
--operation mode is normal
FB1L514 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[28] # !FB1_m_state[1] & (EE1L157)) # !FB1_f_select & FB1_active_data[28];
--FB1_active_data[27] is std_1s10:inst|sdram:the_sdram|active_data[27]
--operation mode is normal
FB1_active_data[27]_lut_out = FB1L12 & (FB1L14 & (EE1L156) # !FB1L14 & FB1_active_data[27]) # !FB1L12 & FB1_active_data[27];
FB1_active_data[27] = DFFEAS(FB1_active_data[27]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[27] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[27]
--operation mode is normal
EE1_entry_1[27]_lut_out = L1_M_st_data[27];
EE1_entry_1[27] = DFFEAS(EE1_entry_1[27]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[27] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[27]
--operation mode is normal
EE1_entry_0[27]_lut_out = L1_M_st_data[27];
EE1_entry_0[27] = DFFEAS(EE1_entry_0[27]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L156 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[27]~514
--operation mode is normal
EE1L156 = EE1_rd_address & EE1_entry_1[27] # !EE1_rd_address & (EE1_entry_0[27]);
--FB1L515 is std_1s10:inst|sdram:the_sdram|Mux122~1170
--operation mode is normal
FB1L515 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[27] # !FB1_m_state[1] & (EE1L156)) # !FB1_f_select & FB1_active_data[27];
--FB1_active_data[26] is std_1s10:inst|sdram:the_sdram|active_data[26]
--operation mode is normal
FB1_active_data[26]_lut_out = FB1L65 & (FB1L66 & EE1L155 # !FB1L66 & (FB1_active_data[26])) # !FB1L65 & (FB1_active_data[26]);
FB1_active_data[26] = DFFEAS(FB1_active_data[26]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[26] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[26]
--operation mode is normal
EE1_entry_1[26]_lut_out = L1_M_st_data[26];
EE1_entry_1[26] = DFFEAS(EE1_entry_1[26]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[26] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[26]
--operation mode is normal
EE1_entry_0[26]_lut_out = L1_M_st_data[26];
EE1_entry_0[26] = DFFEAS(EE1_entry_0[26]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L155 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[26]~515
--operation mode is normal
EE1L155 = EE1_rd_address & EE1_entry_1[26] # !EE1_rd_address & (EE1_entry_0[26]);
--FB1L516 is std_1s10:inst|sdram:the_sdram|Mux123~1170
--operation mode is normal
FB1L516 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[26] # !FB1_m_state[1] & (EE1L155)) # !FB1_f_select & FB1_active_data[26];
--FB1_active_data[25] is std_1s10:inst|sdram:the_sdram|active_data[25]
--operation mode is normal
FB1_active_data[25]_lut_out = FB1L12 & (FB1L14 & (EE1L154) # !FB1L14 & FB1_active_data[25]) # !FB1L12 & FB1_active_data[25];
FB1_active_data[25] = DFFEAS(FB1_active_data[25]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[25] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[25]
--operation mode is normal
EE1_entry_1[25]_lut_out = L1_M_st_data[25];
EE1_entry_1[25] = DFFEAS(EE1_entry_1[25]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[25] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[25]
--operation mode is normal
EE1_entry_0[25]_lut_out = L1_M_st_data[25];
EE1_entry_0[25] = DFFEAS(EE1_entry_0[25]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L154 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[25]~516
--operation mode is normal
EE1L154 = EE1_rd_address & EE1_entry_1[25] # !EE1_rd_address & (EE1_entry_0[25]);
--FB1L517 is std_1s10:inst|sdram:the_sdram|Mux124~1170
--operation mode is normal
FB1L517 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[25] # !FB1_m_state[1] & (EE1L154)) # !FB1_f_select & FB1_active_data[25];
--FB1_active_data[24] is std_1s10:inst|sdram:the_sdram|active_data[24]
--operation mode is normal
FB1_active_data[24]_lut_out = FB1L65 & (FB1L66 & EE1L153 # !FB1L66 & (FB1_active_data[24])) # !FB1L65 & (FB1_active_data[24]);
FB1_active_data[24] = DFFEAS(FB1_active_data[24]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[24] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[24]
--operation mode is normal
EE1_entry_1[24]_lut_out = L1_M_st_data[24];
EE1_entry_1[24] = DFFEAS(EE1_entry_1[24]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[24] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[24]
--operation mode is normal
EE1_entry_0[24]_lut_out = L1_M_st_data[24];
EE1_entry_0[24] = DFFEAS(EE1_entry_0[24]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L153 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[24]~517
--operation mode is normal
EE1L153 = EE1_rd_address & EE1_entry_1[24] # !EE1_rd_address & (EE1_entry_0[24]);
--FB1L518 is std_1s10:inst|sdram:the_sdram|Mux125~1170
--operation mode is normal
FB1L518 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[24] # !FB1_m_state[1] & (EE1L153)) # !FB1_f_select & FB1_active_data[24];
--FB1_active_data[23] is std_1s10:inst|sdram:the_sdram|active_data[23]
--operation mode is normal
FB1_active_data[23]_lut_out = FB1L12 & (FB1L14 & (EE1L152) # !FB1L14 & FB1_active_data[23]) # !FB1L12 & FB1_active_data[23];
FB1_active_data[23] = DFFEAS(FB1_active_data[23]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[23] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[23]
--operation mode is normal
EE1_entry_1[23]_lut_out = L1_M_st_data[23];
EE1_entry_1[23] = DFFEAS(EE1_entry_1[23]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[23] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[23]
--operation mode is normal
EE1_entry_0[23]_lut_out = L1_M_st_data[23];
EE1_entry_0[23] = DFFEAS(EE1_entry_0[23]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L152 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[23]~518
--operation mode is normal
EE1L152 = EE1_rd_address & EE1_entry_1[23] # !EE1_rd_address & (EE1_entry_0[23]);
--FB1L519 is std_1s10:inst|sdram:the_sdram|Mux126~1170
--operation mode is normal
FB1L519 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[23] # !FB1_m_state[1] & (EE1L152)) # !FB1_f_select & FB1_active_data[23];
--FB1_active_data[22] is std_1s10:inst|sdram:the_sdram|active_data[22]
--operation mode is normal
FB1_active_data[22]_lut_out = FB1L65 & (FB1L66 & EE1L151 # !FB1L66 & (FB1_active_data[22])) # !FB1L65 & (FB1_active_data[22]);
FB1_active_data[22] = DFFEAS(FB1_active_data[22]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[22] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[22]
--operation mode is normal
EE1_entry_1[22]_lut_out = L1_M_st_data[22];
EE1_entry_1[22] = DFFEAS(EE1_entry_1[22]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[22] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[22]
--operation mode is normal
EE1_entry_0[22]_lut_out = L1_M_st_data[22];
EE1_entry_0[22] = DFFEAS(EE1_entry_0[22]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L151 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[22]~519
--operation mode is normal
EE1L151 = EE1_rd_address & EE1_entry_1[22] # !EE1_rd_address & (EE1_entry_0[22]);
--FB1L520 is std_1s10:inst|sdram:the_sdram|Mux127~1170
--operation mode is normal
FB1L520 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[22] # !FB1_m_state[1] & (EE1L151)) # !FB1_f_select & FB1_active_data[22];
--FB1_active_data[21] is std_1s10:inst|sdram:the_sdram|active_data[21]
--operation mode is normal
FB1_active_data[21]_lut_out = FB1L12 & (FB1L14 & (EE1L150) # !FB1L14 & FB1_active_data[21]) # !FB1L12 & FB1_active_data[21];
FB1_active_data[21] = DFFEAS(FB1_active_data[21]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[21] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[21]
--operation mode is normal
EE1_entry_1[21]_lut_out = L1_M_st_data[21];
EE1_entry_1[21] = DFFEAS(EE1_entry_1[21]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[21] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[21]
--operation mode is normal
EE1_entry_0[21]_lut_out = L1_M_st_data[21];
EE1_entry_0[21] = DFFEAS(EE1_entry_0[21]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L150 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[21]~520
--operation mode is normal
EE1L150 = EE1_rd_address & EE1_entry_1[21] # !EE1_rd_address & (EE1_entry_0[21]);
--FB1L521 is std_1s10:inst|sdram:the_sdram|Mux128~1170
--operation mode is normal
FB1L521 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[21] # !FB1_m_state[1] & (EE1L150)) # !FB1_f_select & FB1_active_data[21];
--FB1_active_data[20] is std_1s10:inst|sdram:the_sdram|active_data[20]
--operation mode is normal
FB1_active_data[20]_lut_out = FB1L65 & (FB1L66 & EE1L149 # !FB1L66 & (FB1_active_data[20])) # !FB1L65 & (FB1_active_data[20]);
FB1_active_data[20] = DFFEAS(FB1_active_data[20]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[20] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[20]
--operation mode is normal
EE1_entry_1[20]_lut_out = L1_M_st_data[20];
EE1_entry_1[20] = DFFEAS(EE1_entry_1[20]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[20] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[20]
--operation mode is normal
EE1_entry_0[20]_lut_out = L1_M_st_data[20];
EE1_entry_0[20] = DFFEAS(EE1_entry_0[20]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L149 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[20]~521
--operation mode is normal
EE1L149 = EE1_rd_address & EE1_entry_1[20] # !EE1_rd_address & (EE1_entry_0[20]);
--FB1L522 is std_1s10:inst|sdram:the_sdram|Mux129~1170
--operation mode is normal
FB1L522 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[20] # !FB1_m_state[1] & (EE1L149)) # !FB1_f_select & FB1_active_data[20];
--FB1_active_data[19] is std_1s10:inst|sdram:the_sdram|active_data[19]
--operation mode is normal
FB1_active_data[19]_lut_out = FB1L12 & (FB1L14 & (EE1L148) # !FB1L14 & FB1_active_data[19]) # !FB1L12 & FB1_active_data[19];
FB1_active_data[19] = DFFEAS(FB1_active_data[19]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[19] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[19]
--operation mode is normal
EE1_entry_1[19]_lut_out = L1_M_st_data[19];
EE1_entry_1[19] = DFFEAS(EE1_entry_1[19]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[19] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[19]
--operation mode is normal
EE1_entry_0[19]_lut_out = L1_M_st_data[19];
EE1_entry_0[19] = DFFEAS(EE1_entry_0[19]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L148 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[19]~522
--operation mode is normal
EE1L148 = EE1_rd_address & EE1_entry_1[19] # !EE1_rd_address & (EE1_entry_0[19]);
--FB1L523 is std_1s10:inst|sdram:the_sdram|Mux130~1170
--operation mode is normal
FB1L523 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[19] # !FB1_m_state[1] & (EE1L148)) # !FB1_f_select & FB1_active_data[19];
--FB1_active_data[18] is std_1s10:inst|sdram:the_sdram|active_data[18]
--operation mode is normal
FB1_active_data[18]_lut_out = FB1L65 & (FB1L66 & EE1L147 # !FB1L66 & (FB1_active_data[18])) # !FB1L65 & (FB1_active_data[18]);
FB1_active_data[18] = DFFEAS(FB1_active_data[18]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[18] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[18]
--operation mode is normal
EE1_entry_1[18]_lut_out = L1_M_st_data[18];
EE1_entry_1[18] = DFFEAS(EE1_entry_1[18]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[18] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[18]
--operation mode is normal
EE1_entry_0[18]_lut_out = L1_M_st_data[18];
EE1_entry_0[18] = DFFEAS(EE1_entry_0[18]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L147 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[18]~523
--operation mode is normal
EE1L147 = EE1_rd_address & EE1_entry_1[18] # !EE1_rd_address & (EE1_entry_0[18]);
--FB1L524 is std_1s10:inst|sdram:the_sdram|Mux131~1170
--operation mode is normal
FB1L524 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[18] # !FB1_m_state[1] & (EE1L147)) # !FB1_f_select & FB1_active_data[18];
--FB1_active_data[17] is std_1s10:inst|sdram:the_sdram|active_data[17]
--operation mode is normal
FB1_active_data[17]_lut_out = FB1L12 & (FB1L14 & (EE1L146) # !FB1L14 & FB1_active_data[17]) # !FB1L12 & FB1_active_data[17];
FB1_active_data[17] = DFFEAS(FB1_active_data[17]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[17] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[17]
--operation mode is normal
EE1_entry_1[17]_lut_out = L1_M_st_data[17];
EE1_entry_1[17] = DFFEAS(EE1_entry_1[17]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[17] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[17]
--operation mode is normal
EE1_entry_0[17]_lut_out = L1_M_st_data[17];
EE1_entry_0[17] = DFFEAS(EE1_entry_0[17]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L146 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[17]~524
--operation mode is normal
EE1L146 = EE1_rd_address & EE1_entry_1[17] # !EE1_rd_address & (EE1_entry_0[17]);
--FB1L525 is std_1s10:inst|sdram:the_sdram|Mux132~1170
--operation mode is normal
FB1L525 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[17] # !FB1_m_state[1] & (EE1L146)) # !FB1_f_select & FB1_active_data[17];
--FB1_active_data[16] is std_1s10:inst|sdram:the_sdram|active_data[16]
--operation mode is normal
FB1_active_data[16]_lut_out = FB1L65 & (FB1L66 & EE1L145 # !FB1L66 & (FB1_active_data[16])) # !FB1L65 & (FB1_active_data[16]);
FB1_active_data[16] = DFFEAS(FB1_active_data[16]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[16] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[16]
--operation mode is normal
EE1_entry_1[16]_lut_out = L1_M_st_data[16];
EE1_entry_1[16] = DFFEAS(EE1_entry_1[16]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[16] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[16]
--operation mode is normal
EE1_entry_0[16]_lut_out = L1_M_st_data[16];
EE1_entry_0[16] = DFFEAS(EE1_entry_0[16]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L145 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[16]~525
--operation mode is normal
EE1L145 = EE1_rd_address & EE1_entry_1[16] # !EE1_rd_address & (EE1_entry_0[16]);
--FB1L526 is std_1s10:inst|sdram:the_sdram|Mux133~1170
--operation mode is normal
FB1L526 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[16] # !FB1_m_state[1] & (EE1L145)) # !FB1_f_select & FB1_active_data[16];
--FB1_active_data[15] is std_1s10:inst|sdram:the_sdram|active_data[15]
--operation mode is normal
FB1_active_data[15]_lut_out = FB1L12 & (FB1L14 & (EE1L144) # !FB1L14 & FB1_active_data[15]) # !FB1L12 & FB1_active_data[15];
FB1_active_data[15] = DFFEAS(FB1_active_data[15]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[15] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[15]
--operation mode is normal
EE1_entry_1[15]_lut_out = L1_M_st_data[15];
EE1_entry_1[15] = DFFEAS(EE1_entry_1[15]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[15] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[15]
--operation mode is normal
EE1_entry_0[15]_lut_out = L1_M_st_data[15];
EE1_entry_0[15] = DFFEAS(EE1_entry_0[15]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L144 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[15]~526
--operation mode is normal
EE1L144 = EE1_rd_address & EE1_entry_1[15] # !EE1_rd_address & (EE1_entry_0[15]);
--FB1L527 is std_1s10:inst|sdram:the_sdram|Mux134~1170
--operation mode is normal
FB1L527 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[15] # !FB1_m_state[1] & (EE1L144)) # !FB1_f_select & FB1_active_data[15];
--FB1_active_data[14] is std_1s10:inst|sdram:the_sdram|active_data[14]
--operation mode is normal
FB1_active_data[14]_lut_out = FB1L65 & (FB1L66 & EE1L143 # !FB1L66 & (FB1_active_data[14])) # !FB1L65 & (FB1_active_data[14]);
FB1_active_data[14] = DFFEAS(FB1_active_data[14]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[14] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[14]
--operation mode is normal
EE1_entry_1[14]_lut_out = L1_M_st_data[14];
EE1_entry_1[14] = DFFEAS(EE1_entry_1[14]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[14] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[14]
--operation mode is normal
EE1_entry_0[14]_lut_out = L1_M_st_data[14];
EE1_entry_0[14] = DFFEAS(EE1_entry_0[14]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L143 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[14]~527
--operation mode is normal
EE1L143 = EE1_rd_address & EE1_entry_1[14] # !EE1_rd_address & (EE1_entry_0[14]);
--FB1L528 is std_1s10:inst|sdram:the_sdram|Mux135~1170
--operation mode is normal
FB1L528 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[14] # !FB1_m_state[1] & (EE1L143)) # !FB1_f_select & FB1_active_data[14];
--FB1_active_data[13] is std_1s10:inst|sdram:the_sdram|active_data[13]
--operation mode is normal
FB1_active_data[13]_lut_out = FB1L12 & (FB1L14 & (EE1L142) # !FB1L14 & FB1_active_data[13]) # !FB1L12 & FB1_active_data[13];
FB1_active_data[13] = DFFEAS(FB1_active_data[13]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[13] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[13]
--operation mode is normal
EE1_entry_1[13]_lut_out = L1_M_st_data[13];
EE1_entry_1[13] = DFFEAS(EE1_entry_1[13]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[13] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[13]
--operation mode is normal
EE1_entry_0[13]_lut_out = L1_M_st_data[13];
EE1_entry_0[13] = DFFEAS(EE1_entry_0[13]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L142 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[13]~528
--operation mode is normal
EE1L142 = EE1_rd_address & EE1_entry_1[13] # !EE1_rd_address & (EE1_entry_0[13]);
--FB1L529 is std_1s10:inst|sdram:the_sdram|Mux136~1170
--operation mode is normal
FB1L529 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[13] # !FB1_m_state[1] & (EE1L142)) # !FB1_f_select & FB1_active_data[13];
--FB1_active_data[12] is std_1s10:inst|sdram:the_sdram|active_data[12]
--operation mode is normal
FB1_active_data[12]_lut_out = FB1L65 & (FB1L66 & EE1L141 # !FB1L66 & (FB1_active_data[12])) # !FB1L65 & (FB1_active_data[12]);
FB1_active_data[12] = DFFEAS(FB1_active_data[12]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[12] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[12]
--operation mode is normal
EE1_entry_1[12]_lut_out = L1_M_st_data[12];
EE1_entry_1[12] = DFFEAS(EE1_entry_1[12]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[12] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[12]
--operation mode is normal
EE1_entry_0[12]_lut_out = L1_M_st_data[12];
EE1_entry_0[12] = DFFEAS(EE1_entry_0[12]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L141 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[12]~529
--operation mode is normal
EE1L141 = EE1_rd_address & EE1_entry_1[12] # !EE1_rd_address & (EE1_entry_0[12]);
--FB1L530 is std_1s10:inst|sdram:the_sdram|Mux137~1170
--operation mode is normal
FB1L530 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[12] # !FB1_m_state[1] & (EE1L141)) # !FB1_f_select & FB1_active_data[12];
--FB1_active_data[11] is std_1s10:inst|sdram:the_sdram|active_data[11]
--operation mode is normal
FB1_active_data[11]_lut_out = FB1L12 & (FB1L14 & (EE1L140) # !FB1L14 & FB1_active_data[11]) # !FB1L12 & FB1_active_data[11];
FB1_active_data[11] = DFFEAS(FB1_active_data[11]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[11] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[11]
--operation mode is normal
EE1_entry_1[11]_lut_out = L1_M_st_data[11];
EE1_entry_1[11] = DFFEAS(EE1_entry_1[11]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[11] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[11]
--operation mode is normal
EE1_entry_0[11]_lut_out = L1_M_st_data[11];
EE1_entry_0[11] = DFFEAS(EE1_entry_0[11]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L140 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[11]~530
--operation mode is normal
EE1L140 = EE1_rd_address & EE1_entry_1[11] # !EE1_rd_address & (EE1_entry_0[11]);
--FB1L531 is std_1s10:inst|sdram:the_sdram|Mux138~1170
--operation mode is normal
FB1L531 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[11] # !FB1_m_state[1] & (EE1L140)) # !FB1_f_select & FB1_active_data[11];
--FB1_active_data[10] is std_1s10:inst|sdram:the_sdram|active_data[10]
--operation mode is normal
FB1_active_data[10]_lut_out = FB1L65 & (FB1L66 & EE1L139 # !FB1L66 & (FB1_active_data[10])) # !FB1L65 & (FB1_active_data[10]);
FB1_active_data[10] = DFFEAS(FB1_active_data[10]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[10] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[10]
--operation mode is normal
EE1_entry_1[10]_lut_out = L1_M_st_data[10];
EE1_entry_1[10] = DFFEAS(EE1_entry_1[10]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[10] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[10]
--operation mode is normal
EE1_entry_0[10]_lut_out = L1_M_st_data[10];
EE1_entry_0[10] = DFFEAS(EE1_entry_0[10]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L139 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[10]~531
--operation mode is normal
EE1L139 = EE1_rd_address & EE1_entry_1[10] # !EE1_rd_address & (EE1_entry_0[10]);
--FB1L532 is std_1s10:inst|sdram:the_sdram|Mux139~1170
--operation mode is normal
FB1L532 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[10] # !FB1_m_state[1] & (EE1L139)) # !FB1_f_select & FB1_active_data[10];
--FB1_active_data[9] is std_1s10:inst|sdram:the_sdram|active_data[9]
--operation mode is normal
FB1_active_data[9]_lut_out = FB1L12 & (FB1L14 & (EE1L138) # !FB1L14 & FB1_active_data[9]) # !FB1L12 & FB1_active_data[9];
FB1_active_data[9] = DFFEAS(FB1_active_data[9]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[9] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[9]
--operation mode is normal
EE1_entry_1[9]_lut_out = L1_M_st_data[9];
EE1_entry_1[9] = DFFEAS(EE1_entry_1[9]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[9] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[9]
--operation mode is normal
EE1_entry_0[9]_lut_out = L1_M_st_data[9];
EE1_entry_0[9] = DFFEAS(EE1_entry_0[9]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L138 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[9]~532
--operation mode is normal
EE1L138 = EE1_rd_address & EE1_entry_1[9] # !EE1_rd_address & (EE1_entry_0[9]);
--FB1L533 is std_1s10:inst|sdram:the_sdram|Mux140~1170
--operation mode is normal
FB1L533 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[9] # !FB1_m_state[1] & (EE1L138)) # !FB1_f_select & FB1_active_data[9];
--FB1_active_data[8] is std_1s10:inst|sdram:the_sdram|active_data[8]
--operation mode is normal
FB1_active_data[8]_lut_out = FB1L65 & (FB1L66 & EE1L137 # !FB1L66 & (FB1_active_data[8])) # !FB1L65 & (FB1_active_data[8]);
FB1_active_data[8] = DFFEAS(FB1_active_data[8]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[8] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[8]
--operation mode is normal
EE1_entry_1[8]_lut_out = L1_M_st_data[8];
EE1_entry_1[8] = DFFEAS(EE1_entry_1[8]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[8] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[8]
--operation mode is normal
EE1_entry_0[8]_lut_out = L1_M_st_data[8];
EE1_entry_0[8] = DFFEAS(EE1_entry_0[8]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L137 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[8]~533
--operation mode is normal
EE1L137 = EE1_rd_address & EE1_entry_1[8] # !EE1_rd_address & (EE1_entry_0[8]);
--FB1L534 is std_1s10:inst|sdram:the_sdram|Mux141~1170
--operation mode is normal
FB1L534 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[8] # !FB1_m_state[1] & (EE1L137)) # !FB1_f_select & FB1_active_data[8];
--FB1_active_data[7] is std_1s10:inst|sdram:the_sdram|active_data[7]
--operation mode is normal
FB1_active_data[7]_lut_out = FB1L12 & (FB1L14 & (EE1L136) # !FB1L14 & FB1_active_data[7]) # !FB1L12 & FB1_active_data[7];
FB1_active_data[7] = DFFEAS(FB1_active_data[7]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[7] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[7]
--operation mode is normal
EE1_entry_1[7]_lut_out = L1_M_st_data[7];
EE1_entry_1[7] = DFFEAS(EE1_entry_1[7]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[7] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[7]
--operation mode is normal
EE1_entry_0[7]_lut_out = L1_M_st_data[7];
EE1_entry_0[7] = DFFEAS(EE1_entry_0[7]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L136 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[7]~534
--operation mode is normal
EE1L136 = EE1_rd_address & EE1_entry_1[7] # !EE1_rd_address & (EE1_entry_0[7]);
--FB1L535 is std_1s10:inst|sdram:the_sdram|Mux142~1170
--operation mode is normal
FB1L535 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[7] # !FB1_m_state[1] & (EE1L136)) # !FB1_f_select & FB1_active_data[7];
--FB1_active_data[6] is std_1s10:inst|sdram:the_sdram|active_data[6]
--operation mode is normal
FB1_active_data[6]_lut_out = FB1L65 & (FB1L66 & EE1L135 # !FB1L66 & (FB1_active_data[6])) # !FB1L65 & (FB1_active_data[6]);
FB1_active_data[6] = DFFEAS(FB1_active_data[6]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[6] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[6]
--operation mode is normal
EE1_entry_1[6]_lut_out = L1_M_st_data[6];
EE1_entry_1[6] = DFFEAS(EE1_entry_1[6]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[6] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[6]
--operation mode is normal
EE1_entry_0[6]_lut_out = L1_M_st_data[6];
EE1_entry_0[6] = DFFEAS(EE1_entry_0[6]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L135 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[6]~535
--operation mode is normal
EE1L135 = EE1_rd_address & EE1_entry_1[6] # !EE1_rd_address & (EE1_entry_0[6]);
--FB1L536 is std_1s10:inst|sdram:the_sdram|Mux143~1170
--operation mode is normal
FB1L536 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[6] # !FB1_m_state[1] & (EE1L135)) # !FB1_f_select & FB1_active_data[6];
--FB1_active_data[5] is std_1s10:inst|sdram:the_sdram|active_data[5]
--operation mode is normal
FB1_active_data[5]_lut_out = FB1L12 & (FB1L14 & (EE1L134) # !FB1L14 & FB1_active_data[5]) # !FB1L12 & FB1_active_data[5];
FB1_active_data[5] = DFFEAS(FB1_active_data[5]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[5] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[5]
--operation mode is normal
EE1_entry_1[5]_lut_out = L1_M_st_data[5];
EE1_entry_1[5] = DFFEAS(EE1_entry_1[5]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[5] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[5]
--operation mode is normal
EE1_entry_0[5]_lut_out = L1_M_st_data[5];
EE1_entry_0[5] = DFFEAS(EE1_entry_0[5]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L134 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[5]~536
--operation mode is normal
EE1L134 = EE1_rd_address & EE1_entry_1[5] # !EE1_rd_address & (EE1_entry_0[5]);
--FB1L537 is std_1s10:inst|sdram:the_sdram|Mux144~1170
--operation mode is normal
FB1L537 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[5] # !FB1_m_state[1] & (EE1L134)) # !FB1_f_select & FB1_active_data[5];
--FB1_active_data[4] is std_1s10:inst|sdram:the_sdram|active_data[4]
--operation mode is normal
FB1_active_data[4]_lut_out = FB1L65 & (FB1L66 & EE1L133 # !FB1L66 & (FB1_active_data[4])) # !FB1L65 & (FB1_active_data[4]);
FB1_active_data[4] = DFFEAS(FB1_active_data[4]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[4] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[4]
--operation mode is normal
EE1_entry_1[4]_lut_out = L1_M_st_data[4];
EE1_entry_1[4] = DFFEAS(EE1_entry_1[4]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[4] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[4]
--operation mode is normal
EE1_entry_0[4]_lut_out = L1_M_st_data[4];
EE1_entry_0[4] = DFFEAS(EE1_entry_0[4]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L133 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[4]~537
--operation mode is normal
EE1L133 = EE1_rd_address & EE1_entry_1[4] # !EE1_rd_address & (EE1_entry_0[4]);
--FB1L538 is std_1s10:inst|sdram:the_sdram|Mux145~1170
--operation mode is normal
FB1L538 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[4] # !FB1_m_state[1] & (EE1L133)) # !FB1_f_select & FB1_active_data[4];
--FB1_active_data[3] is std_1s10:inst|sdram:the_sdram|active_data[3]
--operation mode is normal
FB1_active_data[3]_lut_out = FB1L12 & (FB1L14 & (EE1L132) # !FB1L14 & FB1_active_data[3]) # !FB1L12 & FB1_active_data[3];
FB1_active_data[3] = DFFEAS(FB1_active_data[3]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[3] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[3]
--operation mode is normal
EE1_entry_1[3]_lut_out = L1_M_st_data[3];
EE1_entry_1[3] = DFFEAS(EE1_entry_1[3]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[3] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[3]
--operation mode is normal
EE1_entry_0[3]_lut_out = L1_M_st_data[3];
EE1_entry_0[3] = DFFEAS(EE1_entry_0[3]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L132 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[3]~538
--operation mode is normal
EE1L132 = EE1_rd_address & EE1_entry_1[3] # !EE1_rd_address & (EE1_entry_0[3]);
--FB1L539 is std_1s10:inst|sdram:the_sdram|Mux146~1170
--operation mode is normal
FB1L539 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[3] # !FB1_m_state[1] & (EE1L132)) # !FB1_f_select & FB1_active_data[3];
--FB1_active_data[2] is std_1s10:inst|sdram:the_sdram|active_data[2]
--operation mode is normal
FB1_active_data[2]_lut_out = FB1L65 & (FB1L66 & EE1L131 # !FB1L66 & (FB1_active_data[2])) # !FB1L65 & (FB1_active_data[2]);
FB1_active_data[2] = DFFEAS(FB1_active_data[2]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[2] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[2]
--operation mode is normal
EE1_entry_1[2]_lut_out = L1_M_st_data[2];
EE1_entry_1[2] = DFFEAS(EE1_entry_1[2]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[2] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[2]
--operation mode is normal
EE1_entry_0[2]_lut_out = L1_M_st_data[2];
EE1_entry_0[2] = DFFEAS(EE1_entry_0[2]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L131 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[2]~539
--operation mode is normal
EE1L131 = EE1_rd_address & EE1_entry_1[2] # !EE1_rd_address & (EE1_entry_0[2]);
--FB1L540 is std_1s10:inst|sdram:the_sdram|Mux147~1170
--operation mode is normal
FB1L540 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[2] # !FB1_m_state[1] & (EE1L131)) # !FB1_f_select & FB1_active_data[2];
--FB1_active_data[1] is std_1s10:inst|sdram:the_sdram|active_data[1]
--operation mode is normal
FB1_active_data[1]_lut_out = FB1L12 & (FB1L14 & (EE1L130) # !FB1L14 & FB1_active_data[1]) # !FB1L12 & FB1_active_data[1];
FB1_active_data[1] = DFFEAS(FB1_active_data[1]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[1] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[1]
--operation mode is normal
EE1_entry_1[1]_lut_out = L1_M_st_data[1];
EE1_entry_1[1] = DFFEAS(EE1_entry_1[1]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[1] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[1]
--operation mode is normal
EE1_entry_0[1]_lut_out = L1_M_st_data[1];
EE1_entry_0[1] = DFFEAS(EE1_entry_0[1]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L130 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[1]~540
--operation mode is normal
EE1L130 = EE1_rd_address & EE1_entry_1[1] # !EE1_rd_address & (EE1_entry_0[1]);
--FB1L541 is std_1s10:inst|sdram:the_sdram|Mux148~1170
--operation mode is normal
FB1L541 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[1] # !FB1_m_state[1] & (EE1L130)) # !FB1_f_select & FB1_active_data[1];
--FB1_active_data[0] is std_1s10:inst|sdram:the_sdram|active_data[0]
--operation mode is normal
FB1_active_data[0]_lut_out = FB1L65 & (FB1L66 & EE1L129 # !FB1L66 & (FB1_active_data[0])) # !FB1L65 & (FB1_active_data[0]);
FB1_active_data[0] = DFFEAS(FB1_active_data[0]_lut_out, DE1__clk0, VCC, , , , , , );
--EE1_entry_1[0] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[0]
--operation mode is normal
EE1_entry_1[0]_lut_out = L1_M_st_data[0];
EE1_entry_1[0] = DFFEAS(EE1_entry_1[0]_lut_out, DE1__clk0, VCC, , EE1L123, , , , );
--EE1_entry_0[0] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[0]
--operation mode is normal
EE1_entry_0[0]_lut_out = L1_M_st_data[0];
EE1_entry_0[0] = DFFEAS(EE1_entry_0[0]_lut_out, DE1__clk0, VCC, , EE1L62, , , , );
--EE1L129 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[0]~541
--operation mode is normal
EE1L129 = EE1_rd_address & EE1_entry_1[0] # !EE1_rd_address & (EE1_entry_0[0]);
--FB1L542 is std_1s10:inst|sdram:the_sdram|Mux149~1170
--operation mode is normal
FB1L542 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[0] # !FB1_m_state[1] & (EE1L129)) # !FB1_f_select & FB1_active_data[0];
--L1L113 is std_1s10:inst|cpu:the_cpu|Add6~104
--operation mode is normal
L1L113 = AMPP_FUNCTION(L1_ic_fill_ap_cnt[1], L1_ic_fill_ap_cnt[0]);
--GB1L57 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_counter_enable~42
--operation mode is normal
GB1L57 = GB1_WideOr1 # !GB1L22 & !GB1L18;
--L1L33 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12914
--operation mode is normal
L1L33 = AMPP_FUNCTION(L1L102, L1L938, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[12] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[12]
--operation mode is normal
L1_M_pipe_flush_waddr[12] = AMPP_FUNCTION(DE1__clk0, L1L47, L1L598, L1_E_pc[12], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L34 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12915
--operation mode is normal
L1L34 = AMPP_FUNCTION(L1L89, L1L946, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[16] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[16]
--operation mode is normal
L1_M_pipe_flush_waddr[16] = AMPP_FUNCTION(DE1__clk0, L1L48, L1L602, L1_E_pc[16], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1_ic_tag_clr_valid_bits is std_1s10:inst|cpu:the_cpu|ic_tag_clr_valid_bits
--operation mode is normal
L1_ic_tag_clr_valid_bits = AMPP_FUNCTION(DE1__clk0, L1_ic_tag_clr_valid_bits_nxt, E1_data_out);
--L1_ic_tag_wren is std_1s10:inst|cpu:the_cpu|ic_tag_wren
--operation mode is normal
L1_ic_tag_wren = AMPP_FUNCTION(L1_i_readdatavalid_d1, L1_ic_tag_clr_valid_bits);
--L1_ic_tag_wraddress[0] is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[0]
--operation mode is normal
L1_ic_tag_wraddress[0] = AMPP_FUNCTION(DE1__clk0, L1_M_alu_result[5], L1L1038, L1L1040, L1_reset_d1, E1_data_out);
--L1L863 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[0]~4242
--operation mode is normal
L1L863 = AMPP_FUNCTION(L1_D_br_taken_waddr_partial[3], L1L920, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[3] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[3]
--operation mode is normal
L1_M_pipe_flush_waddr[3] = AMPP_FUNCTION(DE1__clk0, L1L49, L1L589, L1_E_pc[3], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L864 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[0]~4243
--operation mode is normal
L1L864 = AMPP_FUNCTION(L1L865, L1_M_pipe_flush_waddr[3], L1_M_pipe_flush);
--L1L866 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[1]~4244
--operation mode is normal
L1L866 = AMPP_FUNCTION(L1_D_br_taken_waddr_partial[4], L1L922, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[4] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[4]
--operation mode is normal
L1_M_pipe_flush_waddr[4] = AMPP_FUNCTION(DE1__clk0, L1L50, L1L590, L1_E_pc[4], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L867 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[1]~4245
--operation mode is normal
L1L867 = AMPP_FUNCTION(L1L868, L1_M_pipe_flush_waddr[4], L1_M_pipe_flush);
--L1L869 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[2]~4246
--operation mode is normal
L1L869 = AMPP_FUNCTION(L1_D_br_taken_waddr_partial[5], L1L924, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[5] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[5]
--operation mode is normal
L1_M_pipe_flush_waddr[5] = AMPP_FUNCTION(DE1__clk0, L1L51, L1L591, L1_E_pc[5], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L870 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[2]~4247
--operation mode is normal
L1L870 = AMPP_FUNCTION(L1L871, L1_M_pipe_flush_waddr[5], L1_M_pipe_flush);
--L1L872 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[3]~4248
--operation mode is normal
L1L872 = AMPP_FUNCTION(L1_D_br_taken_waddr_partial[6], L1L926, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[6] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[6]
--operation mode is normal
L1_M_pipe_flush_waddr[6] = AMPP_FUNCTION(DE1__clk0, L1L52, L1L592, L1_E_pc[6], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L873 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[3]~4249
--operation mode is normal
L1L873 = AMPP_FUNCTION(L1L874, L1_M_pipe_flush_waddr[6], L1_M_pipe_flush);
--L1L875 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[4]~4250
--operation mode is normal
L1L875 = AMPP_FUNCTION(L1_D_br_taken_waddr_partial[7], L1L928, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[7] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[7]
--operation mode is normal
L1_M_pipe_flush_waddr[7] = AMPP_FUNCTION(DE1__clk0, L1L53, L1L593, L1_E_pc[7], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L876 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[4]~4251
--operation mode is normal
L1L876 = AMPP_FUNCTION(L1L877, L1_M_pipe_flush_waddr[7], L1_M_pipe_flush);
--L1L878 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~4252
--operation mode is normal
L1L878 = AMPP_FUNCTION(L1_D_br_taken_waddr_partial[8], L1L930, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[8] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[8]
--operation mode is normal
L1_M_pipe_flush_waddr[8] = AMPP_FUNCTION(DE1__clk0, L1L54, L1L594, L1_E_pc[8], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L879 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~4253
--operation mode is normal
L1L879 = AMPP_FUNCTION(L1L880, L1_M_pipe_flush_waddr[8], L1_M_pipe_flush);
--L1L881 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[6]~4254
--operation mode is normal
L1L881 = AMPP_FUNCTION(L1_D_br_taken_waddr_partial[9], L1L932, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[9] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[9]
--operation mode is normal
L1_M_pipe_flush_waddr[9] = AMPP_FUNCTION(DE1__clk0, L1L55, L1L595, L1_E_pc[9], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L882 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[6]~4255
--operation mode is normal
L1L882 = AMPP_FUNCTION(L1L883, L1_M_pipe_flush_waddr[9], L1_M_pipe_flush);
--L1L35 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12916
--operation mode is normal
L1L35 = AMPP_FUNCTION(L1L81, L1L954, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[20] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[20]
--operation mode is normal
L1_M_pipe_flush_waddr[20] = AMPP_FUNCTION(DE1__clk0, L1L56, L1L606, L1_E_pc[20], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L36 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12917
--operation mode is normal
L1L36 = AMPP_FUNCTION(L1L83, L1L952, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[19] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[19]
--operation mode is normal
L1_M_pipe_flush_waddr[19] = AMPP_FUNCTION(DE1__clk0, L1L57, L1L605, L1_E_pc[19], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L37 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12918
--operation mode is normal
L1L37 = AMPP_FUNCTION(L1L98, L1L950, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[18] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[18]
--operation mode is normal
L1_M_pipe_flush_waddr[18] = AMPP_FUNCTION(DE1__clk0, L1L58, L1L604, L1_E_pc[18], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L38 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12919
--operation mode is normal
L1L38 = AMPP_FUNCTION(L1L87, L1L948, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[17] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[17]
--operation mode is normal
L1_M_pipe_flush_waddr[17] = AMPP_FUNCTION(DE1__clk0, L1L59, L1L603, L1_E_pc[17], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L39 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12920
--operation mode is normal
L1L39 = AMPP_FUNCTION(L1L95, L1L956, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[21] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[21]
--operation mode is normal
L1_M_pipe_flush_waddr[21] = AMPP_FUNCTION(DE1__clk0, L1L61, L1L607, L1_E_pc[21], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L40 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12921
--operation mode is normal
L1L40 = AMPP_FUNCTION(L1L93, L1L942, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[14] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[14]
--operation mode is normal
L1_M_pipe_flush_waddr[14] = AMPP_FUNCTION(DE1__clk0, L1L63, L1L600, L1_E_pc[14], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L41 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12922
--operation mode is normal
L1L41 = AMPP_FUNCTION(L1L104, L1L936, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[11] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[11]
--operation mode is normal
L1_M_pipe_flush_waddr[11] = AMPP_FUNCTION(DE1__clk0, L1L64, L1L597, L1_E_pc[11], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L42 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12923
--operation mode is normal
L1L42 = AMPP_FUNCTION(L1L85, L1L958, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[22] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[22]
--operation mode is normal
L1_M_pipe_flush_waddr[22] = AMPP_FUNCTION(DE1__clk0, L1L66, L1L608, L1_E_pc[22], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L43 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12924
--operation mode is normal
L1L43 = AMPP_FUNCTION(L1L97, L1L960, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[23] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[23]
--operation mode is normal
L1_M_pipe_flush_waddr[23] = AMPP_FUNCTION(DE1__clk0, L1L67, L1L609, L1_E_pc[23], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L44 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12925
--operation mode is normal
L1L44 = AMPP_FUNCTION(L1L91, L1L944, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[15] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[15]
--operation mode is normal
L1_M_pipe_flush_waddr[15] = AMPP_FUNCTION(DE1__clk0, L1L68, L1L601, L1_E_pc[15], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L45 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12926
--operation mode is normal
L1L45 = AMPP_FUNCTION(L1L100, L1L940, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[13] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[13]
--operation mode is normal
L1_M_pipe_flush_waddr[13] = AMPP_FUNCTION(DE1__clk0, L1L69, L1L599, L1_E_pc[13], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L46 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12927
--operation mode is normal
L1L46 = AMPP_FUNCTION(L1L106, L1L934, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[10] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[10]
--operation mode is normal
L1_M_pipe_flush_waddr[10] = AMPP_FUNCTION(DE1__clk0, L1L70, L1L596, L1_E_pc[10], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1_ic_fill_valid_bits[5] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[5]
--operation mode is normal
L1_ic_fill_valid_bits[5] = AMPP_FUNCTION(DE1__clk0, L1L1071, L1_ic_fill_valid_bits[5], L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, E1_data_out, L1_ic_fill_valid_bits_en);
--L1L837 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[2]~1818
--operation mode is normal
L1L837 = AMPP_FUNCTION(L1_D_br_taken_waddr_partial[2], L1L918, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[2] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[2]
--operation mode is normal
L1_M_pipe_flush_waddr[2] = AMPP_FUNCTION(DE1__clk0, L1L71, L1L588, L1_E_pc[2], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L838 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[2]~1819
--operation mode is normal
L1L838 = AMPP_FUNCTION(L1L839, L1_M_pipe_flush_waddr[2], L1_M_pipe_flush);
--L1_ic_fill_valid_bits[3] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[3]
--operation mode is normal
L1_ic_fill_valid_bits[3] = AMPP_FUNCTION(DE1__clk0, L1L1069, L1_ic_fill_valid_bits[3], L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, E1_data_out, L1_ic_fill_valid_bits_en);
--L1L834 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[1]~1820
--operation mode is normal
L1L834 = AMPP_FUNCTION(L1_D_br_taken_waddr_partial[1], L1L916, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[1] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[1]
--operation mode is normal
L1_M_pipe_flush_waddr[1] = AMPP_FUNCTION(DE1__clk0, L1L72, L1L587, L1_E_pc[1], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L835 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[1]~1821
--operation mode is normal
L1L835 = AMPP_FUNCTION(L1L836, L1_M_pipe_flush_waddr[1], L1_M_pipe_flush);
--L1_ic_fill_valid_bits[1] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[1]
--operation mode is normal
L1_ic_fill_valid_bits[1] = AMPP_FUNCTION(DE1__clk0, L1L1067, L1_ic_fill_valid_bits[1], L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, E1_data_out, L1_ic_fill_valid_bits_en);
--L1_ic_fill_valid_bits[7] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[7]
--operation mode is normal
L1_ic_fill_valid_bits[7] = AMPP_FUNCTION(DE1__clk0, L1L1072, L1_ic_fill_valid_bits[7], L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, E1_data_out, L1_ic_fill_valid_bits_en);
--L1_ic_fill_valid_bits[2] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[2]
--operation mode is normal
L1_ic_fill_valid_bits[2] = AMPP_FUNCTION(DE1__clk0, L1L1068, L1_ic_fill_valid_bits[2], L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, E1_data_out, L1_ic_fill_valid_bits_en);
--L1_ic_fill_valid_bits[4] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[4]
--operation mode is normal
L1_ic_fill_valid_bits[4] = AMPP_FUNCTION(DE1__clk0, L1L1070, L1_ic_fill_valid_bits[4], L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, E1_data_out, L1_ic_fill_valid_bits_en);
--L1_ic_fill_valid_bits[0] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[0]
--operation mode is normal
L1_ic_fill_valid_bits[0] = AMPP_FUNCTION(DE1__clk0, L1L1066, L1_ic_fill_valid_bits[0], L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, E1_data_out, L1_ic_fill_valid_bits_en);
--L1_ic_fill_valid_bits[6] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[6]
--operation mode is normal
L1_ic_fill_valid_bits[6] = AMPP_FUNCTION(DE1__clk0, L1L828, L1_ic_fill_valid_bits[6], L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, E1_data_out, L1_ic_fill_valid_bits_en);
--L1L831 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[0]~1822
--operation mode is normal
L1L831 = AMPP_FUNCTION(L1_D_br_taken_waddr_partial[0], L1L914, L1_D_issue, L1L161);
--L1_M_pipe_flush_waddr[0] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[0]
--operation mode is normal
L1_M_pipe_flush_waddr[0] = AMPP_FUNCTION(DE1__clk0, L1L73, L1L586, L1_E_pc[0], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L832 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[0]~1823
--operation mode is normal
L1L832 = AMPP_FUNCTION(L1L833, L1_M_pipe_flush_waddr[0], L1_M_pipe_flush);
--L1L433 is std_1s10:inst|cpu:the_cpu|E_ctrl_invalidate_i~117
--operation mode is normal
L1L433 = AMPP_FUNCTION(L1_E_iw[11], L1_E_iw[16], L1_E_iw[13], L1_E_iw[15]);
--N1_cpu_instruction_master_read_but_no_slave_selected is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected
--operation mode is normal
N1_cpu_instruction_master_read_but_no_slave_selected_lut_out = L1_internal_i_read & N1L5 & N1L114 & N1L6;
N1_cpu_instruction_master_read_but_no_slave_selected = DFFEAS(N1_cpu_instruction_master_read_but_no_slave_selected_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]
--operation mode is normal
Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]_lut_out = Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0];
Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] = DFFEAS(Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]
--operation mode is normal
Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]_lut_out = Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0];
Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] = DFFEAS(Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--GB1_cpu_instruction_master_read_data_valid_sdram_s1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_read_data_valid_sdram_s1
--operation mode is normal
GB1_cpu_instruction_master_read_data_valid_sdram_s1 = GE1_fifo_contains_ones_n & FB1_za_valid & GE1_stage_0;
--AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register
--operation mode is normal
AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register_lut_out = AB1L10;
AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register = DFFEAS(AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register_lut_out, DE1__clk0, E1_data_out, , , , , , );
--N1_cpu_instruction_master_dbs_rdv_counter[1] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_dbs_rdv_counter[1]
--operation mode is normal
N1_cpu_instruction_master_dbs_rdv_counter[1]_lut_out = N1_cpu_instruction_master_dbs_rdv_counter[1] $ N1_cpu_instruction_master_dbs_rdv_counter[0];
N1_cpu_instruction_master_dbs_rdv_counter[1] = DFFEAS(N1_cpu_instruction_master_dbs_rdv_counter[1]_lut_out, DE1__clk0, E1_data_out, , Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1], , , , );
--N1_cpu_instruction_master_dbs_rdv_counter[0] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_dbs_rdv_counter[0]
--operation mode is normal
N1_cpu_instruction_master_dbs_rdv_counter[0]_lut_out = !N1_cpu_instruction_master_dbs_rdv_counter[0];
N1_cpu_instruction_master_dbs_rdv_counter[0] = DFFEAS(N1_cpu_instruction_master_dbs_rdv_counter[0]_lut_out, DE1__clk0, E1_data_out, , Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1], , , , );
--Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]
--operation mode is normal
Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]_lut_out = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0];
Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] = DFFEAS(Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--N1L103 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~60
--operation mode is normal
N1L103 = AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register # N1_cpu_instruction_master_dbs_rdv_counter[1] & N1_cpu_instruction_master_dbs_rdv_counter[0] & Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1];
--N1L104 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~61
--operation mode is normal
N1L104 = Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] # Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] # GB1_cpu_instruction_master_read_data_valid_sdram_s1 # N1L103;
--L1L1024 is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[2]~153
--operation mode is normal
L1L1024 = AMPP_FUNCTION(L1_ic_fill_initial_offset[2], L1_D_ic_fill_starting_d1);
--L1L1020 is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset_en~1
--operation mode is normal
L1L1020 = AMPP_FUNCTION(L1_D_ic_fill_starting_d1, L1_i_readdatavalid_d1);
--L1L1021 is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[0]~154
--operation mode is normal
L1L1021 = AMPP_FUNCTION(L1_ic_fill_initial_offset[0], L1_D_ic_fill_starting_d1, L1_ic_fill_dp_offset[0]);
--L1L1022 is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[1]~155
--operation mode is normal
L1L1022 = AMPP_FUNCTION(L1_ic_fill_initial_offset[1], L1_D_ic_fill_starting_d1, L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1]);
--Q1L185 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter_next_value[0]~83
--operation mode is normal
Q1L185 = Q1L194 & Q1_ext_ram_bus_avalon_slave_arb_share_counter[1] & (!Q1_ext_ram_bus_avalon_slave_arb_share_counter[0]);
--FB1_rd_valid[1] is std_1s10:inst|sdram:the_sdram|rd_valid[1]
--operation mode is normal
FB1_rd_valid[1]_lut_out = FB1_rd_valid[0];
FB1_rd_valid[1] = DFFEAS(FB1_rd_valid[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--GE1_stage_2 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_2
--operation mode is normal
GE1_stage_2_lut_out = GE1_full_3 & GE1_stage_3 # !GE1_full_3 & (GB1L19);
GE1_stage_2 = DFFEAS(GE1_stage_2_lut_out, DE1__clk0, VCC, , GE1L24, , , , );
--GE1_full_2 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_2
--operation mode is normal
GE1_full_2_lut_out = FB1_za_valid & (GB1L28 & GE1_full_1 # !GB1L28 & (GE1_full_3)) # !FB1_za_valid & GE1_full_1;
GE1_full_2 = DFFEAS(GE1_full_2_lut_out, DE1__clk0, E1_data_out, , FE1L13, , , , );
--GE1L25 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process10~1
--operation mode is normal
GE1L25 = FB1_za_valid # GB1L28 & (!GE1_full_1);
--FE1L13 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|process1~3
--operation mode is normal
FE1L13 = FB1_za_valid & (!GE1_full_0 # !GB1L28) # !FB1_za_valid & GB1L28;
--FE1_stage_2 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_2
--operation mode is normal
FE1_stage_2_lut_out = GE1_full_3 & FE1_stage_3 # !GE1_full_3 & (GB1L14);
FE1_stage_2 = DFFEAS(FE1_stage_2_lut_out, DE1__clk0, VCC, , GE1L24, , , , );
--WB1_internal_master_write_done is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_write_done
--operation mode is normal
WB1_internal_master_write_done_lut_out = WB1_internal_master_write_done $ (!WB1_master_state[1] & WB1_master_state[2] & WB1_master_state[0]);
WB1_internal_master_write_done = DFFEAS(WB1_internal_master_write_done_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--WB1_internal_master_read_done is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read_done
--operation mode is normal
WB1_internal_master_read_done_lut_out = WB1_internal_master_read_done $ (!WB1_master_state[2] & WB1L2 & WB1L3);
WB1_internal_master_read_done = DFFEAS(WB1_internal_master_read_done_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--DD1_sr[22] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[22]
--operation mode is normal
DD1_sr[22] = AMPP_FUNCTION(!A1L6, DD1L21, DD1_sr[23], DD1L9, DD1L22, !C1_CLR_SIGNAL, DD1L12);
--FB1L380 is std_1s10:inst|sdram:the_sdram|Mux42~1467
--operation mode is normal
FB1L380 = FB1_m_count[0] & (!FB1L349 # !FB1L379) # !FB1_m_count[0] & FB1L149 & FB1L379 & FB1L349;
--FB1L381 is std_1s10:inst|sdram:the_sdram|Mux42~1468
--operation mode is normal
FB1L381 = FB1_m_count[0] # FB1L379 & FB1L349 & FB1L222;
--FB1L382 is std_1s10:inst|sdram:the_sdram|Mux42~1469
--operation mode is normal
FB1L382 = FB1_m_state[0] & !FB1_m_state[7] & !FB1_m_state[2] & !FB1_m_state[1];
--FB1L383 is std_1s10:inst|sdram:the_sdram|Mux42~1470
--operation mode is normal
FB1L383 = EE1L127 & FB1_refresh_request & FB1L382 & !FB1L554;
--FB1L384 is std_1s10:inst|sdram:the_sdram|Mux42~1471
--operation mode is normal
FB1L384 = FB1L299 & (FB1_m_state[0] & FB1L149 # !FB1_m_state[0] & (FB1L176));
--FB1L385 is std_1s10:inst|sdram:the_sdram|Mux42~1472
--operation mode is normal
FB1L385 = FB1_m_state[2] # FB1_m_state[0] & (FB1_m_state[7] $ !FB1_m_state[1]);
--FB1L386 is std_1s10:inst|sdram:the_sdram|Mux42~1473
--operation mode is normal
FB1L386 = FB1_m_state[0] & (FB1_m_state[2] # FB1_m_state[7] $ FB1_m_state[1]);
--FB1L387 is std_1s10:inst|sdram:the_sdram|Mux42~1474
--operation mode is normal
FB1L387 = FB1_m_count[0] & (FB1L385 $ FB1L386 # !FB1L384) # !FB1_m_count[0] & FB1L386 & (FB1L384 # !FB1L385);
--FB1L388 is std_1s10:inst|sdram:the_sdram|Mux42~1475
--operation mode is normal
FB1L388 = FB1_m_state[5] & (FB1_m_state[8]) # !FB1_m_state[5] & (FB1_m_state[8] & FB1L381 # !FB1_m_state[8] & (FB1L390));
--FB1_i_refs[0] is std_1s10:inst|sdram:the_sdram|i_refs[0]
--operation mode is normal
FB1_i_refs[0]_lut_out = FB1_i_refs[0] & (!FB1L139) # !FB1_i_refs[0] & FB1L142;
FB1_i_refs[0] = DFFEAS(FB1_i_refs[0]_lut_out, DE1__clk0, VCC, , , , , , );
--CD1L26 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7313
--operation mode is normal
CD1L26 = AMPP_FUNCTION(FB1_i_state[1], FB1_i_refs[0]);
--FB1_i_refs[1] is std_1s10:inst|sdram:the_sdram|i_refs[1]
--operation mode is normal
FB1_i_refs[1]_lut_out = FB1_i_refs[1] & (FB1L142 & !FB1_i_refs[0] # !FB1L139) # !FB1_i_refs[1] & FB1L142 & FB1_i_refs[0];
FB1_i_refs[1] = DFFEAS(FB1_i_refs[1]_lut_out, DE1__clk0, VCC, , , , , , );
--FB1_i_refs[2] is std_1s10:inst|sdram:the_sdram|i_refs[2]
--operation mode is normal
FB1_i_refs[2]_lut_out = FB1_i_refs[2] & (FB1L142 & !FB1L99 # !FB1L139) # !FB1_i_refs[2] & FB1L142 & FB1L99;
FB1_i_refs[2] = DFFEAS(FB1_i_refs[2]_lut_out, DE1__clk0, VCC, , , , , , );
--CD1L27 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7315
--operation mode is normal
CD1L27 = AMPP_FUNCTION(FB1_i_state[0], FB1_i_state[1], FB1_i_state[2]);
--FB1_i_count[0] is std_1s10:inst|sdram:the_sdram|i_count[0]
--operation mode is normal
FB1_i_count[0]_lut_out = FB1L240 & (FB1L148 $ FB1_i_count[0] # !FB1_i_state[0]);
FB1_i_count[0] = DFFEAS(FB1_i_count[0]_lut_out, DE1__clk0, E1_data_out, , FB1L243, , , , );
--FB1L242 is std_1s10:inst|sdram:the_sdram|Mux10~92
--operation mode is normal
FB1L242 = FB1_i_count[2] & (FB1_i_count[1] # FB1_i_count[0]);
--FB1L243 is std_1s10:inst|sdram:the_sdram|Mux10~94
--operation mode is normal
FB1L243 = FB1_i_state[2] & (FB1_i_state[0] & FB1_i_state[1]) # !FB1_i_state[2] & (FB1_i_state[0] # FB1_i_state[1]);
--FB1L244 is std_1s10:inst|sdram:the_sdram|Mux11~65
--operation mode is normal
FB1L244 = FB1_i_count[1] & FB1_i_count[0] # !FB1_i_count[1] & !FB1_i_count[0] & FB1_i_count[2];
--T1L55 is std_1s10:inst|jtag_uart:the_jtag_uart|process2~43
--operation mode is normal
T1L55 = L1_internal_d_write & EB1L2 & U1L2 & T1L54;
--T1L46 is std_1s10:inst|jtag_uart:the_jtag_uart|ien_AE~15
--operation mode is normal
T1L46 = L1_M_alu_result[2] & T1L55;
--ZD1_safe_q[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[5]
--operation mode is normal
ZD1_safe_q[5]_carry_eqn = ZD1L10;
ZD1_safe_q[5]_lut_out = ZD1_safe_q[5] $ (ZD1_safe_q[5]_carry_eqn);
ZD1_safe_q[5] = DFFEAS(ZD1_safe_q[5]_lut_out, DE1__clk0, E1_data_out, , WD1L1, , , , );
--ZD1_safe_q[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[4]
--operation mode is arithmetic
ZD1_safe_q[4]_carry_eqn = ZD1L8;
ZD1_safe_q[4]_lut_out = ZD1_safe_q[4] $ (!ZD1_safe_q[4]_carry_eqn);
ZD1_safe_q[4] = DFFEAS(ZD1_safe_q[4]_lut_out, DE1__clk0, E1_data_out, , WD1L1, , , , );
--ZD1L10 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella4~COUT
--operation mode is arithmetic
ZD1L10 = CARRY(!ZD1L8 & (ZD1_safe_q[4] $ !T1_fifo_wr));
--ZD1_safe_q[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[3]
--operation mode is arithmetic
ZD1_safe_q[3]_carry_eqn = ZD1L6;
ZD1_safe_q[3]_lut_out = ZD1_safe_q[3] $ (ZD1_safe_q[3]_carry_eqn);
ZD1_safe_q[3] = DFFEAS(ZD1_safe_q[3]_lut_out, DE1__clk0, E1_data_out, , WD1L1, , , , );
--ZD1L8 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella3~COUT
--operation mode is arithmetic
ZD1L8 = CARRY(ZD1_safe_q[3] $ T1_fifo_wr # !ZD1L6);
--ZD1_safe_q[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[0]
--operation mode is arithmetic
ZD1_safe_q[0]_lut_out = !ZD1_safe_q[0];
ZD1_safe_q[0] = DFFEAS(ZD1_safe_q[0]_lut_out, DE1__clk0, E1_data_out, , WD1L1, , , , );
--ZD1L2 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella0~COUT
--operation mode is arithmetic
ZD1L2 = CARRY(ZD1_safe_q[0] $ !T1_fifo_wr);
--ZD1_safe_q[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[2]
--operation mode is arithmetic
ZD1_safe_q[2]_carry_eqn = ZD1L4;
ZD1_safe_q[2]_lut_out = ZD1_safe_q[2] $ (!ZD1_safe_q[2]_carry_eqn);
ZD1_safe_q[2] = DFFEAS(ZD1_safe_q[2]_lut_out, DE1__clk0, E1_data_out, , WD1L1, , , , );
--ZD1L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella2~COUT
--operation mode is arithmetic
ZD1L6 = CARRY(!ZD1L4 & (ZD1_safe_q[2] $ !T1_fifo_wr));
--ZD1_safe_q[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[1]
--operation mode is arithmetic
ZD1_safe_q[1]_carry_eqn = ZD1L2;
ZD1_safe_q[1]_lut_out = ZD1_safe_q[1] $ (ZD1_safe_q[1]_carry_eqn);
ZD1_safe_q[1] = DFFEAS(ZD1_safe_q[1]_lut_out, DE1__clk0, E1_data_out, , WD1L1, , , , );
--ZD1L4 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella1~COUT
--operation mode is arithmetic
ZD1L4 = CARRY(ZD1_safe_q[1] $ T1_fifo_wr # !ZD1L2);
--T1L50 is std_1s10:inst|jtag_uart:the_jtag_uart|LessThan0~84
--operation mode is normal
T1L50 = ZD1_safe_q[3] & (ZD1_safe_q[0] # ZD1_safe_q[2] # ZD1_safe_q[1]);
--WD1_b_full is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_full
--operation mode is normal
WD1_b_full_lut_out = !T1_rd_wfifo & (WD1_b_full # WD1L3 & WD1L4);
WD1_b_full = DFFEAS(WD1_b_full_lut_out, DE1__clk0, E1_data_out, , , , , , );
--T1L3 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~168
--operation mode is arithmetic
T1L3 = WD2_b_full $ (T1L3_carry_eqn);
--T1L4 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~169
--operation mode is arithmetic
T1L4 = CARRY(WD2_b_full & (!T1L14));
--T1L5 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~170
--operation mode is arithmetic
T1L5 = ZD2_safe_q[3] $ (T1L5_carry_eqn);
--T1L6 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~171
--operation mode is arithmetic
T1L6 = CARRY(!ZD2_safe_q[3] & (!T1L10));
--ZD2_safe_q[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[0]
--operation mode is arithmetic
ZD2_safe_q[0]_lut_out = !ZD2_safe_q[0];
ZD2_safe_q[0] = DFFEAS(ZD2_safe_q[0]_lut_out, DE1__clk0, E1_data_out, , WD2L1, , , , );
--ZD2L2 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella0~COUT
--operation mode is arithmetic
ZD2L2 = CARRY(ZD2_safe_q[0] $ !T1_wr_rfifo);
--T1L7 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~172
--operation mode is arithmetic
T1L7 = ZD2_safe_q[1] $ ZD2_safe_q[0];
--T1L8 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~173
--operation mode is arithmetic
T1L8 = CARRY(!ZD2_safe_q[1] & !ZD2_safe_q[0]);
--T1L9 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~174
--operation mode is arithmetic
T1L9 = ZD2_safe_q[2] $ (!T1L9_carry_eqn);
--T1L10 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~175
--operation mode is arithmetic
T1L10 = CARRY(ZD2_safe_q[2] # !T1L8);
--T1L51 is std_1s10:inst|jtag_uart:the_jtag_uart|LessThan1~117
--operation mode is normal
T1L51 = T1L5 & (ZD2_safe_q[0] # T1L7 # T1L9);
--T1L11 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~176
--operation mode is arithmetic
T1L11 = ZD2_safe_q[4] $ (!T1L11_carry_eqn);
--T1L12 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~177
--operation mode is arithmetic
T1L12 = CARRY(ZD2_safe_q[4] # !T1L6);
--T1L13 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~178
--operation mode is arithmetic
T1L13 = ZD2_safe_q[5] $ (T1L13_carry_eqn);
--T1L14 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~179
--operation mode is arithmetic
T1L14 = CARRY(!ZD2_safe_q[5] & (!T1L12));
--T1L52 is std_1s10:inst|jtag_uart:the_jtag_uart|LessThan1~118
--operation mode is normal
--T1L15 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~180
--operation mode is normal
T1L15 = !T1L15_carry_eqn;
--WD2_b_non_empty is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty
--operation mode is normal
WD2_b_non_empty_lut_out = WD2L8 # WD2_b_non_empty & (WD2L3 # !T1L43);
WD2_b_non_empty = DFFEAS(WD2_b_non_empty_lut_out, DE1__clk0, E1_data_out, , , , , , );
--QD1L39Q is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_pause~reg0
--operation mode is normal
QD1L39Q = AMPP_FUNCTION(DE1__clk0, QD1L38, QD1L2, QD1_jupdate1, QD1_jupdate2, E1_data_out);
--T1_read_0 is std_1s10:inst|jtag_uart:the_jtag_uart|read_0
--operation mode is normal
T1_read_0 = DFFEAS(T1_read_0_lut_out, DE1__clk0, E1_data_out, , , , , , );
--SC1L12 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|take_action_oci_intr_mask_reg~8
--operation mode is normal
SC1L12 = AMPP_FUNCTION(P1L15, SC1L1, SC1L2, CD1L61);
--L1_i_readdata_d1[8] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[8]
--operation mode is normal
L1_i_readdata_d1[8] = AMPP_FUNCTION(DE1__clk0, N1L33, FC1L21, FC1L11, P1L10, E1_data_out);
--L1L547 is std_1s10:inst|cpu:the_cpu|E_op_eret~66
--operation mode is normal
L1L547 = AMPP_FUNCTION(L1_E_iw[16], L1_E_iw[15], L1_E_iw[13]);
--L1L548 is std_1s10:inst|cpu:the_cpu|E_op_eret~67
--operation mode is normal
L1L548 = AMPP_FUNCTION(L1_E_iw[11], L1L545, L1L546, L1L547);
--L1_E_wrctl_status is std_1s10:inst|cpu:the_cpu|E_wrctl_status
--operation mode is normal
L1_E_wrctl_status = AMPP_FUNCTION(L1_E_ctrl_wrctl_inst, L1_E_iw[6], L1_E_iw[7], L1_E_iw[8]);
--L1_E_ctrl_exception is std_1s10:inst|cpu:the_cpu|E_ctrl_exception
--operation mode is normal
L1_E_ctrl_exception = AMPP_FUNCTION(DE1__clk0, L1L811, L1L808, L1L209, L1_D_iw[12], E1_data_out, L1_W_stall);
--L1L1328 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie_inst_nxt~0
--operation mode is normal
L1L1328 = AMPP_FUNCTION(L1_E_ctrl_break, L1_E_ctrl_exception);
--L1L1329 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie~150
--operation mode is normal
L1L1329 = AMPP_FUNCTION(L1_M_status_reg_pie, L1_W_stall, L1L1333, L1L800);
--L1L1330 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie~151
--operation mode is normal
L1L1330 = AMPP_FUNCTION(L1_E_wrctl_status, L1L548);
--L1L1331 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie~152
--operation mode is normal
L1L1331 = AMPP_FUNCTION(L1L1330, L1L416, L1L405, L1_E_ctrl_dst_data_sel_cmp);
--L1L1332 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie~153
--operation mode is normal
L1L1332 = AMPP_FUNCTION(L1L548, L1_M_bstatus_reg, L1_M_estatus_reg, L1_E_iw[14]);
--KB1_control_register[0] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|control_register[0]
--operation mode is normal
KB1_control_register[0]_lut_out = L1_M_st_data[0];
KB1_control_register[0] = DFFEAS(KB1_control_register[0]_lut_out, DE1__clk0, E1_data_out, , KB1_control_wr_strobe, , , , );
--KB1_timeout_occurred is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|timeout_occurred
--operation mode is normal
KB1_timeout_occurred_lut_out = KB1L211 & (!HE1L21 # !LB1_cpu_data_master_requests_sys_clk_timer_s1 # !KB1L7);
KB1_timeout_occurred = DFFEAS(KB1_timeout_occurred_lut_out, DE1__clk0, E1_data_out, , , , , , );
--SC1_internal_oci_ienable1[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[1]
--operation mode is normal
SC1_internal_oci_ienable1[1] = AMPP_FUNCTION(DE1__clk0, L1_M_st_data[1], E1_data_out, SC1L12);
--Q1_d1_irq_from_the_lan91c111 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_irq_from_the_lan91c111
--operation mode is normal
Q1_d1_irq_from_the_lan91c111_lut_out = irq_from_the_lan91c111;
Q1_d1_irq_from_the_lan91c111 = DFFEAS(Q1_d1_irq_from_the_lan91c111_lut_out, DE1__clk0, E1_data_out, , , , , , );
--SC1_internal_oci_ienable1[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[0]
--operation mode is normal
SC1_internal_oci_ienable1[0] = AMPP_FUNCTION(DE1__clk0, L1_M_st_data[0], E1_data_out, SC1L12);
--L1_i_readdata_d1[7] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[7]
--operation mode is normal
L1_i_readdata_d1[7] = AMPP_FUNCTION(DE1__clk0, N1L30, FC1L21, FC1L10, P1L10, E1_data_out);
--L1_i_readdata_d1[6] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[6]
--operation mode is normal
L1_i_readdata_d1[6] = AMPP_FUNCTION(DE1__clk0, N1L27, FC1L21, FC1L9, P1L10, E1_data_out);
--L1_i_readdata_d1[4] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[4]
--operation mode is normal
L1_i_readdata_d1[4] = AMPP_FUNCTION(DE1__clk0, N1L21, P1L10, N1L105, E1_data_out);
--L1_i_readdata_d1[15] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[15]
--operation mode is normal
L1_i_readdata_d1[15] = AMPP_FUNCTION(DE1__clk0, N1L54, FC1L21, FC1L18, P1L10, E1_data_out);
--L1_i_readdata_d1[5] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[5]
--operation mode is normal
L1_i_readdata_d1[5] = AMPP_FUNCTION(DE1__clk0, N1L24, P1L10, N1L106, E1_data_out);
--L1_i_readdata_d1[0] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[0]
--operation mode is normal
L1_i_readdata_d1[0] = AMPP_FUNCTION(DE1__clk0, N1L9, FC1L1, FC1L2, P1L10, E1_data_out);
--L1_i_readdata_d1[1] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[1]
--operation mode is normal
L1_i_readdata_d1[1] = AMPP_FUNCTION(DE1__clk0, N1L12, FC1L3, FC1L4, P1L10, E1_data_out);
--L1_i_readdata_d1[2] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[2]
--operation mode is normal
L1_i_readdata_d1[2] = AMPP_FUNCTION(DE1__clk0, N1L15, FC1L5, FC1L6, P1L10, E1_data_out);
--L1_i_readdata_d1[3] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[3]
--operation mode is normal
L1_i_readdata_d1[3] = AMPP_FUNCTION(DE1__clk0, N1L18, FC1L7, FC1L8, P1L10, E1_data_out);
--L1_i_readdata_d1[27] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[27]
--operation mode is normal
L1_i_readdata_d1[27] = AMPP_FUNCTION(DE1__clk0, N1L90, FC1L21, FC1L31, P1L10, E1_data_out);
--L1_i_readdata_d1[28] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[28]
--operation mode is normal
L1_i_readdata_d1[28] = AMPP_FUNCTION(DE1__clk0, N1L93, FC1L21, FC1L32, P1L10, E1_data_out);
--L1_i_readdata_d1[29] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[29]
--operation mode is normal
L1_i_readdata_d1[29] = AMPP_FUNCTION(DE1__clk0, N1L96, FC1L21, FC1L33, P1L10, E1_data_out);
--L1_i_readdata_d1[30] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[30]
--operation mode is normal
L1_i_readdata_d1[30] = AMPP_FUNCTION(DE1__clk0, N1L99, FC1L21, FC1L34, P1L10, E1_data_out);
--L1_i_readdata_d1[31] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[31]
--operation mode is normal
L1_i_readdata_d1[31] = AMPP_FUNCTION(DE1__clk0, N1L102, FC1L21, FC1L35, P1L10, E1_data_out);
--L1_E_ctrl_shift_rot is std_1s10:inst|cpu:the_cpu|E_ctrl_shift_rot
--operation mode is normal
L1_E_ctrl_shift_rot = AMPP_FUNCTION(DE1__clk0, L1L224, E1_data_out, L1_W_stall);
--L1_E_ctrl_shift_rot_right is std_1s10:inst|cpu:the_cpu|E_ctrl_shift_rot_right
--operation mode is normal
L1_E_ctrl_shift_rot_right = AMPP_FUNCTION(DE1__clk0, L1L229, L1L819, L1L821, L1L225, E1_data_out, L1_W_stall);
--L1L580 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_row[0]~40
--operation mode is normal
L1L580 = AMPP_FUNCTION(L1L830, L1_E_ctrl_shift_rot_right, L1L653, L1L654);
--L1L716 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[0]~2295
--operation mode is normal
L1L716 = AMPP_FUNCTION(L1L650, L1L830, L1_E_ctrl_shift_rot, L1L580);
--L1L574 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_col[1]~84
--operation mode is normal
L1L574 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L650, L1L651, L1L652);
--L1L717 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[1]~2296
--operation mode is normal
L1L717 = AMPP_FUNCTION(L1L651, L1L574, L1_E_ctrl_shift_rot, L1L580);
--L1L575 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_col[2]~85
--operation mode is normal
L1L575 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L650, L1L651, L1L652);
--L1L718 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[2]~2297
--operation mode is normal
L1L718 = AMPP_FUNCTION(L1L652, L1L575, L1_E_ctrl_shift_rot, L1L580);
--L1L576 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_col[3]~86
--operation mode is normal
L1L576 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L650, L1L651, L1L652);
--L1L719 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[3]~2298
--operation mode is normal
L1L719 = AMPP_FUNCTION(L1L653, L1L576, L1_E_ctrl_shift_rot, L1L580);
--L1L744 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[28]~2299
--operation mode is normal
L1L744 = AMPP_FUNCTION(L1L652, L1_E_ctrl_shift_rot, L1L651, L1L650);
--L1L720 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[4]~2300
--operation mode is normal
L1L720 = AMPP_FUNCTION(L1L654, L1L744, L1_E_ctrl_shift_rot, L1L580);
--L1L577 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_col[5]~87
--operation mode is normal
L1L577 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L650, L1L651, L1L652);
--L1L721 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[5]~2301
--operation mode is normal
L1L721 = AMPP_FUNCTION(L1L655, L1L577, L1_E_ctrl_shift_rot, L1L580);
--L1L578 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_col[6]~88
--operation mode is normal
L1L578 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L650, L1L651, L1L652);
--L1L722 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[6]~2302
--operation mode is normal
L1L722 = AMPP_FUNCTION(L1L656, L1L578, L1_E_ctrl_shift_rot, L1L580);
--L1L579 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_col[7]~89
--operation mode is normal
L1L579 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L650, L1L651, L1L652);
--L1L723 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[7]~2303
--operation mode is normal
L1L723 = AMPP_FUNCTION(L1L657, L1L579, L1_E_ctrl_shift_rot, L1L580);
--L1L581 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_row[1]~41
--operation mode is normal
L1L581 = AMPP_FUNCTION(L1L830, L1_E_ctrl_shift_rot_right, L1L653, L1L654);
--L1L724 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[8]~2304
--operation mode is normal
L1L724 = AMPP_FUNCTION(L1L830, L1L581, L1L658, L1_E_ctrl_shift_rot);
--L1L725 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[9]~2305
--operation mode is normal
L1L725 = AMPP_FUNCTION(L1L574, L1L581, L1L659, L1_E_ctrl_shift_rot);
--L1L726 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[10]~2306
--operation mode is normal
L1L726 = AMPP_FUNCTION(L1L575, L1L581, L1L660, L1_E_ctrl_shift_rot);
--L1L727 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[11]~2307
--operation mode is normal
L1L727 = AMPP_FUNCTION(L1L576, L1L581, L1L661, L1_E_ctrl_shift_rot);
--L1L728 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[12]~2308
--operation mode is normal
L1L728 = AMPP_FUNCTION(L1L744, L1L581, L1L662, L1_E_ctrl_shift_rot);
--L1L729 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[13]~2309
--operation mode is normal
L1L729 = AMPP_FUNCTION(L1L577, L1L581, L1L663, L1_E_ctrl_shift_rot);
--L1L730 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[14]~2310
--operation mode is normal
L1L730 = AMPP_FUNCTION(L1L578, L1L581, L1L664, L1_E_ctrl_shift_rot);
--L1_E_src1_prelim[26] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[26]
--operation mode is normal
L1_E_src1_prelim[26] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[26], L1_W_wr_data[26], L1L1418, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[26] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[26]
--operation mode is normal
L1_M_mul_shift_rot_result[26] = AMPP_FUNCTION(DE1__clk0, QC1_result[26], QC1_result[58], L1L1242, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1416 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[26]~3697
--operation mode is normal
L1L1416 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[26], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[26] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[26]
--operation mode is normal
L1_av_ld_data_aligned_or_div[26] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[26], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1_M_alu_result[26] is std_1s10:inst|cpu:the_cpu|M_alu_result[26]
--operation mode is normal
L1_M_alu_result[26] = AMPP_FUNCTION(DE1__clk0, L1L74, L1L539, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1L1417 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[26]~3698
--operation mode is normal
L1L1417 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[26], L1_M_alu_result[26], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L610 is std_1s10:inst|cpu:the_cpu|E_src1[26]~1991
--operation mode is normal
L1L610 = AMPP_FUNCTION(L1_E_src1_prelim[26], L1_E_src1_hazard_M, L1L1416, L1L1417);
--L1_E_src1_prelim[27] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[27]
--operation mode is normal
L1_E_src1_prelim[27] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[27], L1_W_wr_data[27], L1L1421, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[27] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[27]
--operation mode is normal
L1_M_mul_shift_rot_result[27] = AMPP_FUNCTION(DE1__clk0, QC1_result[27], QC1_result[59], L1L1243, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1419 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[27]~3699
--operation mode is normal
L1L1419 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[27], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[27] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[27]
--operation mode is normal
L1_av_ld_data_aligned_or_div[27] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[27], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1_M_alu_result[27] is std_1s10:inst|cpu:the_cpu|M_alu_result[27]
--operation mode is normal
L1_M_alu_result[27] = AMPP_FUNCTION(DE1__clk0, L1L75, L1L540, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1L1420 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[27]~3700
--operation mode is normal
L1L1420 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[27], L1_M_alu_result[27], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L611 is std_1s10:inst|cpu:the_cpu|E_src1[27]~1992
--operation mode is normal
L1L611 = AMPP_FUNCTION(L1_E_src1_prelim[27], L1_E_src1_hazard_M, L1L1419, L1L1420);
--L1_E_src1_prelim[28] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[28]
--operation mode is normal
L1_E_src1_prelim[28] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[28], L1_W_wr_data[28], L1L1424, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[28] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[28]
--operation mode is normal
L1_M_mul_shift_rot_result[28] = AMPP_FUNCTION(DE1__clk0, QC1_result[28], QC1_result[60], L1L1244, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1422 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[28]~3701
--operation mode is normal
L1L1422 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[28], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[28] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[28]
--operation mode is normal
L1_av_ld_data_aligned_or_div[28] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[28], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1_M_alu_result[28] is std_1s10:inst|cpu:the_cpu|M_alu_result[28]
--operation mode is normal
L1_M_alu_result[28] = AMPP_FUNCTION(DE1__clk0, L1L76, L1L541, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1L1423 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[28]~3702
--operation mode is normal
L1L1423 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[28], L1_M_alu_result[28], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L612 is std_1s10:inst|cpu:the_cpu|E_src1[28]~1993
--operation mode is normal
L1L612 = AMPP_FUNCTION(L1_E_src1_prelim[28], L1_E_src1_hazard_M, L1L1422, L1L1423);
--L1_E_src1_prelim[29] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[29]
--operation mode is normal
L1_E_src1_prelim[29] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[29], L1_W_wr_data[29], L1L1427, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[29] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[29]
--operation mode is normal
L1_M_mul_shift_rot_result[29] = AMPP_FUNCTION(DE1__clk0, QC1_result[29], QC1_result[61], L1L1245, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1425 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[29]~3703
--operation mode is normal
L1L1425 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[29], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[29] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[29]
--operation mode is normal
L1_av_ld_data_aligned_or_div[29] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[29], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1_M_alu_result[29] is std_1s10:inst|cpu:the_cpu|M_alu_result[29]
--operation mode is normal
L1_M_alu_result[29] = AMPP_FUNCTION(DE1__clk0, L1L77, L1L542, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1L1426 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[29]~3704
--operation mode is normal
L1L1426 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[29], L1_M_alu_result[29], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L613 is std_1s10:inst|cpu:the_cpu|E_src1[29]~1994
--operation mode is normal
L1L613 = AMPP_FUNCTION(L1_E_src1_prelim[29], L1_E_src1_hazard_M, L1L1425, L1L1426);
--L1_E_src1_prelim[30] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[30]
--operation mode is normal
L1_E_src1_prelim[30] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[30], L1_W_wr_data[30], L1L1430, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[30] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[30]
--operation mode is normal
L1_M_mul_shift_rot_result[30] = AMPP_FUNCTION(DE1__clk0, QC1_result[30], QC1_result[62], L1L1246, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1428 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3705
--operation mode is normal
L1L1428 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[30], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[30] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[30]
--operation mode is normal
L1_av_ld_data_aligned_or_div[30] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[30], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1_M_alu_result[30] is std_1s10:inst|cpu:the_cpu|M_alu_result[30]
--operation mode is normal
L1_M_alu_result[30] = AMPP_FUNCTION(DE1__clk0, L1L78, L1L543, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1L1429 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3706
--operation mode is normal
L1L1429 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[30], L1_M_alu_result[30], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L614 is std_1s10:inst|cpu:the_cpu|E_src1[30]~1995
--operation mode is normal
L1L614 = AMPP_FUNCTION(L1_E_src1_prelim[30], L1_E_src1_hazard_M, L1L1428, L1L1429);
--L1_E_src1_prelim[31] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[31]
--operation mode is normal
L1_E_src1_prelim[31] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[31], L1_W_wr_data[31], L1L1433, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[31] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[31]
--operation mode is normal
L1_M_mul_shift_rot_result[31] = AMPP_FUNCTION(DE1__clk0, QC1_result[31], QC1_result[63], L1L1248, L1L1247, E1_data_out, L1_M_ctrl_rot);
--L1L1431 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3707
--operation mode is normal
L1L1431 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[31], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[31] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[31]
--operation mode is normal
L1_av_ld_data_aligned_or_div[31] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[31], L1_M_ctrl_ld_signed, L1L160, L1_M_iw[4], E1_data_out);
--L1_M_alu_result[31] is std_1s10:inst|cpu:the_cpu|M_alu_result[31]
--operation mode is normal
L1_M_alu_result[31] = AMPP_FUNCTION(DE1__clk0, L1L79, L1L544, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1L1432 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3708
--operation mode is normal
L1L1432 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[31], L1_M_alu_result[31], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L615 is std_1s10:inst|cpu:the_cpu|E_src1[31]~1996
--operation mode is normal
L1L615 = AMPP_FUNCTION(L1_E_src1_prelim[31], L1_E_src1_hazard_M, L1L1431, L1L1432);
--L1_E_ctrl_mul_cell_src1_signed is std_1s10:inst|cpu:the_cpu|E_ctrl_mul_cell_src1_signed
--operation mode is normal
L1_E_ctrl_mul_cell_src1_signed = AMPP_FUNCTION(DE1__clk0, L1_D_iw[15], L1L229, L1L220, E1_data_out, L1_W_stall);
--QC1_w7w[32] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|w7w[32]
--operation mode is normal
QC1_w7w[32] = AMPP_FUNCTION(L1L615, L1_E_ctrl_mul_cell_src1_signed);
--L1L731 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[15]~2311
--operation mode is normal
L1L731 = AMPP_FUNCTION(L1L579, L1L581, L1L665, L1_E_ctrl_shift_rot);
--L1L582 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_row[2]~42
--operation mode is normal
L1L582 = AMPP_FUNCTION(L1L830, L1_E_ctrl_shift_rot_right, L1L653, L1L654);
--L1L732 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[16]~2312
--operation mode is normal
L1L732 = AMPP_FUNCTION(L1L830, L1L582, L1L666, L1_E_ctrl_shift_rot);
--L1L733 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[17]~2313
--operation mode is normal
L1L733 = AMPP_FUNCTION(L1L574, L1L582, L1L667, L1_E_ctrl_shift_rot);
--L1L734 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[18]~2314
--operation mode is normal
L1L734 = AMPP_FUNCTION(L1L575, L1L582, L1L668, L1_E_ctrl_shift_rot);
--L1L735 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[19]~2315
--operation mode is normal
L1L735 = AMPP_FUNCTION(L1L576, L1L582, L1L669, L1_E_ctrl_shift_rot);
--L1L736 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[20]~2316
--operation mode is normal
L1L736 = AMPP_FUNCTION(L1L744, L1L582, L1L670, L1_E_ctrl_shift_rot);
--L1L737 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[21]~2317
--operation mode is normal
L1L737 = AMPP_FUNCTION(L1L577, L1L582, L1L671, L1_E_ctrl_shift_rot);
--L1L738 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[22]~2318
--operation mode is normal
L1L738 = AMPP_FUNCTION(L1L578, L1L582, L1L672, L1_E_ctrl_shift_rot);
--L1L739 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[23]~2319
--operation mode is normal
L1L739 = AMPP_FUNCTION(L1L579, L1L582, L1L673, L1_E_ctrl_shift_rot);
--L1L583 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_row[3]~43
--operation mode is normal
L1L583 = AMPP_FUNCTION(L1L830, L1_E_ctrl_shift_rot_right, L1L653, L1L654);
--L1L740 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[24]~2320
--operation mode is normal
L1L740 = AMPP_FUNCTION(L1L830, L1L583, L1L674, L1_E_ctrl_shift_rot);
--L1L741 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[25]~2321
--operation mode is normal
L1L741 = AMPP_FUNCTION(L1L574, L1L583, L1L675, L1_E_ctrl_shift_rot);
--L1_E_src2_imm[26] is std_1s10:inst|cpu:the_cpu|E_src2_imm[26]
--operation mode is normal
L1_E_src2_imm[26] = AMPP_FUNCTION(DE1__clk0, L1L395, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[26] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[26]
--operation mode is normal
L1_E_src2_prelim[26] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[26], L1_W_wr_data[26], L1L1418, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1L784 is std_1s10:inst|cpu:the_cpu|E_src2_reg[26]~474
--operation mode is normal
L1L784 = AMPP_FUNCTION(L1_E_src2_prelim[26], L1_E_src2_hazard_M, L1L1416, L1L1417);
--L1L676 is std_1s10:inst|cpu:the_cpu|E_src2[26]~1517
--operation mode is normal
L1L676 = AMPP_FUNCTION(L1_E_src2_imm[26], L1L784, L1_E_ctrl_src2_is_imm);
--L1L742 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[26]~2322
--operation mode is normal
L1L742 = AMPP_FUNCTION(L1L575, L1L583, L1L676, L1_E_ctrl_shift_rot);
--L1_E_src2_imm[27] is std_1s10:inst|cpu:the_cpu|E_src2_imm[27]
--operation mode is normal
L1_E_src2_imm[27] = AMPP_FUNCTION(DE1__clk0, L1L396, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[27] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[27]
--operation mode is normal
L1_E_src2_prelim[27] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[27], L1_W_wr_data[27], L1L1421, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1L785 is std_1s10:inst|cpu:the_cpu|E_src2_reg[27]~475
--operation mode is normal
L1L785 = AMPP_FUNCTION(L1_E_src2_prelim[27], L1_E_src2_hazard_M, L1L1419, L1L1420);
--L1L677 is std_1s10:inst|cpu:the_cpu|E_src2[27]~1518
--operation mode is normal
L1L677 = AMPP_FUNCTION(L1_E_src2_imm[27], L1L785, L1_E_ctrl_src2_is_imm);
--L1L743 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[27]~2323
--operation mode is normal
L1L743 = AMPP_FUNCTION(L1L576, L1L583, L1L677, L1_E_ctrl_shift_rot);
--L1_E_src2_imm[28] is std_1s10:inst|cpu:the_cpu|E_src2_imm[28]
--operation mode is normal
L1_E_src2_imm[28] = AMPP_FUNCTION(DE1__clk0, L1L397, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[28] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[28]
--operation mode is normal
L1_E_src2_prelim[28] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[28], L1_W_wr_data[28], L1L1424, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1L786 is std_1s10:inst|cpu:the_cpu|E_src2_reg[28]~476
--operation mode is normal
L1L786 = AMPP_FUNCTION(L1_E_src2_prelim[28], L1_E_src2_hazard_M, L1L1422, L1L1423);
--L1L678 is std_1s10:inst|cpu:the_cpu|E_src2[28]~1519
--operation mode is normal
L1L678 = AMPP_FUNCTION(L1_E_src2_imm[28], L1L786, L1_E_ctrl_src2_is_imm);
--L1L745 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[28]~2324
--operation mode is normal
L1L745 = AMPP_FUNCTION(L1L744, L1L583, L1L678, L1_E_ctrl_shift_rot);
--L1_E_src2_imm[29] is std_1s10:inst|cpu:the_cpu|E_src2_imm[29]
--operation mode is normal
L1_E_src2_imm[29] = AMPP_FUNCTION(DE1__clk0, L1L398, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[29] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[29]
--operation mode is normal
L1_E_src2_prelim[29] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[29], L1_W_wr_data[29], L1L1427, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1L787 is std_1s10:inst|cpu:the_cpu|E_src2_reg[29]~477
--operation mode is normal
L1L787 = AMPP_FUNCTION(L1_E_src2_prelim[29], L1_E_src2_hazard_M, L1L1425, L1L1426);
--L1L679 is std_1s10:inst|cpu:the_cpu|E_src2[29]~1520
--operation mode is normal
L1L679 = AMPP_FUNCTION(L1_E_src2_imm[29], L1L787, L1_E_ctrl_src2_is_imm);
--L1L746 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[29]~2325
--operation mode is normal
L1L746 = AMPP_FUNCTION(L1L577, L1L583, L1L679, L1_E_ctrl_shift_rot);
--L1_E_src2_imm[30] is std_1s10:inst|cpu:the_cpu|E_src2_imm[30]
--operation mode is normal
L1_E_src2_imm[30] = AMPP_FUNCTION(DE1__clk0, L1L399, L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[30] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[30]
--operation mode is normal
L1_E_src2_prelim[30] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[30], L1_W_wr_data[30], L1L1430, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1L788 is std_1s10:inst|cpu:the_cpu|E_src2_reg[30]~478
--operation mode is normal
L1L788 = AMPP_FUNCTION(L1_E_src2_prelim[30], L1_E_src2_hazard_M, L1L1428, L1L1429);
--L1L680 is std_1s10:inst|cpu:the_cpu|E_src2[30]~1521
--operation mode is normal
L1L680 = AMPP_FUNCTION(L1_E_src2_imm[30], L1L788, L1_E_ctrl_src2_is_imm);
--L1L747 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[30]~2326
--operation mode is normal
L1L747 = AMPP_FUNCTION(L1L578, L1L583, L1L680, L1_E_ctrl_shift_rot);
--L1_E_src2_imm[31] is std_1s10:inst|cpu:the_cpu|E_src2_imm[31]
--operation mode is normal
L1_E_src2_imm[31] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[21], L1L203, L1L228, L1L227, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[31] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[31]
--operation mode is normal
L1_E_src2_prelim[31] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[31], L1_W_wr_data[31], L1L1433, L1L384, E1_data_out, L1L380, L1_W_stall);
--L1L789 is std_1s10:inst|cpu:the_cpu|E_src2_reg[31]~479
--operation mode is normal
L1L789 = AMPP_FUNCTION(L1_E_src2_prelim[31], L1_E_src2_hazard_M, L1L1431, L1L1432);
--L1L681 is std_1s10:inst|cpu:the_cpu|E_src2[31]~1522
--operation mode is normal
L1L681 = AMPP_FUNCTION(L1_E_src2_imm[31], L1L789, L1_E_ctrl_src2_is_imm);
--L1L748 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[31]~2327
--operation mode is normal
L1L748 = AMPP_FUNCTION(L1L579, L1L583, L1L681, L1_E_ctrl_shift_rot);
--L1_E_ctrl_mul_cell_src2_signed is std_1s10:inst|cpu:the_cpu|E_ctrl_mul_cell_src2_signed
--operation mode is normal
L1_E_ctrl_mul_cell_src2_signed = AMPP_FUNCTION(DE1__clk0, L1_D_iw[11], L1L229, L1L822, E1_data_out, L1_W_stall);
--QC1_w23w[32] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|w23w[32]
--operation mode is normal
QC1_w23w[32] = AMPP_FUNCTION(L1L748, L1_E_ctrl_mul_cell_src2_signed);
--L1L223 is std_1s10:inst|cpu:the_cpu|D_ctrl_mulx~31
--operation mode is normal
L1L223 = AMPP_FUNCTION(L1_D_iw[13], L1_D_iw[11], L1_D_iw[16]);
--L1L224 is std_1s10:inst|cpu:the_cpu|D_ctrl_rot~32
--operation mode is normal
L1L224 = AMPP_FUNCTION(L1_D_iw[12], L1L811, L1L808, L1_D_iw[13]);
--F1L26 is std_1s10:inst|button_pio:the_button_pio|read_mux_out[2]~376
--operation mode is normal
F1L26 = L1_M_alu_result[2] & F1_edge_capture[2] # !L1_M_alu_result[2] & (F1_irq_mask[2]);
--AE2_q_b[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE2_q_b[2]_PORT_A_data_in = QD1_wdata[2];
AE2_q_b[2]_PORT_A_data_in_reg = DFFE(AE2_q_b[2]_PORT_A_data_in, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[2]_PORT_A_address_reg = DFFE(AE2_q_b[2]_PORT_A_address, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[2]_PORT_B_address_reg = DFFE(AE2_q_b[2]_PORT_B_address, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_PORT_A_write_enable = VCC;
AE2_q_b[2]_PORT_A_write_enable_reg = DFFE(AE2_q_b[2]_PORT_A_write_enable, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_read_enable = VCC;
AE2_q_b[2]_PORT_B_read_enable_reg = DFFE(AE2_q_b[2]_PORT_B_read_enable, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_clock_0 = DE1__clk0;
AE2_q_b[2]_clock_1 = DE1__clk0;
AE2_q_b[2]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[2]_clock_enable_1 = T1L61;
AE2_q_b[2]_PORT_B_data_out = MEMORY(AE2_q_b[2]_PORT_A_data_in_reg, , AE2_q_b[2]_PORT_A_address_reg, AE2_q_b[2]_PORT_B_address_reg, AE2_q_b[2]_PORT_A_write_enable_reg, AE2_q_b[2]_PORT_B_read_enable_reg, , , AE2_q_b[2]_clock_0, AE2_q_b[2]_clock_1, AE2_q_b[2]_clock_enable_0, AE2_q_b[2]_clock_enable_1, , );
AE2_q_b[2] = AE2_q_b[2]_PORT_B_data_out[0];
--M1L298 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~18
--operation mode is normal
M1L298 = AE2_q_b[2] & T1_read_0 # !U1L2 # !EB1L2;
--H1_slave_readdata[2] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[2]
--operation mode is normal
H1_slave_readdata[2]_lut_out = H1_slave_readdata_p1[2];
H1_slave_readdata[2] = DFFEAS(H1_slave_readdata[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L270 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[2]~2078
--operation mode is normal
M1L270 = H1_slave_readdata[2] # !J1_cpu_data_master_requests_clock_0_in;
--FB1_za_data[2] is std_1s10:inst|sdram:the_sdram|za_data[2]
--operation mode is normal
FB1_za_data[2]_lut_out = A1L265;
FB1_za_data[2] = DFFEAS(FB1_za_data[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--KB1_counter_snapshot[2] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[2]
--operation mode is normal
KB1_counter_snapshot[2]_lut_out = !KB1_internal_counter[2];
KB1_counter_snapshot[2] = DFFEAS(KB1_counter_snapshot[2]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--HE1L17 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~101
--operation mode is normal
HE1L17 = L1_M_alu_result[4] & (!L1_M_alu_result[2] & !L1_M_alu_result[3]);
--KB1_period_h_register[2] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[2]
--operation mode is normal
KB1_period_h_register[2]_lut_out = !L1_M_st_data[2];
KB1_period_h_register[2] = DFFEAS(KB1_period_h_register[2]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1L164 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[2]~1238
--operation mode is normal
KB1L164 = KB1_counter_snapshot[2] & (HE1L17 # HE1L15 & !KB1_period_h_register[2]) # !KB1_counter_snapshot[2] & (HE1L15 & !KB1_period_h_register[2]);
--KB1_control_register[2] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|control_register[2]
--operation mode is normal
KB1_control_register[2]_lut_out = L1_M_st_data[2];
KB1_control_register[2] = DFFEAS(KB1_control_register[2]_lut_out, DE1__clk0, E1_data_out, , KB1_control_wr_strobe, , , , );
--KB1_counter_snapshot[18] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[18]
--operation mode is normal
KB1_counter_snapshot[18]_lut_out = !KB1_internal_counter[18];
KB1_counter_snapshot[18] = DFFEAS(KB1_counter_snapshot[18]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--HE1L18 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~102
--operation mode is normal
HE1L18 = L1_M_alu_result[2] & L1_M_alu_result[4] & (!L1_M_alu_result[3]);
--HE1L19 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~103
--operation mode is normal
HE1L19 = L1_M_alu_result[2] & (!L1_M_alu_result[3] & !L1_M_alu_result[4]);
--KB1L165 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[2]~1239
--operation mode is normal
KB1L165 = KB1_control_register[2] & (HE1L19 # KB1_counter_snapshot[18] & HE1L18) # !KB1_control_register[2] & KB1_counter_snapshot[18] & HE1L18;
--HE1L20 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~104
--operation mode is normal
HE1L20 = L1_M_alu_result[3] & (!L1_M_alu_result[2] & !L1_M_alu_result[4]);
--KB1_period_l_register[2] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[2]
--operation mode is normal
KB1_period_l_register[2]_lut_out = !L1_M_st_data[2];
KB1_period_l_register[2] = DFFEAS(KB1_period_l_register[2]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--Z1L1 is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|wren~1
--operation mode is normal
Z1L1 = L1_internal_d_write & AB1L3 & (AB1_onchip_ram_64_kbytes_s1_arb_addend[1] # !AB1L11);
--AB1L18 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[0]~98
--operation mode is normal
AB1L18 = AB1L3 & (AB1L1 & L1_ic_fill_ap_offset[0] # !AB1L1 & (L1_M_alu_result[2])) # !AB1L3 & L1_ic_fill_ap_offset[0];
--AB1L19 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[1]~99
--operation mode is normal
AB1L19 = AB1L3 & (AB1L1 & L1_ic_fill_ap_offset[1] # !AB1L1 & (L1_M_alu_result[3])) # !AB1L3 & L1_ic_fill_ap_offset[1];
--AB1L20 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[2]~100
--operation mode is normal
AB1L20 = AB1L3 & (AB1L1 & L1_ic_fill_ap_offset[2] # !AB1L1 & (L1_M_alu_result[4])) # !AB1L3 & L1_ic_fill_ap_offset[2];
--AB1L21 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[3]~101
--operation mode is normal
AB1L21 = AB1L3 & (AB1L1 & L1_ic_fill_line[0] # !AB1L1 & (L1_M_alu_result[5])) # !AB1L3 & L1_ic_fill_line[0];
--AB1L22 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[4]~102
--operation mode is normal
AB1L22 = AB1L3 & (AB1L1 & L1_ic_fill_line[1] # !AB1L1 & (L1_M_alu_result[6])) # !AB1L3 & L1_ic_fill_line[1];
--AB1L23 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[5]~103
--operation mode is normal
AB1L23 = AB1L3 & (AB1L1 & L1_ic_fill_line[2] # !AB1L1 & (L1_M_alu_result[7])) # !AB1L3 & L1_ic_fill_line[2];
--AB1L24 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[6]~104
--operation mode is normal
AB1L24 = AB1L3 & (AB1L1 & L1_ic_fill_line[3] # !AB1L1 & (L1_M_alu_result[8])) # !AB1L3 & L1_ic_fill_line[3];
--AB1L25 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[7]~105
--operation mode is normal
AB1L25 = AB1L3 & (AB1L1 & L1_ic_fill_line[4] # !AB1L1 & (L1_M_alu_result[9])) # !AB1L3 & L1_ic_fill_line[4];
--AB1L26 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[8]~106
--operation mode is normal
AB1L26 = AB1L3 & (AB1L1 & L1_ic_fill_line[5] # !AB1L1 & (L1_M_alu_result[10])) # !AB1L3 & L1_ic_fill_line[5];
--AB1L27 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[9]~107
--operation mode is normal
AB1L27 = AB1L3 & (AB1L1 & L1_ic_fill_line[6] # !AB1L1 & (L1_M_alu_result[11])) # !AB1L3 & L1_ic_fill_line[6];
--AB1L28 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[10]~108
--operation mode is normal
AB1L28 = AB1L3 & (AB1L1 & L1_ic_fill_tag[0] # !AB1L1 & (L1_M_alu_result[12])) # !AB1L3 & L1_ic_fill_tag[0];
--AB1L29 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[11]~109
--operation mode is normal
AB1L29 = AB1L3 & (AB1L1 & L1_ic_fill_tag[1] # !AB1L1 & (L1_M_alu_result[13])) # !AB1L3 & L1_ic_fill_tag[1];
--AB1L30 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[12]~110
--operation mode is normal
AB1L30 = AB1L3 & (AB1L1 & L1_ic_fill_tag[2] # !AB1L1 & (L1_M_alu_result[14])) # !AB1L3 & L1_ic_fill_tag[2];
--AB1L31 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[13]~111
--operation mode is normal
AB1L31 = AB1L3 & (AB1L1 & L1_ic_fill_tag[3] # !AB1L1 & (L1_M_alu_result[15])) # !AB1L3 & L1_ic_fill_tag[3];
--AB1L34 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_byteenable[0]~4
--operation mode is normal
AB1L34 = L1_M_mem_byte_en[0] # AB1L11 & !AB1_onchip_ram_64_kbytes_s1_arb_addend[1] # !AB1L3;
--R1_counter_snapshot[2] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[2]
--operation mode is normal
R1_counter_snapshot[2]_lut_out = !R1_internal_counter[2];
R1_counter_snapshot[2] = DFFEAS(R1_counter_snapshot[2]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_period_h_register[2] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[2]
--operation mode is normal
R1_period_h_register[2]_lut_out = L1_M_st_data[2];
R1_period_h_register[2] = DFFEAS(R1_period_h_register[2]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1L163 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[2]~1249
--operation mode is normal
R1L163 = HE1L15 & (R1_period_h_register[2] # HE1L17 & R1_counter_snapshot[2]) # !HE1L15 & HE1L17 & R1_counter_snapshot[2];
--R1_counter_snapshot[18] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[18]
--operation mode is normal
R1_counter_snapshot[18]_lut_out = R1_internal_counter[18];
R1_counter_snapshot[18] = DFFEAS(R1_counter_snapshot[18]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_control_register[2] is std_1s10:inst|high_res_timer:the_high_res_timer|control_register[2]
--operation mode is normal
R1_control_register[2]_lut_out = L1_M_st_data[2];
R1_control_register[2] = DFFEAS(R1_control_register[2]_lut_out, DE1__clk0, E1_data_out, , R1_control_wr_strobe, , , , );
--R1L164 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[2]~1250
--operation mode is normal
R1L164 = HE1L19 & (R1_control_register[2] # HE1L18 & R1_counter_snapshot[18]) # !HE1L19 & HE1L18 & R1_counter_snapshot[18];
--R1_period_l_register[2] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[2]
--operation mode is normal
R1_period_l_register[2]_lut_out = !L1_M_st_data[2];
R1_period_l_register[2] = DFFEAS(R1_period_l_register[2]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--HE1_control_reg[2] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[2]
--operation mode is normal
HE1_control_reg[2]_lut_out = L1_M_st_data[2];
HE1_control_reg[2] = DFFEAS(HE1_control_reg[2]_lut_out, DE1__clk0, E1_data_out, , HE1L13, , , , );
--HE1L51 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[2]~675
--operation mode is normal
HE1L51 = L1_M_alu_result[3] & (HE1_control_reg[2]) # !L1_M_alu_result[3] & HE1_internal_tx_data[2];
--JE1_break_detect is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|break_detect
--operation mode is normal
JE1_break_detect_lut_out = !HE1L63 & (JE1_break_detect # JE1_got_new_char & !JE1L71);
JE1_break_detect = DFFEAS(JE1_break_detect_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1_rx_data[2] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[2]
--operation mode is normal
JE1_rx_data[2]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3];
JE1_rx_data[2] = DFFEAS(JE1_rx_data[2]_lut_out, DE1__clk0, E1_data_out, , JE1_got_new_char, , , , );
--HE1L52 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[2]~676
--operation mode is normal
HE1L52 = L1_M_alu_result[3] & JE1_break_detect # !L1_M_alu_result[3] & (JE1_rx_data[2]);
--DD1_internal_jdo1[23] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[23]
--operation mode is normal
DD1_internal_jdo1[23] = AMPP_FUNCTION(!A1L9, DD1_sr[23], VCC, DD1L144);
--VC1L5 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_go~102
--operation mode is normal
VC1L5 = AMPP_FUNCTION(DD1_internal_jdo1[34], DD1L189, A1L4, VC1_internal_monitor_go);
--CD1_MonWr is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonWr
--operation mode is normal
CD1_MonWr = AMPP_FUNCTION(DE1__clk0, CD1_MonWr, VC1_resetrequest, GND, P1L30, !C1_CLR_SIGNAL, DD1L191, DD1L189);
--P1L31 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[0]~4
--operation mode is normal
P1L31 = L1_M_mem_byte_en[0] # !P1L3;
--CD1_internal_MonDReg[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[0]
--operation mode is normal
CD1_internal_MonDReg[0] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[3], CD1L28, CD1_MonRd1, DD1L191, !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]
--operation mode is normal
CD1_internal_MonDReg[1] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[1], CD1L19, DD1_internal_jdo1[4], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L30, CD1L29);
--CD1_internal_MonDReg[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[2]
--operation mode is normal
CD1_internal_MonDReg[2] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[2], CD1L20, DD1_internal_jdo1[5], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L30, CD1L29);
--CD1_internal_MonDReg[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[3]
--operation mode is normal
CD1_internal_MonDReg[3] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[3], CD1L1, DD1_internal_jdo1[6], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L30, CD1L29);
--CD1_internal_MonDReg[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[4]
--operation mode is normal
CD1_internal_MonDReg[4] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[4], CD1L19, DD1_internal_jdo1[7], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L30, CD1L29);
--CD1_internal_MonDReg[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[5]
--operation mode is normal
CD1_internal_MonDReg[5] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[5], CD1L21, DD1_internal_jdo1[8], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L30, CD1L29);
--CD1_internal_MonDReg[6] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[6]
--operation mode is normal
CD1_internal_MonDReg[6] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[9], PD1_q_b[6], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[7] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[7]
--operation mode is normal
CD1_internal_MonDReg[7] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[10], PD1_q_b[7], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_MonAReg[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[2]
--operation mode is normal
CD1_MonAReg[2] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[26], CD1L73, CD1L2, DD1L190, !C1_CLR_SIGNAL, DD1L192);
--CD1_MonAReg[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[3]
--operation mode is normal
CD1_MonAReg[3] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[27], CD1L74, CD1L4, DD1L190, !C1_CLR_SIGNAL, DD1L192);
--CD1_MonAReg[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[4]
--operation mode is normal
CD1_MonAReg[4] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[28], CD1L75, CD1L6, DD1L190, !C1_CLR_SIGNAL, DD1L192);
--CD1_MonAReg[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[5]
--operation mode is normal
CD1_MonAReg[5] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[29], CD1L76, CD1L8, DD1L190, !C1_CLR_SIGNAL, DD1L192);
--CD1_MonAReg[6] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[6]
--operation mode is normal
CD1_MonAReg[6] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[30], CD1L77, CD1L10, DD1L190, !C1_CLR_SIGNAL, DD1L192);
--CD1_MonAReg[7] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[7]
--operation mode is normal
CD1_MonAReg[7] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[31], CD1L78, CD1L12, DD1L190, !C1_CLR_SIGNAL, DD1L192);
--CD1_MonAReg[8] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[8]
--operation mode is normal
CD1_MonAReg[8] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[32], CD1L79, CD1L14, DD1L190, !C1_CLR_SIGNAL, DD1L192);
--CD1_MonAReg[9] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[9]
--operation mode is normal
CD1_MonAReg[9] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[33], CD1L80, CD1L16, DD1L190, !C1_CLR_SIGNAL, DD1L192);
--AB1L36 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_byteenable[2]~5
--operation mode is normal
AB1L36 = L1_M_mem_byte_en[2] # AB1L11 & !AB1_onchip_ram_64_kbytes_s1_arb_addend[1] # !AB1L3;
--FB1_za_data[18] is std_1s10:inst|sdram:the_sdram|za_data[18]
--operation mode is normal
FB1_za_data[18]_lut_out = A1L249;
FB1_za_data[18] = DFFEAS(FB1_za_data[18]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L284 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[18]~2080
--operation mode is normal
M1L284 = L1_M_alu_result[25] # FB1_za_data[18] # !QB1L4 # !L1_M_alu_result[24];
--ZD2_safe_q[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[2]
--operation mode is arithmetic
ZD2_safe_q[2]_carry_eqn = ZD2L4;
ZD2_safe_q[2]_lut_out = ZD2_safe_q[2] $ (!ZD2_safe_q[2]_carry_eqn);
ZD2_safe_q[2] = DFFEAS(ZD2_safe_q[2]_lut_out, DE1__clk0, E1_data_out, , WD2L1, , , , );
--ZD2L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella2~COUT
--operation mode is arithmetic
ZD2L6 = CARRY(!ZD2L4 & (ZD2_safe_q[2] $ !T1_wr_rfifo));
--T1L16 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~294
--operation mode is arithmetic
T1L16 = ZD1_safe_q[2] $ (T1L16_carry_eqn);
--T1L17 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~295
--operation mode is arithmetic
T1L17 = CARRY(!ZD1_safe_q[2] & (!T1L33));
--T1L18 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~296
--operation mode is normal
T1L18 = T1_read_0 & ZD2_safe_q[2] # !T1_read_0 & (T1L16);
--M1L310 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|process5~0
--operation mode is normal
M1L310 = M1_internal_cpu_data_master_dbs_address[1] & M1L307 & (!M1_internal_cpu_data_master_dbs_address[0]);
--P1L33 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[2]~5
--operation mode is normal
P1L33 = L1_M_mem_byte_en[2] # !P1L3;
--CD1_internal_MonDReg[16] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[16]
--operation mode is normal
CD1_internal_MonDReg[16] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[19], PD1_q_b[16], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[17] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[17]
--operation mode is normal
CD1_internal_MonDReg[17] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[20], PD1_q_b[17], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[18] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[18]
--operation mode is normal
CD1_internal_MonDReg[18] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[18], CD1L22, DD1_internal_jdo1[21], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L30, CD1L29);
--CD1_internal_MonDReg[19] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[19]
--operation mode is normal
CD1_internal_MonDReg[19] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[22], PD1_q_b[19], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[20] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[20]
--operation mode is normal
CD1_internal_MonDReg[20] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[23], PD1_q_b[20], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[21] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[21]
--operation mode is normal
CD1_internal_MonDReg[21] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[24], PD1_q_b[21], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[22] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[22]
--operation mode is normal
CD1_internal_MonDReg[22] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[25], PD1_q_b[22], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[23] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[23]
--operation mode is normal
CD1_internal_MonDReg[23] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[26], PD1_q_b[23], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--L1_i_readdata_d1[12] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[12]
--operation mode is normal
L1_i_readdata_d1[12] = AMPP_FUNCTION(DE1__clk0, N1L45, FC1L21, FC1L15, P1L10, E1_data_out);
--L1_i_readdata_d1[11] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[11]
--operation mode is normal
L1_i_readdata_d1[11] = AMPP_FUNCTION(DE1__clk0, N1L42, FC1L21, FC1L14, P1L10, E1_data_out);
--L1_i_readdata_d1[16] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[16]
--operation mode is normal
L1_i_readdata_d1[16] = AMPP_FUNCTION(DE1__clk0, N1L57, FC1L21, FC1L19, P1L10, E1_data_out);
--L1_i_readdata_d1[14] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[14]
--operation mode is normal
L1_i_readdata_d1[14] = AMPP_FUNCTION(DE1__clk0, N1L51, FC1L21, FC1L17, P1L10, E1_data_out);
--L1_i_readdata_d1[13] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[13]
--operation mode is normal
L1_i_readdata_d1[13] = AMPP_FUNCTION(DE1__clk0, N1L48, FC1L21, FC1L16, P1L10, E1_data_out);
--L1_i_readdata_d1[21] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[21]
--operation mode is normal
L1_i_readdata_d1[21] = AMPP_FUNCTION(DE1__clk0, N1L72, FC1L21, FC1L25, P1L10, E1_data_out);
--KE1_tx_overrun is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_overrun
--operation mode is normal
KE1_tx_overrun_lut_out = !HE1L63 & (KE1_tx_overrun # KE1_internal_tx_ready & KE1L32);
KE1_tx_overrun = DFFEAS(KE1_tx_overrun_lut_out, DE1__clk0, E1_data_out, , , , , , );
--HE1_control_reg[4] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[4]
--operation mode is normal
HE1_control_reg[4]_lut_out = L1_M_st_data[4];
HE1_control_reg[4] = DFFEAS(HE1_control_reg[4]_lut_out, DE1__clk0, E1_data_out, , HE1L13, , , , );
--HE1_control_reg[5] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[5]
--operation mode is normal
HE1_control_reg[5]_lut_out = L1_M_st_data[5];
HE1_control_reg[5] = DFFEAS(HE1_control_reg[5]_lut_out, DE1__clk0, E1_data_out, , HE1L13, , , , );
--KE1_tx_shift_empty is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_shift_empty
--operation mode is normal
KE1_tx_shift_empty_lut_out = KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] # KE1_internal_tx_ready # !KE1L28;
KE1_tx_shift_empty = DFFEAS(KE1_tx_shift_empty_lut_out, DE1__clk0, E1_data_out, , , , , , );
--HE1L33 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~115
--operation mode is normal
HE1L33 = KE1_tx_overrun & (HE1_control_reg[4] # HE1_control_reg[5] & !KE1_tx_shift_empty) # !KE1_tx_overrun & (HE1_control_reg[5] & !KE1_tx_shift_empty);
--JE1_framing_error is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|framing_error
--operation mode is normal
JE1_framing_error_lut_out = JE1L39 & (!HE1L63);
JE1_framing_error = DFFEAS(JE1_framing_error_lut_out, DE1__clk0, E1_data_out, , , , , , );
--HE1_control_reg[1] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[1]
--operation mode is normal
HE1_control_reg[1]_lut_out = L1_M_st_data[1];
HE1_control_reg[1] = DFFEAS(HE1_control_reg[1]_lut_out, DE1__clk0, E1_data_out, , HE1L13, , , , );
--HE1_control_reg[6] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[6]
--operation mode is normal
HE1_control_reg[6]_lut_out = L1_M_st_data[6];
HE1_control_reg[6] = DFFEAS(HE1_control_reg[6]_lut_out, DE1__clk0, E1_data_out, , HE1L13, , , , );
--KE1_internal_tx_ready is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|internal_tx_ready
--operation mode is normal
KE1_internal_tx_ready_lut_out = L1_internal_d_write & HE1L19 & JE1L54 # !KE1L24;
KE1_internal_tx_ready = DFFEAS(KE1_internal_tx_ready_lut_out, DE1__clk0, E1_data_out, , , , , , );
--HE1L34 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~116
--operation mode is normal
HE1L34 = JE1_framing_error & (HE1_control_reg[1] # HE1_control_reg[6] & !KE1_internal_tx_ready) # !JE1_framing_error & (HE1_control_reg[6] & !KE1_internal_tx_ready);
--HE1_control_reg[8] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[8]
--operation mode is normal
HE1_control_reg[8]_lut_out = L1_M_st_data[8];
HE1_control_reg[8] = DFFEAS(HE1_control_reg[8]_lut_out, DE1__clk0, E1_data_out, , HE1L13, , , , );
--JE1_rx_overrun is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_overrun
--operation mode is normal
JE1_rx_overrun_lut_out = !HE1L63 & (JE1_rx_overrun # JE1_internal_rx_char_ready & JE1_got_new_char);
JE1_rx_overrun = DFFEAS(JE1_rx_overrun_lut_out, DE1__clk0, E1_data_out, , , , , , );
--HE1L1 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|any_error~21
--operation mode is normal
HE1L1 = JE1_break_detect # JE1_framing_error # JE1_rx_overrun # KE1_tx_overrun;
--HE1L35 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~117
--operation mode is normal
HE1L35 = HE1L33 # HE1L34 # HE1_control_reg[8] & HE1L1;
--HE1_control_reg[3] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[3]
--operation mode is normal
HE1_control_reg[3]_lut_out = L1_M_st_data[3];
HE1_control_reg[3] = DFFEAS(HE1_control_reg[3]_lut_out, DE1__clk0, E1_data_out, , HE1L13, , , , );
--HE1L36 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~118
--operation mode is normal
HE1L36 = JE1_break_detect & (HE1_control_reg[2] # JE1_rx_overrun & HE1_control_reg[3]) # !JE1_break_detect & JE1_rx_overrun & HE1_control_reg[3];
--HE1_control_reg[7] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[7]
--operation mode is normal
HE1_control_reg[7]_lut_out = L1_M_st_data[7];
HE1_control_reg[7] = DFFEAS(HE1_control_reg[7]_lut_out, DE1__clk0, E1_data_out, , HE1L13, , , , );
--JE1_internal_rx_char_ready is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|internal_rx_char_ready
--operation mode is normal
JE1_internal_rx_char_ready_lut_out = JE1L42 & (!JE1L54 # !HE1L21 # !L1_internal_d_read);
JE1_internal_rx_char_ready = DFFEAS(JE1_internal_rx_char_ready_lut_out, DE1__clk0, E1_data_out, , , , , , );
--F1L27 is std_1s10:inst|button_pio:the_button_pio|read_mux_out[3]~378
--operation mode is normal
F1L27 = L1_M_alu_result[2] & F1_edge_capture[3] # !L1_M_alu_result[2] & (F1_irq_mask[3]);
--AE2_q_b[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE2_q_b[3]_PORT_A_data_in = QD1_wdata[3];
AE2_q_b[3]_PORT_A_data_in_reg = DFFE(AE2_q_b[3]_PORT_A_data_in, AE2_q_b[3]_clock_0, , , AE2_q_b[3]_clock_enable_0);
AE2_q_b[3]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[3]_PORT_A_address_reg = DFFE(AE2_q_b[3]_PORT_A_address, AE2_q_b[3]_clock_0, , , AE2_q_b[3]_clock_enable_0);
AE2_q_b[3]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[3]_PORT_B_address_reg = DFFE(AE2_q_b[3]_PORT_B_address, AE2_q_b[3]_clock_1, , , AE2_q_b[3]_clock_enable_1);
AE2_q_b[3]_PORT_A_write_enable = VCC;
AE2_q_b[3]_PORT_A_write_enable_reg = DFFE(AE2_q_b[3]_PORT_A_write_enable, AE2_q_b[3]_clock_0, , , AE2_q_b[3]_clock_enable_0);
AE2_q_b[3]_PORT_B_read_enable = VCC;
AE2_q_b[3]_PORT_B_read_enable_reg = DFFE(AE2_q_b[3]_PORT_B_read_enable, AE2_q_b[3]_clock_1, , , AE2_q_b[3]_clock_enable_1);
AE2_q_b[3]_clock_0 = DE1__clk0;
AE2_q_b[3]_clock_1 = DE1__clk0;
AE2_q_b[3]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[3]_clock_enable_1 = T1L61;
AE2_q_b[3]_PORT_B_data_out = MEMORY(AE2_q_b[3]_PORT_A_data_in_reg, , AE2_q_b[3]_PORT_A_address_reg, AE2_q_b[3]_PORT_B_address_reg, AE2_q_b[3]_PORT_A_write_enable_reg, AE2_q_b[3]_PORT_B_read_enable_reg, , , AE2_q_b[3]_clock_0, AE2_q_b[3]_clock_1, AE2_q_b[3]_clock_enable_0, AE2_q_b[3]_clock_enable_1, , );
AE2_q_b[3] = AE2_q_b[3]_PORT_B_data_out[0];
--M1L299 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~19
--operation mode is normal
M1L299 = AE2_q_b[3] & T1_read_0 # !U1L2 # !EB1L2;
--H1_slave_readdata[3] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[3]
--operation mode is normal
H1_slave_readdata[3]_lut_out = H1_slave_readdata_p1[3];
H1_slave_readdata[3] = DFFEAS(H1_slave_readdata[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L271 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[3]~2082
--operation mode is normal
M1L271 = H1_slave_readdata[3] # !J1_cpu_data_master_requests_clock_0_in;
--FB1_za_data[3] is std_1s10:inst|sdram:the_sdram|za_data[3]
--operation mode is normal
FB1_za_data[3]_lut_out = A1L264;
FB1_za_data[3] = DFFEAS(FB1_za_data[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--KB1_counter_snapshot[3] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[3]
--operation mode is normal
KB1_counter_snapshot[3]_lut_out = !KB1_internal_counter[3];
KB1_counter_snapshot[3] = DFFEAS(KB1_counter_snapshot[3]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_period_h_register[3] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[3]
--operation mode is normal
KB1_period_h_register[3]_lut_out = L1_M_st_data[3];
KB1_period_h_register[3] = DFFEAS(KB1_period_h_register[3]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1L166 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[3]~1240
--operation mode is normal
KB1L166 = HE1L15 & (KB1_period_h_register[3] # HE1L17 & KB1_counter_snapshot[3]) # !HE1L15 & HE1L17 & KB1_counter_snapshot[3];
--KB1_counter_snapshot[19] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[19]
--operation mode is normal
KB1_counter_snapshot[19]_lut_out = KB1_internal_counter[19];
KB1_counter_snapshot[19] = DFFEAS(KB1_counter_snapshot[19]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_control_register[3] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|control_register[3]
--operation mode is normal
KB1_control_register[3]_lut_out = L1_M_st_data[3];
KB1_control_register[3] = DFFEAS(KB1_control_register[3]_lut_out, DE1__clk0, E1_data_out, , KB1_control_wr_strobe, , , , );
--KB1L167 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[3]~1241
--operation mode is normal
KB1L167 = HE1L19 & (KB1_control_register[3] # HE1L18 & KB1_counter_snapshot[19]) # !HE1L19 & HE1L18 & KB1_counter_snapshot[19];
--KB1_period_l_register[3] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[3]
--operation mode is normal
KB1_period_l_register[3]_lut_out = !L1_M_st_data[3];
KB1_period_l_register[3] = DFFEAS(KB1_period_l_register[3]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--R1_counter_snapshot[3] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[3]
--operation mode is normal
R1_counter_snapshot[3]_lut_out = !R1_internal_counter[3];
R1_counter_snapshot[3] = DFFEAS(R1_counter_snapshot[3]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_period_h_register[3] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[3]
--operation mode is normal
R1_period_h_register[3]_lut_out = L1_M_st_data[3];
R1_period_h_register[3] = DFFEAS(R1_period_h_register[3]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1L165 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[3]~1251
--operation mode is normal
R1L165 = HE1L15 & (R1_period_h_register[3] # HE1L17 & R1_counter_snapshot[3]) # !HE1L15 & HE1L17 & R1_counter_snapshot[3];
--R1_counter_snapshot[19] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[19]
--operation mode is normal
R1_counter_snapshot[19]_lut_out = R1_internal_counter[19];
R1_counter_snapshot[19] = DFFEAS(R1_counter_snapshot[19]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_control_register[3] is std_1s10:inst|high_res_timer:the_high_res_timer|control_register[3]
--operation mode is normal
R1_control_register[3]_lut_out = L1_M_st_data[3];
R1_control_register[3] = DFFEAS(R1_control_register[3]_lut_out, DE1__clk0, E1_data_out, , R1_control_wr_strobe, , , , );
--R1L166 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[3]~1252
--operation mode is normal
R1L166 = HE1L19 & (R1_control_register[3] # HE1L18 & R1_counter_snapshot[19]) # !HE1L19 & HE1L18 & R1_counter_snapshot[19];
--R1_period_l_register[3] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[3]
--operation mode is normal
R1_period_l_register[3]_lut_out = !L1_M_st_data[3];
R1_period_l_register[3] = DFFEAS(R1_period_l_register[3]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--HE1L53 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[3]~678
--operation mode is normal
HE1L53 = L1_M_alu_result[3] & (HE1_control_reg[3]) # !L1_M_alu_result[3] & HE1_internal_tx_data[3];
--JE1_rx_data[3] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[3]
--operation mode is normal
JE1_rx_data[3]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4];
JE1_rx_data[3] = DFFEAS(JE1_rx_data[3]_lut_out, DE1__clk0, E1_data_out, , JE1_got_new_char, , , , );
--HE1L54 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[3]~679
--operation mode is normal
HE1L54 = L1_M_alu_result[3] & JE1_rx_overrun # !L1_M_alu_result[3] & (JE1_rx_data[3]);
--FB1_za_data[19] is std_1s10:inst|sdram:the_sdram|za_data[19]
--operation mode is normal
FB1_za_data[19]_lut_out = A1L248;
FB1_za_data[19] = DFFEAS(FB1_za_data[19]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L285 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[19]~2084
--operation mode is normal
M1L285 = L1_M_alu_result[25] # FB1_za_data[19] # !QB1L4 # !L1_M_alu_result[24];
--ZD2_safe_q[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[3]
--operation mode is arithmetic
ZD2_safe_q[3]_carry_eqn = ZD2L6;
ZD2_safe_q[3]_lut_out = ZD2_safe_q[3] $ (ZD2_safe_q[3]_carry_eqn);
ZD2_safe_q[3] = DFFEAS(ZD2_safe_q[3]_lut_out, DE1__clk0, E1_data_out, , WD2L1, , , , );
--ZD2L8 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella3~COUT
--operation mode is arithmetic
ZD2L8 = CARRY(ZD2_safe_q[3] $ T1_wr_rfifo # !ZD2L6);
--T1L19 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~297
--operation mode is arithmetic
T1L19 = ZD1_safe_q[3] $ (!T1L19_carry_eqn);
--T1L20 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~298
--operation mode is arithmetic
T1L20 = CARRY(ZD1_safe_q[3] # !T1L17);
--T1L21 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~299
--operation mode is normal
T1L21 = T1_read_0 & ZD2_safe_q[3] # !T1_read_0 & (T1L19);
--L1_i_readdata_d1[9] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[9]
--operation mode is normal
L1_i_readdata_d1[9] = AMPP_FUNCTION(DE1__clk0, N1L36, FC1L21, FC1L12, P1L10, E1_data_out);
--AE2_q_b[7] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE2_q_b[7]_PORT_A_data_in = QD1_wdata[7];
AE2_q_b[7]_PORT_A_data_in_reg = DFFE(AE2_q_b[7]_PORT_A_data_in, AE2_q_b[7]_clock_0, , , AE2_q_b[7]_clock_enable_0);
AE2_q_b[7]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[7]_PORT_A_address_reg = DFFE(AE2_q_b[7]_PORT_A_address, AE2_q_b[7]_clock_0, , , AE2_q_b[7]_clock_enable_0);
AE2_q_b[7]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[7]_PORT_B_address_reg = DFFE(AE2_q_b[7]_PORT_B_address, AE2_q_b[7]_clock_1, , , AE2_q_b[7]_clock_enable_1);
AE2_q_b[7]_PORT_A_write_enable = VCC;
AE2_q_b[7]_PORT_A_write_enable_reg = DFFE(AE2_q_b[7]_PORT_A_write_enable, AE2_q_b[7]_clock_0, , , AE2_q_b[7]_clock_enable_0);
AE2_q_b[7]_PORT_B_read_enable = VCC;
AE2_q_b[7]_PORT_B_read_enable_reg = DFFE(AE2_q_b[7]_PORT_B_read_enable, AE2_q_b[7]_clock_1, , , AE2_q_b[7]_clock_enable_1);
AE2_q_b[7]_clock_0 = DE1__clk0;
AE2_q_b[7]_clock_1 = DE1__clk0;
AE2_q_b[7]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[7]_clock_enable_1 = T1L61;
AE2_q_b[7]_PORT_B_data_out = MEMORY(AE2_q_b[7]_PORT_A_data_in_reg, , AE2_q_b[7]_PORT_A_address_reg, AE2_q_b[7]_PORT_B_address_reg, AE2_q_b[7]_PORT_A_write_enable_reg, AE2_q_b[7]_PORT_B_read_enable_reg, , , AE2_q_b[7]_clock_0, AE2_q_b[7]_clock_1, AE2_q_b[7]_clock_enable_0, AE2_q_b[7]_clock_enable_1, , );
AE2_q_b[7] = AE2_q_b[7]_PORT_B_data_out[0];
--M1L303 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~23
--operation mode is normal
M1L303 = AE2_q_b[7] & T1_read_0 # !U1L2 # !EB1L2;
--H1_slave_readdata[7] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[7]
--operation mode is normal
H1_slave_readdata[7]_lut_out = H1_slave_readdata_p1[7];
H1_slave_readdata[7] = DFFEAS(H1_slave_readdata[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L275 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[7]~2086
--operation mode is normal
M1L275 = H1_slave_readdata[7] # !J1_cpu_data_master_requests_clock_0_in;
--FB1_za_data[7] is std_1s10:inst|sdram:the_sdram|za_data[7]
--operation mode is normal
FB1_za_data[7]_lut_out = A1L260;
FB1_za_data[7] = DFFEAS(FB1_za_data[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--HE1L61 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[7]~681
--operation mode is normal
HE1L61 = L1_M_alu_result[3] & (HE1_control_reg[7]) # !L1_M_alu_result[3] & HE1_internal_tx_data[7];
--JE1_rx_data[7] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[7]
--operation mode is normal
JE1_rx_data[7]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8];
JE1_rx_data[7] = DFFEAS(JE1_rx_data[7]_lut_out, DE1__clk0, E1_data_out, , JE1_got_new_char, , , , );
--HE1L62 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[7]~682
--operation mode is normal
HE1L62 = L1_M_alu_result[3] & JE1_internal_rx_char_ready # !L1_M_alu_result[3] & (JE1_rx_data[7]);
--R1_counter_snapshot[7] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[7]
--operation mode is normal
R1_counter_snapshot[7]_lut_out = R1_internal_counter[7];
R1_counter_snapshot[7] = DFFEAS(R1_counter_snapshot[7]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_counter_snapshot[23] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[23]
--operation mode is normal
R1_counter_snapshot[23]_lut_out = R1_internal_counter[23];
R1_counter_snapshot[23] = DFFEAS(R1_counter_snapshot[23]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L173 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[7]~1253
--operation mode is normal
R1L173 = L1_M_alu_result[2] & (R1_counter_snapshot[23] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & R1_counter_snapshot[7];
--R1_period_h_register[7] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[7]
--operation mode is normal
R1_period_h_register[7]_lut_out = L1_M_st_data[7];
R1_period_h_register[7] = DFFEAS(R1_period_h_register[7]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1_period_l_register[7] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[7]
--operation mode is normal
R1_period_l_register[7]_lut_out = L1_M_st_data[7];
R1_period_l_register[7] = DFFEAS(R1_period_l_register[7]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--R1L174 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[7]~1254
--operation mode is normal
R1L174 = R1L173 & R1_period_h_register[7] # !R1L173 & (R1_period_l_register[7]);
--KB1_counter_snapshot[7] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[7]
--operation mode is normal
KB1_counter_snapshot[7]_lut_out = KB1_internal_counter[7];
KB1_counter_snapshot[7] = DFFEAS(KB1_counter_snapshot[7]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_counter_snapshot[23] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[23]
--operation mode is normal
KB1_counter_snapshot[23]_lut_out = KB1_internal_counter[23];
KB1_counter_snapshot[23] = DFFEAS(KB1_counter_snapshot[23]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1L174 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[7]~1242
--operation mode is normal
KB1L174 = L1_M_alu_result[2] & (KB1_counter_snapshot[23] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & KB1_counter_snapshot[7];
--KB1_period_h_register[7] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[7]
--operation mode is normal
KB1_period_h_register[7]_lut_out = L1_M_st_data[7];
KB1_period_h_register[7] = DFFEAS(KB1_period_h_register[7]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1_period_l_register[7] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[7]
--operation mode is normal
KB1_period_l_register[7]_lut_out = L1_M_st_data[7];
KB1_period_l_register[7] = DFFEAS(KB1_period_l_register[7]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--KB1L175 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[7]~1243
--operation mode is normal
KB1L175 = KB1L174 & KB1_period_h_register[7] # !KB1L174 & (KB1_period_l_register[7]);
--T1L22 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~300
--operation mode is normal
T1L22 = !T1L22_carry_eqn;
--M1L289 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[23]~2088
--operation mode is normal
M1L289 = T1L22 & !T1_read_0 # !U1L2 # !EB1L2;
--FB1_za_data[23] is std_1s10:inst|sdram:the_sdram|za_data[23]
--operation mode is normal
FB1_za_data[23]_lut_out = A1L244;
FB1_za_data[23] = DFFEAS(FB1_za_data[23]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--GC1L5 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~563
--operation mode is arithmetic
GC1L5 = AMPP_FUNCTION(L1L614, L1L680, GC1L7);
--L1_E_ctrl_alu_signed_cmp is std_1s10:inst|cpu:the_cpu|E_ctrl_alu_signed_cmp
--operation mode is normal
L1_E_ctrl_alu_signed_cmp = AMPP_FUNCTION(DE1__clk0, L1L190, L1L205, L1L819, L1L820, E1_data_out, L1_W_stall);
--L1L415 is std_1s10:inst|cpu:the_cpu|E_arith_src2~0
--operation mode is normal
L1L415 = AMPP_FUNCTION(L1_E_ctrl_src2_is_imm, L1L789, L1_E_src2_imm[31], L1_E_ctrl_alu_signed_cmp);
--L1L414 is std_1s10:inst|cpu:the_cpu|E_arith_src1~0
--operation mode is normal
L1L414 = AMPP_FUNCTION(L1L615, L1_E_ctrl_alu_signed_cmp);
--HC1_result[30] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[30]
--operation mode is arithmetic
HC1_result[30] = AMPP_FUNCTION(L1L680, L1L614, HC1L61, L1_E_ctrl_alu_subtract);
--HC1L63 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[30]~COUT
--operation mode is arithmetic
HC1L63 = AMPP_FUNCTION(L1L680, L1L614, HC1L61, L1_E_ctrl_alu_subtract);
--DD1_sr[19] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[19]
--operation mode is normal
DD1_sr[19] = AMPP_FUNCTION(!A1L6, DD1_sr[20], DD1L70, DD1L23, DD1L24, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[18] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[18]
--operation mode is normal
DD1_sr[18] = AMPP_FUNCTION(!A1L6, DD1L26, DD1_sr[19], DD1L9, DD1L27, !C1_CLR_SIGNAL, DD1L12);
--TC1_break_readreg[20] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[20]
--operation mode is normal
TC1_break_readreg[20] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[20], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L7 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19891
--operation mode is normal
DD1L7 = AMPP_FUNCTION(TC1_break_readreg[20], CD1_internal_MonDReg[20], DD1_ir[1]);
--DD1L8 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19892
--operation mode is normal
DD1L8 = AMPP_FUNCTION(DD1L144, DD1L142, DD1L7, DD1_ir[0]);
--DD1L9 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19893
--operation mode is normal
DD1L9 = AMPP_FUNCTION(DD1_ir[0], DD1_ir[1], DD1L144, A1L5);
--DD1L10 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19894
--operation mode is normal
DD1L10 = AMPP_FUNCTION(DD1L7, DD1L144, A1L5, DD1_ir[0]);
--DD1L11 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19896
--operation mode is normal
DD1L11 = AMPP_FUNCTION(DD1_ir[0], DD1_ir[1]);
--DD1L12 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19897
--operation mode is normal
DD1L12 = AMPP_FUNCTION(DD1L143, DD1L141, DD1L11, DD1_st_updateir);
--C1L27 is sld_hub:sld_hub_inst|jtag_debug_mode~171
--operation mode is normal
C1L27 = AMPP_FUNCTION(A1L8, RE1_state[12], RE1_state[2]);
--RE1_state[15] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15]
--operation mode is normal
RE1_state[15] = AMPP_FUNCTION(!A1L6, RE1_state[12], RE1_state[14], VCC, A1L8);
--SE1_dffe1a[1] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[1]
--operation mode is normal
SE1_dffe1a[1] = AMPP_FUNCTION(!A1L6, ME3_Q[1], C1L26, ME3_Q[3], ME3_Q[2], !C1_CLR_SIGNAL, C1L5);
--SE1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[2]
--operation mode is normal
SE1_dffe1a[2] = AMPP_FUNCTION(!A1L6, ME3_Q[2], C1L26, ME3_Q[1], ME3_Q[3], !C1_CLR_SIGNAL, C1L5);
--C1L1 is sld_hub:sld_hub_inst|BROADCAST_ENA~28
--operation mode is normal
C1L1 = AMPP_FUNCTION(RE1_state[8], C1_OK_TO_UPDATE_IR_Q, SE1_dffe1a[1], SE1_dffe1a[2]);
--TC1_break_readreg[19] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[19]
--operation mode is normal
TC1_break_readreg[19] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[19], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L13 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19898
--operation mode is normal
DD1L13 = AMPP_FUNCTION(TC1_break_readreg[19], CD1_internal_MonDReg[19], DD1_ir[1]);
--DD1L14 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19899
--operation mode is normal
DD1L14 = AMPP_FUNCTION(DD1L144, DD1L142, DD1L13, DD1_ir[0]);
--DD1L15 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19900
--operation mode is normal
DD1L15 = AMPP_FUNCTION(DD1L13, DD1L144, A1L5, DD1_ir[0]);
--SE1_dffe1a[7] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[7]
--operation mode is normal
SE1_dffe1a[7] = AMPP_FUNCTION(!A1L6, ME3_Q[1], ME3_Q[3], ME3_Q[2], C1L26, !C1_CLR_SIGNAL, C1L5);
--C1L2 is sld_hub:sld_hub_inst|BROADCAST_ENA~29
--operation mode is normal
C1L2 = AMPP_FUNCTION(RE1_state[8], C1_OK_TO_UPDATE_IR_Q);
--VC1_internal_monitor_error is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_error
--operation mode is normal
VC1_internal_monitor_error = AMPP_FUNCTION(DE1__clk0, VC1L3, L1_M_st_data[1], SC1L13, DD1L190, VCC);
--DD1L16 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19902
--operation mode is normal
DD1L16 = AMPP_FUNCTION(VC1_internal_monitor_error, DD1_ir[0], DD1_ir[1]);
--DD1L17 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19903
--operation mode is normal
DD1L17 = AMPP_FUNCTION(DD1_ir[0], DD1_ir[1], DD1L144, A1L5);
--DD1_st_updatedr is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updatedr
--operation mode is normal
DD1_st_updatedr = AMPP_FUNCTION(!A1L6, DD1L144, VCC, !A1L9);
--DD1L131 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux41~108
--operation mode is normal
DD1L131 = AMPP_FUNCTION(DD1_DRsize[2], altera_internal_jtag, DD1_DRsize[1], DD1_DRsize[0]);
--DD1_sr[36] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[36]
--operation mode is normal
DD1_sr[36] = AMPP_FUNCTION(!A1L6, DD1_sr[37], DD1L28, DD1L144, A1L5, !C1_CLR_SIGNAL, DD1L30);
--DD1L132 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux41~109
--operation mode is normal
DD1L132 = AMPP_FUNCTION(DD1_sr[36], DD1_DRsize[1], DD1_DRsize[0], DD1_DRsize[2]);
--DD1L18 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19905
--operation mode is normal
DD1L18 = AMPP_FUNCTION(DD1L144, DD1L131, DD1L132, A1L5);
--DD1L133 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux41~110
--operation mode is normal
DD1L133 = AMPP_FUNCTION(DD1L131, DD1L132);
--DD1L19 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19906
--operation mode is normal
DD1L19 = AMPP_FUNCTION(DD1L133, DD1L143, L1_hbreak_enabled, DD1_ir[1]);
--ME7_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[0]
--operation mode is normal
ME7_Q[0] = AMPP_FUNCTION(!A1L6, ME3_Q[0], !C1_CLR_SIGNAL, C1L8);
--C1L9 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~18
--operation mode is normal
C1L9 = AMPP_FUNCTION(C1_OK_TO_UPDATE_IR_Q, RE1_state[5]);
--C1L19 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~125
--operation mode is normal
C1L19 = AMPP_FUNCTION(ME9_Q[0], ME2_Q[0], SE1_dffe1a[2]);
--C1L20 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~126
--operation mode is normal
C1L20 = AMPP_FUNCTION(C1L9, C1L19, ME8_Q[0], ME2_Q[0]);
--DD1L145 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process4~0
--operation mode is normal
DD1L145 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, ME8_Q[0], C1_jtag_debug_mode, ME2_Q[0]);
--ME7_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[1]
--operation mode is normal
ME7_Q[1] = AMPP_FUNCTION(!A1L6, ME3_Q[1], !C1_CLR_SIGNAL, C1L8);
--R1_control_wr_strobe is std_1s10:inst|high_res_timer:the_high_res_timer|control_wr_strobe
--operation mode is normal
R1_control_wr_strobe = KB1L7 & LB1L2 & S1L2 & HE1L19;
--R1_internal_counter[0] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[0]
--operation mode is arithmetic
R1_internal_counter[0]_lut_out = !R1_internal_counter[0];
R1_internal_counter[0] = DFFEAS(R1_internal_counter[0]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[0], , , R1L156);
--R1L57 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[0]~2944
--operation mode is arithmetic
R1L57 = CARRY(!R1_internal_counter[0]);
--R1_internal_counter[1] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[1]
--operation mode is arithmetic
R1_internal_counter[1]_carry_eqn = R1L57;
R1_internal_counter[1]_lut_out = R1_internal_counter[1] $ (!R1_internal_counter[1]_carry_eqn);
R1_internal_counter[1] = DFFEAS(R1_internal_counter[1]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[1], , , R1L156);
--R1L59 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[1]~2945
--operation mode is arithmetic
R1L59 = CARRY(R1_internal_counter[1] & (!R1L57));
--R1_internal_counter[2] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[2]
--operation mode is arithmetic
R1_internal_counter[2]_carry_eqn = R1L59;
R1_internal_counter[2]_lut_out = R1_internal_counter[2] $ (R1_internal_counter[2]_carry_eqn);
R1_internal_counter[2] = DFFEAS(R1_internal_counter[2]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[2], , , R1L156);
--R1L61 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[2]~2946
--operation mode is arithmetic
R1L61 = CARRY(!R1L59 # !R1_internal_counter[2]);
--R1_internal_counter[3] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[3]
--operation mode is arithmetic
R1_internal_counter[3]_carry_eqn = R1L61;
R1_internal_counter[3]_lut_out = R1_internal_counter[3] $ (!R1_internal_counter[3]_carry_eqn);
R1_internal_counter[3] = DFFEAS(R1_internal_counter[3]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[3], , , R1L156);
--R1L63 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[3]~2947
--operation mode is arithmetic
R1L63 = CARRY(R1_internal_counter[3] & (!R1L61));
--R1L44 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~364
--operation mode is normal
R1L44 = R1_internal_counter[0] & R1_internal_counter[1] & R1_internal_counter[2] & R1_internal_counter[3];
--R1_internal_counter[6] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[6]
--operation mode is arithmetic
R1_internal_counter[6]_carry_eqn = R1L67;
R1_internal_counter[6]_lut_out = R1_internal_counter[6] $ (R1_internal_counter[6]_carry_eqn);
R1_internal_counter[6] = DFFEAS(R1_internal_counter[6]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[6], , , R1L156);
--R1L69 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[6]~2948
--operation mode is arithmetic
R1L69 = CARRY(!R1L67 # !R1_internal_counter[6]);
--R1_internal_counter[4] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[4]
--operation mode is arithmetic
R1_internal_counter[4]_carry_eqn = R1L63;
R1_internal_counter[4]_lut_out = R1_internal_counter[4] $ (R1_internal_counter[4]_carry_eqn);
R1_internal_counter[4] = DFFEAS(R1_internal_counter[4]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[4], , , R1L156);
--R1L65 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[4]~2949
--operation mode is arithmetic
R1L65 = CARRY(R1_internal_counter[4] # !R1L63);
--R1_internal_counter[5] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[5]
--operation mode is arithmetic
R1_internal_counter[5]_carry_eqn = R1L65;
R1_internal_counter[5]_lut_out = R1_internal_counter[5] $ (!R1_internal_counter[5]_carry_eqn);
R1_internal_counter[5] = DFFEAS(R1_internal_counter[5]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[5], , , R1L156);
--R1L67 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[5]~2950
--operation mode is arithmetic
R1L67 = CARRY(!R1_internal_counter[5] & (!R1L65));
--R1_internal_counter[7] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[7]
--operation mode is arithmetic
R1_internal_counter[7]_carry_eqn = R1L69;
R1_internal_counter[7]_lut_out = R1_internal_counter[7] $ (!R1_internal_counter[7]_carry_eqn);
R1_internal_counter[7] = DFFEAS(R1_internal_counter[7]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[7], , , R1L156);
--R1L71 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[7]~2951
--operation mode is arithmetic
R1L71 = CARRY(!R1_internal_counter[7] & (!R1L69));
--R1L45 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~365
--operation mode is normal
R1L45 = R1_internal_counter[6] & !R1_internal_counter[4] & !R1_internal_counter[5] & !R1_internal_counter[7];
--R1_internal_counter[8] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[8]
--operation mode is arithmetic
R1_internal_counter[8]_carry_eqn = R1L71;
R1_internal_counter[8]_lut_out = R1_internal_counter[8] $ (R1_internal_counter[8]_carry_eqn);
R1_internal_counter[8] = DFFEAS(R1_internal_counter[8]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[8], , , R1L156);
--R1L73 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[8]~2952
--operation mode is arithmetic
R1L73 = CARRY(!R1L71 # !R1_internal_counter[8]);
--R1_internal_counter[9] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[9]
--operation mode is arithmetic
R1_internal_counter[9]_carry_eqn = R1L73;
R1_internal_counter[9]_lut_out = R1_internal_counter[9] $ (!R1_internal_counter[9]_carry_eqn);
R1_internal_counter[9] = DFFEAS(R1_internal_counter[9]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[9], , , R1L156);
--R1L75 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[9]~2953
--operation mode is arithmetic
R1L75 = CARRY(R1_internal_counter[9] & (!R1L73));
--R1_internal_counter[10] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[10]
--operation mode is arithmetic
R1_internal_counter[10]_carry_eqn = R1L75;
R1_internal_counter[10]_lut_out = R1_internal_counter[10] $ (R1_internal_counter[10]_carry_eqn);
R1_internal_counter[10] = DFFEAS(R1_internal_counter[10]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[10], , , R1L156);
--R1L77 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[10]~2954
--operation mode is arithmetic
R1L77 = CARRY(R1_internal_counter[10] # !R1L75);
--R1_internal_counter[11] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[11]
--operation mode is arithmetic
R1_internal_counter[11]_carry_eqn = R1L77;
R1_internal_counter[11]_lut_out = R1_internal_counter[11] $ (!R1_internal_counter[11]_carry_eqn);
R1_internal_counter[11] = DFFEAS(R1_internal_counter[11]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[11], , , R1L156);
--R1L79 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[11]~2955
--operation mode is arithmetic
R1L79 = CARRY(!R1_internal_counter[11] & (!R1L77));
--R1L46 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~366
--operation mode is normal
R1L46 = R1_internal_counter[8] & R1_internal_counter[9] & !R1_internal_counter[10] & !R1_internal_counter[11];
--R1_internal_counter[14] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[14]
--operation mode is arithmetic
R1_internal_counter[14]_carry_eqn = R1L83;
R1_internal_counter[14]_lut_out = R1_internal_counter[14] $ (R1_internal_counter[14]_carry_eqn);
R1_internal_counter[14] = DFFEAS(R1_internal_counter[14]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[14], , , R1L156);
--R1L85 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[14]~2956
--operation mode is arithmetic
R1L85 = CARRY(!R1L83 # !R1_internal_counter[14]);
--R1_internal_counter[15] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[15]
--operation mode is arithmetic
R1_internal_counter[15]_carry_eqn = R1L85;
R1_internal_counter[15]_lut_out = R1_internal_counter[15] $ (!R1_internal_counter[15]_carry_eqn);
R1_internal_counter[15] = DFFEAS(R1_internal_counter[15]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[15], , , R1L156);
--R1L87 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[15]~2957
--operation mode is arithmetic
R1L87 = CARRY(R1_internal_counter[15] & (!R1L85));
--R1_internal_counter[12] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[12]
--operation mode is arithmetic
R1_internal_counter[12]_carry_eqn = R1L79;
R1_internal_counter[12]_lut_out = R1_internal_counter[12] $ (R1_internal_counter[12]_carry_eqn);
R1_internal_counter[12] = DFFEAS(R1_internal_counter[12]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[12], , , R1L156);
--R1L81 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[12]~2958
--operation mode is arithmetic
R1L81 = CARRY(R1_internal_counter[12] # !R1L79);
--R1_internal_counter[13] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[13]
--operation mode is arithmetic
R1_internal_counter[13]_carry_eqn = R1L81;
R1_internal_counter[13]_lut_out = R1_internal_counter[13] $ (!R1_internal_counter[13]_carry_eqn);
R1_internal_counter[13] = DFFEAS(R1_internal_counter[13]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_l_register[13], , , R1L156);
--R1L83 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[13]~2959
--operation mode is arithmetic
R1L83 = CARRY(!R1_internal_counter[13] & (!R1L81));
--R1L47 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~367
--operation mode is normal
R1L47 = R1_internal_counter[14] & R1_internal_counter[15] & !R1_internal_counter[12] & !R1_internal_counter[13];
--R1L48 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~368
--operation mode is normal
R1L48 = R1L44 & R1L45 & R1L46 & R1L47;
--R1_internal_counter[16] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[16]
--operation mode is arithmetic
R1_internal_counter[16]_carry_eqn = R1L87;
R1_internal_counter[16]_lut_out = R1_internal_counter[16] $ (R1_internal_counter[16]_carry_eqn);
R1_internal_counter[16] = DFFEAS(R1_internal_counter[16]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[0], , , R1L156);
--R1L89 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[16]~2960
--operation mode is arithmetic
R1L89 = CARRY(R1_internal_counter[16] # !R1L87);
--R1_internal_counter[17] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[17]
--operation mode is arithmetic
R1_internal_counter[17]_carry_eqn = R1L89;
R1_internal_counter[17]_lut_out = R1_internal_counter[17] $ (!R1_internal_counter[17]_carry_eqn);
R1_internal_counter[17] = DFFEAS(R1_internal_counter[17]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[1], , , R1L156);
--R1L91 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[17]~2961
--operation mode is arithmetic
R1L91 = CARRY(!R1_internal_counter[17] & (!R1L89));
--R1_internal_counter[18] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[18]
--operation mode is arithmetic
R1_internal_counter[18]_carry_eqn = R1L91;
R1_internal_counter[18]_lut_out = R1_internal_counter[18] $ (R1_internal_counter[18]_carry_eqn);
R1_internal_counter[18] = DFFEAS(R1_internal_counter[18]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[2], , , R1L156);
--R1L93 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[18]~2962
--operation mode is arithmetic
R1L93 = CARRY(R1_internal_counter[18] # !R1L91);
--R1_internal_counter[19] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[19]
--operation mode is arithmetic
R1_internal_counter[19]_carry_eqn = R1L93;
R1_internal_counter[19]_lut_out = R1_internal_counter[19] $ (!R1_internal_counter[19]_carry_eqn);
R1_internal_counter[19] = DFFEAS(R1_internal_counter[19]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[3], , , R1L156);
--R1L95 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[19]~2963
--operation mode is arithmetic
R1L95 = CARRY(!R1_internal_counter[19] & (!R1L93));
--R1L49 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~369
--operation mode is normal
R1L49 = !R1_internal_counter[16] & !R1_internal_counter[17] & !R1_internal_counter[18] & !R1_internal_counter[19];
--R1_internal_counter[20] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[20]
--operation mode is arithmetic
R1_internal_counter[20]_carry_eqn = R1L95;
R1_internal_counter[20]_lut_out = R1_internal_counter[20] $ (R1_internal_counter[20]_carry_eqn);
R1_internal_counter[20] = DFFEAS(R1_internal_counter[20]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[4], , , R1L156);
--R1L97 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[20]~2964
--operation mode is arithmetic
R1L97 = CARRY(R1_internal_counter[20] # !R1L95);
--R1_internal_counter[21] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[21]
--operation mode is arithmetic
R1_internal_counter[21]_carry_eqn = R1L97;
R1_internal_counter[21]_lut_out = R1_internal_counter[21] $ (!R1_internal_counter[21]_carry_eqn);
R1_internal_counter[21] = DFFEAS(R1_internal_counter[21]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[5], , , R1L156);
--R1L99 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[21]~2965
--operation mode is arithmetic
R1L99 = CARRY(!R1_internal_counter[21] & (!R1L97));
--R1_internal_counter[22] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[22]
--operation mode is arithmetic
R1_internal_counter[22]_carry_eqn = R1L99;
R1_internal_counter[22]_lut_out = R1_internal_counter[22] $ (R1_internal_counter[22]_carry_eqn);
R1_internal_counter[22] = DFFEAS(R1_internal_counter[22]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[6], , , R1L156);
--R1L101 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[22]~2966
--operation mode is arithmetic
R1L101 = CARRY(R1_internal_counter[22] # !R1L99);
--R1_internal_counter[23] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[23]
--operation mode is arithmetic
R1_internal_counter[23]_carry_eqn = R1L101;
R1_internal_counter[23]_lut_out = R1_internal_counter[23] $ (!R1_internal_counter[23]_carry_eqn);
R1_internal_counter[23] = DFFEAS(R1_internal_counter[23]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[7], , , R1L156);
--R1L103 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[23]~2967
--operation mode is arithmetic
R1L103 = CARRY(!R1_internal_counter[23] & (!R1L101));
--R1L50 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~370
--operation mode is normal
R1L50 = !R1_internal_counter[20] & !R1_internal_counter[21] & !R1_internal_counter[22] & !R1_internal_counter[23];
--R1_internal_counter[24] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[24]
--operation mode is arithmetic
R1_internal_counter[24]_carry_eqn = R1L103;
R1_internal_counter[24]_lut_out = R1_internal_counter[24] $ (R1_internal_counter[24]_carry_eqn);
R1_internal_counter[24] = DFFEAS(R1_internal_counter[24]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[8], , , R1L156);
--R1L105 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[24]~2968
--operation mode is arithmetic
R1L105 = CARRY(R1_internal_counter[24] # !R1L103);
--R1_internal_counter[25] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[25]
--operation mode is arithmetic
R1_internal_counter[25]_carry_eqn = R1L105;
R1_internal_counter[25]_lut_out = R1_internal_counter[25] $ (!R1_internal_counter[25]_carry_eqn);
R1_internal_counter[25] = DFFEAS(R1_internal_counter[25]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[9], , , R1L156);
--R1L107 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[25]~2969
--operation mode is arithmetic
R1L107 = CARRY(!R1_internal_counter[25] & (!R1L105));
--R1_internal_counter[26] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[26]
--operation mode is arithmetic
R1_internal_counter[26]_carry_eqn = R1L107;
R1_internal_counter[26]_lut_out = R1_internal_counter[26] $ (R1_internal_counter[26]_carry_eqn);
R1_internal_counter[26] = DFFEAS(R1_internal_counter[26]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[10], , , R1L156);
--R1L109 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[26]~2970
--operation mode is arithmetic
R1L109 = CARRY(R1_internal_counter[26] # !R1L107);
--R1_internal_counter[27] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[27]
--operation mode is arithmetic
R1_internal_counter[27]_carry_eqn = R1L109;
R1_internal_counter[27]_lut_out = R1_internal_counter[27] $ (!R1_internal_counter[27]_carry_eqn);
R1_internal_counter[27] = DFFEAS(R1_internal_counter[27]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[11], , , R1L156);
--R1L111 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[27]~2971
--operation mode is arithmetic
R1L111 = CARRY(!R1_internal_counter[27] & (!R1L109));
--R1L51 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~371
--operation mode is normal
R1L51 = !R1_internal_counter[24] & !R1_internal_counter[25] & !R1_internal_counter[26] & !R1_internal_counter[27];
--R1_internal_counter[28] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[28]
--operation mode is arithmetic
R1_internal_counter[28]_carry_eqn = R1L111;
R1_internal_counter[28]_lut_out = R1_internal_counter[28] $ (R1_internal_counter[28]_carry_eqn);
R1_internal_counter[28] = DFFEAS(R1_internal_counter[28]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[12], , , R1L156);
--R1L113 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[28]~2972
--operation mode is arithmetic
R1L113 = CARRY(R1_internal_counter[28] # !R1L111);
--R1_internal_counter[29] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[29]
--operation mode is arithmetic
R1_internal_counter[29]_carry_eqn = R1L113;
R1_internal_counter[29]_lut_out = R1_internal_counter[29] $ (!R1_internal_counter[29]_carry_eqn);
R1_internal_counter[29] = DFFEAS(R1_internal_counter[29]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[13], , , R1L156);
--R1L115 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[29]~2973
--operation mode is arithmetic
R1L115 = CARRY(!R1_internal_counter[29] & (!R1L113));
--R1_internal_counter[30] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[30]
--operation mode is arithmetic
R1_internal_counter[30]_carry_eqn = R1L115;
R1_internal_counter[30]_lut_out = R1_internal_counter[30] $ (R1_internal_counter[30]_carry_eqn);
R1_internal_counter[30] = DFFEAS(R1_internal_counter[30]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[14], , , R1L156);
--R1L117 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[30]~2974
--operation mode is arithmetic
R1L117 = CARRY(R1_internal_counter[30] # !R1L115);
--R1_internal_counter[31] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[31]
--operation mode is normal
R1_internal_counter[31]_carry_eqn = R1L117;
R1_internal_counter[31]_lut_out = R1_internal_counter[31] $ (!R1_internal_counter[31]_carry_eqn);
R1_internal_counter[31] = DFFEAS(R1_internal_counter[31]_lut_out, DE1__clk0, E1_data_out, , R1L155, R1_period_h_register[15], , , R1L156);
--R1L52 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~372
--operation mode is normal
R1L52 = !R1_internal_counter[28] & !R1_internal_counter[29] & !R1_internal_counter[30] & !R1_internal_counter[31];
--R1L53 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~373
--operation mode is normal
R1L53 = R1L49 & R1L50 & R1L51 & R1L52;
--R1_delayed_unxcounter_is_zeroxx0 is std_1s10:inst|high_res_timer:the_high_res_timer|delayed_unxcounter_is_zeroxx0
--operation mode is normal
R1_delayed_unxcounter_is_zeroxx0_lut_out = R1L48 & R1L53;
R1_delayed_unxcounter_is_zeroxx0 = DFFEAS(R1_delayed_unxcounter_is_zeroxx0_lut_out, DE1__clk0, E1_data_out, , , , , , );
--R1L210 is std_1s10:inst|high_res_timer:the_high_res_timer|timeout_occurred~37
--operation mode is normal
R1L210 = R1_timeout_occurred # R1L48 & R1L53 & !R1_delayed_unxcounter_is_zeroxx0;
--HE1L21 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~105
--operation mode is normal
HE1L21 = !L1_M_alu_result[2] & !L1_M_alu_result[3] & !L1_M_alu_result[4];
--AE2_q_b[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE2_q_b[4]_PORT_A_data_in = QD1_wdata[4];
AE2_q_b[4]_PORT_A_data_in_reg = DFFE(AE2_q_b[4]_PORT_A_data_in, AE2_q_b[4]_clock_0, , , AE2_q_b[4]_clock_enable_0);
AE2_q_b[4]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[4]_PORT_A_address_reg = DFFE(AE2_q_b[4]_PORT_A_address, AE2_q_b[4]_clock_0, , , AE2_q_b[4]_clock_enable_0);
AE2_q_b[4]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[4]_PORT_B_address_reg = DFFE(AE2_q_b[4]_PORT_B_address, AE2_q_b[4]_clock_1, , , AE2_q_b[4]_clock_enable_1);
AE2_q_b[4]_PORT_A_write_enable = VCC;
AE2_q_b[4]_PORT_A_write_enable_reg = DFFE(AE2_q_b[4]_PORT_A_write_enable, AE2_q_b[4]_clock_0, , , AE2_q_b[4]_clock_enable_0);
AE2_q_b[4]_PORT_B_read_enable = VCC;
AE2_q_b[4]_PORT_B_read_enable_reg = DFFE(AE2_q_b[4]_PORT_B_read_enable, AE2_q_b[4]_clock_1, , , AE2_q_b[4]_clock_enable_1);
AE2_q_b[4]_clock_0 = DE1__clk0;
AE2_q_b[4]_clock_1 = DE1__clk0;
AE2_q_b[4]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[4]_clock_enable_1 = T1L61;
AE2_q_b[4]_PORT_B_data_out = MEMORY(AE2_q_b[4]_PORT_A_data_in_reg, , AE2_q_b[4]_PORT_A_address_reg, AE2_q_b[4]_PORT_B_address_reg, AE2_q_b[4]_PORT_A_write_enable_reg, AE2_q_b[4]_PORT_B_read_enable_reg, , , AE2_q_b[4]_clock_0, AE2_q_b[4]_clock_1, AE2_q_b[4]_clock_enable_0, AE2_q_b[4]_clock_enable_1, , );
AE2_q_b[4] = AE2_q_b[4]_PORT_B_data_out[0];
--M1L300 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~20
--operation mode is normal
M1L300 = AE2_q_b[4] & T1_read_0 # !U1L2 # !EB1L2;
--H1_slave_readdata[4] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[4]
--operation mode is normal
H1_slave_readdata[4]_lut_out = H1_slave_readdata_p1[4];
H1_slave_readdata[4] = DFFEAS(H1_slave_readdata[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L272 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[4]~2090
--operation mode is normal
M1L272 = H1_slave_readdata[4] # !J1_cpu_data_master_requests_clock_0_in;
--FB1_za_data[4] is std_1s10:inst|sdram:the_sdram|za_data[4]
--operation mode is normal
FB1_za_data[4]_lut_out = A1L263;
FB1_za_data[4] = DFFEAS(FB1_za_data[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--HE1L55 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[4]~684
--operation mode is normal
HE1L55 = L1_M_alu_result[3] & (HE1_control_reg[4]) # !L1_M_alu_result[3] & HE1_internal_tx_data[4];
--JE1_rx_data[4] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[4]
--operation mode is normal
JE1_rx_data[4]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5];
JE1_rx_data[4] = DFFEAS(JE1_rx_data[4]_lut_out, DE1__clk0, E1_data_out, , JE1_got_new_char, , , , );
--HE1L56 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[4]~685
--operation mode is normal
HE1L56 = L1_M_alu_result[3] & KE1_tx_overrun # !L1_M_alu_result[3] & (JE1_rx_data[4]);
--R1_counter_snapshot[4] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[4]
--operation mode is normal
R1_counter_snapshot[4]_lut_out = R1_internal_counter[4];
R1_counter_snapshot[4] = DFFEAS(R1_counter_snapshot[4]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_counter_snapshot[20] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[20]
--operation mode is normal
R1_counter_snapshot[20]_lut_out = R1_internal_counter[20];
R1_counter_snapshot[20] = DFFEAS(R1_counter_snapshot[20]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L167 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[4]~1256
--operation mode is normal
R1L167 = L1_M_alu_result[2] & (R1_counter_snapshot[20] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & R1_counter_snapshot[4];
--R1_period_h_register[4] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[4]
--operation mode is normal
R1_period_h_register[4]_lut_out = L1_M_st_data[4];
R1_period_h_register[4] = DFFEAS(R1_period_h_register[4]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1_period_l_register[4] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[4]
--operation mode is normal
R1_period_l_register[4]_lut_out = L1_M_st_data[4];
R1_period_l_register[4] = DFFEAS(R1_period_l_register[4]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--R1L168 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[4]~1257
--operation mode is normal
R1L168 = R1L167 & R1_period_h_register[4] # !R1L167 & (R1_period_l_register[4]);
--KB1_counter_snapshot[4] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[4]
--operation mode is normal
KB1_counter_snapshot[4]_lut_out = !KB1_internal_counter[4];
KB1_counter_snapshot[4] = DFFEAS(KB1_counter_snapshot[4]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_counter_snapshot[20] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[20]
--operation mode is normal
KB1_counter_snapshot[20]_lut_out = KB1_internal_counter[20];
KB1_counter_snapshot[20] = DFFEAS(KB1_counter_snapshot[20]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1L168 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[4]~1245
--operation mode is normal
KB1L168 = L1_M_alu_result[2] & (KB1_counter_snapshot[20] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & KB1_counter_snapshot[4];
--KB1_period_h_register[4] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[4]
--operation mode is normal
KB1_period_h_register[4]_lut_out = L1_M_st_data[4];
KB1_period_h_register[4] = DFFEAS(KB1_period_h_register[4]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1_period_l_register[4] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[4]
--operation mode is normal
KB1_period_l_register[4]_lut_out = !L1_M_st_data[4];
KB1_period_l_register[4] = DFFEAS(KB1_period_l_register[4]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--KB1L169 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[4]~1246
--operation mode is normal
KB1L169 = KB1L168 & KB1_period_h_register[4] # !KB1L168 & (!KB1_period_l_register[4]);
--FB1_za_data[20] is std_1s10:inst|sdram:the_sdram|za_data[20]
--operation mode is normal
FB1_za_data[20]_lut_out = A1L247;
FB1_za_data[20] = DFFEAS(FB1_za_data[20]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L286 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[20]~2092
--operation mode is normal
M1L286 = L1_M_alu_result[25] # FB1_za_data[20] # !QB1L4 # !L1_M_alu_result[24];
--ZD2_safe_q[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[4]
--operation mode is arithmetic
ZD2_safe_q[4]_carry_eqn = ZD2L8;
ZD2_safe_q[4]_lut_out = ZD2_safe_q[4] $ (!ZD2_safe_q[4]_carry_eqn);
ZD2_safe_q[4] = DFFEAS(ZD2_safe_q[4]_lut_out, DE1__clk0, E1_data_out, , WD2L1, , , , );
--ZD2L10 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella4~COUT
--operation mode is arithmetic
ZD2L10 = CARRY(!ZD2L8 & (ZD2_safe_q[4] $ !T1_wr_rfifo));
--T1L23 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~302
--operation mode is arithmetic
T1L23 = ZD1_safe_q[4] $ (T1L23_carry_eqn);
--T1L24 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~303
--operation mode is arithmetic
T1L24 = CARRY(!ZD1_safe_q[4] & (!T1L20));
--T1L25 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~304
--operation mode is normal
T1L25 = T1_read_0 & ZD2_safe_q[4] # !T1_read_0 & (T1L23);
--L1_i_readdata_d1[10] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[10]
--operation mode is normal
L1_i_readdata_d1[10] = AMPP_FUNCTION(DE1__clk0, N1L39, FC1L21, FC1L13, P1L10, E1_data_out);
--FB1_za_data[22] is std_1s10:inst|sdram:the_sdram|za_data[22]
--operation mode is normal
FB1_za_data[22]_lut_out = A1L245;
FB1_za_data[22] = DFFEAS(FB1_za_data[22]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L288 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[22]~2094
--operation mode is normal
M1L288 = L1_M_alu_result[25] # FB1_za_data[22] # !QB1L4 # !L1_M_alu_result[24];
--WD2_b_full is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_full
--operation mode is normal
WD2_b_full_lut_out = WD2_b_non_empty & !T1L43 & (WD2_b_full # WD2L6) # !WD2_b_non_empty & WD2_b_full;
WD2_b_full = DFFEAS(WD2_b_full_lut_out, DE1__clk0, E1_data_out, , , , , , );
--T1L26 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~305
--operation mode is arithmetic
T1L26 = WD1_b_full $ (!T1L26_carry_eqn);
--T1L27 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~306
--operation mode is arithmetic
T1L27 = CARRY(!T1L30 # !WD1_b_full);
--T1L28 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~307
--operation mode is normal
T1L28 = T1_read_0 & WD2_b_full # !T1_read_0 & (T1L26);
--T1_rvalid is std_1s10:inst|jtag_uart:the_jtag_uart|rvalid
--operation mode is normal
T1_rvalid_lut_out = T1L43 & WD2_b_non_empty # !T1L43 & (T1_rvalid);
T1_rvalid = DFFEAS(T1_rvalid_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_readdata[15] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[15]
--operation mode is normal
H1_slave_readdata[15]_lut_out = H1_slave_readdata_p1[15];
H1_slave_readdata[15] = DFFEAS(H1_slave_readdata[15]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_za_data[15] is std_1s10:inst|sdram:the_sdram|za_data[15]
--operation mode is normal
FB1_za_data[15]_lut_out = A1L252;
FB1_za_data[15] = DFFEAS(FB1_za_data[15]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L283 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[15]~2096
--operation mode is normal
M1L283 = J1_cpu_data_master_requests_clock_0_in & (!FB1_za_data[15] & GB1L18 # !H1_slave_readdata[15]) # !J1_cpu_data_master_requests_clock_0_in & (!FB1_za_data[15] & GB1L18);
--AB1L35 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_byteenable[1]~6
--operation mode is normal
AB1L35 = L1_M_mem_byte_en[1] # AB1L11 & !AB1_onchip_ram_64_kbytes_s1_arb_addend[1] # !AB1L3;
--KB1_counter_snapshot[15] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[15]
--operation mode is normal
KB1_counter_snapshot[15]_lut_out = !KB1_internal_counter[15];
KB1_counter_snapshot[15] = DFFEAS(KB1_counter_snapshot[15]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_counter_snapshot[31] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[31]
--operation mode is normal
KB1_counter_snapshot[31]_lut_out = KB1_internal_counter[31];
KB1_counter_snapshot[31] = DFFEAS(KB1_counter_snapshot[31]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1L190 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[15]~1248
--operation mode is normal
KB1L190 = L1_M_alu_result[2] & (KB1_counter_snapshot[31] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & KB1_counter_snapshot[15];
--KB1_period_h_register[15] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[15]
--operation mode is normal
KB1_period_h_register[15]_lut_out = L1_M_st_data[15];
KB1_period_h_register[15] = DFFEAS(KB1_period_h_register[15]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1_period_l_register[15] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[15]
--operation mode is normal
KB1_period_l_register[15]_lut_out = !L1_M_st_data[15];
KB1_period_l_register[15] = DFFEAS(KB1_period_l_register[15]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--KB1L191 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[15]~1249
--operation mode is normal
KB1L191 = KB1L190 & KB1_period_h_register[15] # !KB1L190 & (!KB1_period_l_register[15]);
--R1_counter_snapshot[15] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[15]
--operation mode is normal
R1_counter_snapshot[15]_lut_out = !R1_internal_counter[15];
R1_counter_snapshot[15] = DFFEAS(R1_counter_snapshot[15]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_counter_snapshot[31] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[31]
--operation mode is normal
R1_counter_snapshot[31]_lut_out = R1_internal_counter[31];
R1_counter_snapshot[31] = DFFEAS(R1_counter_snapshot[31]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L189 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[15]~1259
--operation mode is normal
R1L189 = L1_M_alu_result[2] & (R1_counter_snapshot[31] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & R1_counter_snapshot[15];
--R1_period_h_register[15] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[15]
--operation mode is normal
R1_period_h_register[15]_lut_out = L1_M_st_data[15];
R1_period_h_register[15] = DFFEAS(R1_period_h_register[15]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1_period_l_register[15] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[15]
--operation mode is normal
R1_period_l_register[15]_lut_out = !L1_M_st_data[15];
R1_period_l_register[15] = DFFEAS(R1_period_l_register[15]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--R1L190 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[15]~1260
--operation mode is normal
R1L190 = R1L189 & R1_period_h_register[15] # !R1L189 & (!R1_period_l_register[15]);
--M1L309 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|process4~0
--operation mode is normal
M1L309 = M1_internal_cpu_data_master_dbs_address[0] & M1L307 & (!M1_internal_cpu_data_master_dbs_address[1]);
--P1L32 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[1]~6
--operation mode is normal
P1L32 = L1_M_mem_byte_en[1] # !P1L3;
--CD1_internal_MonDReg[8] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[8]
--operation mode is normal
CD1_internal_MonDReg[8] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[11], PD1_q_b[8], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[9] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[9]
--operation mode is normal
CD1_internal_MonDReg[9] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[9], CD1L19, DD1_internal_jdo1[12], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L30, CD1L29);
--CD1_internal_MonDReg[10] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[10]
--operation mode is normal
CD1_internal_MonDReg[10] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[13], PD1_q_b[10], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[11] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[11]
--operation mode is normal
CD1_internal_MonDReg[11] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[11], CD1L19, DD1_internal_jdo1[14], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L30, CD1L29);
--CD1_internal_MonDReg[12] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[12]
--operation mode is normal
CD1_internal_MonDReg[12] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[12], CD1L19, DD1_internal_jdo1[15], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L30, CD1L29);
--CD1_internal_MonDReg[13] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[13]
--operation mode is normal
CD1_internal_MonDReg[13] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[16], PD1_q_b[13], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[14] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[14]
--operation mode is normal
CD1_internal_MonDReg[14] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[17], PD1_q_b[14], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[15] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[15]
--operation mode is normal
CD1_internal_MonDReg[15] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[18], PD1_q_b[15], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--AB1L37 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_byteenable[3]~7
--operation mode is normal
AB1L37 = L1_M_mem_byte_en[3] # AB1L11 & !AB1_onchip_ram_64_kbytes_s1_arb_addend[1] # !AB1L3;
--FB1_za_data[31] is std_1s10:inst|sdram:the_sdram|za_data[31]
--operation mode is normal
FB1_za_data[31]_lut_out = A1L236;
FB1_za_data[31] = DFFEAS(FB1_za_data[31]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L297 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[31]~2098
--operation mode is normal
M1L297 = L1_M_alu_result[25] # FB1_za_data[31] # !QB1L4 # !L1_M_alu_result[24];
--P1L34 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[3]~7
--operation mode is normal
P1L34 = L1_M_mem_byte_en[3] # !P1L3;
--CD1_internal_MonDReg[24] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[24]
--operation mode is normal
CD1_internal_MonDReg[24] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[24], CD1L21, DD1_internal_jdo1[27], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L30, CD1L29);
--CD1_internal_MonDReg[25] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[25]
--operation mode is normal
CD1_internal_MonDReg[25] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[28], PD1_q_b[25], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[26] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[26]
--operation mode is normal
CD1_internal_MonDReg[26] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[29], PD1_q_b[26], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[27] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[27]
--operation mode is normal
CD1_internal_MonDReg[27] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[27], CD1L20, DD1_internal_jdo1[30], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L30, CD1L29);
--CD1_internal_MonDReg[28] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[28]
--operation mode is normal
CD1_internal_MonDReg[28] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[31], PD1_q_b[28], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[29] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[29]
--operation mode is normal
CD1_internal_MonDReg[29] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[29], CD1L20, DD1_internal_jdo1[32], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L30, CD1L29);
--CD1_internal_MonDReg[30] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[30]
--operation mode is normal
CD1_internal_MonDReg[30] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[33], PD1_q_b[30], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--CD1_internal_MonDReg[31] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[31]
--operation mode is normal
CD1_internal_MonDReg[31] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[34], PD1_q_b[31], CD1L30, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L29);
--FB1_za_data[21] is std_1s10:inst|sdram:the_sdram|za_data[21]
--operation mode is normal
FB1_za_data[21]_lut_out = A1L246;
FB1_za_data[21] = DFFEAS(FB1_za_data[21]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L287 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[21]~2100
--operation mode is normal
M1L287 = L1_M_alu_result[25] # FB1_za_data[21] # !QB1L4 # !L1_M_alu_result[24];
--ZD2_safe_q[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[5]
--operation mode is normal
ZD2_safe_q[5]_carry_eqn = ZD2L10;
ZD2_safe_q[5]_lut_out = ZD2_safe_q[5] $ (ZD2_safe_q[5]_carry_eqn);
ZD2_safe_q[5] = DFFEAS(ZD2_safe_q[5]_lut_out, DE1__clk0, E1_data_out, , WD2L1, , , , );
--T1L29 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~308
--operation mode is arithmetic
T1L29 = ZD1_safe_q[5] $ (!T1L29_carry_eqn);
--T1L30 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~309
--operation mode is arithmetic
T1L30 = CARRY(ZD1_safe_q[5] # !T1L24);
--T1L31 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~310
--operation mode is normal
T1L31 = T1_read_0 & ZD2_safe_q[5] # !T1_read_0 & (T1L29);
--L1_i_readdata_d1[22] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[22]
--operation mode is normal
L1_i_readdata_d1[22] = AMPP_FUNCTION(DE1__clk0, N1L75, FC1L21, FC1L26, P1L10, E1_data_out);
--L1_i_readdata_d1[23] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[23]
--operation mode is normal
L1_i_readdata_d1[23] = AMPP_FUNCTION(DE1__clk0, N1L78, FC1L21, FC1L27, P1L10, E1_data_out);
--L1_i_readdata_d1[24] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[24]
--operation mode is normal
L1_i_readdata_d1[24] = AMPP_FUNCTION(DE1__clk0, N1L81, FC1L21, FC1L28, P1L10, E1_data_out);
--L1_i_readdata_d1[25] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[25]
--operation mode is normal
L1_i_readdata_d1[25] = AMPP_FUNCTION(DE1__clk0, N1L84, FC1L21, FC1L29, P1L10, E1_data_out);
--L1_i_readdata_d1[26] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[26]
--operation mode is normal
L1_i_readdata_d1[26] = AMPP_FUNCTION(DE1__clk0, N1L87, FC1L21, FC1L30, P1L10, E1_data_out);
--FB1_za_data[24] is std_1s10:inst|sdram:the_sdram|za_data[24]
--operation mode is normal
FB1_za_data[24]_lut_out = A1L243;
FB1_za_data[24] = DFFEAS(FB1_za_data[24]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L290 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[24]~2102
--operation mode is normal
M1L290 = L1_M_alu_result[25] # FB1_za_data[24] # !QB1L4 # !L1_M_alu_result[24];
--ZD2_safe_q[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[1]
--operation mode is arithmetic
ZD2_safe_q[1]_carry_eqn = ZD2L2;
ZD2_safe_q[1]_lut_out = ZD2_safe_q[1] $ (ZD2_safe_q[1]_carry_eqn);
ZD2_safe_q[1] = DFFEAS(ZD2_safe_q[1]_lut_out, DE1__clk0, E1_data_out, , WD2L1, , , , );
--ZD2L4 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella1~COUT
--operation mode is arithmetic
ZD2L4 = CARRY(ZD2_safe_q[1] $ T1_wr_rfifo # !ZD2L2);
--T1L32 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~311
--operation mode is arithmetic
T1L32 = ZD1_safe_q[1] $ (!T1L32_carry_eqn);
--T1L33 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~312
--operation mode is arithmetic
T1L33 = CARRY(ZD1_safe_q[1] # !T1L37);
--T1L34 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~313
--operation mode is normal
T1L34 = T1_read_0 & ZD2_safe_q[1] # !T1_read_0 & (T1L32);
--FB1_za_data[17] is std_1s10:inst|sdram:the_sdram|za_data[17]
--operation mode is normal
FB1_za_data[17]_lut_out = A1L250;
FB1_za_data[17] = DFFEAS(FB1_za_data[17]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--T1L35 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~314
--operation mode is normal
T1L35 = T1_read_0 & ZD2_safe_q[0] # !T1_read_0 & (ZD1_safe_q[0]);
--FB1_za_data[16] is std_1s10:inst|sdram:the_sdram|za_data[16]
--operation mode is normal
FB1_za_data[16]_lut_out = A1L251;
FB1_za_data[16] = DFFEAS(FB1_za_data[16]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_za_data[25] is std_1s10:inst|sdram:the_sdram|za_data[25]
--operation mode is normal
FB1_za_data[25]_lut_out = A1L242;
FB1_za_data[25] = DFFEAS(FB1_za_data[25]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L291 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[25]~2106
--operation mode is normal
M1L291 = L1_M_alu_result[25] # FB1_za_data[25] # !QB1L4 # !L1_M_alu_result[24];
--L1_i_readdata_d1[20] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[20]
--operation mode is normal
L1_i_readdata_d1[20] = AMPP_FUNCTION(DE1__clk0, N1L69, FC1L21, FC1L24, P1L10, E1_data_out);
--T1_woverflow is std_1s10:inst|jtag_uart:the_jtag_uart|woverflow
--operation mode is normal
T1_woverflow_lut_out = T1L55 & (L1_M_alu_result[2] & T1_woverflow # !L1_M_alu_result[2] & (WD1_b_full)) # !T1L55 & T1_woverflow;
T1_woverflow = DFFEAS(T1_woverflow_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_readdata[14] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[14]
--operation mode is normal
H1_slave_readdata[14]_lut_out = H1_slave_readdata_p1[14];
H1_slave_readdata[14] = DFFEAS(H1_slave_readdata[14]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_za_data[14] is std_1s10:inst|sdram:the_sdram|za_data[14]
--operation mode is normal
FB1_za_data[14]_lut_out = A1L253;
FB1_za_data[14] = DFFEAS(FB1_za_data[14]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L282 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[14]~2108
--operation mode is normal
M1L282 = J1_cpu_data_master_requests_clock_0_in & (!FB1_za_data[14] & GB1L18 # !H1_slave_readdata[14]) # !J1_cpu_data_master_requests_clock_0_in & (!FB1_za_data[14] & GB1L18);
--KB1_counter_snapshot[14] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[14]
--operation mode is normal
KB1_counter_snapshot[14]_lut_out = KB1_internal_counter[14];
KB1_counter_snapshot[14] = DFFEAS(KB1_counter_snapshot[14]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_counter_snapshot[30] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[30]
--operation mode is normal
KB1_counter_snapshot[30]_lut_out = KB1_internal_counter[30];
KB1_counter_snapshot[30] = DFFEAS(KB1_counter_snapshot[30]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1L188 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[14]~1251
--operation mode is normal
KB1L188 = L1_M_alu_result[2] & (KB1_counter_snapshot[30] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & KB1_counter_snapshot[14];
--KB1_period_h_register[14] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[14]
--operation mode is normal
KB1_period_h_register[14]_lut_out = L1_M_st_data[14];
KB1_period_h_register[14] = DFFEAS(KB1_period_h_register[14]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1_period_l_register[14] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[14]
--operation mode is normal
KB1_period_l_register[14]_lut_out = L1_M_st_data[14];
KB1_period_l_register[14] = DFFEAS(KB1_period_l_register[14]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--KB1L189 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[14]~1252
--operation mode is normal
KB1L189 = KB1L188 & KB1_period_h_register[14] # !KB1L188 & (KB1_period_l_register[14]);
--R1_counter_snapshot[14] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[14]
--operation mode is normal
R1_counter_snapshot[14]_lut_out = !R1_internal_counter[14];
R1_counter_snapshot[14] = DFFEAS(R1_counter_snapshot[14]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_counter_snapshot[30] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[30]
--operation mode is normal
R1_counter_snapshot[30]_lut_out = R1_internal_counter[30];
R1_counter_snapshot[30] = DFFEAS(R1_counter_snapshot[30]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L187 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[14]~1262
--operation mode is normal
R1L187 = L1_M_alu_result[2] & (R1_counter_snapshot[30] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & R1_counter_snapshot[14];
--R1_period_h_register[14] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[14]
--operation mode is normal
R1_period_h_register[14]_lut_out = L1_M_st_data[14];
R1_period_h_register[14] = DFFEAS(R1_period_h_register[14]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1_period_l_register[14] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[14]
--operation mode is normal
R1_period_l_register[14]_lut_out = !L1_M_st_data[14];
R1_period_l_register[14] = DFFEAS(R1_period_l_register[14]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--R1L188 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[14]~1263
--operation mode is normal
R1L188 = R1L187 & R1_period_h_register[14] # !R1L187 & (!R1_period_l_register[14]);
--FB1_za_data[30] is std_1s10:inst|sdram:the_sdram|za_data[30]
--operation mode is normal
FB1_za_data[30]_lut_out = A1L237;
FB1_za_data[30] = DFFEAS(FB1_za_data[30]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L296 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[30]~2110
--operation mode is normal
M1L296 = L1_M_alu_result[25] # FB1_za_data[30] # !QB1L4 # !L1_M_alu_result[24];
--L1_i_readdata_d1[19] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[19]
--operation mode is normal
L1_i_readdata_d1[19] = AMPP_FUNCTION(DE1__clk0, N1L66, FC1L21, FC1L23, P1L10, E1_data_out);
--H1_slave_readdata[13] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[13]
--operation mode is normal
H1_slave_readdata[13]_lut_out = H1_slave_readdata_p1[13];
H1_slave_readdata[13] = DFFEAS(H1_slave_readdata[13]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_za_data[13] is std_1s10:inst|sdram:the_sdram|za_data[13]
--operation mode is normal
FB1_za_data[13]_lut_out = A1L254;
FB1_za_data[13] = DFFEAS(FB1_za_data[13]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L281 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[13]~2112
--operation mode is normal
M1L281 = J1_cpu_data_master_requests_clock_0_in & (!FB1_za_data[13] & GB1L18 # !H1_slave_readdata[13]) # !J1_cpu_data_master_requests_clock_0_in & (!FB1_za_data[13] & GB1L18);
--KB1_counter_snapshot[13] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[13]
--operation mode is normal
KB1_counter_snapshot[13]_lut_out = !KB1_internal_counter[13];
KB1_counter_snapshot[13] = DFFEAS(KB1_counter_snapshot[13]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_counter_snapshot[29] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[29]
--operation mode is normal
KB1_counter_snapshot[29]_lut_out = KB1_internal_counter[29];
KB1_counter_snapshot[29] = DFFEAS(KB1_counter_snapshot[29]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1L186 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[13]~1254
--operation mode is normal
KB1L186 = L1_M_alu_result[2] & (KB1_counter_snapshot[29] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & KB1_counter_snapshot[13];
--KB1_period_h_register[13] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[13]
--operation mode is normal
KB1_period_h_register[13]_lut_out = L1_M_st_data[13];
KB1_period_h_register[13] = DFFEAS(KB1_period_h_register[13]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1_period_l_register[13] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[13]
--operation mode is normal
KB1_period_l_register[13]_lut_out = !L1_M_st_data[13];
KB1_period_l_register[13] = DFFEAS(KB1_period_l_register[13]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--KB1L187 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[13]~1255
--operation mode is normal
KB1L187 = KB1L186 & KB1_period_h_register[13] # !KB1L186 & (!KB1_period_l_register[13]);
--R1_counter_snapshot[13] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[13]
--operation mode is normal
R1_counter_snapshot[13]_lut_out = R1_internal_counter[13];
R1_counter_snapshot[13] = DFFEAS(R1_counter_snapshot[13]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_counter_snapshot[29] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[29]
--operation mode is normal
R1_counter_snapshot[29]_lut_out = R1_internal_counter[29];
R1_counter_snapshot[29] = DFFEAS(R1_counter_snapshot[29]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L185 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[13]~1265
--operation mode is normal
R1L185 = L1_M_alu_result[2] & (R1_counter_snapshot[29] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & R1_counter_snapshot[13];
--R1_period_h_register[13] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[13]
--operation mode is normal
R1_period_h_register[13]_lut_out = L1_M_st_data[13];
R1_period_h_register[13] = DFFEAS(R1_period_h_register[13]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1_period_l_register[13] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[13]
--operation mode is normal
R1_period_l_register[13]_lut_out = L1_M_st_data[13];
R1_period_l_register[13] = DFFEAS(R1_period_l_register[13]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--R1L186 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[13]~1266
--operation mode is normal
R1L186 = R1L185 & R1_period_h_register[13] # !R1L185 & (R1_period_l_register[13]);
--FB1_za_data[29] is std_1s10:inst|sdram:the_sdram|za_data[29]
--operation mode is normal
FB1_za_data[29]_lut_out = A1L238;
FB1_za_data[29] = DFFEAS(FB1_za_data[29]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L295 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[29]~2114
--operation mode is normal
M1L295 = L1_M_alu_result[25] # FB1_za_data[29] # !QB1L4 # !L1_M_alu_result[24];
--L1_D_br_taken_waddr_partial[10] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[10]
--operation mode is normal
L1_D_br_taken_waddr_partial[10] = AMPP_FUNCTION(DE1__clk0, E1_data_out, L1_W_stall, L1L182);
--L1_i_readdata_d1[18] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[18]
--operation mode is normal
L1_i_readdata_d1[18] = AMPP_FUNCTION(DE1__clk0, N1L63, FC1L21, FC1L22, P1L10, E1_data_out);
--H1_slave_readdata[12] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[12]
--operation mode is normal
H1_slave_readdata[12]_lut_out = H1_slave_readdata_p1[12];
H1_slave_readdata[12] = DFFEAS(H1_slave_readdata[12]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_za_data[12] is std_1s10:inst|sdram:the_sdram|za_data[12]
--operation mode is normal
FB1_za_data[12]_lut_out = A1L255;
FB1_za_data[12] = DFFEAS(FB1_za_data[12]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L280 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[12]~2116
--operation mode is normal
M1L280 = J1_cpu_data_master_requests_clock_0_in & (!FB1_za_data[12] & GB1L18 # !H1_slave_readdata[12]) # !J1_cpu_data_master_requests_clock_0_in & (!FB1_za_data[12] & GB1L18);
--R1_counter_snapshot[12] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[12]
--operation mode is normal
R1_counter_snapshot[12]_lut_out = R1_internal_counter[12];
R1_counter_snapshot[12] = DFFEAS(R1_counter_snapshot[12]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_counter_snapshot[28] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[28]
--operation mode is normal
R1_counter_snapshot[28]_lut_out = R1_internal_counter[28];
R1_counter_snapshot[28] = DFFEAS(R1_counter_snapshot[28]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L183 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[12]~1268
--operation mode is normal
R1L183 = L1_M_alu_result[2] & (R1_counter_snapshot[28] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & R1_counter_snapshot[12];
--R1_period_h_register[12] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[12]
--operation mode is normal
R1_period_h_register[12]_lut_out = L1_M_st_data[12];
R1_period_h_register[12] = DFFEAS(R1_period_h_register[12]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1_period_l_register[12] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[12]
--operation mode is normal
R1_period_l_register[12]_lut_out = L1_M_st_data[12];
R1_period_l_register[12] = DFFEAS(R1_period_l_register[12]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--R1L184 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[12]~1269
--operation mode is normal
R1L184 = R1L183 & R1_period_h_register[12] # !R1L183 & (R1_period_l_register[12]);
--KB1_counter_snapshot[12] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[12]
--operation mode is normal
KB1_counter_snapshot[12]_lut_out = KB1_internal_counter[12];
KB1_counter_snapshot[12] = DFFEAS(KB1_counter_snapshot[12]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_counter_snapshot[28] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[28]
--operation mode is normal
KB1_counter_snapshot[28]_lut_out = KB1_internal_counter[28];
KB1_counter_snapshot[28] = DFFEAS(KB1_counter_snapshot[28]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1L184 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[12]~1257
--operation mode is normal
KB1L184 = L1_M_alu_result[2] & (KB1_counter_snapshot[28] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & KB1_counter_snapshot[12];
--KB1_period_h_register[12] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[12]
--operation mode is normal
KB1_period_h_register[12]_lut_out = L1_M_st_data[12];
KB1_period_h_register[12] = DFFEAS(KB1_period_h_register[12]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1_period_l_register[12] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[12]
--operation mode is normal
KB1_period_l_register[12]_lut_out = L1_M_st_data[12];
KB1_period_l_register[12] = DFFEAS(KB1_period_l_register[12]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--KB1L185 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[12]~1258
--operation mode is normal
KB1L185 = KB1L184 & KB1_period_h_register[12] # !KB1L184 & (KB1_period_l_register[12]);
--FB1_za_data[28] is std_1s10:inst|sdram:the_sdram|za_data[28]
--operation mode is normal
FB1_za_data[28]_lut_out = A1L239;
FB1_za_data[28] = DFFEAS(FB1_za_data[28]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L294 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[28]~2118
--operation mode is normal
M1L294 = L1_M_alu_result[25] # FB1_za_data[28] # !QB1L4 # !L1_M_alu_result[24];
--L1_i_readdata_d1[17] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[17]
--operation mode is normal
L1_i_readdata_d1[17] = AMPP_FUNCTION(DE1__clk0, N1L60, FC1L21, FC1L20, P1L10, E1_data_out);
--H1_slave_readdata[11] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[11]
--operation mode is normal
H1_slave_readdata[11]_lut_out = H1_slave_readdata_p1[11];
H1_slave_readdata[11] = DFFEAS(H1_slave_readdata[11]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L279 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[11]~2120
--operation mode is normal
M1L279 = H1_slave_readdata[11] # !J1_cpu_data_master_requests_clock_0_in;
--FB1_za_data[11] is std_1s10:inst|sdram:the_sdram|za_data[11]
--operation mode is normal
FB1_za_data[11]_lut_out = A1L256;
FB1_za_data[11] = DFFEAS(FB1_za_data[11]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--KB1_counter_snapshot[11] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[11]
--operation mode is normal
KB1_counter_snapshot[11]_lut_out = KB1_internal_counter[11];
KB1_counter_snapshot[11] = DFFEAS(KB1_counter_snapshot[11]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_counter_snapshot[27] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[27]
--operation mode is normal
KB1_counter_snapshot[27]_lut_out = KB1_internal_counter[27];
KB1_counter_snapshot[27] = DFFEAS(KB1_counter_snapshot[27]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1L182 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[11]~1260
--operation mode is normal
KB1L182 = L1_M_alu_result[2] & (KB1_counter_snapshot[27] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & KB1_counter_snapshot[11];
--KB1_period_h_register[11] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[11]
--operation mode is normal
KB1_period_h_register[11]_lut_out = L1_M_st_data[11];
KB1_period_h_register[11] = DFFEAS(KB1_period_h_register[11]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1_period_l_register[11] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[11]
--operation mode is normal
KB1_period_l_register[11]_lut_out = L1_M_st_data[11];
KB1_period_l_register[11] = DFFEAS(KB1_period_l_register[11]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--KB1L183 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[11]~1261
--operation mode is normal
KB1L183 = KB1L182 & KB1_period_h_register[11] # !KB1L182 & (KB1_period_l_register[11]);
--R1_counter_snapshot[11] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[11]
--operation mode is normal
R1_counter_snapshot[11]_lut_out = R1_internal_counter[11];
R1_counter_snapshot[11] = DFFEAS(R1_counter_snapshot[11]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_counter_snapshot[27] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[27]
--operation mode is normal
R1_counter_snapshot[27]_lut_out = R1_internal_counter[27];
R1_counter_snapshot[27] = DFFEAS(R1_counter_snapshot[27]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L181 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[11]~1271
--operation mode is normal
R1L181 = L1_M_alu_result[2] & (R1_counter_snapshot[27] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & R1_counter_snapshot[11];
--R1_period_h_register[11] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[11]
--operation mode is normal
R1_period_h_register[11]_lut_out = L1_M_st_data[11];
R1_period_h_register[11] = DFFEAS(R1_period_h_register[11]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1_period_l_register[11] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[11]
--operation mode is normal
R1_period_l_register[11]_lut_out = L1_M_st_data[11];
R1_period_l_register[11] = DFFEAS(R1_period_l_register[11]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--R1L182 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[11]~1272
--operation mode is normal
R1L182 = R1L181 & R1_period_h_register[11] # !R1L181 & (R1_period_l_register[11]);
--FB1_za_data[27] is std_1s10:inst|sdram:the_sdram|za_data[27]
--operation mode is normal
FB1_za_data[27]_lut_out = A1L240;
FB1_za_data[27] = DFFEAS(FB1_za_data[27]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L293 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[27]~2122
--operation mode is normal
M1L293 = L1_M_alu_result[25] # FB1_za_data[27] # !QB1L4 # !L1_M_alu_result[24];
--T1_ac is std_1s10:inst|jtag_uart:the_jtag_uart|ac
--operation mode is normal
T1_ac_lut_out = T1L2 # T1_ac & (!T1L46 # !L1_M_st_data[10]);
T1_ac = DFFEAS(T1_ac_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_readdata[10] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[10]
--operation mode is normal
H1_slave_readdata[10]_lut_out = H1_slave_readdata_p1[10];
H1_slave_readdata[10] = DFFEAS(H1_slave_readdata[10]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_za_data[10] is std_1s10:inst|sdram:the_sdram|za_data[10]
--operation mode is normal
FB1_za_data[10]_lut_out = A1L257;
FB1_za_data[10] = DFFEAS(FB1_za_data[10]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L278 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[10]~2124
--operation mode is normal
M1L278 = J1_cpu_data_master_requests_clock_0_in & (!FB1_za_data[10] & GB1L18 # !H1_slave_readdata[10]) # !J1_cpu_data_master_requests_clock_0_in & (!FB1_za_data[10] & GB1L18);
--R1_counter_snapshot[10] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[10]
--operation mode is normal
R1_counter_snapshot[10]_lut_out = R1_internal_counter[10];
R1_counter_snapshot[10] = DFFEAS(R1_counter_snapshot[10]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_counter_snapshot[26] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[26]
--operation mode is normal
R1_counter_snapshot[26]_lut_out = R1_internal_counter[26];
R1_counter_snapshot[26] = DFFEAS(R1_counter_snapshot[26]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L179 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[10]~1274
--operation mode is normal
R1L179 = L1_M_alu_result[2] & (R1_counter_snapshot[26] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & R1_counter_snapshot[10];
--R1_period_h_register[10] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[10]
--operation mode is normal
R1_period_h_register[10]_lut_out = L1_M_st_data[10];
R1_period_h_register[10] = DFFEAS(R1_period_h_register[10]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1_period_l_register[10] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[10]
--operation mode is normal
R1_period_l_register[10]_lut_out = L1_M_st_data[10];
R1_period_l_register[10] = DFFEAS(R1_period_l_register[10]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--R1L180 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[10]~1275
--operation mode is normal
R1L180 = R1L179 & R1_period_h_register[10] # !R1L179 & (R1_period_l_register[10]);
--KB1_counter_snapshot[10] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[10]
--operation mode is normal
KB1_counter_snapshot[10]_lut_out = KB1_internal_counter[10];
KB1_counter_snapshot[10] = DFFEAS(KB1_counter_snapshot[10]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_counter_snapshot[26] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[26]
--operation mode is normal
KB1_counter_snapshot[26]_lut_out = KB1_internal_counter[26];
KB1_counter_snapshot[26] = DFFEAS(KB1_counter_snapshot[26]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1L180 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[10]~1263
--operation mode is normal
KB1L180 = L1_M_alu_result[2] & (KB1_counter_snapshot[26] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & KB1_counter_snapshot[10];
--KB1_period_h_register[10] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[10]
--operation mode is normal
KB1_period_h_register[10]_lut_out = L1_M_st_data[10];
KB1_period_h_register[10] = DFFEAS(KB1_period_h_register[10]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1_period_l_register[10] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[10]
--operation mode is normal
KB1_period_l_register[10]_lut_out = L1_M_st_data[10];
KB1_period_l_register[10] = DFFEAS(KB1_period_l_register[10]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--KB1L181 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[10]~1264
--operation mode is normal
KB1L181 = KB1L180 & KB1_period_h_register[10] # !KB1L180 & (KB1_period_l_register[10]);
--FB1_za_data[26] is std_1s10:inst|sdram:the_sdram|za_data[26]
--operation mode is normal
FB1_za_data[26]_lut_out = A1L241;
FB1_za_data[26] = DFFEAS(FB1_za_data[26]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L292 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[26]~2126
--operation mode is normal
M1L292 = L1_M_alu_result[25] # FB1_za_data[26] # !QB1L4 # !L1_M_alu_result[24];
--H1_slave_readdata[9] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[9]
--operation mode is normal
H1_slave_readdata[9]_lut_out = H1_slave_readdata_p1[9];
H1_slave_readdata[9] = DFFEAS(H1_slave_readdata[9]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_za_data[9] is std_1s10:inst|sdram:the_sdram|za_data[9]
--operation mode is normal
FB1_za_data[9]_lut_out = A1L258;
FB1_za_data[9] = DFFEAS(FB1_za_data[9]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L277 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[9]~2128
--operation mode is normal
M1L277 = J1_cpu_data_master_requests_clock_0_in & (!FB1_za_data[9] & GB1L18 # !H1_slave_readdata[9]) # !J1_cpu_data_master_requests_clock_0_in & (!FB1_za_data[9] & GB1L18);
--R1_counter_snapshot[9] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[9]
--operation mode is normal
R1_counter_snapshot[9]_lut_out = !R1_internal_counter[9];
R1_counter_snapshot[9] = DFFEAS(R1_counter_snapshot[9]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_counter_snapshot[25] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[25]
--operation mode is normal
R1_counter_snapshot[25]_lut_out = R1_internal_counter[25];
R1_counter_snapshot[25] = DFFEAS(R1_counter_snapshot[25]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L177 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[9]~1277
--operation mode is normal
R1L177 = L1_M_alu_result[2] & (R1_counter_snapshot[25] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & R1_counter_snapshot[9];
--R1_period_h_register[9] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[9]
--operation mode is normal
R1_period_h_register[9]_lut_out = L1_M_st_data[9];
R1_period_h_register[9] = DFFEAS(R1_period_h_register[9]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1_period_l_register[9] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[9]
--operation mode is normal
R1_period_l_register[9]_lut_out = !L1_M_st_data[9];
R1_period_l_register[9] = DFFEAS(R1_period_l_register[9]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--R1L178 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[9]~1278
--operation mode is normal
R1L178 = R1L177 & R1_period_h_register[9] # !R1L177 & (!R1_period_l_register[9]);
--KB1_counter_snapshot[9] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[9]
--operation mode is normal
KB1_counter_snapshot[9]_lut_out = KB1_internal_counter[9];
KB1_counter_snapshot[9] = DFFEAS(KB1_counter_snapshot[9]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_counter_snapshot[25] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[25]
--operation mode is normal
KB1_counter_snapshot[25]_lut_out = KB1_internal_counter[25];
KB1_counter_snapshot[25] = DFFEAS(KB1_counter_snapshot[25]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1L178 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[9]~1266
--operation mode is normal
KB1L178 = L1_M_alu_result[2] & (KB1_counter_snapshot[25] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & KB1_counter_snapshot[9];
--KB1_period_h_register[9] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[9]
--operation mode is normal
KB1_period_h_register[9]_lut_out = L1_M_st_data[9];
KB1_period_h_register[9] = DFFEAS(KB1_period_h_register[9]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1_period_l_register[9] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[9]
--operation mode is normal
KB1_period_l_register[9]_lut_out = L1_M_st_data[9];
KB1_period_l_register[9] = DFFEAS(KB1_period_l_register[9]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--KB1L179 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[9]~1267
--operation mode is normal
KB1L179 = KB1L178 & KB1_period_h_register[9] # !KB1L178 & (KB1_period_l_register[9]);
--H1_slave_readdata[8] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[8]
--operation mode is normal
H1_slave_readdata[8]_lut_out = H1_slave_readdata_p1[8];
H1_slave_readdata[8] = DFFEAS(H1_slave_readdata[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_za_data[8] is std_1s10:inst|sdram:the_sdram|za_data[8]
--operation mode is normal
FB1_za_data[8]_lut_out = A1L259;
FB1_za_data[8] = DFFEAS(FB1_za_data[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L276 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[8]~2130
--operation mode is normal
M1L276 = J1_cpu_data_master_requests_clock_0_in & (!FB1_za_data[8] & GB1L18 # !H1_slave_readdata[8]) # !J1_cpu_data_master_requests_clock_0_in & (!FB1_za_data[8] & GB1L18);
--R1_counter_snapshot[8] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[8]
--operation mode is normal
R1_counter_snapshot[8]_lut_out = !R1_internal_counter[8];
R1_counter_snapshot[8] = DFFEAS(R1_counter_snapshot[8]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_counter_snapshot[24] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[24]
--operation mode is normal
R1_counter_snapshot[24]_lut_out = R1_internal_counter[24];
R1_counter_snapshot[24] = DFFEAS(R1_counter_snapshot[24]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L175 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[8]~1280
--operation mode is normal
R1L175 = L1_M_alu_result[2] & (R1_counter_snapshot[24] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & R1_counter_snapshot[8];
--R1_period_h_register[8] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[8]
--operation mode is normal
R1_period_h_register[8]_lut_out = L1_M_st_data[8];
R1_period_h_register[8] = DFFEAS(R1_period_h_register[8]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1_period_l_register[8] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[8]
--operation mode is normal
R1_period_l_register[8]_lut_out = !L1_M_st_data[8];
R1_period_l_register[8] = DFFEAS(R1_period_l_register[8]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--R1L176 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[8]~1281
--operation mode is normal
R1L176 = R1L175 & R1_period_h_register[8] # !R1L175 & (!R1_period_l_register[8]);
--KB1_counter_snapshot[8] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[8]
--operation mode is normal
KB1_counter_snapshot[8]_lut_out = !KB1_internal_counter[8];
KB1_counter_snapshot[8] = DFFEAS(KB1_counter_snapshot[8]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_counter_snapshot[24] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[24]
--operation mode is normal
KB1_counter_snapshot[24]_lut_out = KB1_internal_counter[24];
KB1_counter_snapshot[24] = DFFEAS(KB1_counter_snapshot[24]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1L176 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[8]~1269
--operation mode is normal
KB1L176 = L1_M_alu_result[2] & (KB1_counter_snapshot[24] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & KB1_counter_snapshot[8];
--KB1_period_h_register[8] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[8]
--operation mode is normal
KB1_period_h_register[8]_lut_out = L1_M_st_data[8];
KB1_period_h_register[8] = DFFEAS(KB1_period_h_register[8]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1_period_l_register[8] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[8]
--operation mode is normal
KB1_period_l_register[8]_lut_out = !L1_M_st_data[8];
KB1_period_l_register[8] = DFFEAS(KB1_period_l_register[8]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--KB1L177 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[8]~1270
--operation mode is normal
KB1L177 = KB1L176 & KB1_period_h_register[8] # !KB1L176 & (!KB1_period_l_register[8]);
--F1_d2_data_in[3] is std_1s10:inst|button_pio:the_button_pio|d2_data_in[3]
--operation mode is normal
F1_d2_data_in[3]_lut_out = F1_d1_data_in[3];
F1_d2_data_in[3] = DFFEAS(F1_d2_data_in[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--F1_d1_data_in[3] is std_1s10:inst|button_pio:the_button_pio|d1_data_in[3]
--operation mode is normal
F1_d1_data_in[3]_lut_out = in_port_to_the_button_pio[3];
F1_d1_data_in[3] = DFFEAS(F1_d1_data_in[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--F1L16 is std_1s10:inst|button_pio:the_button_pio|edge_capture_wr_strobe~27
--operation mode is normal
F1L16 = L1_M_alu_result[3] & L1_internal_d_write & (!M1_internal_cpu_data_master_waitrequest);
--F1L17 is std_1s10:inst|button_pio:the_button_pio|edge_capture_wr_strobe~28
--operation mode is normal
F1L17 = L1_M_alu_result[2] & G1L1 & F1L16 & !L1_M_alu_result[7];
--F1_d2_data_in[1] is std_1s10:inst|button_pio:the_button_pio|d2_data_in[1]
--operation mode is normal
F1_d2_data_in[1]_lut_out = F1_d1_data_in[1];
F1_d2_data_in[1] = DFFEAS(F1_d2_data_in[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--F1_d1_data_in[1] is std_1s10:inst|button_pio:the_button_pio|d1_data_in[1]
--operation mode is normal
F1_d1_data_in[1]_lut_out = in_port_to_the_button_pio[1];
F1_d1_data_in[1] = DFFEAS(F1_d1_data_in[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--F1L23 is std_1s10:inst|button_pio:the_button_pio|process1~12
--operation mode is normal
F1L23 = G1L1 & F1L16 & !L1_M_alu_result[7] & !L1_M_alu_result[2];
--F1_d2_data_in[2] is std_1s10:inst|button_pio:the_button_pio|d2_data_in[2]
--operation mode is normal
F1_d2_data_in[2]_lut_out = F1_d1_data_in[2];
F1_d2_data_in[2] = DFFEAS(F1_d2_data_in[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--F1_d1_data_in[2] is std_1s10:inst|button_pio:the_button_pio|d1_data_in[2]
--operation mode is normal
F1_d1_data_in[2]_lut_out = in_port_to_the_button_pio[2];
F1_d1_data_in[2] = DFFEAS(F1_d1_data_in[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--F1_d2_data_in[0] is std_1s10:inst|button_pio:the_button_pio|d2_data_in[0]
--operation mode is normal
F1_d2_data_in[0]_lut_out = F1_d1_data_in[0];
F1_d2_data_in[0] = DFFEAS(F1_d2_data_in[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--F1_d1_data_in[0] is std_1s10:inst|button_pio:the_button_pio|d1_data_in[0]
--operation mode is normal
F1_d1_data_in[0]_lut_out = in_port_to_the_button_pio[0];
F1_d1_data_in[0] = DFFEAS(F1_d1_data_in[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--AE2_q_b[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE2_q_b[5]_PORT_A_data_in = QD1_wdata[5];
AE2_q_b[5]_PORT_A_data_in_reg = DFFE(AE2_q_b[5]_PORT_A_data_in, AE2_q_b[5]_clock_0, , , AE2_q_b[5]_clock_enable_0);
AE2_q_b[5]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[5]_PORT_A_address_reg = DFFE(AE2_q_b[5]_PORT_A_address, AE2_q_b[5]_clock_0, , , AE2_q_b[5]_clock_enable_0);
AE2_q_b[5]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[5]_PORT_B_address_reg = DFFE(AE2_q_b[5]_PORT_B_address, AE2_q_b[5]_clock_1, , , AE2_q_b[5]_clock_enable_1);
AE2_q_b[5]_PORT_A_write_enable = VCC;
AE2_q_b[5]_PORT_A_write_enable_reg = DFFE(AE2_q_b[5]_PORT_A_write_enable, AE2_q_b[5]_clock_0, , , AE2_q_b[5]_clock_enable_0);
AE2_q_b[5]_PORT_B_read_enable = VCC;
AE2_q_b[5]_PORT_B_read_enable_reg = DFFE(AE2_q_b[5]_PORT_B_read_enable, AE2_q_b[5]_clock_1, , , AE2_q_b[5]_clock_enable_1);
AE2_q_b[5]_clock_0 = DE1__clk0;
AE2_q_b[5]_clock_1 = DE1__clk0;
AE2_q_b[5]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[5]_clock_enable_1 = T1L61;
AE2_q_b[5]_PORT_B_data_out = MEMORY(AE2_q_b[5]_PORT_A_data_in_reg, , AE2_q_b[5]_PORT_A_address_reg, AE2_q_b[5]_PORT_B_address_reg, AE2_q_b[5]_PORT_A_write_enable_reg, AE2_q_b[5]_PORT_B_read_enable_reg, , , AE2_q_b[5]_clock_0, AE2_q_b[5]_clock_1, AE2_q_b[5]_clock_enable_0, AE2_q_b[5]_clock_enable_1, , );
AE2_q_b[5] = AE2_q_b[5]_PORT_B_data_out[0];
--M1L301 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~21
--operation mode is normal
M1L301 = AE2_q_b[5] & T1_read_0 # !U1L2 # !EB1L2;
--H1_slave_readdata[5] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[5]
--operation mode is normal
H1_slave_readdata[5]_lut_out = H1_slave_readdata_p1[5];
H1_slave_readdata[5] = DFFEAS(H1_slave_readdata[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L273 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[5]~2132
--operation mode is normal
M1L273 = H1_slave_readdata[5] # !J1_cpu_data_master_requests_clock_0_in;
--FB1_za_data[5] is std_1s10:inst|sdram:the_sdram|za_data[5]
--operation mode is normal
FB1_za_data[5]_lut_out = A1L262;
FB1_za_data[5] = DFFEAS(FB1_za_data[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--R1_counter_snapshot[5] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[5]
--operation mode is normal
R1_counter_snapshot[5]_lut_out = R1_internal_counter[5];
R1_counter_snapshot[5] = DFFEAS(R1_counter_snapshot[5]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_counter_snapshot[21] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[21]
--operation mode is normal
R1_counter_snapshot[21]_lut_out = R1_internal_counter[21];
R1_counter_snapshot[21] = DFFEAS(R1_counter_snapshot[21]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L169 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[5]~1283
--operation mode is normal
R1L169 = L1_M_alu_result[2] & (R1_counter_snapshot[21] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & R1_counter_snapshot[5];
--R1_period_h_register[5] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[5]
--operation mode is normal
R1_period_h_register[5]_lut_out = L1_M_st_data[5];
R1_period_h_register[5] = DFFEAS(R1_period_h_register[5]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1_period_l_register[5] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[5]
--operation mode is normal
R1_period_l_register[5]_lut_out = L1_M_st_data[5];
R1_period_l_register[5] = DFFEAS(R1_period_l_register[5]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--R1L170 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[5]~1284
--operation mode is normal
R1L170 = R1L169 & R1_period_h_register[5] # !R1L169 & (R1_period_l_register[5]);
--HE1L57 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[5]~687
--operation mode is normal
HE1L57 = L1_M_alu_result[3] & (HE1_control_reg[5]) # !L1_M_alu_result[3] & HE1_internal_tx_data[5];
--JE1_rx_data[5] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[5]
--operation mode is normal
JE1_rx_data[5]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6];
JE1_rx_data[5] = DFFEAS(JE1_rx_data[5]_lut_out, DE1__clk0, E1_data_out, , JE1_got_new_char, , , , );
--HE1L58 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[5]~688
--operation mode is normal
HE1L58 = L1_M_alu_result[3] & !KE1_tx_shift_empty # !L1_M_alu_result[3] & (JE1_rx_data[5]);
--KB1_counter_snapshot[5] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[5]
--operation mode is normal
KB1_counter_snapshot[5]_lut_out = KB1_internal_counter[5];
KB1_counter_snapshot[5] = DFFEAS(KB1_counter_snapshot[5]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_counter_snapshot[21] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[21]
--operation mode is normal
KB1_counter_snapshot[21]_lut_out = KB1_internal_counter[21];
KB1_counter_snapshot[21] = DFFEAS(KB1_counter_snapshot[21]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1L170 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[5]~1272
--operation mode is normal
KB1L170 = L1_M_alu_result[2] & (KB1_counter_snapshot[21] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & KB1_counter_snapshot[5];
--KB1_period_h_register[5] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[5]
--operation mode is normal
KB1_period_h_register[5]_lut_out = L1_M_st_data[5];
KB1_period_h_register[5] = DFFEAS(KB1_period_h_register[5]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1_period_l_register[5] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[5]
--operation mode is normal
KB1_period_l_register[5]_lut_out = L1_M_st_data[5];
KB1_period_l_register[5] = DFFEAS(KB1_period_l_register[5]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--KB1L171 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[5]~1273
--operation mode is normal
KB1L171 = KB1L170 & KB1_period_h_register[5] # !KB1L170 & (KB1_period_l_register[5]);
--AE2_q_b[6] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE2_q_b[6]_PORT_A_data_in = QD1_wdata[6];
AE2_q_b[6]_PORT_A_data_in_reg = DFFE(AE2_q_b[6]_PORT_A_data_in, AE2_q_b[6]_clock_0, , , AE2_q_b[6]_clock_enable_0);
AE2_q_b[6]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[6]_PORT_A_address_reg = DFFE(AE2_q_b[6]_PORT_A_address, AE2_q_b[6]_clock_0, , , AE2_q_b[6]_clock_enable_0);
AE2_q_b[6]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[6]_PORT_B_address_reg = DFFE(AE2_q_b[6]_PORT_B_address, AE2_q_b[6]_clock_1, , , AE2_q_b[6]_clock_enable_1);
AE2_q_b[6]_PORT_A_write_enable = VCC;
AE2_q_b[6]_PORT_A_write_enable_reg = DFFE(AE2_q_b[6]_PORT_A_write_enable, AE2_q_b[6]_clock_0, , , AE2_q_b[6]_clock_enable_0);
AE2_q_b[6]_PORT_B_read_enable = VCC;
AE2_q_b[6]_PORT_B_read_enable_reg = DFFE(AE2_q_b[6]_PORT_B_read_enable, AE2_q_b[6]_clock_1, , , AE2_q_b[6]_clock_enable_1);
AE2_q_b[6]_clock_0 = DE1__clk0;
AE2_q_b[6]_clock_1 = DE1__clk0;
AE2_q_b[6]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[6]_clock_enable_1 = T1L61;
AE2_q_b[6]_PORT_B_data_out = MEMORY(AE2_q_b[6]_PORT_A_data_in_reg, , AE2_q_b[6]_PORT_A_address_reg, AE2_q_b[6]_PORT_B_address_reg, AE2_q_b[6]_PORT_A_write_enable_reg, AE2_q_b[6]_PORT_B_read_enable_reg, , , AE2_q_b[6]_clock_0, AE2_q_b[6]_clock_1, AE2_q_b[6]_clock_enable_0, AE2_q_b[6]_clock_enable_1, , );
AE2_q_b[6] = AE2_q_b[6]_PORT_B_data_out[0];
--M1L302 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~22
--operation mode is normal
M1L302 = AE2_q_b[6] & T1_read_0 # !U1L2 # !EB1L2;
--H1_slave_readdata[6] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[6]
--operation mode is normal
H1_slave_readdata[6]_lut_out = H1_slave_readdata_p1[6];
H1_slave_readdata[6] = DFFEAS(H1_slave_readdata[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L274 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[6]~2134
--operation mode is normal
M1L274 = H1_slave_readdata[6] # !J1_cpu_data_master_requests_clock_0_in;
--FB1_za_data[6] is std_1s10:inst|sdram:the_sdram|za_data[6]
--operation mode is normal
FB1_za_data[6]_lut_out = A1L261;
FB1_za_data[6] = DFFEAS(FB1_za_data[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--R1_counter_snapshot[6] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[6]
--operation mode is normal
R1_counter_snapshot[6]_lut_out = !R1_internal_counter[6];
R1_counter_snapshot[6] = DFFEAS(R1_counter_snapshot[6]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1_counter_snapshot[22] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[22]
--operation mode is normal
R1_counter_snapshot[22]_lut_out = R1_internal_counter[22];
R1_counter_snapshot[22] = DFFEAS(R1_counter_snapshot[22]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L171 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[6]~1286
--operation mode is normal
R1L171 = L1_M_alu_result[2] & (R1_counter_snapshot[22] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & R1_counter_snapshot[6];
--R1_period_h_register[6] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[6]
--operation mode is normal
R1_period_h_register[6]_lut_out = L1_M_st_data[6];
R1_period_h_register[6] = DFFEAS(R1_period_h_register[6]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1_period_l_register[6] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[6]
--operation mode is normal
R1_period_l_register[6]_lut_out = !L1_M_st_data[6];
R1_period_l_register[6] = DFFEAS(R1_period_l_register[6]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--R1L172 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[6]~1287
--operation mode is normal
R1L172 = R1L171 & R1_period_h_register[6] # !R1L171 & (!R1_period_l_register[6]);
--HE1L59 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[6]~690
--operation mode is normal
HE1L59 = L1_M_alu_result[3] & (HE1_control_reg[6]) # !L1_M_alu_result[3] & HE1_internal_tx_data[6];
--JE1_rx_data[6] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[6]
--operation mode is normal
JE1_rx_data[6]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7];
JE1_rx_data[6] = DFFEAS(JE1_rx_data[6]_lut_out, DE1__clk0, E1_data_out, , JE1_got_new_char, , , , );
--HE1L60 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[6]~691
--operation mode is normal
HE1L60 = L1_M_alu_result[3] & !KE1_internal_tx_ready # !L1_M_alu_result[3] & (JE1_rx_data[6]);
--KB1_counter_snapshot[6] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[6]
--operation mode is normal
KB1_counter_snapshot[6]_lut_out = KB1_internal_counter[6];
KB1_counter_snapshot[6] = DFFEAS(KB1_counter_snapshot[6]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_counter_snapshot[22] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[22]
--operation mode is normal
KB1_counter_snapshot[22]_lut_out = KB1_internal_counter[22];
KB1_counter_snapshot[22] = DFFEAS(KB1_counter_snapshot[22]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1L172 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[6]~1275
--operation mode is normal
KB1L172 = L1_M_alu_result[2] & (KB1_counter_snapshot[22] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & KB1_counter_snapshot[6];
--KB1_period_h_register[6] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[6]
--operation mode is normal
KB1_period_h_register[6]_lut_out = L1_M_st_data[6];
KB1_period_h_register[6] = DFFEAS(KB1_period_h_register[6]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1_period_l_register[6] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[6]
--operation mode is normal
KB1_period_l_register[6]_lut_out = L1_M_st_data[6];
KB1_period_l_register[6] = DFFEAS(KB1_period_l_register[6]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--KB1L173 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[6]~1276
--operation mode is normal
KB1L173 = KB1L172 & KB1_period_h_register[6] # !KB1L172 & (KB1_period_l_register[6]);
--F1_readdata[0] is std_1s10:inst|button_pio:the_button_pio|readdata[0]
--operation mode is normal
F1_readdata[0]_lut_out = L1_M_alu_result[3] & F1L24 # !L1_M_alu_result[3] & (in_port_to_the_button_pio[0] & !L1_M_alu_result[2]);
F1_readdata[0] = DFFEAS(F1_readdata[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L19 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5002
--operation mode is normal
M1L19 = L1_M_alu_result[7] & A1L143 # !L1_M_alu_result[7] & (F1_readdata[0]) # !G1L1;
--M1_registered_cpu_data_master_readdata[0] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[0]
--operation mode is normal
M1_registered_cpu_data_master_readdata[0]_lut_out = !M1L267 & (M1L266 # !U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[0] = DFFEAS(M1_registered_cpu_data_master_readdata[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L20 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5003
--operation mode is normal
M1L20 = M1L19 & (M1_registered_cpu_data_master_readdata[0] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L21 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5004
--operation mode is normal
M1L21 = BE1_q_a[0] & (Q1_internal_incoming_ext_ram_bus_data[0] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[0] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[0] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_dbs_8_reg_segment_0[0] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[0]
--operation mode is normal
M1_dbs_8_reg_segment_0[0]_lut_out = Q1_internal_incoming_ext_ram_bus_data[0];
M1_dbs_8_reg_segment_0[0] = DFFEAS(M1_dbs_8_reg_segment_0[0]_lut_out, DE1__clk0, E1_data_out, , M1L308, , , , );
--M1L22 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5005
--operation mode is normal
M1L22 = M1_registered_cpu_data_master_readdata[0] & (M1_dbs_8_reg_segment_0[0] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[0] & !GB1L18 & (M1_dbs_8_reg_segment_0[0] # !Q1_cpu_data_master_requests_ext_flash_s1);
--DB1_readdata is std_1s10:inst|reconfig_request_pio:the_reconfig_request_pio|readdata
--operation mode is normal
DB1_readdata_lut_out = !L1_M_alu_result[3] & (L1_M_alu_result[2] & DB1_data_dir # !L1_M_alu_result[2] & (A1L22));
DB1_readdata = DFFEAS(DB1_readdata_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L23 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5006
--operation mode is normal
M1L23 = M1L27 & (DB1_readdata # !EB1L2 # !L1_M_alu_result[7]);
--HE1_readdata[0] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[0]
--operation mode is normal
HE1_readdata[0]_lut_out = L1_M_alu_result[4] & HE1L15 & HE1_control_reg[0] # !L1_M_alu_result[4] & (HE1L48 # HE1L15 & HE1_control_reg[0]);
HE1_readdata[0] = DFFEAS(HE1_readdata[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L24 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5007
--operation mode is normal
M1L24 = M1L21 & M1L23 & (HE1_readdata[0] # !QB1_cpu_data_master_granted_uart1_s1);
--R1_readdata[0] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[0]
--operation mode is normal
R1_readdata[0]_lut_out = R1L157 # R1L158 # R1L159;
R1_readdata[0] = DFFEAS(R1_readdata[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--KB1_readdata[0] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[0]
--operation mode is normal
KB1_readdata[0]_lut_out = KB1L158 # KB1L159 # KB1L160;
KB1_readdata[0] = DFFEAS(KB1_readdata[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L25 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5008
--operation mode is normal
M1L25 = R1_readdata[0] & (KB1_readdata[0] # !LB1_cpu_data_master_requests_sys_clk_timer_s1) # !R1_readdata[0] & !S1_cpu_data_master_requests_high_res_timer_s1 & (KB1_readdata[0] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--M1L26 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5009
--operation mode is normal
M1L26 = M1L20 & M1L24 & M1L25;
--FC1L1 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[0]~1226
--operation mode is normal
FC1L1 = AMPP_FUNCTION(FC1L21, SC1L3, SC1_internal_oci_ienable1[0]);
--FC1L2 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[0]~1227
--operation mode is normal
FC1L2 = AMPP_FUNCTION(SC1L3, VC1_internal_monitor_error, PD1_q_a[0], P1L23);
--F1_readdata[1] is std_1s10:inst|button_pio:the_button_pio|readdata[1]
--operation mode is normal
F1_readdata[1]_lut_out = L1_M_alu_result[3] & F1L25 # !L1_M_alu_result[3] & (in_port_to_the_button_pio[1] & !L1_M_alu_result[2]);
F1_readdata[1] = DFFEAS(F1_readdata[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L28 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5010
--operation mode is normal
M1L28 = L1_M_alu_result[7] & A1L142 # !L1_M_alu_result[7] & (F1_readdata[1]) # !G1L1;
--M1_registered_cpu_data_master_readdata[1] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[1]
--operation mode is normal
M1_registered_cpu_data_master_readdata[1]_lut_out = !M1L269 & (M1L268 # !U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[1] = DFFEAS(M1_registered_cpu_data_master_readdata[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L29 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5011
--operation mode is normal
M1L29 = M1L28 & !EB1_cpu_data_master_requests_reconfig_request_pio_s1 & (M1_registered_cpu_data_master_readdata[1] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
--M1L30 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5012
--operation mode is normal
M1L30 = BE1_q_a[1] & (Q1_internal_incoming_ext_ram_bus_data[1] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[1] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[1] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_dbs_8_reg_segment_0[1] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[1]
--operation mode is normal
M1_dbs_8_reg_segment_0[1]_lut_out = Q1_internal_incoming_ext_ram_bus_data[1];
M1_dbs_8_reg_segment_0[1] = DFFEAS(M1_dbs_8_reg_segment_0[1]_lut_out, DE1__clk0, E1_data_out, , M1L308, , , , );
--M1L31 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5013
--operation mode is normal
M1L31 = M1_registered_cpu_data_master_readdata[1] & (M1_dbs_8_reg_segment_0[1] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[1] & !GB1L18 & (M1_dbs_8_reg_segment_0[1] # !Q1_cpu_data_master_requests_ext_flash_s1);
--HE1_readdata[1] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[1]
--operation mode is normal
HE1_readdata[1]_lut_out = !L1_M_alu_result[4] & (L1_M_alu_result[2] & HE1L49 # !L1_M_alu_result[2] & (HE1L50));
HE1_readdata[1] = DFFEAS(HE1_readdata[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L32 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5014
--operation mode is normal
M1L32 = M1L36 & (HE1_readdata[1] # !QB1L2 # !LB1L2);
--KB1_readdata[1] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[1]
--operation mode is normal
KB1_readdata[1]_lut_out = KB1L161 # KB1L162 # KB1L163;
KB1_readdata[1] = DFFEAS(KB1_readdata[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L33 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5015
--operation mode is normal
M1L33 = M1L30 & M1L32 & (KB1_readdata[1] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--R1_readdata[1] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[1]
--operation mode is normal
R1_readdata[1]_lut_out = R1L160 # R1L161 # R1L162;
R1_readdata[1] = DFFEAS(R1_readdata[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L34 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5016
--operation mode is normal
M1L34 = R1_readdata[1] & (M1_registered_cpu_data_master_readdata[1] # !J1_cpu_data_master_requests_clock_0_in) # !R1_readdata[1] & !S1_cpu_data_master_requests_high_res_timer_s1 & (M1_registered_cpu_data_master_readdata[1] # !J1_cpu_data_master_requests_clock_0_in);
--M1L35 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5017
--operation mode is normal
M1L35 = M1L29 & M1L33 & M1L34;
--FC1L3 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[1]~1228
--operation mode is normal
FC1L3 = AMPP_FUNCTION(FC1L21, SC1L3, SC1_internal_oci_ienable1[1]);
--FC1L4 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[1]~1229
--operation mode is normal
FC1L4 = AMPP_FUNCTION(SC1L3, VC1_internal_monitor_ready, PD1_q_a[1], P1L23);
--KE1_baud_rate_counter[0] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[0]
--operation mode is arithmetic
KE1_baud_rate_counter[0]_lut_out = !KE1_baud_rate_counter[0];
KE1_baud_rate_counter[0] = DFFEAS(KE1_baud_rate_counter[0]_lut_out, DE1__clk0, E1_data_out, , , A1L275, , , KE1L29);
--KE1L4 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[0]~54
--operation mode is arithmetic
KE1L4 = CARRY(KE1_baud_rate_counter[0]);
--KE1_baud_rate_counter[1] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[1]
--operation mode is arithmetic
KE1_baud_rate_counter[1]_carry_eqn = KE1L4;
KE1_baud_rate_counter[1]_lut_out = KE1_baud_rate_counter[1] $ (!KE1_baud_rate_counter[1]_carry_eqn);
KE1_baud_rate_counter[1] = DFFEAS(KE1_baud_rate_counter[1]_lut_out, DE1__clk0, E1_data_out, , , VCC, , , KE1L29);
--KE1L6 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[1]~55
--operation mode is arithmetic
KE1L6 = CARRY(!KE1_baud_rate_counter[1] & (!KE1L4));
--KE1_baud_rate_counter[2] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[2]
--operation mode is arithmetic
KE1_baud_rate_counter[2]_carry_eqn = KE1L6;
KE1_baud_rate_counter[2]_lut_out = KE1_baud_rate_counter[2] $ (KE1_baud_rate_counter[2]_carry_eqn);
KE1_baud_rate_counter[2] = DFFEAS(KE1_baud_rate_counter[2]_lut_out, DE1__clk0, E1_data_out, , , A1L275, , , KE1L29);
--KE1L8 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[2]~56
--operation mode is arithmetic
KE1L8 = CARRY(KE1_baud_rate_counter[2] # !KE1L6);
--KE1_baud_rate_counter[3] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[3]
--operation mode is arithmetic
KE1_baud_rate_counter[3]_carry_eqn = KE1L8;
KE1_baud_rate_counter[3]_lut_out = KE1_baud_rate_counter[3] $ (!KE1_baud_rate_counter[3]_carry_eqn);
KE1_baud_rate_counter[3] = DFFEAS(KE1_baud_rate_counter[3]_lut_out, DE1__clk0, E1_data_out, , , A1L275, , , KE1L29);
--KE1L10 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[3]~57
--operation mode is arithmetic
KE1L10 = CARRY(!KE1_baud_rate_counter[3] & (!KE1L8));
--KE1L21 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|Equal0~133
--operation mode is normal
KE1L21 = !KE1_baud_rate_counter[0] & !KE1_baud_rate_counter[1] & !KE1_baud_rate_counter[2] & !KE1_baud_rate_counter[3];
--KE1_baud_rate_counter[4] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[4]
--operation mode is arithmetic
KE1_baud_rate_counter[4]_carry_eqn = KE1L10;
KE1_baud_rate_counter[4]_lut_out = KE1_baud_rate_counter[4] $ (KE1_baud_rate_counter[4]_carry_eqn);
KE1_baud_rate_counter[4] = DFFEAS(KE1_baud_rate_counter[4]_lut_out, DE1__clk0, E1_data_out, , , VCC, , , KE1L29);
--KE1L12 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[4]~58
--operation mode is arithmetic
KE1L12 = CARRY(KE1_baud_rate_counter[4] # !KE1L10);
--KE1_baud_rate_counter[5] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[5]
--operation mode is arithmetic
KE1_baud_rate_counter[5]_carry_eqn = KE1L12;
KE1_baud_rate_counter[5]_lut_out = KE1_baud_rate_counter[5] $ (!KE1_baud_rate_counter[5]_carry_eqn);
KE1_baud_rate_counter[5] = DFFEAS(KE1_baud_rate_counter[5]_lut_out, DE1__clk0, E1_data_out, , , VCC, , , KE1L29);
--KE1L14 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[5]~59
--operation mode is arithmetic
KE1L14 = CARRY(!KE1_baud_rate_counter[5] & (!KE1L12));
--KE1_baud_rate_counter[6] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[6]
--operation mode is arithmetic
KE1_baud_rate_counter[6]_carry_eqn = KE1L14;
KE1_baud_rate_counter[6]_lut_out = KE1_baud_rate_counter[6] $ (KE1_baud_rate_counter[6]_carry_eqn);
KE1_baud_rate_counter[6] = DFFEAS(KE1_baud_rate_counter[6]_lut_out, DE1__clk0, E1_data_out, , , A1L275, , , KE1L29);
--KE1L16 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[6]~60
--operation mode is arithmetic
KE1L16 = CARRY(KE1_baud_rate_counter[6] # !KE1L14);
--KE1_baud_rate_counter[7] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[7]
--operation mode is arithmetic
KE1_baud_rate_counter[7]_carry_eqn = KE1L16;
KE1_baud_rate_counter[7]_lut_out = KE1_baud_rate_counter[7] $ (!KE1_baud_rate_counter[7]_carry_eqn);
KE1_baud_rate_counter[7] = DFFEAS(KE1_baud_rate_counter[7]_lut_out, DE1__clk0, E1_data_out, , , VCC, , , KE1L29);
--KE1L18 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[7]~61
--operation mode is arithmetic
KE1L18 = CARRY(!KE1_baud_rate_counter[7] & (!KE1L16));
--KE1L22 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|Equal0~134
--operation mode is normal
KE1L22 = !KE1_baud_rate_counter[4] & !KE1_baud_rate_counter[5] & !KE1_baud_rate_counter[6] & !KE1_baud_rate_counter[7];
--KE1_baud_rate_counter[8] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[8]
--operation mode is normal
KE1_baud_rate_counter[8]_carry_eqn = KE1L18;
KE1_baud_rate_counter[8]_lut_out = KE1_baud_rate_counter[8] $ (KE1_baud_rate_counter[8]_carry_eqn);
KE1_baud_rate_counter[8] = DFFEAS(KE1_baud_rate_counter[8]_lut_out, DE1__clk0, E1_data_out, , , VCC, , , KE1L29);
--HE1L64 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|tx_wr_strobe~10
--operation mode is normal
HE1L64 = L1_internal_d_write & LB1L2 & QB1L2 & HE1L19;
--L1_E_wrctl_bstatus is std_1s10:inst|cpu:the_cpu|E_wrctl_bstatus
--operation mode is normal
L1_E_wrctl_bstatus = AMPP_FUNCTION(L1_E_iw[7], L1_E_ctrl_wrctl_inst, L1_E_iw[6], L1_E_iw[8]);
--L1_E_wrctl_estatus is std_1s10:inst|cpu:the_cpu|E_wrctl_estatus
--operation mode is normal
L1_E_wrctl_estatus = AMPP_FUNCTION(L1_E_iw[6], L1_E_ctrl_wrctl_inst, L1_E_iw[7], L1_E_iw[8]);
--DD1L119Q is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir_out[1]~reg0
--operation mode is normal
DD1L119Q = AMPP_FUNCTION(!A1L6, L1_hbreak_enabled, !C1_CLR_SIGNAL);
--ME6_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF|Q[0]
--operation mode is normal
ME6_Q[0] = AMPP_FUNCTION(!A1L6, ME3_Q[0], ME6_Q[0], ME8_Q[1], C1L9, !C1_CLR_SIGNAL);
--ME4L3 is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0]~203
--operation mode is normal
ME4L3 = AMPP_FUNCTION(ME6_Q[0], ME3_Q[0], ME2_Q[0]);
--C1L21 is sld_hub:sld_hub_inst|IRF_ENABLE[2]~127
--operation mode is normal
C1L21 = AMPP_FUNCTION(C1L9, C1L19, ME8_Q[1], ME2_Q[0]);
--NE1_WORD_SR[2] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[2]
--operation mode is normal
NE1_WORD_SR[2] = AMPP_FUNCTION(!A1L6, NE1L12, NE1L13, NE1_WORD_SR[3], NE1_word_counter[2], VCC, NE1_clear_signal, RE1_state[4], NE1L20);
--NE1L15 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux2~28
--operation mode is normal
NE1L15 = AMPP_FUNCTION(NE1_word_counter[0], NE1_word_counter[1], NE1_word_counter[2], NE1_word_counter[3]);
--NE1L1 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~72
--operation mode is normal
NE1L1 = AMPP_FUNCTION(NE1_word_counter[4], NE1L9);
--NE1L11 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Equal0~41
--operation mode is normal
NE1L11 = AMPP_FUNCTION(NE1_word_counter[4], NE1_word_counter[0], NE1_word_counter[1], NE1_word_counter[2]);
--NE1L21 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1253
--operation mode is normal
NE1L21 = AMPP_FUNCTION(NE1_clear_signal, RE1_state[3], C1_jtag_debug_mode_usr0, RE1_state[4]);
--NE1L2 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~74
--operation mode is arithmetic
NE1L2 = AMPP_FUNCTION(NE1_word_counter[0]);
--NE1L3 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~75
--operation mode is arithmetic
NE1L3 = AMPP_FUNCTION(NE1_word_counter[0]);
--NE1L4 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~76
--operation mode is arithmetic
NE1L4 = AMPP_FUNCTION(NE1_word_counter[1], NE1L3);
--NE1L5 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~77
--operation mode is arithmetic
NE1L5 = AMPP_FUNCTION(NE1_word_counter[1], NE1L3);
--NE1L6 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~78
--operation mode is arithmetic
NE1L6 = AMPP_FUNCTION(NE1_word_counter[2], NE1L5);
--NE1L7 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~79
--operation mode is arithmetic
NE1L7 = AMPP_FUNCTION(NE1_word_counter[2], NE1L5);
--NE1L8 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~80
--operation mode is arithmetic
NE1L8 = AMPP_FUNCTION(NE1_word_counter[3], NE1L7);
--NE1L9 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~81
--operation mode is arithmetic
NE1L9 = AMPP_FUNCTION(NE1_word_counter[3], NE1L7);
--QD1_rvalid0 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rvalid0
--operation mode is normal
QD1_rvalid0 = AMPP_FUNCTION(DE1__clk0, QD1L19, QD1_user_saw_rvalid, QD1L2, QD1_read_req, E1_data_out);
--QD1L53 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3498
--operation mode is normal
QD1L53 = AMPP_FUNCTION(RE1_state[3], ME4_Q[0], RE1_state[4]);
--QD1_write_stalled is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|write_stalled
--operation mode is normal
QD1_write_stalled = AMPP_FUNCTION(!A1L6, QD1_td_shift[10], QD1_write_stalled, altera_internal_jtag, T1_t_dav, !C1_CLR_SIGNAL, QD1L72);
--QD1_td_shift[2] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[2]
--operation mode is normal
QD1_td_shift[2] = AMPP_FUNCTION(!A1L6, QD1L53, QD1L63, QD1L56, !C1_CLR_SIGNAL, QD1L52);
--QD1L54 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3499
--operation mode is normal
QD1L54 = AMPP_FUNCTION(QD1_write_stalled, QD1_td_shift[2], QD1_count[9]);
--QD1_count[8] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[8]
--operation mode is normal
QD1_count[8] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1_count[7], !C1_CLR_SIGNAL, QD1L52);
--QD1L55 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3501
--operation mode is normal
QD1L55 = AMPP_FUNCTION(RE1_state[4], QD1_count[8], QD1L66, ME4_Q[0]);
--QD1L36 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|state~198
--operation mode is normal
QD1L36 = AMPP_FUNCTION(RE1_state[3], ME4_Q[0], QD1_state);
--QD1_count[0] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[0]
--operation mode is normal
QD1_count[0] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1_count[9], !C1_CLR_SIGNAL, QD1L52);
--QD1_td_shift[10] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[10]
--operation mode is normal
QD1_td_shift[10] = AMPP_FUNCTION(!A1L6, C1L11, !C1_CLR_SIGNAL, QD1L52);
--QD1_rdata[7] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[7]
--operation mode is normal
QD1_rdata[7] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[7], E1_data_out, QD1L18);
--QD1L69 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|user_saw_rvalid~142
--operation mode is normal
QD1L69 = AMPP_FUNCTION(RE1_state[4], QD1_state, QD1L1, ME4_Q[0]);
--TC1_break_readreg[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[0]
--operation mode is normal
TC1_break_readreg[0] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[0], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L130 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux39~14
--operation mode is normal
DD1L130 = AMPP_FUNCTION(CD1_internal_MonDReg[0], DD1_ir[1], TC1_break_readreg[0], DD1_ir[0]);
--DD1_sr[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[2]
--operation mode is normal
DD1_sr[2] = AMPP_FUNCTION(!A1L6, DD1L129, DD1_sr[3], DD1L143, DD1L141, !C1_CLR_SIGNAL, DD1L6);
--DD1L121 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux0~33
--operation mode is normal
DD1L121 = AMPP_FUNCTION(ME5_Q[0], ME5_Q[1]);
--DD1_internal_jdo1[25] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[25]
--operation mode is normal
DD1_internal_jdo1[25] = AMPP_FUNCTION(!A1L9, DD1_sr[25], VCC, DD1L144);
--VC1L7 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_ready~119
--operation mode is normal
VC1L7 = AMPP_FUNCTION(VC1_internal_monitor_ready, DD1_internal_jdo1[34], DD1L189, DD1_internal_jdo1[25]);
--DD1_st_shiftdr is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_shiftdr
--operation mode is normal
DD1_st_shiftdr = AMPP_FUNCTION(!A1L6, DD1L143, A1L9);
--RE1_state[11] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11]
--operation mode is normal
RE1_state[11] = AMPP_FUNCTION(!A1L6, RE1_state[10], RE1_state[11], RE1_state[14], VCC, !A1L8);
--RE1_state[9] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9]
--operation mode is normal
RE1_state[9] = AMPP_FUNCTION(!A1L6, RE1_state[2], A1L8, VCC);
--RE1_tms_cnt[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[2]
--operation mode is normal
RE1_tms_cnt[2] = AMPP_FUNCTION(!A1L6, RE1_tms_cnt[2], RE1_tms_cnt[0], RE1_tms_cnt[1], VCC, A1L8);
--RE1_tms_cnt[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[1]
--operation mode is normal
RE1_tms_cnt[1] = AMPP_FUNCTION(!A1L6, RE1_tms_cnt[0], RE1_tms_cnt[1], VCC, A1L8);
--RE1_tms_cnt[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0]
--operation mode is normal
RE1_tms_cnt[0] = AMPP_FUNCTION(!A1L6, A1L8, RE1_tms_cnt[0], VCC);
--RE1L18 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~214
--operation mode is normal
RE1L18 = AMPP_FUNCTION(RE1_tms_cnt[2], RE1_tms_cnt[1], RE1_tms_cnt[0]);
--RE1_state[10] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10]
--operation mode is normal
RE1_state[10] = AMPP_FUNCTION(!A1L6, A1L8, RE1_state[9], VCC);
--RE1_state[6] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[6]
--operation mode is normal
RE1_state[6] = AMPP_FUNCTION(!A1L6, RE1_state[5], RE1_state[6], VCC, !A1L8);
--FB1L65 is std_1s10:inst|sdram:the_sdram|active_data[30]~6664
--operation mode is normal
FB1L65 = E1_data_out & FB1L395 & (FB1L423 # !FB1L393);
--FB1L66 is std_1s10:inst|sdram:the_sdram|active_data[30]~6665
--operation mode is normal
FB1L66 = FB1_m_state[0] & (FB1L393 & !FB1L554 # !FB1L393 & (FB1L396)) # !FB1_m_state[0] & (FB1L393);
--L1_E_iw[18] is std_1s10:inst|cpu:the_cpu|E_iw[18]
--operation mode is normal
L1_E_iw[18] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[18], E1_data_out, L1_W_stall);
--L1_E_ctrl_jmp_direct is std_1s10:inst|cpu:the_cpu|E_ctrl_jmp_direct
--operation mode is normal
L1_E_ctrl_jmp_direct = AMPP_FUNCTION(DE1__clk0, L1L188, E1_data_out, L1_W_stall);
--L1L47 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12928
--operation mode is normal
L1L47 = AMPP_FUNCTION(L1_E_iw[18], L1_E_ctrl_jmp_direct, L1_E_extra_pc[12], L1L1328);
--L1_E_pc[12] is std_1s10:inst|cpu:the_cpu|E_pc[12]
--operation mode is normal
L1_E_pc[12] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[12], E1_data_out, L1_W_stall);
--L1_E_ctrl_jmp_indirect is std_1s10:inst|cpu:the_cpu|E_ctrl_jmp_indirect
--operation mode is normal
L1_E_ctrl_jmp_indirect = AMPP_FUNCTION(DE1__clk0, L1L811, L1L808, L1L218, L1_D_iw[12], E1_data_out, L1_W_stall);
--L1_E_iw[22] is std_1s10:inst|cpu:the_cpu|E_iw[22]
--operation mode is normal
L1_E_iw[22] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[22], E1_data_out, L1_W_stall);
--L1L48 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12929
--operation mode is normal
L1L48 = AMPP_FUNCTION(L1_E_iw[22], L1_E_ctrl_jmp_direct, L1_E_extra_pc[16], L1L1328);
--L1_E_pc[16] is std_1s10:inst|cpu:the_cpu|E_pc[16]
--operation mode is normal
L1_E_pc[16] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[16], E1_data_out, L1_W_stall);
--L1_ic_tag_clr_valid_bits_nxt is std_1s10:inst|cpu:the_cpu|ic_tag_clr_valid_bits_nxt
--operation mode is normal
L1_ic_tag_clr_valid_bits_nxt = AMPP_FUNCTION(L1L1040, L1L240, L1L241, L1_reset_d1);
--L1_E_iw[9] is std_1s10:inst|cpu:the_cpu|E_iw[9]
--operation mode is normal
L1_E_iw[9] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[9], E1_data_out, L1_W_stall);
--L1L49 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12930
--operation mode is normal
L1L49 = AMPP_FUNCTION(L1_E_iw[9], L1_E_extra_pc[3], L1L1328, L1_E_ctrl_jmp_direct);
--L1_E_pc[3] is std_1s10:inst|cpu:the_cpu|E_pc[3]
--operation mode is normal
L1_E_pc[3] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[3], E1_data_out, L1_W_stall);
--L1_E_iw[10] is std_1s10:inst|cpu:the_cpu|E_iw[10]
--operation mode is normal
L1_E_iw[10] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[10], E1_data_out, L1_W_stall);
--L1L50 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12931
--operation mode is normal
L1L50 = AMPP_FUNCTION(L1_E_iw[10], L1_E_ctrl_jmp_direct, L1_E_extra_pc[4], L1L1328);
--L1_E_pc[4] is std_1s10:inst|cpu:the_cpu|E_pc[4]
--operation mode is normal
L1_E_pc[4] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[4], E1_data_out, L1_W_stall);
--L1L51 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12932
--operation mode is normal
L1L51 = AMPP_FUNCTION(L1_E_iw[11], L1_E_ctrl_jmp_direct, L1_E_extra_pc[5], L1L1328);
--L1_E_pc[5] is std_1s10:inst|cpu:the_cpu|E_pc[5]
--operation mode is normal
L1_E_pc[5] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[5], E1_data_out, L1_W_stall);
--L1L52 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12933
--operation mode is normal
L1L52 = AMPP_FUNCTION(L1_E_iw[12], L1_E_ctrl_jmp_direct, L1_E_extra_pc[6], L1L1328);
--L1_E_pc[6] is std_1s10:inst|cpu:the_cpu|E_pc[6]
--operation mode is normal
L1_E_pc[6] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[6], E1_data_out, L1_W_stall);
--L1L53 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12934
--operation mode is normal
L1L53 = AMPP_FUNCTION(L1_E_iw[13], L1_E_ctrl_jmp_direct, L1_E_extra_pc[7], L1L1328);
--L1_E_pc[7] is std_1s10:inst|cpu:the_cpu|E_pc[7]
--operation mode is normal
L1_E_pc[7] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[7], E1_data_out, L1_W_stall);
--L1L54 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12935
--operation mode is normal
L1L54 = AMPP_FUNCTION(L1_E_iw[14], L1_E_ctrl_jmp_direct, L1_E_extra_pc[8], L1L1328);
--L1_E_pc[8] is std_1s10:inst|cpu:the_cpu|E_pc[8]
--operation mode is normal
L1_E_pc[8] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[8], E1_data_out, L1_W_stall);
--L1L55 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12936
--operation mode is normal
L1L55 = AMPP_FUNCTION(L1_E_iw[15], L1_E_ctrl_jmp_direct, L1_E_extra_pc[9], L1L1328);
--L1_E_pc[9] is std_1s10:inst|cpu:the_cpu|E_pc[9]
--operation mode is normal
L1_E_pc[9] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[9], E1_data_out, L1_W_stall);
--L1_E_iw[26] is std_1s10:inst|cpu:the_cpu|E_iw[26]
--operation mode is normal
L1_E_iw[26] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[26], E1_data_out, L1_W_stall);
--L1L56 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12937
--operation mode is normal
L1L56 = AMPP_FUNCTION(L1_E_iw[26], L1_E_ctrl_jmp_direct, L1_E_extra_pc[20], L1L1328);
--L1_E_pc[20] is std_1s10:inst|cpu:the_cpu|E_pc[20]
--operation mode is normal
L1_E_pc[20] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[20], E1_data_out, L1_W_stall);
--L1_E_iw[25] is std_1s10:inst|cpu:the_cpu|E_iw[25]
--operation mode is normal
L1_E_iw[25] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[25], E1_data_out, L1_W_stall);
--L1L57 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12938
--operation mode is normal
L1L57 = AMPP_FUNCTION(L1_E_iw[25], L1_E_ctrl_jmp_direct, L1_E_extra_pc[19], L1L1328);
--L1_E_pc[19] is std_1s10:inst|cpu:the_cpu|E_pc[19]
--operation mode is normal
L1_E_pc[19] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[19], E1_data_out, L1_W_stall);
--L1_E_iw[24] is std_1s10:inst|cpu:the_cpu|E_iw[24]
--operation mode is normal
L1_E_iw[24] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[24], E1_data_out, L1_W_stall);
--L1L58 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12939
--operation mode is normal
L1L58 = AMPP_FUNCTION(L1_E_iw[24], L1_E_ctrl_jmp_direct, L1_E_extra_pc[18], L1L1328);
--L1_E_pc[18] is std_1s10:inst|cpu:the_cpu|E_pc[18]
--operation mode is normal
L1_E_pc[18] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[18], E1_data_out, L1_W_stall);
--L1_E_iw[23] is std_1s10:inst|cpu:the_cpu|E_iw[23]
--operation mode is normal
L1_E_iw[23] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[23], E1_data_out, L1_W_stall);
--L1L59 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12940
--operation mode is normal
L1L59 = AMPP_FUNCTION(L1_E_iw[23], L1_E_ctrl_jmp_direct, L1_E_extra_pc[17], L1L1328);
--L1_E_pc[17] is std_1s10:inst|cpu:the_cpu|E_pc[17]
--operation mode is normal
L1_E_pc[17] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[17], E1_data_out, L1_W_stall);
--L1_E_iw[27] is std_1s10:inst|cpu:the_cpu|E_iw[27]
--operation mode is normal
L1_E_iw[27] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[27], E1_data_out, L1_W_stall);
--L1L60 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12941
--operation mode is normal
L1L60 = AMPP_FUNCTION(L1_E_extra_pc[21], L1_E_ctrl_break);
--L1L61 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12942
--operation mode is normal
L1L61 = AMPP_FUNCTION(L1_E_iw[27], L1_E_ctrl_jmp_direct, L1L60, L1_E_ctrl_exception);
--L1_E_pc[21] is std_1s10:inst|cpu:the_cpu|E_pc[21]
--operation mode is normal
L1_E_pc[21] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[21], E1_data_out, L1_W_stall);
--L1_E_iw[20] is std_1s10:inst|cpu:the_cpu|E_iw[20]
--operation mode is normal
L1_E_iw[20] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[20], E1_data_out, L1_W_stall);
--L1L62 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12943
--operation mode is normal
L1L62 = AMPP_FUNCTION(L1_E_extra_pc[14], L1_E_ctrl_break);
--L1L63 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12944
--operation mode is normal
L1L63 = AMPP_FUNCTION(L1_E_iw[20], L1_E_ctrl_jmp_direct, L1L62, L1_E_ctrl_exception);
--L1_E_pc[14] is std_1s10:inst|cpu:the_cpu|E_pc[14]
--operation mode is normal
L1_E_pc[14] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[14], E1_data_out, L1_W_stall);
--L1_E_iw[17] is std_1s10:inst|cpu:the_cpu|E_iw[17]
--operation mode is normal
L1_E_iw[17] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[17], E1_data_out, L1_W_stall);
--L1L64 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12945
--operation mode is normal
L1L64 = AMPP_FUNCTION(L1_E_iw[17], L1_E_ctrl_jmp_direct, L1_E_extra_pc[11], L1L1328);
--L1_E_pc[11] is std_1s10:inst|cpu:the_cpu|E_pc[11]
--operation mode is normal
L1_E_pc[11] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[11], E1_data_out, L1_W_stall);
--L1_E_iw[28] is std_1s10:inst|cpu:the_cpu|E_iw[28]
--operation mode is normal
L1_E_iw[28] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[28], E1_data_out, L1_W_stall);
--L1L65 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12946
--operation mode is normal
L1L65 = AMPP_FUNCTION(L1_E_extra_pc[22], L1_E_ctrl_break);
--L1L66 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12947
--operation mode is normal
L1L66 = AMPP_FUNCTION(L1_E_iw[28], L1_E_ctrl_exception, L1L65, L1_E_ctrl_jmp_direct);
--L1_E_pc[22] is std_1s10:inst|cpu:the_cpu|E_pc[22]
--operation mode is normal
L1_E_pc[22] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[22], E1_data_out, L1_W_stall);
--L1_E_iw[29] is std_1s10:inst|cpu:the_cpu|E_iw[29]
--operation mode is normal
L1_E_iw[29] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[29], E1_data_out, L1_W_stall);
--L1L67 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12948
--operation mode is normal
L1L67 = AMPP_FUNCTION(L1_E_iw[29], L1_E_ctrl_jmp_direct, L1_E_extra_pc[23], L1L1328);
--L1_E_pc[23] is std_1s10:inst|cpu:the_cpu|E_pc[23]
--operation mode is normal
L1_E_pc[23] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[23], E1_data_out, L1_W_stall);
--L1L68 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12949
--operation mode is normal
L1L68 = AMPP_FUNCTION(L1_E_iw[21], L1_E_ctrl_jmp_direct, L1_E_extra_pc[15], L1L1328);
--L1_E_pc[15] is std_1s10:inst|cpu:the_cpu|E_pc[15]
--operation mode is normal
L1_E_pc[15] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[15], E1_data_out, L1_W_stall);
--L1_E_iw[19] is std_1s10:inst|cpu:the_cpu|E_iw[19]
--operation mode is normal
L1_E_iw[19] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[19], E1_data_out, L1_W_stall);
--L1L69 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12950
--operation mode is normal
L1L69 = AMPP_FUNCTION(L1_E_iw[19], L1_E_ctrl_jmp_direct, L1_E_extra_pc[13], L1L1328);
--L1_E_pc[13] is std_1s10:inst|cpu:the_cpu|E_pc[13]
--operation mode is normal
L1_E_pc[13] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[13], E1_data_out, L1_W_stall);
--L1L70 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12951
--operation mode is normal
L1L70 = AMPP_FUNCTION(L1_E_iw[16], L1_E_ctrl_jmp_direct, L1_E_extra_pc[10], L1L1328);
--L1_E_pc[10] is std_1s10:inst|cpu:the_cpu|E_pc[10]
--operation mode is normal
L1_E_pc[10] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[10], E1_data_out, L1_W_stall);
--L1L1071 is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[5]~301
--operation mode is normal
L1L1071 = AMPP_FUNCTION(L1L1021, L1L1024, L1L1023, L1L1022);
--L1L1075 is std_1s10:inst|cpu:the_cpu|ic_tag_clr_valid_bits_nxt~32
--operation mode is normal
L1L1075 = AMPP_FUNCTION(L1_M_valid_from_E, L1_M_ctrl_invalidate_i, L1_reset_d1);
--L1_ic_fill_valid_bits_en is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_en
--operation mode is normal
L1_ic_fill_valid_bits_en = AMPP_FUNCTION(L1L1075, L1L240, L1L241, L1L1020);
--L1L71 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12952
--operation mode is normal
L1L71 = AMPP_FUNCTION(L1_E_iw[8], L1_E_ctrl_jmp_direct, L1_E_extra_pc[2], L1L1328);
--L1_E_pc[2] is std_1s10:inst|cpu:the_cpu|E_pc[2]
--operation mode is normal
L1_E_pc[2] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[2], E1_data_out, L1_W_stall);
--L1L1069 is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[3]~303
--operation mode is normal
L1L1069 = AMPP_FUNCTION(L1L1022, L1L1021, L1L1024, L1L1023);
--L1L72 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12953
--operation mode is normal
L1L72 = AMPP_FUNCTION(L1_E_iw[7], L1_E_ctrl_jmp_direct, L1_E_extra_pc[1], L1L1328);
--L1_E_pc[1] is std_1s10:inst|cpu:the_cpu|E_pc[1]
--operation mode is normal
L1_E_pc[1] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[1], E1_data_out, L1_W_stall);
--L1L1067 is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[1]~305
--operation mode is normal
L1L1067 = AMPP_FUNCTION(L1L1021, L1L1024, L1L1023, L1L1022);
--L1L1072 is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[7]~307
--operation mode is normal
L1L1072 = AMPP_FUNCTION(L1L1022, L1L1021, L1L1024, L1L1023);
--L1L1068 is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[2]~309
--operation mode is normal
L1L1068 = AMPP_FUNCTION(L1L1022, L1L1024, L1L1023, L1L1021);
--L1L1070 is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[4]~311
--operation mode is normal
L1L1070 = AMPP_FUNCTION(L1L1024, L1L1023, L1L1022, L1L1021);
--L1L1066 is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[0]~313
--operation mode is normal
L1L1066 = AMPP_FUNCTION(L1L1024, L1L1023, L1L1022, L1L1021);
--L1L828 is std_1s10:inst|cpu:the_cpu|Equal158~57
--operation mode is normal
L1L828 = AMPP_FUNCTION(L1L1022, L1L1024, L1L1023, L1L1021);
--L1L73 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12954
--operation mode is normal
L1L73 = AMPP_FUNCTION(L1_E_iw[6], L1_E_ctrl_jmp_direct, L1_E_extra_pc[0], L1L1328);
--L1_E_pc[0] is std_1s10:inst|cpu:the_cpu|E_pc[0]
--operation mode is normal
L1_E_pc[0] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[0], E1_data_out, L1_W_stall);
--AB1L10 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_granted_onchip_ram_64_kbytes_s1~84
--operation mode is normal
AB1L10 = AB1L11 & (!AB1L2 # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 # !AB1_onchip_ram_64_kbytes_s1_arb_addend[1]);
--N1L6 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~43
--operation mode is normal
N1L6 = !GB1L19 & !P1L9 & !AB1L10;
--Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0]
--operation mode is normal
Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0]_lut_out = Q1L81;
Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0] = DFFEAS(Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0]
--operation mode is normal
Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0]_lut_out = Q1L244 & Q1L93 & (Q1L4 # Q1L6);
Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0] = DFFEAS(Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0]
--operation mode is normal
Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0]_lut_out = N1L146 & Q1L86 & (Q1L16 # Q1L18);
Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0] = DFFEAS(Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--FB1_rd_valid[0] is std_1s10:inst|sdram:the_sdram|rd_valid[0]
--operation mode is normal
FB1_rd_valid[0]_lut_out = FB1_m_cmd[1] & (!FB1_m_cmd[2] & !FB1_m_cmd[0]);
FB1_rd_valid[0] = DFFEAS(FB1_rd_valid[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--GE1_stage_3 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_3
--operation mode is normal
GE1_stage_3_lut_out = GE1_full_4 & GE1_stage_4 # !GE1_full_4 & (GB1L19);
GE1_stage_3 = DFFEAS(GE1_stage_3_lut_out, DE1__clk0, VCC, , GE1L23, , , , );
--GE1_full_3 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_3
--operation mode is normal
GE1_full_3_lut_out = FB1_za_valid & (GB1L28 & GE1_full_2 # !GB1L28 & (GE1_full_4)) # !FB1_za_valid & GE1_full_2;
GE1_full_3 = DFFEAS(GE1_full_3_lut_out, DE1__clk0, E1_data_out, , FE1L13, , , , );
--GE1L24 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process8~1
--operation mode is normal
GE1L24 = FB1_za_valid # GB1L28 & (!GE1_full_2);
--FE1_stage_3 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_3
--operation mode is normal
FE1_stage_3_lut_out = GE1_full_4 & FE1_stage_4 # !GE1_full_4 & (GB1L14);
FE1_stage_3 = DFFEAS(FE1_stage_3_lut_out, DE1__clk0, VCC, , GE1L23, , , , );
--WB1_master_state[1] is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[1]
--operation mode is normal
WB1_master_state[1]_lut_out = !WB1_master_state[2] & (WB1L10 # WB1L2 & !WB1L3);
WB1_master_state[1] = DFFEAS(WB1_master_state[1]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--WB1_master_state[2] is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[2]
--operation mode is normal
WB1_master_state[2]_lut_out = !WB1_master_state[0] & !WB1L9 & (XB4_data_in_d1 $ UB1_data_out);
WB1_master_state[2] = DFFEAS(WB1_master_state[2]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--WB1_master_state[0] is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[0]
--operation mode is normal
WB1_master_state[0]_lut_out = !WB1L11 & (WB1_master_state[1] # !WB1_master_state[0] & !WB1L12);
WB1_master_state[0] = DFFEAS(WB1_master_state[0]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--D1_data_out is std_1s10:inst|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch|data_out
--operation mode is normal
D1_data_out_lut_out = D1_data_in_d1;
D1_data_out = DFFEAS(D1_data_out_lut_out, PLD_CLOCKINPUT, !B1L1, , , , , , );
--WB1L2 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read_done~49
--operation mode is normal
WB1L2 = WB1_master_state[1] & WB1_master_state[0];
--CB1_d1_reasons_to_wait is std_1s10:inst|pll_s1_arbitrator:the_pll_s1|d1_reasons_to_wait
--operation mode is normal
CB1_d1_reasons_to_wait_lut_out = !WB1L3;
CB1_d1_reasons_to_wait = DFFEAS(CB1_d1_reasons_to_wait_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--WB1L3 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read_done~50
--operation mode is normal
WB1L3 = CB1_d1_reasons_to_wait # !WB1_master_state[1];
--TC1_break_readreg[21] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[21]
--operation mode is normal
TC1_break_readreg[21] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[21], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L20 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19908
--operation mode is normal
DD1L20 = AMPP_FUNCTION(TC1_break_readreg[21], CD1_internal_MonDReg[21], DD1_ir[1]);
--DD1L21 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19909
--operation mode is normal
DD1L21 = AMPP_FUNCTION(DD1L144, DD1L142, DD1L20, DD1_ir[0]);
--DD1_sr[23] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[23]
--operation mode is normal
DD1_sr[23] = AMPP_FUNCTION(!A1L6, DD1L32, DD1_sr[24], DD1L9, DD1L33, !C1_CLR_SIGNAL, DD1L12);
--DD1L22 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19910
--operation mode is normal
DD1L22 = AMPP_FUNCTION(DD1L20, DD1L144, A1L5, DD1_ir[0]);
--FB1L142 is std_1s10:inst|sdram:the_sdram|i_refs[2]~279
--operation mode is normal
FB1L142 = E1_data_out & FB1_i_state[1] & !FB1_i_state[0] & !FB1_i_state[2];
--FB1L139 is std_1s10:inst|sdram:the_sdram|i_refs[0]~280
--operation mode is normal
FB1L139 = E1_data_out & (!FB1_i_state[0] & !FB1_i_state[2]);
--FB1L99 is std_1s10:inst|sdram:the_sdram|Add1~37
--operation mode is normal
FB1L99 = FB1_i_refs[0] & FB1_i_refs[1];
--T1_fifo_wr is std_1s10:inst|jtag_uart:the_jtag_uart|fifo_wr
--operation mode is normal
T1_fifo_wr_lut_out = !L1_M_alu_result[2] & !WD1_b_full & (T1L55);
T1_fifo_wr = DFFEAS(T1_fifo_wr_lut_out, DE1__clk0, E1_data_out, , , , , , );
--WD1_b_non_empty is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty
--operation mode is normal
WD1_b_non_empty_lut_out = WD1_b_full # T1_fifo_wr # WD1_b_non_empty & WD1L7;
WD1_b_non_empty = DFFEAS(WD1_b_non_empty_lut_out, DE1__clk0, E1_data_out, , , , , , );
--T1_r_val is std_1s10:inst|jtag_uart:the_jtag_uart|r_val
--operation mode is normal
T1_r_val_lut_out = T1_rd_wfifo;
T1_r_val = DFFEAS(T1_r_val_lut_out, DE1__clk0, E1_data_out, , , , , , );
--QD1_r_ena1 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena1
--operation mode is normal
QD1_r_ena1 = AMPP_FUNCTION(DE1__clk0, QD1L19, E1_data_out);
--T1_rd_wfifo is std_1s10:inst|jtag_uart:the_jtag_uart|rd_wfifo
--operation mode is normal
T1_rd_wfifo = WD1_b_non_empty & !QD1_rvalid0 & (!QD1_r_ena1 # !T1_r_val);
--WD1L1 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|_~28
--operation mode is normal
WD1L1 = T1_fifo_wr $ T1_rd_wfifo;
--WD1L3 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_full~122
--operation mode is normal
WD1L3 = ZD1_safe_q[3] & ZD1_safe_q[0] & ZD1_safe_q[2] & ZD1_safe_q[1];
--WD1L4 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_full~123
--operation mode is normal
WD1L4 = ZD1_safe_q[5] & ZD1_safe_q[4] & T1_fifo_wr & WD1_b_non_empty;
--QD1L37Q is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_ena~reg0
--operation mode is normal
QD1L37Q = AMPP_FUNCTION(DE1__clk0, QD1_read_write1, QD1_read_write2, QD1L37Q, QD1L38, E1_data_out);
--T1_wr_rfifo is std_1s10:inst|jtag_uart:the_jtag_uart|wr_rfifo
--operation mode is normal
T1_wr_rfifo = QD1L37Q & (!WD2_b_full);
--T1L42 is std_1s10:inst|jtag_uart:the_jtag_uart|fifo_rd~32
--operation mode is normal
T1L42 = L1_internal_d_read & (!L1_M_alu_result[2]);
--T1L43 is std_1s10:inst|jtag_uart:the_jtag_uart|fifo_rd~33
--operation mode is normal
T1L43 = EB1L2 & U1L2 & T1L54 & T1L42;
--WD2L8 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~98
--operation mode is normal
WD2L8 = WD2_b_full # QD1L37Q & (!WD2_b_non_empty);
--WD2L2 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|_~85
--operation mode is normal
WD2L2 = ZD2_safe_q[3] # ZD2_safe_q[4] # ZD2_safe_q[5] # ZD2_safe_q[1];
--WD2L3 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|_~86
--operation mode is normal
WD2L3 = ZD2_safe_q[2] # T1_wr_rfifo # WD2L2 # !ZD2_safe_q[0];
--QD1_write_valid is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|write_valid
--operation mode is normal
QD1_write_valid = AMPP_FUNCTION(!A1L6, QD1_td_shift[10], !C1_CLR_SIGNAL, QD1L72);
--QD1L38 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_pause~71
--operation mode is normal
QD1L38 = AMPP_FUNCTION(T1_t_dav, QD1_write_stalled, QD1_write_valid);
--QD1_read_write1 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write1
--operation mode is normal
QD1_read_write1 = AMPP_FUNCTION(DE1__clk0, QD1_read_write, E1_data_out);
--QD1_read_write2 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write2
--operation mode is normal
QD1_read_write2 = AMPP_FUNCTION(DE1__clk0, QD1_read_write1, E1_data_out);
--QD1L2 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|always2~2
--operation mode is normal
QD1L2 = AMPP_FUNCTION(QD1_read_write1, QD1_read_write2);
--QD1_jupdate1 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate1
--operation mode is normal
QD1_jupdate1 = AMPP_FUNCTION(DE1__clk0, QD1_jupdate, E1_data_out);
--QD1_jupdate2 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate2
--operation mode is normal
QD1_jupdate2 = AMPP_FUNCTION(DE1__clk0, QD1_jupdate1, E1_data_out);
--N1_dbs_latent_8_reg_segment_1[0] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[0]
--operation mode is normal
N1_dbs_latent_8_reg_segment_1[0]_lut_out = Q1_internal_incoming_ext_ram_bus_data[0];
N1_dbs_latent_8_reg_segment_1[0] = DFFEAS(N1_dbs_latent_8_reg_segment_1[0]_lut_out, DE1__clk0, E1_data_out, , N1L155, , , , );
--N1L31 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[8]~1864
--operation mode is normal
N1L31 = BE1_q_a[8] & (N1_dbs_latent_8_reg_segment_1[0] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[8] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_1[0] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L32 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[8]~1865
--operation mode is normal
N1L32 = Q1_internal_incoming_ext_ram_bus_data[8] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L33 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[8]~1866
--operation mode is normal
N1L33 = N1L31 & N1L32 & (FB1_za_data[8] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--L1L209 is std_1s10:inst|cpu:the_cpu|D_ctrl_exception~33
--operation mode is normal
L1L209 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[15], L1_D_iw[14], L1_D_iw[13]);
--KB1_control_wr_strobe is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|control_wr_strobe
--operation mode is normal
KB1_control_wr_strobe = KB1L7 & LB1L2 & LB1L3 & HE1L19;
--KB1_internal_counter[0] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[0]
--operation mode is arithmetic
KB1_internal_counter[0]_lut_out = !KB1_internal_counter[0];
KB1_internal_counter[0] = DFFEAS(KB1_internal_counter[0]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[0], , , KB1L157);
--KB1L58 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[0]~7760
--operation mode is arithmetic
KB1L58 = CARRY(!KB1_internal_counter[0]);
--KB1_internal_counter[1] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[1]
--operation mode is arithmetic
KB1_internal_counter[1]_carry_eqn = KB1L58;
KB1_internal_counter[1]_lut_out = KB1_internal_counter[1] $ (!KB1_internal_counter[1]_carry_eqn);
KB1_internal_counter[1] = DFFEAS(KB1_internal_counter[1]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[1], , , KB1L157);
--KB1L60 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[1]~7761
--operation mode is arithmetic
KB1L60 = CARRY(KB1_internal_counter[1] & (!KB1L58));
--KB1_internal_counter[2] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[2]
--operation mode is arithmetic
KB1_internal_counter[2]_carry_eqn = KB1L60;
KB1_internal_counter[2]_lut_out = KB1_internal_counter[2] $ (KB1_internal_counter[2]_carry_eqn);
KB1_internal_counter[2] = DFFEAS(KB1_internal_counter[2]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[2], , , KB1L157);
--KB1L62 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[2]~7762
--operation mode is arithmetic
KB1L62 = CARRY(!KB1L60 # !KB1_internal_counter[2]);
--KB1_internal_counter[3] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[3]
--operation mode is arithmetic
KB1_internal_counter[3]_carry_eqn = KB1L62;
KB1_internal_counter[3]_lut_out = KB1_internal_counter[3] $ (!KB1_internal_counter[3]_carry_eqn);
KB1_internal_counter[3] = DFFEAS(KB1_internal_counter[3]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[3], , , KB1L157);
--KB1L64 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[3]~7763
--operation mode is arithmetic
KB1L64 = CARRY(KB1_internal_counter[3] & (!KB1L62));
--KB1L45 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~364
--operation mode is normal
KB1L45 = KB1_internal_counter[0] & KB1_internal_counter[1] & KB1_internal_counter[2] & KB1_internal_counter[3];
--KB1_internal_counter[4] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[4]
--operation mode is arithmetic
KB1_internal_counter[4]_carry_eqn = KB1L64;
KB1_internal_counter[4]_lut_out = KB1_internal_counter[4] $ (KB1_internal_counter[4]_carry_eqn);
KB1_internal_counter[4] = DFFEAS(KB1_internal_counter[4]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[4], , , KB1L157);
--KB1L66 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[4]~7764
--operation mode is arithmetic
KB1L66 = CARRY(!KB1L64 # !KB1_internal_counter[4]);
--KB1_internal_counter[5] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[5]
--operation mode is arithmetic
KB1_internal_counter[5]_carry_eqn = KB1L66;
KB1_internal_counter[5]_lut_out = KB1_internal_counter[5] $ (!KB1_internal_counter[5]_carry_eqn);
KB1_internal_counter[5] = DFFEAS(KB1_internal_counter[5]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[5], , , KB1L157);
--KB1L68 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[5]~7765
--operation mode is arithmetic
KB1L68 = CARRY(!KB1_internal_counter[5] & (!KB1L66));
--KB1_internal_counter[6] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[6]
--operation mode is arithmetic
KB1_internal_counter[6]_carry_eqn = KB1L68;
KB1_internal_counter[6]_lut_out = KB1_internal_counter[6] $ (KB1_internal_counter[6]_carry_eqn);
KB1_internal_counter[6] = DFFEAS(KB1_internal_counter[6]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[6], , , KB1L157);
--KB1L70 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[6]~7766
--operation mode is arithmetic
KB1L70 = CARRY(KB1_internal_counter[6] # !KB1L68);
--KB1_internal_counter[7] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[7]
--operation mode is arithmetic
KB1_internal_counter[7]_carry_eqn = KB1L70;
KB1_internal_counter[7]_lut_out = KB1_internal_counter[7] $ (!KB1_internal_counter[7]_carry_eqn);
KB1_internal_counter[7] = DFFEAS(KB1_internal_counter[7]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[7], , , KB1L157);
--KB1L72 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[7]~7767
--operation mode is arithmetic
KB1L72 = CARRY(!KB1_internal_counter[7] & (!KB1L70));
--KB1L46 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~365
--operation mode is normal
KB1L46 = KB1_internal_counter[4] & !KB1_internal_counter[5] & !KB1_internal_counter[6] & !KB1_internal_counter[7];
--KB1_internal_counter[8] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[8]
--operation mode is arithmetic
KB1_internal_counter[8]_carry_eqn = KB1L72;
KB1_internal_counter[8]_lut_out = KB1_internal_counter[8] $ (KB1_internal_counter[8]_carry_eqn);
KB1_internal_counter[8] = DFFEAS(KB1_internal_counter[8]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[8], , , KB1L157);
--KB1L74 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[8]~7768
--operation mode is arithmetic
KB1L74 = CARRY(!KB1L72 # !KB1_internal_counter[8]);
--KB1_internal_counter[9] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[9]
--operation mode is arithmetic
KB1_internal_counter[9]_carry_eqn = KB1L74;
KB1_internal_counter[9]_lut_out = KB1_internal_counter[9] $ (!KB1_internal_counter[9]_carry_eqn);
KB1_internal_counter[9] = DFFEAS(KB1_internal_counter[9]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[9], , , KB1L157);
--KB1L76 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[9]~7769
--operation mode is arithmetic
KB1L76 = CARRY(!KB1_internal_counter[9] & (!KB1L74));
--KB1_internal_counter[10] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[10]
--operation mode is arithmetic
KB1_internal_counter[10]_carry_eqn = KB1L76;
KB1_internal_counter[10]_lut_out = KB1_internal_counter[10] $ (KB1_internal_counter[10]_carry_eqn);
KB1_internal_counter[10] = DFFEAS(KB1_internal_counter[10]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[10], , , KB1L157);
--KB1L78 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[10]~7770
--operation mode is arithmetic
KB1L78 = CARRY(KB1_internal_counter[10] # !KB1L76);
--KB1_internal_counter[11] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[11]
--operation mode is arithmetic
KB1_internal_counter[11]_carry_eqn = KB1L78;
KB1_internal_counter[11]_lut_out = KB1_internal_counter[11] $ (!KB1_internal_counter[11]_carry_eqn);
KB1_internal_counter[11] = DFFEAS(KB1_internal_counter[11]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[11], , , KB1L157);
--KB1L80 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[11]~7771
--operation mode is arithmetic
KB1L80 = CARRY(!KB1_internal_counter[11] & (!KB1L78));
--KB1L47 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~366
--operation mode is normal
KB1L47 = KB1_internal_counter[8] & !KB1_internal_counter[9] & !KB1_internal_counter[10] & !KB1_internal_counter[11];
--KB1_internal_counter[13] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[13]
--operation mode is arithmetic
KB1_internal_counter[13]_carry_eqn = KB1L82;
KB1_internal_counter[13]_lut_out = KB1_internal_counter[13] $ (!KB1_internal_counter[13]_carry_eqn);
KB1_internal_counter[13] = DFFEAS(KB1_internal_counter[13]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[13], , , KB1L157);
--KB1L84 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[13]~7772
--operation mode is arithmetic
KB1L84 = CARRY(KB1_internal_counter[13] & (!KB1L82));
--KB1_internal_counter[15] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[15]
--operation mode is arithmetic
KB1_internal_counter[15]_carry_eqn = KB1L86;
KB1_internal_counter[15]_lut_out = KB1_internal_counter[15] $ (!KB1_internal_counter[15]_carry_eqn);
KB1_internal_counter[15] = DFFEAS(KB1_internal_counter[15]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[15], , , KB1L157);
--KB1L88 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[15]~7773
--operation mode is arithmetic
KB1L88 = CARRY(KB1_internal_counter[15] & (!KB1L86));
--KB1_internal_counter[12] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[12]
--operation mode is arithmetic
KB1_internal_counter[12]_carry_eqn = KB1L80;
KB1_internal_counter[12]_lut_out = KB1_internal_counter[12] $ (KB1_internal_counter[12]_carry_eqn);
KB1_internal_counter[12] = DFFEAS(KB1_internal_counter[12]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[12], , , KB1L157);
--KB1L82 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[12]~7774
--operation mode is arithmetic
KB1L82 = CARRY(KB1_internal_counter[12] # !KB1L80);
--KB1_internal_counter[14] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[14]
--operation mode is arithmetic
KB1_internal_counter[14]_carry_eqn = KB1L84;
KB1_internal_counter[14]_lut_out = KB1_internal_counter[14] $ (KB1_internal_counter[14]_carry_eqn);
KB1_internal_counter[14] = DFFEAS(KB1_internal_counter[14]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_l_register[14], , , KB1L157);
--KB1L86 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[14]~7775
--operation mode is arithmetic
KB1L86 = CARRY(KB1_internal_counter[14] # !KB1L84);
--KB1L48 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~367
--operation mode is normal
KB1L48 = KB1_internal_counter[13] & KB1_internal_counter[15] & !KB1_internal_counter[12] & !KB1_internal_counter[14];
--KB1L49 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~368
--operation mode is normal
KB1L49 = KB1L45 & KB1L46 & KB1L47 & KB1L48;
--KB1_internal_counter[16] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[16]
--operation mode is arithmetic
KB1_internal_counter[16]_carry_eqn = KB1L88;
KB1_internal_counter[16]_lut_out = KB1_internal_counter[16] $ (KB1_internal_counter[16]_carry_eqn);
KB1_internal_counter[16] = DFFEAS(KB1_internal_counter[16]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[0], , , KB1L157);
--KB1L90 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[16]~7776
--operation mode is arithmetic
KB1L90 = CARRY(!KB1L88 # !KB1_internal_counter[16]);
--KB1_internal_counter[17] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[17]
--operation mode is arithmetic
KB1_internal_counter[17]_carry_eqn = KB1L90;
KB1_internal_counter[17]_lut_out = KB1_internal_counter[17] $ (!KB1_internal_counter[17]_carry_eqn);
KB1_internal_counter[17] = DFFEAS(KB1_internal_counter[17]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[1], , , KB1L157);
--KB1L92 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[17]~7777
--operation mode is arithmetic
KB1L92 = CARRY(KB1_internal_counter[17] & (!KB1L90));
--KB1_internal_counter[18] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[18]
--operation mode is arithmetic
KB1_internal_counter[18]_carry_eqn = KB1L92;
KB1_internal_counter[18]_lut_out = KB1_internal_counter[18] $ (KB1_internal_counter[18]_carry_eqn);
KB1_internal_counter[18] = DFFEAS(KB1_internal_counter[18]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[2], , , KB1L157);
--KB1L94 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[18]~7778
--operation mode is arithmetic
KB1L94 = CARRY(!KB1L92 # !KB1_internal_counter[18]);
--KB1_internal_counter[19] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[19]
--operation mode is arithmetic
KB1_internal_counter[19]_carry_eqn = KB1L94;
KB1_internal_counter[19]_lut_out = KB1_internal_counter[19] $ (!KB1_internal_counter[19]_carry_eqn);
KB1_internal_counter[19] = DFFEAS(KB1_internal_counter[19]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[3], , , KB1L157);
--KB1L96 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[19]~7779
--operation mode is arithmetic
KB1L96 = CARRY(!KB1_internal_counter[19] & (!KB1L94));
--KB1L50 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~369
--operation mode is normal
KB1L50 = KB1_internal_counter[16] & KB1_internal_counter[17] & KB1_internal_counter[18] & !KB1_internal_counter[19];
--KB1_internal_counter[20] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[20]
--operation mode is arithmetic
KB1_internal_counter[20]_carry_eqn = KB1L96;
KB1_internal_counter[20]_lut_out = KB1_internal_counter[20] $ (KB1_internal_counter[20]_carry_eqn);
KB1_internal_counter[20] = DFFEAS(KB1_internal_counter[20]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[4], , , KB1L157);
--KB1L98 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[20]~7780
--operation mode is arithmetic
KB1L98 = CARRY(KB1_internal_counter[20] # !KB1L96);
--KB1_internal_counter[21] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[21]
--operation mode is arithmetic
KB1_internal_counter[21]_carry_eqn = KB1L98;
KB1_internal_counter[21]_lut_out = KB1_internal_counter[21] $ (!KB1_internal_counter[21]_carry_eqn);
KB1_internal_counter[21] = DFFEAS(KB1_internal_counter[21]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[5], , , KB1L157);
--KB1L100 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[21]~7781
--operation mode is arithmetic
KB1L100 = CARRY(!KB1_internal_counter[21] & (!KB1L98));
--KB1_internal_counter[22] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[22]
--operation mode is arithmetic
KB1_internal_counter[22]_carry_eqn = KB1L100;
KB1_internal_counter[22]_lut_out = KB1_internal_counter[22] $ (KB1_internal_counter[22]_carry_eqn);
KB1_internal_counter[22] = DFFEAS(KB1_internal_counter[22]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[6], , , KB1L157);
--KB1L102 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[22]~7782
--operation mode is arithmetic
KB1L102 = CARRY(KB1_internal_counter[22] # !KB1L100);
--KB1_internal_counter[23] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[23]
--operation mode is arithmetic
KB1_internal_counter[23]_carry_eqn = KB1L102;
KB1_internal_counter[23]_lut_out = KB1_internal_counter[23] $ (!KB1_internal_counter[23]_carry_eqn);
KB1_internal_counter[23] = DFFEAS(KB1_internal_counter[23]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[7], , , KB1L157);
--KB1L104 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[23]~7783
--operation mode is arithmetic
KB1L104 = CARRY(!KB1_internal_counter[23] & (!KB1L102));
--KB1L51 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~370
--operation mode is normal
KB1L51 = !KB1_internal_counter[20] & !KB1_internal_counter[21] & !KB1_internal_counter[22] & !KB1_internal_counter[23];
--KB1_internal_counter[24] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[24]
--operation mode is arithmetic
KB1_internal_counter[24]_carry_eqn = KB1L104;
KB1_internal_counter[24]_lut_out = KB1_internal_counter[24] $ (KB1_internal_counter[24]_carry_eqn);
KB1_internal_counter[24] = DFFEAS(KB1_internal_counter[24]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[8], , , KB1L157);
--KB1L106 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[24]~7784
--operation mode is arithmetic
KB1L106 = CARRY(KB1_internal_counter[24] # !KB1L104);
--KB1_internal_counter[25] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[25]
--operation mode is arithmetic
KB1_internal_counter[25]_carry_eqn = KB1L106;
KB1_internal_counter[25]_lut_out = KB1_internal_counter[25] $ (!KB1_internal_counter[25]_carry_eqn);
KB1_internal_counter[25] = DFFEAS(KB1_internal_counter[25]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[9], , , KB1L157);
--KB1L108 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[25]~7785
--operation mode is arithmetic
KB1L108 = CARRY(!KB1_internal_counter[25] & (!KB1L106));
--KB1_internal_counter[26] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[26]
--operation mode is arithmetic
KB1_internal_counter[26]_carry_eqn = KB1L108;
KB1_internal_counter[26]_lut_out = KB1_internal_counter[26] $ (KB1_internal_counter[26]_carry_eqn);
KB1_internal_counter[26] = DFFEAS(KB1_internal_counter[26]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[10], , , KB1L157);
--KB1L110 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[26]~7786
--operation mode is arithmetic
KB1L110 = CARRY(KB1_internal_counter[26] # !KB1L108);
--KB1_internal_counter[27] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[27]
--operation mode is arithmetic
KB1_internal_counter[27]_carry_eqn = KB1L110;
KB1_internal_counter[27]_lut_out = KB1_internal_counter[27] $ (!KB1_internal_counter[27]_carry_eqn);
KB1_internal_counter[27] = DFFEAS(KB1_internal_counter[27]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[11], , , KB1L157);
--KB1L112 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[27]~7787
--operation mode is arithmetic
KB1L112 = CARRY(!KB1_internal_counter[27] & (!KB1L110));
--KB1L52 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~371
--operation mode is normal
KB1L52 = !KB1_internal_counter[24] & !KB1_internal_counter[25] & !KB1_internal_counter[26] & !KB1_internal_counter[27];
--KB1_internal_counter[28] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[28]
--operation mode is arithmetic
KB1_internal_counter[28]_carry_eqn = KB1L112;
KB1_internal_counter[28]_lut_out = KB1_internal_counter[28] $ (KB1_internal_counter[28]_carry_eqn);
KB1_internal_counter[28] = DFFEAS(KB1_internal_counter[28]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[12], , , KB1L157);
--KB1L114 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[28]~7788
--operation mode is arithmetic
KB1L114 = CARRY(KB1_internal_counter[28] # !KB1L112);
--KB1_internal_counter[29] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[29]
--operation mode is arithmetic
KB1_internal_counter[29]_carry_eqn = KB1L114;
KB1_internal_counter[29]_lut_out = KB1_internal_counter[29] $ (!KB1_internal_counter[29]_carry_eqn);
KB1_internal_counter[29] = DFFEAS(KB1_internal_counter[29]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[13], , , KB1L157);
--KB1L116 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[29]~7789
--operation mode is arithmetic
KB1L116 = CARRY(!KB1_internal_counter[29] & (!KB1L114));
--KB1_internal_counter[30] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[30]
--operation mode is arithmetic
KB1_internal_counter[30]_carry_eqn = KB1L116;
KB1_internal_counter[30]_lut_out = KB1_internal_counter[30] $ (KB1_internal_counter[30]_carry_eqn);
KB1_internal_counter[30] = DFFEAS(KB1_internal_counter[30]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[14], , , KB1L157);
--KB1L118 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[30]~7790
--operation mode is arithmetic
KB1L118 = CARRY(KB1_internal_counter[30] # !KB1L116);
--KB1_internal_counter[31] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[31]
--operation mode is normal
KB1_internal_counter[31]_carry_eqn = KB1L118;
KB1_internal_counter[31]_lut_out = KB1_internal_counter[31] $ (!KB1_internal_counter[31]_carry_eqn);
KB1_internal_counter[31] = DFFEAS(KB1_internal_counter[31]_lut_out, DE1__clk0, E1_data_out, , KB1L156, KB1_period_h_register[15], , , KB1L157);
--KB1L53 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~372
--operation mode is normal
KB1L53 = !KB1_internal_counter[28] & !KB1_internal_counter[29] & !KB1_internal_counter[30] & !KB1_internal_counter[31];
--KB1L54 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~373
--operation mode is normal
KB1L54 = KB1L50 & KB1L51 & KB1L52 & KB1L53;
--KB1_delayed_unxcounter_is_zeroxx0 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|delayed_unxcounter_is_zeroxx0
--operation mode is normal
KB1_delayed_unxcounter_is_zeroxx0_lut_out = KB1L49 & KB1L54;
KB1_delayed_unxcounter_is_zeroxx0 = DFFEAS(KB1_delayed_unxcounter_is_zeroxx0_lut_out, DE1__clk0, E1_data_out, , , , , , );
--KB1L211 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|timeout_occurred~37
--operation mode is normal
KB1L211 = KB1_timeout_occurred # KB1L49 & KB1L54 & !KB1_delayed_unxcounter_is_zeroxx0;
--N1_dbs_latent_8_reg_segment_0[7] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[7]
--operation mode is normal
N1_dbs_latent_8_reg_segment_0[7]_lut_out = Q1_internal_incoming_ext_ram_bus_data[7];
N1_dbs_latent_8_reg_segment_0[7] = DFFEAS(N1_dbs_latent_8_reg_segment_0[7]_lut_out, DE1__clk0, E1_data_out, , N1L154, , , , );
--N1L28 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[7]~1868
--operation mode is normal
N1L28 = BE1_q_a[7] & (N1_dbs_latent_8_reg_segment_0[7] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[7] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_0[7] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L29 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[7]~1869
--operation mode is normal
N1L29 = Q1_internal_incoming_ext_ram_bus_data[7] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L30 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[7]~1870
--operation mode is normal
N1L30 = N1L28 & N1L29 & (FB1_za_data[7] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1_dbs_latent_8_reg_segment_0[6] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[6]
--operation mode is normal
N1_dbs_latent_8_reg_segment_0[6]_lut_out = Q1_internal_incoming_ext_ram_bus_data[6];
N1_dbs_latent_8_reg_segment_0[6] = DFFEAS(N1_dbs_latent_8_reg_segment_0[6]_lut_out, DE1__clk0, E1_data_out, , N1L154, , , , );
--N1L25 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[6]~1872
--operation mode is normal
N1L25 = BE1_q_a[6] & (N1_dbs_latent_8_reg_segment_0[6] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[6] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_0[6] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L26 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[6]~1873
--operation mode is normal
N1L26 = Q1_internal_incoming_ext_ram_bus_data[6] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L27 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[6]~1874
--operation mode is normal
N1L27 = N1L25 & N1L26 & (FB1_za_data[6] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1_dbs_latent_8_reg_segment_0[4] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[4]
--operation mode is normal
N1_dbs_latent_8_reg_segment_0[4]_lut_out = Q1_internal_incoming_ext_ram_bus_data[4];
N1_dbs_latent_8_reg_segment_0[4] = DFFEAS(N1_dbs_latent_8_reg_segment_0[4]_lut_out, DE1__clk0, E1_data_out, , N1L154, , , , );
--N1L19 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[4]~1876
--operation mode is normal
N1L19 = BE1_q_a[4] & (N1_dbs_latent_8_reg_segment_0[4] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[4] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_0[4] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L20 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[4]~1877
--operation mode is normal
N1L20 = Q1_internal_incoming_ext_ram_bus_data[4] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L21 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[4]~1878
--operation mode is normal
N1L21 = N1L19 & N1L20 & (FB1_za_data[4] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1_dbs_latent_8_reg_segment_1[7] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[7]
--operation mode is normal
N1_dbs_latent_8_reg_segment_1[7]_lut_out = Q1_internal_incoming_ext_ram_bus_data[7];
N1_dbs_latent_8_reg_segment_1[7] = DFFEAS(N1_dbs_latent_8_reg_segment_1[7]_lut_out, DE1__clk0, E1_data_out, , N1L155, , , , );
--N1L52 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~1880
--operation mode is normal
N1L52 = BE1_q_a[15] & (N1_dbs_latent_8_reg_segment_1[7] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[15] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_1[7] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L53 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~1881
--operation mode is normal
N1L53 = Q1_internal_incoming_ext_ram_bus_data[15] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L54 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~1882
--operation mode is normal
N1L54 = N1L52 & N1L53 & (FB1_za_data[15] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1_dbs_latent_8_reg_segment_0[5] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[5]
--operation mode is normal
N1_dbs_latent_8_reg_segment_0[5]_lut_out = Q1_internal_incoming_ext_ram_bus_data[5];
N1_dbs_latent_8_reg_segment_0[5] = DFFEAS(N1_dbs_latent_8_reg_segment_0[5]_lut_out, DE1__clk0, E1_data_out, , N1L154, , , , );
--N1L22 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[5]~1884
--operation mode is normal
N1L22 = BE1_q_a[5] & (N1_dbs_latent_8_reg_segment_0[5] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[5] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_0[5] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L23 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[5]~1885
--operation mode is normal
N1L23 = Q1_internal_incoming_ext_ram_bus_data[5] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L24 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[5]~1886
--operation mode is normal
N1L24 = N1L22 & N1L23 & (FB1_za_data[5] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1_dbs_latent_8_reg_segment_0[0] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[0]
--operation mode is normal
N1_dbs_latent_8_reg_segment_0[0]_lut_out = Q1_internal_incoming_ext_ram_bus_data[0];
N1_dbs_latent_8_reg_segment_0[0] = DFFEAS(N1_dbs_latent_8_reg_segment_0[0]_lut_out, DE1__clk0, E1_data_out, , N1L154, , , , );
--N1L7 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[0]~1888
--operation mode is normal
N1L7 = BE1_q_a[0] & (N1_dbs_latent_8_reg_segment_0[0] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[0] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_0[0] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L8 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[0]~1889
--operation mode is normal
N1L8 = Q1_internal_incoming_ext_ram_bus_data[0] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--FB1_za_data[0] is std_1s10:inst|sdram:the_sdram|za_data[0]
--operation mode is normal
FB1_za_data[0]_lut_out = A1L267;
FB1_za_data[0] = DFFEAS(FB1_za_data[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--N1L9 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[0]~1890
--operation mode is normal
N1L9 = N1L7 & N1L8 & (FB1_za_data[0] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1_dbs_latent_8_reg_segment_0[1] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[1]
--operation mode is normal
N1_dbs_latent_8_reg_segment_0[1]_lut_out = Q1_internal_incoming_ext_ram_bus_data[1];
N1_dbs_latent_8_reg_segment_0[1] = DFFEAS(N1_dbs_latent_8_reg_segment_0[1]_lut_out, DE1__clk0, E1_data_out, , N1L154, , , , );
--N1L10 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[1]~1892
--operation mode is normal
N1L10 = BE1_q_a[1] & (N1_dbs_latent_8_reg_segment_0[1] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[1] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_0[1] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L11 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[1]~1893
--operation mode is normal
N1L11 = Q1_internal_incoming_ext_ram_bus_data[1] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--FB1_za_data[1] is std_1s10:inst|sdram:the_sdram|za_data[1]
--operation mode is normal
FB1_za_data[1]_lut_out = A1L266;
FB1_za_data[1] = DFFEAS(FB1_za_data[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--N1L12 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[1]~1894
--operation mode is normal
N1L12 = N1L10 & N1L11 & (FB1_za_data[1] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1_dbs_latent_8_reg_segment_0[2] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[2]
--operation mode is normal
N1_dbs_latent_8_reg_segment_0[2]_lut_out = Q1_internal_incoming_ext_ram_bus_data[2];
N1_dbs_latent_8_reg_segment_0[2] = DFFEAS(N1_dbs_latent_8_reg_segment_0[2]_lut_out, DE1__clk0, E1_data_out, , N1L154, , , , );
--N1L13 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[2]~1896
--operation mode is normal
N1L13 = BE1_q_a[2] & (N1_dbs_latent_8_reg_segment_0[2] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[2] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_0[2] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L14 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[2]~1897
--operation mode is normal
N1L14 = Q1_internal_incoming_ext_ram_bus_data[2] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L15 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[2]~1898
--operation mode is normal
N1L15 = N1L13 & N1L14 & (FB1_za_data[2] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1_dbs_latent_8_reg_segment_0[3] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[3]
--operation mode is normal
N1_dbs_latent_8_reg_segment_0[3]_lut_out = Q1_internal_incoming_ext_ram_bus_data[3];
N1_dbs_latent_8_reg_segment_0[3] = DFFEAS(N1_dbs_latent_8_reg_segment_0[3]_lut_out, DE1__clk0, E1_data_out, , N1L154, , , , );
--N1L16 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[3]~1900
--operation mode is normal
N1L16 = BE1_q_a[3] & (N1_dbs_latent_8_reg_segment_0[3] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[3] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_0[3] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L17 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[3]~1901
--operation mode is normal
N1L17 = Q1_internal_incoming_ext_ram_bus_data[3] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L18 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[3]~1902
--operation mode is normal
N1L18 = N1L16 & N1L17 & (FB1_za_data[3] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L88 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[27]~1904
--operation mode is normal
N1L88 = Q1_internal_incoming_ext_ram_bus_data[3] & (BE1_q_a[27] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_internal_incoming_ext_ram_bus_data[3] & !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[27] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1L89 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[27]~1905
--operation mode is normal
N1L89 = Q1_internal_incoming_ext_ram_bus_data[27] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L90 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[27]~1906
--operation mode is normal
N1L90 = N1L88 & N1L89 & (FB1_za_data[27] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L91 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[28]~1908
--operation mode is normal
N1L91 = Q1_internal_incoming_ext_ram_bus_data[4] & (BE1_q_a[28] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_internal_incoming_ext_ram_bus_data[4] & !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[28] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1L92 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[28]~1909
--operation mode is normal
N1L92 = Q1_internal_incoming_ext_ram_bus_data[28] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L93 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[28]~1910
--operation mode is normal
N1L93 = N1L91 & N1L92 & (FB1_za_data[28] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L94 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[29]~1912
--operation mode is normal
N1L94 = BE1_q_a[29] & (Q1_internal_incoming_ext_ram_bus_data[5] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[29] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (Q1_internal_incoming_ext_ram_bus_data[5] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L95 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[29]~1913
--operation mode is normal
N1L95 = Q1_internal_incoming_ext_ram_bus_data[29] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L96 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[29]~1914
--operation mode is normal
N1L96 = N1L94 & N1L95 & (FB1_za_data[29] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L97 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[30]~1916
--operation mode is normal
N1L97 = BE1_q_a[30] & (Q1_internal_incoming_ext_ram_bus_data[6] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[30] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (Q1_internal_incoming_ext_ram_bus_data[6] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L98 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[30]~1917
--operation mode is normal
N1L98 = Q1_internal_incoming_ext_ram_bus_data[30] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L99 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[30]~1918
--operation mode is normal
N1L99 = N1L97 & N1L98 & (FB1_za_data[30] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L100 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[31]~1920
--operation mode is normal
N1L100 = Q1_internal_incoming_ext_ram_bus_data[7] & (BE1_q_a[31] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_internal_incoming_ext_ram_bus_data[7] & !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[31] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1L101 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[31]~1921
--operation mode is normal
N1L101 = Q1_internal_incoming_ext_ram_bus_data[31] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L102 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[31]~1922
--operation mode is normal
N1L102 = N1L100 & N1L101 & (FB1_za_data[31] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--MC1_q_b[26] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[26]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[26] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1418, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[26] is std_1s10:inst|cpu:the_cpu|W_wr_data[26]
--operation mode is normal
L1_W_wr_data[26] = AMPP_FUNCTION(DE1__clk0, L1L1418, E1_data_out, L1_W_stall);
--L1L1242 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[26]~1371
--operation mode is normal
L1L1242 = AMPP_FUNCTION(QC1_result[26], QC1_result[58]);
--HC1_result[26] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[26]
--operation mode is arithmetic
HC1_result[26] = AMPP_FUNCTION(L1L676, L1L610, HC1L53, L1_E_ctrl_alu_subtract);
--HC1L55 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[26]~COUT
--operation mode is arithmetic
HC1L55 = AMPP_FUNCTION(L1L676, L1L610, HC1L53, L1_E_ctrl_alu_subtract);
--L1L74 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12955
--operation mode is normal
L1L74 = AMPP_FUNCTION(HC1_result[26], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1L539 is std_1s10:inst|cpu:the_cpu|E_logic_result[26]~16137
--operation mode is normal
L1L539 = AMPP_FUNCTION(L1_E_logic_op[1], L1L610, L1L676, L1_E_logic_op[0]);
--MC1_q_b[27] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[27]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[27] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1421, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[27] is std_1s10:inst|cpu:the_cpu|W_wr_data[27]
--operation mode is normal
L1_W_wr_data[27] = AMPP_FUNCTION(DE1__clk0, L1L1421, E1_data_out, L1_W_stall);
--L1L1243 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[27]~1372
--operation mode is normal
L1L1243 = AMPP_FUNCTION(QC1_result[27], QC1_result[59]);
--HC1_result[27] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[27]
--operation mode is arithmetic
HC1_result[27] = AMPP_FUNCTION(L1L677, L1L611, HC1L55, L1_E_ctrl_alu_subtract);
--HC1L57 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[27]~COUT
--operation mode is arithmetic
HC1L57 = AMPP_FUNCTION(L1L677, L1L611, HC1L55, L1_E_ctrl_alu_subtract);
--L1L75 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12956
--operation mode is normal
L1L75 = AMPP_FUNCTION(HC1_result[27], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1L540 is std_1s10:inst|cpu:the_cpu|E_logic_result[27]~16138
--operation mode is normal
L1L540 = AMPP_FUNCTION(L1_E_logic_op[1], L1L611, L1L677, L1_E_logic_op[0]);
--MC1_q_b[28] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[28]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[28] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1424, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[28] is std_1s10:inst|cpu:the_cpu|W_wr_data[28]
--operation mode is normal
L1_W_wr_data[28] = AMPP_FUNCTION(DE1__clk0, L1L1424, E1_data_out, L1_W_stall);
--L1L1244 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[28]~1373
--operation mode is normal
L1L1244 = AMPP_FUNCTION(QC1_result[28], QC1_result[60]);
--HC1_result[28] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[28]
--operation mode is arithmetic
HC1_result[28] = AMPP_FUNCTION(L1L678, L1L612, HC1L57, L1_E_ctrl_alu_subtract);
--HC1L59 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[28]~COUT
--operation mode is arithmetic
HC1L59 = AMPP_FUNCTION(L1L678, L1L612, HC1L57, L1_E_ctrl_alu_subtract);
--L1L76 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12957
--operation mode is normal
L1L76 = AMPP_FUNCTION(HC1_result[28], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1L541 is std_1s10:inst|cpu:the_cpu|E_logic_result[28]~16139
--operation mode is normal
L1L541 = AMPP_FUNCTION(L1_E_logic_op[1], L1L612, L1L678, L1_E_logic_op[0]);
--MC1_q_b[29] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[29]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[29] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1427, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[29] is std_1s10:inst|cpu:the_cpu|W_wr_data[29]
--operation mode is normal
L1_W_wr_data[29] = AMPP_FUNCTION(DE1__clk0, L1L1427, E1_data_out, L1_W_stall);
--L1L1245 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[29]~1374
--operation mode is normal
L1L1245 = AMPP_FUNCTION(QC1_result[29], QC1_result[61]);
--HC1_result[29] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[29]
--operation mode is arithmetic
HC1_result[29] = AMPP_FUNCTION(L1L679, L1L613, HC1L59, L1_E_ctrl_alu_subtract);
--HC1L61 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[29]~COUT
--operation mode is arithmetic
HC1L61 = AMPP_FUNCTION(L1L679, L1L613, HC1L59, L1_E_ctrl_alu_subtract);
--L1L77 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12958
--operation mode is normal
L1L77 = AMPP_FUNCTION(HC1_result[29], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1L542 is std_1s10:inst|cpu:the_cpu|E_logic_result[29]~16140
--operation mode is normal
L1L542 = AMPP_FUNCTION(L1_E_logic_op[1], L1L613, L1L679, L1_E_logic_op[0]);
--MC1_q_b[30] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[30]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[30] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1430, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[30] is std_1s10:inst|cpu:the_cpu|W_wr_data[30]
--operation mode is normal
L1_W_wr_data[30] = AMPP_FUNCTION(DE1__clk0, L1L1430, E1_data_out, L1_W_stall);
--L1L1246 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[30]~1375
--operation mode is normal
L1L1246 = AMPP_FUNCTION(QC1_result[30], QC1_result[62]);
--L1L78 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12959
--operation mode is normal
L1L78 = AMPP_FUNCTION(HC1_result[30], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1L543 is std_1s10:inst|cpu:the_cpu|E_logic_result[30]~16141
--operation mode is normal
L1L543 = AMPP_FUNCTION(L1_E_logic_op[1], L1L614, L1L680, L1_E_logic_op[0]);
--MC1_q_b[31] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[31]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[31] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1433, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31]);
--L1_W_wr_data[31] is std_1s10:inst|cpu:the_cpu|W_wr_data[31]
--operation mode is normal
L1_W_wr_data[31] = AMPP_FUNCTION(DE1__clk0, L1L1433, E1_data_out, L1_W_stall);
--L1L1248 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[31]~1376
--operation mode is normal
L1L1248 = AMPP_FUNCTION(QC1_result[31], QC1_result[63]);
--L1L79 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12960
--operation mode is normal
L1L79 = AMPP_FUNCTION(HC1_result[31], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1L544 is std_1s10:inst|cpu:the_cpu|E_logic_result[31]~16142
--operation mode is normal
L1L544 = AMPP_FUNCTION(L1_E_logic_op[1], L1L615, L1L681, L1_E_logic_op[0]);
--L1L220 is std_1s10:inst|cpu:the_cpu|D_ctrl_mul_cell_src1_signed~102
--operation mode is normal
L1L220 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[11], L1_D_iw[14], L1_D_iw[13]);
--L1L395 is std_1s10:inst|cpu:the_cpu|D_src2_imm[26]~2263
--operation mode is normal
L1L395 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[21], L1L217);
--NC1_q_b[26] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[26]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[26] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1418, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L396 is std_1s10:inst|cpu:the_cpu|D_src2_imm[27]~2265
--operation mode is normal
L1L396 = AMPP_FUNCTION(L1_D_iw[17], L1_D_iw[21], L1L217);
--NC1_q_b[27] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[27]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[27] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1421, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L397 is std_1s10:inst|cpu:the_cpu|D_src2_imm[28]~2267
--operation mode is normal
L1L397 = AMPP_FUNCTION(L1_D_iw[18], L1_D_iw[21], L1L217);
--NC1_q_b[28] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[28]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[28] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1424, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L398 is std_1s10:inst|cpu:the_cpu|D_src2_imm[29]~2269
--operation mode is normal
L1L398 = AMPP_FUNCTION(L1_D_iw[19], L1_D_iw[21], L1L217);
--NC1_q_b[29] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[29]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[29] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1427, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--L1L399 is std_1s10:inst|cpu:the_cpu|D_src2_imm[30]~2271
--operation mode is normal
L1L399 = AMPP_FUNCTION(L1_D_iw[20], L1_D_iw[21], L1L217);
--NC1_q_b[30] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[30]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[30] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1430, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--NC1_q_b[31] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[31]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 1, Port B Depth: 32, Port B Width: 1
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[31] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1433, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26]);
--T1L61 is std_1s10:inst|jtag_uart:the_jtag_uart|rvalid~18
--operation mode is normal
T1L61 = WD2_b_non_empty & T1L43;
--QD1_wdata[2] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[2]
--operation mode is normal
QD1_wdata[2] = AMPP_FUNCTION(!A1L6, QD1_td_shift[6], !C1_CLR_SIGNAL, QD1L74);
--YD4_safe_q[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[0]
--operation mode is arithmetic
YD4_safe_q[0]_lut_out = YD4_safe_q[0] $ T1_wr_rfifo;
YD4_safe_q[0] = DFFEAS(YD4_safe_q[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD4L2 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella0~COUT
--operation mode is arithmetic
YD4L2 = CARRY(YD4_safe_q[0]);
--YD4_safe_q[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[1]
--operation mode is arithmetic
YD4_safe_q[1]_carry_eqn = YD4L2;
YD4_safe_q[1]_lut_out = YD4_safe_q[1] $ (T1_wr_rfifo & YD4_safe_q[1]_carry_eqn);
YD4_safe_q[1] = DFFEAS(YD4_safe_q[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD4L4 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella1~COUT
--operation mode is arithmetic
YD4L4 = CARRY(!YD4L2 # !YD4_safe_q[1]);
--YD4_safe_q[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[2]
--operation mode is arithmetic
YD4_safe_q[2]_carry_eqn = YD4L4;
YD4_safe_q[2]_lut_out = YD4_safe_q[2] $ (T1_wr_rfifo & !YD4_safe_q[2]_carry_eqn);
YD4_safe_q[2] = DFFEAS(YD4_safe_q[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD4L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella2~COUT
--operation mode is arithmetic
YD4L6 = CARRY(YD4_safe_q[2] & (!YD4L4));
--YD4_safe_q[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[3]
--operation mode is arithmetic
YD4_safe_q[3]_carry_eqn = YD4L6;
YD4_safe_q[3]_lut_out = YD4_safe_q[3] $ (T1_wr_rfifo & YD4_safe_q[3]_carry_eqn);
YD4_safe_q[3] = DFFEAS(YD4_safe_q[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD4L8 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella3~COUT
--operation mode is arithmetic
YD4L8 = CARRY(!YD4L6 # !YD4_safe_q[3]);
--YD4_safe_q[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[4]
--operation mode is arithmetic
YD4_safe_q[4]_carry_eqn = YD4L8;
YD4_safe_q[4]_lut_out = YD4_safe_q[4] $ (T1_wr_rfifo & !YD4_safe_q[4]_carry_eqn);
YD4_safe_q[4] = DFFEAS(YD4_safe_q[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD4L10 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella4~COUT
--operation mode is arithmetic
YD4L10 = CARRY(YD4_safe_q[4] & (!YD4L8));
--YD4_safe_q[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[5]
--operation mode is normal
YD4_safe_q[5]_carry_eqn = YD4L10;
YD4_safe_q[5]_lut_out = YD4_safe_q[5] $ (T1_wr_rfifo & YD4_safe_q[5]_carry_eqn);
YD4_safe_q[5] = DFFEAS(YD4_safe_q[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD3_safe_q[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[0]
--operation mode is arithmetic
YD3_safe_q[0]_lut_out = YD3_safe_q[0] $ T1L61;
YD3_safe_q[0] = DFFEAS(YD3_safe_q[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD3L2 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella0~COUT
--operation mode is arithmetic
YD3L2 = CARRY(YD3_safe_q[0]);
--YD3_safe_q[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[1]
--operation mode is arithmetic
YD3_safe_q[1]_carry_eqn = YD3L2;
YD3_safe_q[1]_lut_out = YD3_safe_q[1] $ (T1L61 & YD3_safe_q[1]_carry_eqn);
YD3_safe_q[1] = DFFEAS(YD3_safe_q[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD3L4 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella1~COUT
--operation mode is arithmetic
YD3L4 = CARRY(!YD3L2 # !YD3_safe_q[1]);
--YD3_safe_q[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[2]
--operation mode is arithmetic
YD3_safe_q[2]_carry_eqn = YD3L4;
YD3_safe_q[2]_lut_out = YD3_safe_q[2] $ (T1L61 & !YD3_safe_q[2]_carry_eqn);
YD3_safe_q[2] = DFFEAS(YD3_safe_q[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD3L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella2~COUT
--operation mode is arithmetic
YD3L6 = CARRY(YD3_safe_q[2] & (!YD3L4));
--YD3_safe_q[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[3]
--operation mode is arithmetic
YD3_safe_q[3]_carry_eqn = YD3L6;
YD3_safe_q[3]_lut_out = YD3_safe_q[3] $ (T1L61 & YD3_safe_q[3]_carry_eqn);
YD3_safe_q[3] = DFFEAS(YD3_safe_q[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD3L8 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella3~COUT
--operation mode is arithmetic
YD3L8 = CARRY(!YD3L6 # !YD3_safe_q[3]);
--YD3_safe_q[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[4]
--operation mode is arithmetic
YD3_safe_q[4]_carry_eqn = YD3L8;
YD3_safe_q[4]_lut_out = YD3_safe_q[4] $ (T1L61 & !YD3_safe_q[4]_carry_eqn);
YD3_safe_q[4] = DFFEAS(YD3_safe_q[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD3L10 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella4~COUT
--operation mode is arithmetic
YD3L10 = CARRY(YD3_safe_q[4] & (!YD3L8));
--YD3_safe_q[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[5]
--operation mode is normal
YD3_safe_q[5]_carry_eqn = YD3L10;
YD3_safe_q[5]_lut_out = YD3_safe_q[5] $ (T1L61 & YD3_safe_q[5]_carry_eqn);
YD3_safe_q[5] = DFFEAS(YD3_safe_q[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_readdata_p1[2] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[2]
--operation mode is normal
H1_slave_readdata_p1[2]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[2];
H1_slave_readdata_p1[2] = DFFEAS(H1_slave_readdata_p1[2]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--HE1L22 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~106
--operation mode is normal
HE1L22 = L1_M_alu_result[4] & (!L1_M_alu_result[3]);
--KB1L209 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|snap_strobe~22
--operation mode is normal
KB1L209 = KB1L7 & LB1L2 & LB1L3 & HE1L22;
--KB1_period_h_wr_strobe is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_wr_strobe
--operation mode is normal
KB1_period_h_wr_strobe = KB1L7 & HE1L15 & LB1L2 & LB1L3;
--KB1_period_l_wr_strobe is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_wr_strobe
--operation mode is normal
KB1_period_l_wr_strobe = KB1L7 & LB1L2 & LB1L3 & HE1L20;
--R1L208 is std_1s10:inst|high_res_timer:the_high_res_timer|snap_strobe~16
--operation mode is normal
R1L208 = KB1L7 & LB1L2 & S1L2 & HE1L22;
--R1_period_h_wr_strobe is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_wr_strobe
--operation mode is normal
R1_period_h_wr_strobe = KB1L7 & HE1L15 & LB1L2 & S1L2;
--R1_period_l_wr_strobe is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_wr_strobe
--operation mode is normal
R1_period_l_wr_strobe = KB1L7 & LB1L2 & S1L2 & HE1L20;
--JE1_delayed_unxrx_in_processxx3 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|delayed_unxrx_in_processxx3
--operation mode is normal
JE1_delayed_unxrx_in_processxx3_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0];
JE1_delayed_unxrx_in_processxx3 = DFFEAS(JE1_delayed_unxrx_in_processxx3_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] # JE1_do_start_rx;
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]_lut_out, DE1__clk0, E1_data_out, , JE1L62, , , , );
--JE1_got_new_char is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|got_new_char
--operation mode is normal
JE1_got_new_char = JE1_delayed_unxrx_in_processxx3 & (!JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]);
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1]
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] # JE1_do_start_rx;
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1]_lut_out, DE1__clk0, E1_data_out, , JE1L62, , , , );
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8]
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] # JE1_do_start_rx;
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8]_lut_out, DE1__clk0, E1_data_out, , JE1L62, , , , );
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] # JE1_do_start_rx;
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]_lut_out, DE1__clk0, E1_data_out, , JE1L62, , , , );
--JE1L69 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|WideOr0~60
--operation mode is normal
JE1L69 = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3];
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2]
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] # JE1_do_start_rx;
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2]_lut_out, DE1__clk0, E1_data_out, , JE1L62, , , , );
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4]
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] # JE1_do_start_rx;
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4]_lut_out, DE1__clk0, E1_data_out, , JE1L62, , , , );
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5]
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] # JE1_do_start_rx;
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5]_lut_out, DE1__clk0, E1_data_out, , JE1L62, , , , );
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] # JE1_do_start_rx;
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]_lut_out, DE1__clk0, E1_data_out, , JE1L62, , , , );
--JE1L70 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|WideOr0~61
--operation mode is normal
JE1L70 = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6];
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] # JE1_do_start_rx;
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]_lut_out, DE1__clk0, E1_data_out, , JE1L62, , , , );
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]_lut_out = JE1_do_start_rx # JE1L1 & JE1_sync_rxd # !JE1L1 & (JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]);
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1L71 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|WideOr0~62
--operation mode is normal
JE1L71 = JE1L69 # JE1L70 # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9];
--HE1L63 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|status_wr_strobe~11
--operation mode is normal
HE1L63 = L1_internal_d_write & LB1L2 & QB1L2 & HE1L20;
--DD1L191 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_b~22
--operation mode is normal
DD1L191 = AMPP_FUNCTION(DD1_internal_jdo1[35], DD1_jxdr, DD1_ir[0], DD1_ir[1]);
--DD1_internal_jdo1[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[3]
--operation mode is normal
DD1_internal_jdo1[3] = AMPP_FUNCTION(!A1L9, DD1_sr[3], VCC, DD1L144);
--CD1_MonAReg[10] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[10]
--operation mode is normal
CD1_MonAReg[10] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[17], CD1L81, CD1L18, DD1L190, !C1_CLR_SIGNAL, DD1L192);
--CD1L28 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7316
--operation mode is normal
CD1L28 = AMPP_FUNCTION(PD1_q_b[0], CD1_MonAReg[10]);
--CD1_MonRd1 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonRd1
--operation mode is normal
CD1_MonRd1 = AMPP_FUNCTION(DE1__clk0, CD1_MonRd, !C1_CLR_SIGNAL);
--CD1L29 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7318
--operation mode is normal
CD1L29 = AMPP_FUNCTION(DD1L191, CD1_MonRd1, DD1L189);
--CD1L19 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~88
--operation mode is normal
CD1L19 = AMPP_FUNCTION(CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4]);
--DD1_internal_jdo1[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[4]
--operation mode is normal
DD1_internal_jdo1[4] = AMPP_FUNCTION(!A1L9, DD1_sr[4], VCC, DD1L144);
--CD1L30 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7319
--operation mode is normal
CD1L30 = AMPP_FUNCTION(CD1_MonRd1, DD1L191);
--CD1L20 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~89
--operation mode is normal
CD1L20 = AMPP_FUNCTION(CD1_MonAReg[4], CD1_MonAReg[2], CD1_MonAReg[3]);
--DD1_internal_jdo1[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[5]
--operation mode is normal
DD1_internal_jdo1[5] = AMPP_FUNCTION(!A1L9, DD1_sr[5], VCC, DD1L144);
--CD1L1 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|A_WE_StdLogicVector~138
--operation mode is normal
CD1L1 = AMPP_FUNCTION(CD1_MonAReg[2], CD1_MonAReg[4], CD1_MonAReg[3]);
--DD1_internal_jdo1[6] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[6]
--operation mode is normal
DD1_internal_jdo1[6] = AMPP_FUNCTION(!A1L9, DD1_sr[6], VCC, DD1L144);
--DD1_internal_jdo1[7] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[7]
--operation mode is normal
DD1_internal_jdo1[7] = AMPP_FUNCTION(!A1L9, DD1_sr[7], VCC, DD1L144);
--CD1L21 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~90
--operation mode is normal
CD1L21 = AMPP_FUNCTION(CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4]);
--DD1_internal_jdo1[8] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[8]
--operation mode is normal
DD1_internal_jdo1[8] = AMPP_FUNCTION(!A1L9, DD1_sr[8], VCC, DD1L144);
--DD1_internal_jdo1[9] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[9]
--operation mode is normal
DD1_internal_jdo1[9] = AMPP_FUNCTION(!A1L9, DD1_sr[9], VCC, DD1L144);
--DD1_internal_jdo1[10] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[10]
--operation mode is normal
DD1_internal_jdo1[10] = AMPP_FUNCTION(!A1L9, DD1_sr[10], VCC, DD1L144);
--DD1_internal_jdo1[26] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[26]
--operation mode is normal
DD1_internal_jdo1[26] = AMPP_FUNCTION(!A1L9, DD1_sr[26], VCC, DD1L144);
--CD1L2 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~132
--operation mode is arithmetic
CD1L2 = AMPP_FUNCTION(CD1_MonAReg[2]);
--CD1L3 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~133
--operation mode is arithmetic
CD1L3 = AMPP_FUNCTION(CD1_MonAReg[2]);
--CD1L73 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1144
--operation mode is normal
CD1L73 = AMPP_FUNCTION(CD1L2, CD1_MonAReg[2], DD1L191);
--DD1L192 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_no_action_ocimem_a~16
--operation mode is normal
DD1L192 = AMPP_FUNCTION(DD1L189, DD1_internal_jdo1[34]);
--DD1_internal_jdo1[27] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[27]
--operation mode is normal
DD1_internal_jdo1[27] = AMPP_FUNCTION(!A1L9, DD1_sr[27], VCC, DD1L144);
--CD1L4 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~134
--operation mode is arithmetic
CD1L4 = AMPP_FUNCTION(CD1_MonAReg[3], CD1L3);
--CD1L5 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~135
--operation mode is arithmetic
CD1L5 = AMPP_FUNCTION(CD1_MonAReg[3], CD1L3);
--CD1L74 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1145
--operation mode is normal
CD1L74 = AMPP_FUNCTION(CD1L4, CD1_MonAReg[3], DD1L191);
--DD1_internal_jdo1[28] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[28]
--operation mode is normal
DD1_internal_jdo1[28] = AMPP_FUNCTION(!A1L9, DD1_sr[28], VCC, DD1L144);
--CD1L6 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~136
--operation mode is arithmetic
CD1L6 = AMPP_FUNCTION(CD1_MonAReg[4], CD1L5);
--CD1L7 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~137
--operation mode is arithmetic
CD1L7 = AMPP_FUNCTION(CD1_MonAReg[4], CD1L5);
--CD1L75 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1146
--operation mode is normal
CD1L75 = AMPP_FUNCTION(CD1L6, CD1_MonAReg[4], DD1L191);
--DD1_internal_jdo1[29] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[29]
--operation mode is normal
DD1_internal_jdo1[29] = AMPP_FUNCTION(!A1L9, DD1_sr[29], VCC, DD1L144);
--CD1L8 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~138
--operation mode is arithmetic
CD1L8 = AMPP_FUNCTION(CD1_MonAReg[5], CD1L7);
--CD1L9 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~139
--operation mode is arithmetic
CD1L9 = AMPP_FUNCTION(CD1_MonAReg[5], CD1L7);
--CD1L76 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1147
--operation mode is normal
CD1L76 = AMPP_FUNCTION(CD1L8, CD1_MonAReg[5], DD1L191);
--DD1_internal_jdo1[30] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[30]
--operation mode is normal
DD1_internal_jdo1[30] = AMPP_FUNCTION(!A1L9, DD1_sr[30], VCC, DD1L144);
--CD1L10 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~140
--operation mode is arithmetic
CD1L10 = AMPP_FUNCTION(CD1_MonAReg[6], CD1L9);
--CD1L11 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~141
--operation mode is arithmetic
CD1L11 = AMPP_FUNCTION(CD1_MonAReg[6], CD1L9);
--CD1L77 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1148
--operation mode is normal
CD1L77 = AMPP_FUNCTION(CD1L10, CD1_MonAReg[6], DD1L191);
--DD1_internal_jdo1[31] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[31]
--operation mode is normal
DD1_internal_jdo1[31] = AMPP_FUNCTION(!A1L9, DD1_sr[31], VCC, DD1L144);
--CD1L12 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~142
--operation mode is arithmetic
CD1L12 = AMPP_FUNCTION(CD1_MonAReg[7], CD1L11);
--CD1L13 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~143
--operation mode is arithmetic
CD1L13 = AMPP_FUNCTION(CD1_MonAReg[7], CD1L11);
--CD1L78 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1149
--operation mode is normal
CD1L78 = AMPP_FUNCTION(CD1L12, CD1_MonAReg[7], DD1L191);
--DD1_internal_jdo1[32] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[32]
--operation mode is normal
DD1_internal_jdo1[32] = AMPP_FUNCTION(!A1L9, DD1_sr[32], VCC, DD1L144);
--CD1L14 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~144
--operation mode is arithmetic
CD1L14 = AMPP_FUNCTION(CD1_MonAReg[8], CD1L13);
--CD1L15 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~145
--operation mode is arithmetic
CD1L15 = AMPP_FUNCTION(CD1_MonAReg[8], CD1L13);
--CD1L79 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1150
--operation mode is normal
CD1L79 = AMPP_FUNCTION(CD1L14, CD1_MonAReg[8], DD1L191);
--DD1_internal_jdo1[33] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[33]
--operation mode is normal
DD1_internal_jdo1[33] = AMPP_FUNCTION(!A1L9, DD1_sr[33], VCC, DD1L144);
--CD1L16 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~146
--operation mode is arithmetic
CD1L16 = AMPP_FUNCTION(CD1_MonAReg[9], CD1L15);
--CD1L17 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~147
--operation mode is arithmetic
CD1L17 = AMPP_FUNCTION(CD1_MonAReg[9], CD1L15);
--CD1L80 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1151
--operation mode is normal
CD1L80 = AMPP_FUNCTION(CD1L16, CD1_MonAReg[9], DD1L191);
--CD1L22 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~91
--operation mode is normal
CD1L22 = AMPP_FUNCTION(CD1_MonAReg[3], CD1_MonAReg[2], CD1_MonAReg[4]);
--DD1_internal_jdo1[24] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[24]
--operation mode is normal
DD1_internal_jdo1[24] = AMPP_FUNCTION(!A1L9, DD1_sr[24], VCC, DD1L144);
--N1_dbs_latent_8_reg_segment_1[4] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[4]
--operation mode is normal
N1_dbs_latent_8_reg_segment_1[4]_lut_out = Q1_internal_incoming_ext_ram_bus_data[4];
N1_dbs_latent_8_reg_segment_1[4] = DFFEAS(N1_dbs_latent_8_reg_segment_1[4]_lut_out, DE1__clk0, E1_data_out, , N1L155, , , , );
--N1L43 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[12]~1924
--operation mode is normal
N1L43 = BE1_q_a[12] & (N1_dbs_latent_8_reg_segment_1[4] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[12] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_1[4] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L44 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[12]~1925
--operation mode is normal
N1L44 = Q1_internal_incoming_ext_ram_bus_data[12] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L45 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[12]~1926
--operation mode is normal
N1L45 = N1L43 & N1L44 & (FB1_za_data[12] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1_dbs_latent_8_reg_segment_1[3] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[3]
--operation mode is normal
N1_dbs_latent_8_reg_segment_1[3]_lut_out = Q1_internal_incoming_ext_ram_bus_data[3];
N1_dbs_latent_8_reg_segment_1[3] = DFFEAS(N1_dbs_latent_8_reg_segment_1[3]_lut_out, DE1__clk0, E1_data_out, , N1L155, , , , );
--N1L40 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[11]~1928
--operation mode is normal
N1L40 = BE1_q_a[11] & (N1_dbs_latent_8_reg_segment_1[3] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[11] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_1[3] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L41 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[11]~1929
--operation mode is normal
N1L41 = Q1_internal_incoming_ext_ram_bus_data[11] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L42 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[11]~1930
--operation mode is normal
N1L42 = N1L40 & N1L41 & (FB1_za_data[11] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1_dbs_latent_8_reg_segment_2[0] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[0]
--operation mode is normal
N1_dbs_latent_8_reg_segment_2[0]_lut_out = Q1_internal_incoming_ext_ram_bus_data[0];
N1_dbs_latent_8_reg_segment_2[0] = DFFEAS(N1_dbs_latent_8_reg_segment_2[0]_lut_out, DE1__clk0, E1_data_out, , N1L156, , , , );
--N1L55 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[16]~1932
--operation mode is normal
N1L55 = BE1_q_a[16] & (N1_dbs_latent_8_reg_segment_2[0] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[16] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_2[0] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L56 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[16]~1933
--operation mode is normal
N1L56 = Q1_internal_incoming_ext_ram_bus_data[16] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L57 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[16]~1934
--operation mode is normal
N1L57 = N1L55 & N1L56 & (FB1_za_data[16] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1_dbs_latent_8_reg_segment_1[6] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[6]
--operation mode is normal
N1_dbs_latent_8_reg_segment_1[6]_lut_out = Q1_internal_incoming_ext_ram_bus_data[6];
N1_dbs_latent_8_reg_segment_1[6] = DFFEAS(N1_dbs_latent_8_reg_segment_1[6]_lut_out, DE1__clk0, E1_data_out, , N1L155, , , , );
--N1L49 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[14]~1936
--operation mode is normal
N1L49 = BE1_q_a[14] & (N1_dbs_latent_8_reg_segment_1[6] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[14] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_1[6] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L50 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[14]~1937
--operation mode is normal
N1L50 = Q1_internal_incoming_ext_ram_bus_data[14] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L51 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[14]~1938
--operation mode is normal
N1L51 = N1L49 & N1L50 & (FB1_za_data[14] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1_dbs_latent_8_reg_segment_1[5] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[5]
--operation mode is normal
N1_dbs_latent_8_reg_segment_1[5]_lut_out = Q1_internal_incoming_ext_ram_bus_data[5];
N1_dbs_latent_8_reg_segment_1[5] = DFFEAS(N1_dbs_latent_8_reg_segment_1[5]_lut_out, DE1__clk0, E1_data_out, , N1L155, , , , );
--N1L46 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[13]~1940
--operation mode is normal
N1L46 = BE1_q_a[13] & (N1_dbs_latent_8_reg_segment_1[5] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[13] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_1[5] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L47 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[13]~1941
--operation mode is normal
N1L47 = Q1_internal_incoming_ext_ram_bus_data[13] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L48 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[13]~1942
--operation mode is normal
N1L48 = N1L46 & N1L47 & (FB1_za_data[13] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1_dbs_latent_8_reg_segment_2[5] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[5]
--operation mode is normal
N1_dbs_latent_8_reg_segment_2[5]_lut_out = Q1_internal_incoming_ext_ram_bus_data[5];
N1_dbs_latent_8_reg_segment_2[5] = DFFEAS(N1_dbs_latent_8_reg_segment_2[5]_lut_out, DE1__clk0, E1_data_out, , N1L156, , , , );
--N1L70 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[21]~1944
--operation mode is normal
N1L70 = BE1_q_a[21] & (N1_dbs_latent_8_reg_segment_2[5] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[21] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_2[5] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L71 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[21]~1945
--operation mode is normal
N1L71 = Q1_internal_incoming_ext_ram_bus_data[21] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L72 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[21]~1946
--operation mode is normal
N1L72 = N1L70 & N1L71 & (FB1_za_data[21] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--QB1_d1_reasons_to_wait is std_1s10:inst|uart1_s1_arbitrator:the_uart1_s1|d1_reasons_to_wait
--operation mode is normal
QB1_d1_reasons_to_wait_lut_out = L1_M_alu_result[6] & !L1_M_alu_result[5] & !QB1_d1_reasons_to_wait & LB1L2;
QB1_d1_reasons_to_wait = DFFEAS(QB1_d1_reasons_to_wait_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1L53 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_rd_strobe_onset~25
--operation mode is normal
JE1L53 = L1_M_alu_result[6] & (!L1_M_alu_result[5] & !QB1_d1_reasons_to_wait);
--JE1L54 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_rd_strobe_onset~26
--operation mode is normal
JE1L54 = P1L7 & NB1L2 & JE1L53 & !L1_M_alu_result[7];
--KE1L32 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_wr_strobe_onset~16
--operation mode is normal
KE1L32 = L1_internal_d_write & HE1L19 & JE1L54;
--JE1L39 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|framing_error~94
--operation mode is normal
JE1L39 = JE1_framing_error # JE1_got_new_char & JE1L71 & !JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9];
--KE1L24 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|internal_tx_ready~34
--operation mode is normal
KE1L24 = KE1_do_load_shifter # !KE1_internal_tx_ready;
--JE1L42 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|internal_rx_char_ready~30
--operation mode is normal
JE1L42 = JE1_internal_rx_char_ready # JE1_delayed_unxrx_in_processxx3 & (!JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]);
--QD1_wdata[3] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[3]
--operation mode is normal
QD1_wdata[3] = AMPP_FUNCTION(!A1L6, QD1_td_shift[7], !C1_CLR_SIGNAL, QD1L74);
--H1_slave_readdata_p1[3] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[3]
--operation mode is normal
H1_slave_readdata_p1[3]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[3];
H1_slave_readdata_p1[3] = DFFEAS(H1_slave_readdata_p1[3]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--N1_dbs_latent_8_reg_segment_1[1] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[1]
--operation mode is normal
N1_dbs_latent_8_reg_segment_1[1]_lut_out = Q1_internal_incoming_ext_ram_bus_data[1];
N1_dbs_latent_8_reg_segment_1[1] = DFFEAS(N1_dbs_latent_8_reg_segment_1[1]_lut_out, DE1__clk0, E1_data_out, , N1L155, , , , );
--N1L34 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~1948
--operation mode is normal
N1L34 = BE1_q_a[9] & (N1_dbs_latent_8_reg_segment_1[1] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[9] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_1[1] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L35 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~1949
--operation mode is normal
N1L35 = Q1_internal_incoming_ext_ram_bus_data[9] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L36 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~1950
--operation mode is normal
N1L36 = N1L34 & N1L35 & (FB1_za_data[9] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--QD1_wdata[7] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[7]
--operation mode is normal
QD1_wdata[7] = AMPP_FUNCTION(!A1L6, altera_internal_jtag, !C1_CLR_SIGNAL, QD1L74);
--H1_slave_readdata_p1[7] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[7]
--operation mode is normal
H1_slave_readdata_p1[7]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[7];
H1_slave_readdata_p1[7] = DFFEAS(H1_slave_readdata_p1[7]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--GC1L7 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~565
--operation mode is arithmetic
GC1L7 = AMPP_FUNCTION(L1L613, L1L679, GC1L9);
--L1L190 is std_1s10:inst|cpu:the_cpu|D_ctrl_alu_signed_cmp~319
--operation mode is normal
L1L190 = AMPP_FUNCTION(L1L189, L1_D_iw[4], L1L194, L1_D_iw[5]);
--TC1_break_readreg[18] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[18]
--operation mode is normal
TC1_break_readreg[18] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[18], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L23 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19912
--operation mode is normal
DD1L23 = AMPP_FUNCTION(TC1_break_readreg[18], CD1_internal_MonDReg[18], DD1_ir[1]);
--DD1L24 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19913
--operation mode is normal
DD1L24 = AMPP_FUNCTION(DD1L143, DD1_ir[1], DD1L23, DD1_ir[0]);
--TC1_break_readreg[17] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[17]
--operation mode is normal
TC1_break_readreg[17] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[17], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L25 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19915
--operation mode is normal
DD1L25 = AMPP_FUNCTION(TC1_break_readreg[17], CD1_internal_MonDReg[17], DD1_ir[1]);
--DD1L26 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19916
--operation mode is normal
DD1L26 = AMPP_FUNCTION(DD1L144, DD1L142, DD1L25, DD1_ir[0]);
--DD1L27 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19917
--operation mode is normal
DD1L27 = AMPP_FUNCTION(DD1L25, DD1L144, A1L5, DD1_ir[0]);
--DD1_internal_jdo1[37] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[37]
--operation mode is normal
DD1_internal_jdo1[37] = AMPP_FUNCTION(!A1L9, DD1_sr[37], VCC, DD1L144);
--DD1_internal_jdo1[36] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[36]
--operation mode is normal
DD1_internal_jdo1[36] = AMPP_FUNCTION(!A1L9, DD1_sr[36], VCC, DD1L144);
--DD1L188 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_break_c~45
--operation mode is normal
DD1L188 = AMPP_FUNCTION(DD1_jxdr, DD1_ir[1], DD1_ir[0]);
--RE1_state[14] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14]
--operation mode is normal
RE1_state[14] = AMPP_FUNCTION(!A1L6, RE1_state[13], A1L8, VCC);
--VC1L3 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_error~106
--operation mode is normal
VC1L3 = AMPP_FUNCTION(VC1_internal_monitor_error, DD1_internal_jdo1[34], DD1L189, DD1_internal_jdo1[25]);
--DD1_sr[37] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[37]
--operation mode is normal
DD1_sr[37] = AMPP_FUNCTION(!A1L6, DD1L28, DD1L144, A1L5, altera_internal_jtag, !C1_CLR_SIGNAL, DD1L30);
--DD1L28 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19919
--operation mode is normal
DD1L28 = AMPP_FUNCTION(DD1_ir[0], DD1_ir[1]);
--DD1L29 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19921
--operation mode is normal
DD1L29 = AMPP_FUNCTION(DD1_ir[0], DD1_ir[1]);
--DD1L30 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19922
--operation mode is normal
DD1L30 = AMPP_FUNCTION(DD1L143, DD1L141, DD1L29, DD1_st_updateir);
--C1L8 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~1
--operation mode is normal
C1L8 = AMPP_FUNCTION(ME8_Q[0], C1_OK_TO_UPDATE_IR_Q, RE1_state[5]);
--R1_period_l_register[0] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[0]
--operation mode is normal
R1_period_l_register[0]_lut_out = !L1_M_st_data[0];
R1_period_l_register[0] = DFFEAS(R1_period_l_register[0]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--R1_force_reload is std_1s10:inst|high_res_timer:the_high_res_timer|force_reload
--operation mode is normal
R1_force_reload_lut_out = KB1L7 & NB1L3 & LB1L2 & S1L2;
R1_force_reload = DFFEAS(R1_force_reload_lut_out, DE1__clk0, E1_data_out, , , , , , );
--R1L156 is std_1s10:inst|high_res_timer:the_high_res_timer|process0~1
--operation mode is normal
R1L156 = R1_force_reload # R1L48 & R1L53;
--R1_counter_is_running is std_1s10:inst|high_res_timer:the_high_res_timer|counter_is_running
--operation mode is normal
R1_counter_is_running_lut_out = R1_control_wr_strobe & (L1_M_st_data[2] # R1L9 & !L1_M_st_data[3]) # !R1_control_wr_strobe & (R1L9);
R1_counter_is_running = DFFEAS(R1_counter_is_running_lut_out, DE1__clk0, E1_data_out, , , , , , );
--R1L155 is std_1s10:inst|high_res_timer:the_high_res_timer|process0~0
--operation mode is normal
R1L155 = R1_force_reload # R1_counter_is_running;
--R1_period_l_register[1] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[1]
--operation mode is normal
R1_period_l_register[1]_lut_out = !L1_M_st_data[1];
R1_period_l_register[1] = DFFEAS(R1_period_l_register[1]_lut_out, DE1__clk0, E1_data_out, , R1_period_l_wr_strobe, , , , );
--R1_period_h_register[0] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[0]
--operation mode is normal
R1_period_h_register[0]_lut_out = L1_M_st_data[0];
R1_period_h_register[0] = DFFEAS(R1_period_h_register[0]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--R1_period_h_register[1] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[1]
--operation mode is normal
R1_period_h_register[1]_lut_out = L1_M_st_data[1];
R1_period_h_register[1] = DFFEAS(R1_period_h_register[1]_lut_out, DE1__clk0, E1_data_out, , R1_period_h_wr_strobe, , , , );
--QD1_wdata[4] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[4]
--operation mode is normal
QD1_wdata[4] = AMPP_FUNCTION(!A1L6, QD1_td_shift[8], !C1_CLR_SIGNAL, QD1L74);
--H1_slave_readdata_p1[4] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[4]
--operation mode is normal
H1_slave_readdata_p1[4]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[4];
H1_slave_readdata_p1[4] = DFFEAS(H1_slave_readdata_p1[4]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--N1_dbs_latent_8_reg_segment_1[2] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[2]
--operation mode is normal
N1_dbs_latent_8_reg_segment_1[2]_lut_out = Q1_internal_incoming_ext_ram_bus_data[2];
N1_dbs_latent_8_reg_segment_1[2] = DFFEAS(N1_dbs_latent_8_reg_segment_1[2]_lut_out, DE1__clk0, E1_data_out, , N1L155, , , , );
--N1L37 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~1952
--operation mode is normal
N1L37 = BE1_q_a[10] & (N1_dbs_latent_8_reg_segment_1[2] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[10] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_1[2] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L38 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~1953
--operation mode is normal
N1L38 = Q1_internal_incoming_ext_ram_bus_data[10] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L39 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~1954
--operation mode is normal
N1L39 = N1L37 & N1L38 & (FB1_za_data[10] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--WD2L5 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_full~86
--operation mode is normal
WD2L5 = ZD2_safe_q[4] & ZD2_safe_q[5] & ZD2_safe_q[1] & QD1L37Q;
--WD2L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_full~87
--operation mode is normal
WD2L6 = ZD2_safe_q[0] & ZD2_safe_q[2] & ZD2_safe_q[3] & WD2L5;
--H1_slave_readdata_p1[15] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[15]
--operation mode is normal
H1_slave_readdata_p1[15]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[15];
H1_slave_readdata_p1[15] = DFFEAS(H1_slave_readdata_p1[15]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--DD1_internal_jdo1[11] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[11]
--operation mode is normal
DD1_internal_jdo1[11] = AMPP_FUNCTION(!A1L9, DD1_sr[11], VCC, DD1L144);
--DD1_internal_jdo1[12] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[12]
--operation mode is normal
DD1_internal_jdo1[12] = AMPP_FUNCTION(!A1L9, DD1_sr[12], VCC, DD1L144);
--DD1_internal_jdo1[13] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[13]
--operation mode is normal
DD1_internal_jdo1[13] = AMPP_FUNCTION(!A1L9, DD1_sr[13], VCC, DD1L144);
--DD1_internal_jdo1[14] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[14]
--operation mode is normal
DD1_internal_jdo1[14] = AMPP_FUNCTION(!A1L9, DD1_sr[14], VCC, DD1L144);
--DD1_internal_jdo1[15] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[15]
--operation mode is normal
DD1_internal_jdo1[15] = AMPP_FUNCTION(!A1L9, DD1_sr[15], VCC, DD1L144);
--DD1_internal_jdo1[16] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[16]
--operation mode is normal
DD1_internal_jdo1[16] = AMPP_FUNCTION(!A1L9, DD1_sr[16], VCC, DD1L144);
--DD1_internal_jdo1[17] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[17]
--operation mode is normal
DD1_internal_jdo1[17] = AMPP_FUNCTION(!A1L9, DD1_sr[17], VCC, DD1L144);
--N1_dbs_latent_8_reg_segment_2[6] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[6]
--operation mode is normal
N1_dbs_latent_8_reg_segment_2[6]_lut_out = Q1_internal_incoming_ext_ram_bus_data[6];
N1_dbs_latent_8_reg_segment_2[6] = DFFEAS(N1_dbs_latent_8_reg_segment_2[6]_lut_out, DE1__clk0, E1_data_out, , N1L156, , , , );
--N1L73 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[22]~1956
--operation mode is normal
N1L73 = BE1_q_a[22] & (N1_dbs_latent_8_reg_segment_2[6] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[22] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_2[6] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L74 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[22]~1957
--operation mode is normal
N1L74 = Q1_internal_incoming_ext_ram_bus_data[22] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L75 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[22]~1958
--operation mode is normal
N1L75 = N1L73 & N1L74 & (FB1_za_data[22] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1_dbs_latent_8_reg_segment_2[7] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[7]
--operation mode is normal
N1_dbs_latent_8_reg_segment_2[7]_lut_out = Q1_internal_incoming_ext_ram_bus_data[7];
N1_dbs_latent_8_reg_segment_2[7] = DFFEAS(N1_dbs_latent_8_reg_segment_2[7]_lut_out, DE1__clk0, E1_data_out, , N1L156, , , , );
--N1L76 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[23]~1960
--operation mode is normal
N1L76 = BE1_q_a[23] & (N1_dbs_latent_8_reg_segment_2[7] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[23] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_2[7] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L77 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[23]~1961
--operation mode is normal
N1L77 = Q1_internal_incoming_ext_ram_bus_data[23] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L78 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[23]~1962
--operation mode is normal
N1L78 = N1L76 & N1L77 & (FB1_za_data[23] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L79 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[24]~1964
--operation mode is normal
N1L79 = BE1_q_a[24] & (Q1_internal_incoming_ext_ram_bus_data[0] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[24] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (Q1_internal_incoming_ext_ram_bus_data[0] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L80 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[24]~1965
--operation mode is normal
N1L80 = Q1_internal_incoming_ext_ram_bus_data[24] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L81 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[24]~1966
--operation mode is normal
N1L81 = N1L79 & N1L80 & (FB1_za_data[24] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L82 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[25]~1968
--operation mode is normal
N1L82 = BE1_q_a[25] & (Q1_internal_incoming_ext_ram_bus_data[1] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[25] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (Q1_internal_incoming_ext_ram_bus_data[1] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L83 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[25]~1969
--operation mode is normal
N1L83 = Q1_internal_incoming_ext_ram_bus_data[25] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L84 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[25]~1970
--operation mode is normal
N1L84 = N1L82 & N1L83 & (FB1_za_data[25] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L85 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[26]~1972
--operation mode is normal
N1L85 = Q1_internal_incoming_ext_ram_bus_data[2] & (BE1_q_a[26] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_internal_incoming_ext_ram_bus_data[2] & !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[26] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1L86 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[26]~1973
--operation mode is normal
N1L86 = Q1_internal_incoming_ext_ram_bus_data[26] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L87 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[26]~1974
--operation mode is normal
N1L87 = N1L85 & N1L86 & (FB1_za_data[26] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--T1L37 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~316
--operation mode is arithmetic
T1L37 = CARRY(!ZD1_safe_q[0]);
--N1_dbs_latent_8_reg_segment_2[4] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[4]
--operation mode is normal
N1_dbs_latent_8_reg_segment_2[4]_lut_out = Q1_internal_incoming_ext_ram_bus_data[4];
N1_dbs_latent_8_reg_segment_2[4] = DFFEAS(N1_dbs_latent_8_reg_segment_2[4]_lut_out, DE1__clk0, E1_data_out, , N1L156, , , , );
--N1L67 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[20]~1976
--operation mode is normal
N1L67 = BE1_q_a[20] & (N1_dbs_latent_8_reg_segment_2[4] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[20] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_2[4] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L68 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[20]~1977
--operation mode is normal
N1L68 = Q1_internal_incoming_ext_ram_bus_data[20] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L69 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[20]~1978
--operation mode is normal
N1L69 = N1L67 & N1L68 & (FB1_za_data[20] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--H1_slave_readdata_p1[14] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[14]
--operation mode is normal
H1_slave_readdata_p1[14]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[14];
H1_slave_readdata_p1[14] = DFFEAS(H1_slave_readdata_p1[14]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--N1_dbs_latent_8_reg_segment_2[3] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[3]
--operation mode is normal
N1_dbs_latent_8_reg_segment_2[3]_lut_out = Q1_internal_incoming_ext_ram_bus_data[3];
N1_dbs_latent_8_reg_segment_2[3] = DFFEAS(N1_dbs_latent_8_reg_segment_2[3]_lut_out, DE1__clk0, E1_data_out, , N1L156, , , , );
--N1L64 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[19]~1980
--operation mode is normal
N1L64 = BE1_q_a[19] & (N1_dbs_latent_8_reg_segment_2[3] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[19] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_2[3] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L65 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[19]~1981
--operation mode is normal
N1L65 = Q1_internal_incoming_ext_ram_bus_data[19] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L66 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[19]~1982
--operation mode is normal
N1L66 = N1L64 & N1L65 & (FB1_za_data[19] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--H1_slave_readdata_p1[13] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[13]
--operation mode is normal
H1_slave_readdata_p1[13]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[13];
H1_slave_readdata_p1[13] = DFFEAS(H1_slave_readdata_p1[13]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--N1_dbs_latent_8_reg_segment_2[2] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[2]
--operation mode is normal
N1_dbs_latent_8_reg_segment_2[2]_lut_out = Q1_internal_incoming_ext_ram_bus_data[2];
N1_dbs_latent_8_reg_segment_2[2] = DFFEAS(N1_dbs_latent_8_reg_segment_2[2]_lut_out, DE1__clk0, E1_data_out, , N1L156, , , , );
--N1L61 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[18]~1984
--operation mode is normal
N1L61 = BE1_q_a[18] & (N1_dbs_latent_8_reg_segment_2[2] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[18] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_2[2] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L62 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[18]~1985
--operation mode is normal
N1L62 = Q1_internal_incoming_ext_ram_bus_data[18] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L63 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[18]~1986
--operation mode is normal
N1L63 = N1L61 & N1L62 & (FB1_za_data[18] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--H1_slave_readdata_p1[12] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[12]
--operation mode is normal
H1_slave_readdata_p1[12]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[12];
H1_slave_readdata_p1[12] = DFFEAS(H1_slave_readdata_p1[12]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--N1_dbs_latent_8_reg_segment_2[1] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[1]
--operation mode is normal
N1_dbs_latent_8_reg_segment_2[1]_lut_out = Q1_internal_incoming_ext_ram_bus_data[1];
N1_dbs_latent_8_reg_segment_2[1] = DFFEAS(N1_dbs_latent_8_reg_segment_2[1]_lut_out, DE1__clk0, E1_data_out, , N1L156, , , , );
--N1L58 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[17]~1988
--operation mode is normal
N1L58 = BE1_q_a[17] & (N1_dbs_latent_8_reg_segment_2[1] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[17] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_2[1] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L59 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[17]~1989
--operation mode is normal
N1L59 = Q1_internal_incoming_ext_ram_bus_data[17] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L60 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[17]~1990
--operation mode is normal
N1L60 = N1L58 & N1L59 & (FB1_za_data[17] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--H1_slave_readdata_p1[11] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[11]
--operation mode is normal
H1_slave_readdata_p1[11]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[11];
H1_slave_readdata_p1[11] = DFFEAS(H1_slave_readdata_p1[11]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--T1L2 is std_1s10:inst|jtag_uart:the_jtag_uart|ac~73
--operation mode is normal
--H1_slave_readdata_p1[10] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[10]
--operation mode is normal
H1_slave_readdata_p1[10]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[10];
H1_slave_readdata_p1[10] = DFFEAS(H1_slave_readdata_p1[10]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--H1_slave_readdata_p1[9] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[9]
--operation mode is normal
H1_slave_readdata_p1[9]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[9];
H1_slave_readdata_p1[9] = DFFEAS(H1_slave_readdata_p1[9]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--H1_slave_readdata_p1[8] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[8]
--operation mode is normal
H1_slave_readdata_p1[8]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[8];
H1_slave_readdata_p1[8] = DFFEAS(H1_slave_readdata_p1[8]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--QD1_wdata[5] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[5]
--operation mode is normal
QD1_wdata[5] = AMPP_FUNCTION(!A1L6, QD1_td_shift[9], !C1_CLR_SIGNAL, QD1L74);
--H1_slave_readdata_p1[5] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[5]
--operation mode is normal
H1_slave_readdata_p1[5]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[5];
H1_slave_readdata_p1[5] = DFFEAS(H1_slave_readdata_p1[5]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--QD1_wdata[6] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[6]
--operation mode is normal
QD1_wdata[6] = AMPP_FUNCTION(!A1L6, QD1_td_shift[10], !C1_CLR_SIGNAL, QD1L74);
--H1_slave_readdata_p1[6] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[6]
--operation mode is normal
H1_slave_readdata_p1[6]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[6];
H1_slave_readdata_p1[6] = DFFEAS(H1_slave_readdata_p1[6]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--F1L24 is std_1s10:inst|button_pio:the_button_pio|read_mux_out[0]~380
--operation mode is normal
F1L24 = L1_M_alu_result[2] & F1_edge_capture[0] # !L1_M_alu_result[2] & (F1_irq_mask[0]);
--AE2_q_b[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE2_q_b[0]_PORT_A_data_in = QD1_wdata[0];
AE2_q_b[0]_PORT_A_data_in_reg = DFFE(AE2_q_b[0]_PORT_A_data_in, AE2_q_b[0]_clock_0, , , AE2_q_b[0]_clock_enable_0);
AE2_q_b[0]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[0]_PORT_A_address_reg = DFFE(AE2_q_b[0]_PORT_A_address, AE2_q_b[0]_clock_0, , , AE2_q_b[0]_clock_enable_0);
AE2_q_b[0]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[0]_PORT_B_address_reg = DFFE(AE2_q_b[0]_PORT_B_address, AE2_q_b[0]_clock_1, , , AE2_q_b[0]_clock_enable_1);
AE2_q_b[0]_PORT_A_write_enable = VCC;
AE2_q_b[0]_PORT_A_write_enable_reg = DFFE(AE2_q_b[0]_PORT_A_write_enable, AE2_q_b[0]_clock_0, , , AE2_q_b[0]_clock_enable_0);
AE2_q_b[0]_PORT_B_read_enable = VCC;
AE2_q_b[0]_PORT_B_read_enable_reg = DFFE(AE2_q_b[0]_PORT_B_read_enable, AE2_q_b[0]_clock_1, , , AE2_q_b[0]_clock_enable_1);
AE2_q_b[0]_clock_0 = DE1__clk0;
AE2_q_b[0]_clock_1 = DE1__clk0;
AE2_q_b[0]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[0]_clock_enable_1 = T1L61;
AE2_q_b[0]_PORT_B_data_out = MEMORY(AE2_q_b[0]_PORT_A_data_in_reg, , AE2_q_b[0]_PORT_A_address_reg, AE2_q_b[0]_PORT_B_address_reg, AE2_q_b[0]_PORT_A_write_enable_reg, AE2_q_b[0]_PORT_B_read_enable_reg, , , AE2_q_b[0]_clock_0, AE2_q_b[0]_clock_1, AE2_q_b[0]_clock_enable_0, AE2_q_b[0]_clock_enable_1, , );
AE2_q_b[0] = AE2_q_b[0]_PORT_B_data_out[0];
--M1L266 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[0]~2136
--operation mode is normal
M1L266 = T1_read_0 & AE2_q_b[0] # !T1_read_0 & (T1_ien_AF);
--H1_slave_readdata[0] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[0]
--operation mode is normal
H1_slave_readdata[0]_lut_out = H1_slave_readdata_p1[0];
H1_slave_readdata[0] = DFFEAS(H1_slave_readdata[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L267 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[0]~2137
--operation mode is normal
M1L267 = H1_slave_readdata[0] & (!FB1_za_data[0] & GB1L18) # !H1_slave_readdata[0] & (J1_cpu_data_master_requests_clock_0_in # !FB1_za_data[0] & GB1L18);
--HE1_control_reg[0] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[0]
--operation mode is normal
HE1_control_reg[0]_lut_out = L1_M_st_data[0];
HE1_control_reg[0] = DFFEAS(HE1_control_reg[0]_lut_out, DE1__clk0, E1_data_out, , HE1L13, , , , );
--JE1_rx_data[0] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[0]
--operation mode is normal
JE1_rx_data[0]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1];
JE1_rx_data[0] = DFFEAS(JE1_rx_data[0]_lut_out, DE1__clk0, E1_data_out, , JE1_got_new_char, , , , );
--HE1L48 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[0]~693
--operation mode is normal
HE1L48 = !L1_M_alu_result[3] & (L1_M_alu_result[2] & HE1_internal_tx_data[0] # !L1_M_alu_result[2] & (JE1_rx_data[0]));
--R1_counter_snapshot[16] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[16]
--operation mode is normal
R1_counter_snapshot[16]_lut_out = R1_internal_counter[16];
R1_counter_snapshot[16] = DFFEAS(R1_counter_snapshot[16]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L157 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[0]~1289
--operation mode is normal
R1L157 = HE1L15 & (R1_period_h_register[0] # HE1L18 & R1_counter_snapshot[16]) # !HE1L15 & HE1L18 & R1_counter_snapshot[16];
--R1L158 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[0]~1290
--operation mode is normal
R1L158 = R1_control_register[0] & (HE1L19 # R1_timeout_occurred & HE1L21) # !R1_control_register[0] & R1_timeout_occurred & HE1L21;
--R1_counter_snapshot[0] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[0]
--operation mode is normal
R1_counter_snapshot[0]_lut_out = !R1_internal_counter[0];
R1_counter_snapshot[0] = DFFEAS(R1_counter_snapshot[0]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L159 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[0]~1291
--operation mode is normal
R1L159 = HE1L17 & (R1_counter_snapshot[0] # HE1L20 & !R1_period_l_register[0]) # !HE1L17 & (HE1L20 & !R1_period_l_register[0]);
--KB1_counter_snapshot[16] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[16]
--operation mode is normal
KB1_counter_snapshot[16]_lut_out = !KB1_internal_counter[16];
KB1_counter_snapshot[16] = DFFEAS(KB1_counter_snapshot[16]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_period_h_register[0] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[0]
--operation mode is normal
KB1_period_h_register[0]_lut_out = !L1_M_st_data[0];
KB1_period_h_register[0] = DFFEAS(KB1_period_h_register[0]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1L158 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[0]~1278
--operation mode is normal
KB1L158 = HE1L18 & (KB1_counter_snapshot[16] # HE1L15 & !KB1_period_h_register[0]) # !HE1L18 & (HE1L15 & !KB1_period_h_register[0]);
--KB1L159 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[0]~1279
--operation mode is normal
KB1L159 = KB1_control_register[0] & (HE1L19 # KB1_timeout_occurred & HE1L21) # !KB1_control_register[0] & KB1_timeout_occurred & HE1L21;
--KB1_counter_snapshot[0] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[0]
--operation mode is normal
KB1_counter_snapshot[0]_lut_out = !KB1_internal_counter[0];
KB1_counter_snapshot[0] = DFFEAS(KB1_counter_snapshot[0]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_period_l_register[0] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[0]
--operation mode is normal
KB1_period_l_register[0]_lut_out = !L1_M_st_data[0];
KB1_period_l_register[0] = DFFEAS(KB1_period_l_register[0]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--KB1L160 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[0]~1280
--operation mode is normal
KB1L160 = HE1L17 & (KB1_counter_snapshot[0] # HE1L20 & !KB1_period_l_register[0]) # !HE1L17 & (HE1L20 & !KB1_period_l_register[0]);
--F1L25 is std_1s10:inst|button_pio:the_button_pio|read_mux_out[1]~382
--operation mode is normal
F1L25 = L1_M_alu_result[2] & F1_edge_capture[1] # !L1_M_alu_result[2] & (F1_irq_mask[1]);
--AE2_q_b[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE2_q_b[1]_PORT_A_data_in = QD1_wdata[1];
AE2_q_b[1]_PORT_A_data_in_reg = DFFE(AE2_q_b[1]_PORT_A_data_in, AE2_q_b[1]_clock_0, , , AE2_q_b[1]_clock_enable_0);
AE2_q_b[1]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[1]_PORT_A_address_reg = DFFE(AE2_q_b[1]_PORT_A_address, AE2_q_b[1]_clock_0, , , AE2_q_b[1]_clock_enable_0);
AE2_q_b[1]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[1]_PORT_B_address_reg = DFFE(AE2_q_b[1]_PORT_B_address, AE2_q_b[1]_clock_1, , , AE2_q_b[1]_clock_enable_1);
AE2_q_b[1]_PORT_A_write_enable = VCC;
AE2_q_b[1]_PORT_A_write_enable_reg = DFFE(AE2_q_b[1]_PORT_A_write_enable, AE2_q_b[1]_clock_0, , , AE2_q_b[1]_clock_enable_0);
AE2_q_b[1]_PORT_B_read_enable = VCC;
AE2_q_b[1]_PORT_B_read_enable_reg = DFFE(AE2_q_b[1]_PORT_B_read_enable, AE2_q_b[1]_clock_1, , , AE2_q_b[1]_clock_enable_1);
AE2_q_b[1]_clock_0 = DE1__clk0;
AE2_q_b[1]_clock_1 = DE1__clk0;
AE2_q_b[1]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[1]_clock_enable_1 = T1L61;
AE2_q_b[1]_PORT_B_data_out = MEMORY(AE2_q_b[1]_PORT_A_data_in_reg, , AE2_q_b[1]_PORT_A_address_reg, AE2_q_b[1]_PORT_B_address_reg, AE2_q_b[1]_PORT_A_write_enable_reg, AE2_q_b[1]_PORT_B_read_enable_reg, , , AE2_q_b[1]_clock_0, AE2_q_b[1]_clock_1, AE2_q_b[1]_clock_enable_0, AE2_q_b[1]_clock_enable_1, , );
AE2_q_b[1] = AE2_q_b[1]_PORT_B_data_out[0];
--M1L268 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[1]~2139
--operation mode is normal
M1L268 = T1_read_0 & AE2_q_b[1] # !T1_read_0 & (T1_ien_AE);
--H1_slave_readdata[1] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[1]
--operation mode is normal
H1_slave_readdata[1]_lut_out = H1_slave_readdata_p1[1];
H1_slave_readdata[1] = DFFEAS(H1_slave_readdata[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--M1L269 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[1]~2140
--operation mode is normal
M1L269 = H1_slave_readdata[1] & (!FB1_za_data[1] & GB1L18) # !H1_slave_readdata[1] & (J1_cpu_data_master_requests_clock_0_in # !FB1_za_data[1] & GB1L18);
--HE1L49 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[1]~695
--operation mode is normal
HE1L49 = L1_M_alu_result[3] & (HE1_control_reg[1]) # !L1_M_alu_result[3] & HE1_internal_tx_data[1];
--JE1_rx_data[1] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[1]
--operation mode is normal
JE1_rx_data[1]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2];
JE1_rx_data[1] = DFFEAS(JE1_rx_data[1]_lut_out, DE1__clk0, E1_data_out, , JE1_got_new_char, , , , );
--HE1L50 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[1]~696
--operation mode is normal
HE1L50 = L1_M_alu_result[3] & JE1_framing_error # !L1_M_alu_result[3] & (JE1_rx_data[1]);
--KB1_counter_snapshot[17] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[17]
--operation mode is normal
KB1_counter_snapshot[17]_lut_out = !KB1_internal_counter[17];
KB1_counter_snapshot[17] = DFFEAS(KB1_counter_snapshot[17]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_period_h_register[1] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[1]
--operation mode is normal
KB1_period_h_register[1]_lut_out = !L1_M_st_data[1];
KB1_period_h_register[1] = DFFEAS(KB1_period_h_register[1]_lut_out, DE1__clk0, E1_data_out, , KB1_period_h_wr_strobe, , , , );
--KB1L161 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[1]~1281
--operation mode is normal
KB1L161 = HE1L18 & (KB1_counter_snapshot[17] # HE1L15 & !KB1_period_h_register[1]) # !HE1L18 & (HE1L15 & !KB1_period_h_register[1]);
--KB1_counter_is_running is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_is_running
--operation mode is normal
KB1_counter_is_running_lut_out = KB1_control_wr_strobe & (L1_M_st_data[2] # KB1L10 & !L1_M_st_data[3]) # !KB1_control_wr_strobe & (KB1L10);
KB1_counter_is_running = DFFEAS(KB1_counter_is_running_lut_out, DE1__clk0, E1_data_out, , , , , , );
--KB1_control_register[1] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|control_register[1]
--operation mode is normal
KB1_control_register[1]_lut_out = L1_M_st_data[1];
KB1_control_register[1] = DFFEAS(KB1_control_register[1]_lut_out, DE1__clk0, E1_data_out, , KB1_control_wr_strobe, , , , );
--KB1L162 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[1]~1282
--operation mode is normal
KB1L162 = HE1L19 & (KB1_control_register[1] # HE1L21 & KB1_counter_is_running) # !HE1L19 & HE1L21 & KB1_counter_is_running;
--KB1_counter_snapshot[1] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[1]
--operation mode is normal
KB1_counter_snapshot[1]_lut_out = !KB1_internal_counter[1];
KB1_counter_snapshot[1] = DFFEAS(KB1_counter_snapshot[1]_lut_out, DE1__clk0, E1_data_out, , KB1L209, , , , );
--KB1_period_l_register[1] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[1]
--operation mode is normal
KB1_period_l_register[1]_lut_out = !L1_M_st_data[1];
KB1_period_l_register[1] = DFFEAS(KB1_period_l_register[1]_lut_out, DE1__clk0, E1_data_out, , KB1_period_l_wr_strobe, , , , );
--KB1L163 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[1]~1283
--operation mode is normal
KB1L163 = HE1L17 & (KB1_counter_snapshot[1] # HE1L20 & !KB1_period_l_register[1]) # !HE1L17 & (HE1L20 & !KB1_period_l_register[1]);
--R1_counter_snapshot[17] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[17]
--operation mode is normal
R1_counter_snapshot[17]_lut_out = R1_internal_counter[17];
R1_counter_snapshot[17] = DFFEAS(R1_counter_snapshot[17]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L160 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[1]~1292
--operation mode is normal
R1L160 = HE1L15 & (R1_period_h_register[1] # HE1L18 & R1_counter_snapshot[17]) # !HE1L15 & HE1L18 & R1_counter_snapshot[17];
--R1_control_register[1] is std_1s10:inst|high_res_timer:the_high_res_timer|control_register[1]
--operation mode is normal
R1_control_register[1]_lut_out = L1_M_st_data[1];
R1_control_register[1] = DFFEAS(R1_control_register[1]_lut_out, DE1__clk0, E1_data_out, , R1_control_wr_strobe, , , , );
--R1L161 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[1]~1293
--operation mode is normal
R1L161 = HE1L19 & (R1_control_register[1] # HE1L21 & R1_counter_is_running) # !HE1L19 & HE1L21 & R1_counter_is_running;
--R1_counter_snapshot[1] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[1]
--operation mode is normal
R1_counter_snapshot[1]_lut_out = !R1_internal_counter[1];
R1_counter_snapshot[1] = DFFEAS(R1_counter_snapshot[1]_lut_out, DE1__clk0, E1_data_out, , R1L208, , , , );
--R1L162 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[1]~1294
--operation mode is normal
R1L162 = HE1L17 & (R1_counter_snapshot[1] # HE1L20 & !R1_period_l_register[1]) # !HE1L17 & (HE1L20 & !R1_period_l_register[1]);
--KE1L29 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|process4~0
--operation mode is normal
KE1L29 = KE1_do_load_shifter # KE1L21 & KE1L22 & !KE1_baud_rate_counter[8];
--NE1L12 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux1~63
--operation mode is normal
NE1L12 = AMPP_FUNCTION(NE1_word_counter[0], NE1_word_counter[1], NE1_word_counter[4], NE1_word_counter[3]);
--NE1L13 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux1~64
--operation mode is normal
NE1L13 = AMPP_FUNCTION(NE1_word_counter[4], NE1_word_counter[1], NE1_word_counter[0], NE1_word_counter[3]);
--NE1_WORD_SR[3] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3]
--operation mode is normal
NE1_WORD_SR[3] = AMPP_FUNCTION(!A1L6, NE1L14, RE1_state[4], altera_internal_jtag, NE1_clear_signal, VCC, NE1L20);
--QD1L19 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena~1
--operation mode is normal
QD1L19 = AMPP_FUNCTION(QD1_rvalid0, T1_r_val, QD1_r_ena1);
--QD1_read_req is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_req
--operation mode is normal
QD1_read_req = AMPP_FUNCTION(!A1L6, QD1_td_shift[9], !C1_CLR_SIGNAL, QD1L72);
--QD1L72 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[0]~7
--operation mode is normal
QD1L72 = AMPP_FUNCTION(QD1_count[1], QD1L69);
--QD1_rdata[0] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[0]
--operation mode is normal
QD1_rdata[0] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[0], E1_data_out, QD1L18);
--QD1_td_shift[3] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[3]
--operation mode is normal
QD1_td_shift[3] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1L57, ME4_Q[0], QD1L62, !C1_CLR_SIGNAL, QD1L52);
--QD1L56 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3503
--operation mode is normal
QD1L56 = AMPP_FUNCTION(QD1_rdata[0], QD1_td_shift[3], QD1_count[9]);
--QD1_count[7] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[7]
--operation mode is normal
QD1_count[7] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1_count[6], !C1_CLR_SIGNAL, QD1L52);
--AE1_q_b[7] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[7]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE1_q_b[7]_PORT_A_data_in = L1_M_st_data[7];
AE1_q_b[7]_PORT_A_data_in_reg = DFFE(AE1_q_b[7]_PORT_A_data_in, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[7]_PORT_A_address_reg = DFFE(AE1_q_b[7]_PORT_A_address, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[7]_PORT_B_address_reg = DFFE(AE1_q_b[7]_PORT_B_address, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_PORT_A_write_enable = VCC;
AE1_q_b[7]_PORT_A_write_enable_reg = DFFE(AE1_q_b[7]_PORT_A_write_enable, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_read_enable = VCC;
AE1_q_b[7]_PORT_B_read_enable_reg = DFFE(AE1_q_b[7]_PORT_B_read_enable, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_clock_0 = DE1__clk0;
AE1_q_b[7]_clock_1 = DE1__clk0;
AE1_q_b[7]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[7]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[7]_PORT_B_data_out = MEMORY(AE1_q_b[7]_PORT_A_data_in_reg, , AE1_q_b[7]_PORT_A_address_reg, AE1_q_b[7]_PORT_B_address_reg, AE1_q_b[7]_PORT_A_write_enable_reg, AE1_q_b[7]_PORT_B_read_enable_reg, , , AE1_q_b[7]_clock_0, AE1_q_b[7]_clock_1, AE1_q_b[7]_clock_enable_0, AE1_q_b[7]_clock_enable_1, , );
AE1_q_b[7] = AE1_q_b[7]_PORT_B_data_out[0];
--QD1L18 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena~0
--operation mode is normal
QD1L18 = AMPP_FUNCTION(T1_r_val, QD1_r_ena1);
--DD1_internal_jdo1[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[0]
--operation mode is normal
DD1_internal_jdo1[0] = AMPP_FUNCTION(!A1L9, DD1_sr[0], VCC, DD1L144);
--TC1_break_readreg[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[1]
--operation mode is normal
TC1_break_readreg[1] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[1], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L129 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux38~14
--operation mode is normal
DD1L129 = AMPP_FUNCTION(CD1_internal_MonDReg[1], DD1_ir[1], TC1_break_readreg[1], DD1_ir[0]);
--DD1_sr[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[3]
--operation mode is normal
DD1_sr[3] = AMPP_FUNCTION(!A1L6, DD1L128, DD1_sr[4], DD1L143, DD1L141, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[25] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[25]
--operation mode is normal
DD1_sr[25] = AMPP_FUNCTION(!A1L6, DD1L70, DD1_sr[26], DD1L35, DD1L34, !C1_CLR_SIGNAL, DD1L12);
--L1L218 is std_1s10:inst|cpu:the_cpu|D_ctrl_jmp_indirect~36
--operation mode is normal
L1L218 = AMPP_FUNCTION(L1_D_iw[11], L1_D_iw[16]);
--GE1_stage_4 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_4
--operation mode is normal
GE1_stage_4_lut_out = GE1_full_5 & GE1_stage_5 # !GE1_full_5 & (GB1L19);
GE1_stage_4 = DFFEAS(GE1_stage_4_lut_out, DE1__clk0, VCC, , GE1L22, , , , );
--GE1_full_4 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_4
--operation mode is normal
GE1_full_4_lut_out = FB1_za_valid & (GB1L28 & GE1_full_3 # !GB1L28 & (GE1_full_5)) # !FB1_za_valid & GE1_full_3;
GE1_full_4 = DFFEAS(GE1_full_4_lut_out, DE1__clk0, E1_data_out, , FE1L13, , , , );
--GE1L23 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process6~1
--operation mode is normal
GE1L23 = FB1_za_valid # GB1L28 & (!GE1_full_3);
--FE1_stage_4 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_4
--operation mode is normal
FE1_stage_4_lut_out = GE1_full_5 & FE1_stage_5 # !GE1_full_5 & (GB1L14);
FE1_stage_4 = DFFEAS(FE1_stage_4_lut_out, DE1__clk0, VCC, , GE1L22, , , , );
--XB3_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_request_edge_to_pulse|data_in_d1
--operation mode is normal
XB3_data_in_d1_lut_out = TB1_data_out;
XB3_data_in_d1 = DFFEAS(XB3_data_in_d1_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--TB1_data_out is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_out
--operation mode is normal
TB1_data_out_lut_out = TB1_data_in_d1;
TB1_data_out = DFFEAS(TB1_data_out_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--WB1L10 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux1~124
--operation mode is normal
WB1L10 = !WB1_master_state[1] & !WB1_master_state[0] & (XB3_data_in_d1 $ TB1_data_out);
--XB4_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_request_edge_to_pulse|data_in_d1
--operation mode is normal
XB4_data_in_d1_lut_out = UB1_data_out;
XB4_data_in_d1 = DFFEAS(XB4_data_in_d1_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--UB1_data_out is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_out
--operation mode is normal
UB1_data_out_lut_out = UB1_data_in_d1;
UB1_data_out = DFFEAS(UB1_data_out_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--WB1L9 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux0~176
--operation mode is normal
WB1L9 = WB1_master_state[2] # WB1_master_state[1] # XB3_data_in_d1 $ TB1_data_out;
--WB1L11 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux2~236
--operation mode is normal
WB1L11 = WB1_master_state[2] # WB1_master_state[1] & (CB1_d1_reasons_to_wait # !WB1_master_state[0]);
--WB1L12 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux2~237
--operation mode is normal
WB1L12 = XB3_data_in_d1 & TB1_data_out & (XB4_data_in_d1 $ !UB1_data_out) # !XB3_data_in_d1 & !TB1_data_out & (XB4_data_in_d1 $ !UB1_data_out);
--D1_data_in_d1 is std_1s10:inst|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch|data_in_d1
--operation mode is normal
D1_data_in_d1_lut_out = VCC;
D1_data_in_d1 = DFFEAS(D1_data_in_d1_lut_out, PLD_CLOCKINPUT, !B1L1, , , , , , );
--TC1_break_readreg[22] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[22]
--operation mode is normal
TC1_break_readreg[22] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[22], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L31 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19924
--operation mode is normal
DD1L31 = AMPP_FUNCTION(TC1_break_readreg[22], CD1_internal_MonDReg[22], DD1_ir[1]);
--DD1L32 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19925
--operation mode is normal
DD1L32 = AMPP_FUNCTION(DD1L144, DD1L142, DD1L31, DD1_ir[0]);
--DD1_sr[24] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[24]
--operation mode is normal
DD1_sr[24] = AMPP_FUNCTION(!A1L6, DD1L37, DD1_sr[25], DD1L9, DD1L38, !C1_CLR_SIGNAL, DD1L12);
--DD1L33 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19926
--operation mode is normal
DD1L33 = AMPP_FUNCTION(DD1L31, DD1L144, A1L5, DD1_ir[0]);
--WD1L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~141
--operation mode is normal
WD1L6 = ZD1_safe_q[2] # ZD1_safe_q[1] # ZD1_safe_q[5] # ZD1_safe_q[4];
--WD1L7 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~142
--operation mode is normal
WD1L7 = ZD1_safe_q[3] # WD1L6 # !T1_rd_wfifo # !ZD1_safe_q[0];
--QD1_read_write is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write
--operation mode is normal
QD1_read_write = AMPP_FUNCTION(!A1L6, QD1_read_write, !C1_CLR_SIGNAL, QD1L74);
--QD1_jupdate is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate
--operation mode is normal
QD1_jupdate = AMPP_FUNCTION(A1L6, QD1_jupdate, ME4_Q[0], RE1_state[8], QD1L1, !C1_CLR_SIGNAL);
--N1L155 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process3~0
--operation mode is normal
N1L155 = N1_cpu_instruction_master_dbs_rdv_counter[0] & Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!N1_cpu_instruction_master_dbs_rdv_counter[1]);
--KB1_force_reload is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|force_reload
--operation mode is normal
KB1_force_reload_lut_out = KB1L7 & NB1L3 & LB1L2 & LB1L3;
KB1_force_reload = DFFEAS(KB1_force_reload_lut_out, DE1__clk0, E1_data_out, , , , , , );
--KB1L157 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|process0~1
--operation mode is normal
KB1L157 = KB1_force_reload # KB1L49 & KB1L54;
--KB1L156 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|process0~0
--operation mode is normal
KB1L156 = KB1_counter_is_running # KB1_force_reload;
--N1L154 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process2~0
--operation mode is normal
N1L154 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!N1_cpu_instruction_master_dbs_rdv_counter[1] & !N1_cpu_instruction_master_dbs_rdv_counter[0]);
--QD1_td_shift[6] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[6]
--operation mode is normal
QD1_td_shift[6] = AMPP_FUNCTION(!A1L6, QD1L53, QD1L63, QD1L58, !C1_CLR_SIGNAL, QD1L52);
--QD1L74 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[1]~6
--operation mode is normal
QD1L74 = AMPP_FUNCTION(QD1_count[8], QD1L69);
--H1_master_nativeaddress[0] is std_1s10:inst|clock_0:the_clock_0|master_nativeaddress[0]
--operation mode is normal
H1_master_nativeaddress[0]_lut_out = H1_slave_nativeaddress_d1[0];
H1_master_nativeaddress[0] = DFFEAS(H1_master_nativeaddress[0]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--BB1_control_reg_out[2] is std_1s10:inst|pll:the_pll|control_reg_out[2]
--operation mode is normal
BB1_control_reg_out[2]_lut_out = H1_master_writedata[2];
BB1_control_reg_out[2] = DFFEAS(BB1_control_reg_out[2]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--H1L22 is std_1s10:inst|clock_0:the_clock_0|process0~9
--operation mode is normal
H1L22 = WB1_master_state[1] & CB1_d1_reasons_to_wait;
--JE1_do_start_rx is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|do_start_rx
--operation mode is normal
JE1_do_start_rx_lut_out = JE1_delayed_unxsync_rxdxx2 & (!JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] & !JE1_sync_rxd);
JE1_do_start_rx = DFFEAS(JE1_do_start_rx_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1_baud_clk_en is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_clk_en
--operation mode is normal
JE1_baud_clk_en_lut_out = JE1L35 & JE1L36 & !JE1_rxd_edge & !JE1_baud_rate_counter[8];
JE1_baud_clk_en = DFFEAS(JE1_baud_clk_en_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1L62 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]~7381
--operation mode is normal
JE1L62 = JE1_do_start_rx # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] & JE1_baud_clk_en;
--JE1_sync_rxd is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|sync_rxd
--operation mode is normal
JE1_sync_rxd_lut_out = JE1_d1_source_rxd;
JE1_sync_rxd = DFFEAS(JE1_sync_rxd_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1L1 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|A_WE_StdLogicVector~22
--operation mode is normal
JE1L1 = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] & JE1_baud_clk_en;
--CD1L18 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~148
--operation mode is normal
CD1L18 = AMPP_FUNCTION(CD1_MonAReg[10], CD1L17);
--CD1L81 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1152
--operation mode is normal
CD1L81 = AMPP_FUNCTION(CD1L18, CD1_MonAReg[10], DD1L191);
--CD1_MonRd is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonRd
--operation mode is normal
CD1_MonRd = AMPP_FUNCTION(DE1__clk0, DD1L189, CD1_MonRd, DD1L191, CD1L84, !C1_CLR_SIGNAL);
--DD1_sr[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[4]
--operation mode is normal
DD1_sr[4] = AMPP_FUNCTION(!A1L6, DD1L127, DD1_sr[5], DD1L143, DD1L141, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[5]
--operation mode is normal
DD1_sr[5] = AMPP_FUNCTION(!A1L6, DD1L126, DD1_sr[6], DD1L143, DD1L141, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[6] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[6]
--operation mode is normal
DD1_sr[6] = AMPP_FUNCTION(!A1L6, DD1_sr[7], DD1L125, DD1L141, DD1L143, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[7] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[7]
--operation mode is normal
DD1_sr[7] = AMPP_FUNCTION(!A1L6, DD1_sr[8], altera_internal_jtag, DD1L124, DD1L138, !C1_CLR_SIGNAL, DD1L143, DD1L6);
--DD1_sr[8] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[8]
--operation mode is normal
DD1_sr[8] = AMPP_FUNCTION(!A1L6, DD1L123, DD1_sr[9], DD1L143, DD1L141, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[9] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[9]
--operation mode is normal
DD1_sr[9] = AMPP_FUNCTION(!A1L6, DD1L39, DD1_sr[10], DD1L143, DD1L141, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[10] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[10]
--operation mode is normal
DD1_sr[10] = AMPP_FUNCTION(!A1L6, DD1L40, DD1_sr[11], DD1L143, DD1L141, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[26] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[26]
--operation mode is normal
DD1_sr[26] = AMPP_FUNCTION(!A1L6, DD1L42, DD1_sr[27], DD1L9, DD1L43, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[27] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[27]
--operation mode is normal
DD1_sr[27] = AMPP_FUNCTION(!A1L6, DD1L45, DD1_sr[28], DD1L9, DD1L46, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[28] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[28]
--operation mode is normal
DD1_sr[28] = AMPP_FUNCTION(!A1L6, DD1L70, DD1_sr[29], DD1L48, DD1L47, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[29] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[29]
--operation mode is normal
DD1_sr[29] = AMPP_FUNCTION(!A1L6, DD1L50, DD1_sr[30], DD1L9, DD1L51, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[30] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[30]
--operation mode is normal
DD1_sr[30] = AMPP_FUNCTION(!A1L6, DD1_sr[31], DD1L70, DD1L52, DD1L53, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[31] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[31]
--operation mode is normal
DD1_sr[31] = AMPP_FUNCTION(!A1L6, DD1L54, DD1L136, DD1L71, DD1_ir[1], !C1_CLR_SIGNAL, !DD1_ir[0], DD1L12);
--DD1_sr[32] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[32]
--operation mode is normal
DD1_sr[32] = AMPP_FUNCTION(!A1L6, DD1L57, DD1_sr[33], DD1L9, DD1L58, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[33] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[33]
--operation mode is normal
DD1_sr[33] = AMPP_FUNCTION(!A1L6, DD1_sr[34], DD1L59, DD1L141, DD1L17, !C1_CLR_SIGNAL, DD1L12);
--N1L156 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process4~0
--operation mode is normal
N1L156 = N1_cpu_instruction_master_dbs_rdv_counter[1] & Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (!N1_cpu_instruction_master_dbs_rdv_counter[0]);
--QD1_td_shift[7] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[7]
--operation mode is normal
QD1_td_shift[7] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1L59, ME4_Q[0], QD1L62, !C1_CLR_SIGNAL, QD1L52);
--BB1_control_reg_out[3] is std_1s10:inst|pll:the_pll|control_reg_out[3]
--operation mode is normal
BB1_control_reg_out[3]_lut_out = H1_master_writedata[3];
BB1_control_reg_out[3] = DFFEAS(BB1_control_reg_out[3]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--BB1_control_reg_out[7] is std_1s10:inst|pll:the_pll|control_reg_out[7]
--operation mode is normal
BB1_control_reg_out[7]_lut_out = H1_master_writedata[7];
BB1_control_reg_out[7] = DFFEAS(BB1_control_reg_out[7]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--GC1L9 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~567
--operation mode is arithmetic
GC1L9 = AMPP_FUNCTION(L1L612, L1L678, GC1L11);
--RE1_state[13] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[13]
--operation mode is normal
RE1_state[13] = AMPP_FUNCTION(!A1L6, RE1_state[12], RE1_state[13], VCC, !A1L8);
--R1L8 is std_1s10:inst|high_res_timer:the_high_res_timer|counter_is_running~91
--operation mode is normal
R1L8 = R1_counter_is_running & (!R1_force_reload);
--R1L9 is std_1s10:inst|high_res_timer:the_high_res_timer|counter_is_running~92
--operation mode is normal
R1L9 = R1L8 & (R1_control_register[1] # !R1L53 # !R1L48);
--QD1_td_shift[8] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[8]
--operation mode is normal
QD1_td_shift[8] = AMPP_FUNCTION(!A1L6, QD1_td_shift[9], QD1_rdata[6], QD1_count[9], !C1_CLR_SIGNAL, !RE1_state[4], QD1L52);
--BB1_control_reg_out[4] is std_1s10:inst|pll:the_pll|control_reg_out[4]
--operation mode is normal
BB1_control_reg_out[4]_lut_out = H1_master_writedata[4];
BB1_control_reg_out[4] = DFFEAS(BB1_control_reg_out[4]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--BB1_control_reg_out[15] is std_1s10:inst|pll:the_pll|control_reg_out[15]
--operation mode is normal
BB1_control_reg_out[15]_lut_out = H1_master_writedata[15];
BB1_control_reg_out[15] = DFFEAS(BB1_control_reg_out[15]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--DD1_sr[11] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[11]
--operation mode is normal
DD1_sr[11] = AMPP_FUNCTION(!A1L6, DD1L60, DD1_sr[12], DD1L143, DD1L141, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[12] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[12]
--operation mode is normal
DD1_sr[12] = AMPP_FUNCTION(!A1L6, DD1L61, DD1_sr[13], DD1L143, DD1L141, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[13] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[13]
--operation mode is normal
DD1_sr[13] = AMPP_FUNCTION(!A1L6, DD1L62, DD1_sr[14], DD1L143, DD1L141, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[14] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[14]
--operation mode is normal
DD1_sr[14] = AMPP_FUNCTION(!A1L6, DD1_sr[15], DD1L63, DD1L141, DD1L143, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[15] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[15]
--operation mode is normal
DD1_sr[15] = AMPP_FUNCTION(!A1L6, DD1_sr[16], altera_internal_jtag, DD1L122, DD1L137, !C1_CLR_SIGNAL, DD1L143, DD1L6);
--DD1_sr[16] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[16]
--operation mode is normal
DD1_sr[16] = AMPP_FUNCTION(!A1L6, DD1L65, DD1_sr[17], DD1L9, DD1L66, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[17] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[17]
--operation mode is normal
DD1_sr[17] = AMPP_FUNCTION(!A1L6, DD1L68, DD1_sr[18], DD1L9, DD1L69, !C1_CLR_SIGNAL, DD1L12);
--BB1_control_reg_out[14] is std_1s10:inst|pll:the_pll|control_reg_out[14]
--operation mode is normal
BB1_control_reg_out[14]_lut_out = H1_master_writedata[14];
BB1_control_reg_out[14] = DFFEAS(BB1_control_reg_out[14]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--BB1_control_reg_out[13] is std_1s10:inst|pll:the_pll|control_reg_out[13]
--operation mode is normal
BB1_control_reg_out[13]_lut_out = H1_master_writedata[13];
BB1_control_reg_out[13] = DFFEAS(BB1_control_reg_out[13]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--BB1_control_reg_out[12] is std_1s10:inst|pll:the_pll|control_reg_out[12]
--operation mode is normal
BB1_control_reg_out[12]_lut_out = H1_master_writedata[12];
BB1_control_reg_out[12] = DFFEAS(BB1_control_reg_out[12]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--BB1_control_reg_out[11] is std_1s10:inst|pll:the_pll|control_reg_out[11]
--operation mode is normal
BB1_control_reg_out[11]_lut_out = H1_master_writedata[11];
BB1_control_reg_out[11] = DFFEAS(BB1_control_reg_out[11]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--BB1_control_reg_out[10] is std_1s10:inst|pll:the_pll|control_reg_out[10]
--operation mode is normal
BB1_control_reg_out[10]_lut_out = H1_master_writedata[10];
BB1_control_reg_out[10] = DFFEAS(BB1_control_reg_out[10]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--BB1_control_reg_out[9] is std_1s10:inst|pll:the_pll|control_reg_out[9]
--operation mode is normal
BB1_control_reg_out[9]_lut_out = H1_master_writedata[9];
BB1_control_reg_out[9] = DFFEAS(BB1_control_reg_out[9]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--BB1_control_reg_out[8] is std_1s10:inst|pll:the_pll|control_reg_out[8]
--operation mode is normal
BB1_control_reg_out[8]_lut_out = H1_master_writedata[8];
BB1_control_reg_out[8] = DFFEAS(BB1_control_reg_out[8]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--BB1_control_reg_out[5] is std_1s10:inst|pll:the_pll|control_reg_out[5]
--operation mode is normal
BB1_control_reg_out[5]_lut_out = H1_master_writedata[5];
BB1_control_reg_out[5] = DFFEAS(BB1_control_reg_out[5]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--BB1_control_reg_out[6] is std_1s10:inst|pll:the_pll|control_reg_out[6]
--operation mode is normal
BB1_control_reg_out[6]_lut_out = H1_master_writedata[6];
BB1_control_reg_out[6] = DFFEAS(BB1_control_reg_out[6]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--QD1_wdata[0] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[0]
--operation mode is normal
QD1_wdata[0] = AMPP_FUNCTION(!A1L6, altera_internal_jtag, !C1_CLR_SIGNAL, QD1L72);
--H1_slave_readdata_p1[0] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[0]
--operation mode is normal
H1_slave_readdata_p1[0]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[0];
H1_slave_readdata_p1[0] = DFFEAS(H1_slave_readdata_p1[0]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--QD1_wdata[1] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[1]
--operation mode is normal
QD1_wdata[1] = AMPP_FUNCTION(!A1L6, QD1_td_shift[5], !C1_CLR_SIGNAL, QD1L74);
--H1_slave_readdata_p1[1] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[1]
--operation mode is normal
H1_slave_readdata_p1[1]_lut_out = !BB1_control_reg_out[1] & (H1_master_nativeaddress[0]);
H1_slave_readdata_p1[1] = DFFEAS(H1_slave_readdata_p1[1]_lut_out, PLD_CLOCKINPUT, D1_data_out, , H1L22, , , , );
--KB1L9 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_is_running~91
--operation mode is normal
KB1L9 = KB1_counter_is_running & (!KB1_force_reload);
--KB1L10 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_is_running~92
--operation mode is normal
KB1L10 = KB1L9 & (KB1_control_register[1] # !KB1L54 # !KB1L49);
--NE1L14 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux1~65
--operation mode is normal
NE1L14 = AMPP_FUNCTION(NE1_word_counter[1], NE1_word_counter[0], NE1_word_counter[3]);
--AE1_q_b[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[0]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE1_q_b[0]_PORT_A_data_in = L1_M_st_data[0];
AE1_q_b[0]_PORT_A_data_in_reg = DFFE(AE1_q_b[0]_PORT_A_data_in, AE1_q_b[0]_clock_0, , , AE1_q_b[0]_clock_enable_0);
AE1_q_b[0]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[0]_PORT_A_address_reg = DFFE(AE1_q_b[0]_PORT_A_address, AE1_q_b[0]_clock_0, , , AE1_q_b[0]_clock_enable_0);
AE1_q_b[0]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[0]_PORT_B_address_reg = DFFE(AE1_q_b[0]_PORT_B_address, AE1_q_b[0]_clock_1, , , AE1_q_b[0]_clock_enable_1);
AE1_q_b[0]_PORT_A_write_enable = VCC;
AE1_q_b[0]_PORT_A_write_enable_reg = DFFE(AE1_q_b[0]_PORT_A_write_enable, AE1_q_b[0]_clock_0, , , AE1_q_b[0]_clock_enable_0);
AE1_q_b[0]_PORT_B_read_enable = VCC;
AE1_q_b[0]_PORT_B_read_enable_reg = DFFE(AE1_q_b[0]_PORT_B_read_enable, AE1_q_b[0]_clock_1, , , AE1_q_b[0]_clock_enable_1);
AE1_q_b[0]_clock_0 = DE1__clk0;
AE1_q_b[0]_clock_1 = DE1__clk0;
AE1_q_b[0]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[0]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[0]_PORT_B_data_out = MEMORY(AE1_q_b[0]_PORT_A_data_in_reg, , AE1_q_b[0]_PORT_A_address_reg, AE1_q_b[0]_PORT_B_address_reg, AE1_q_b[0]_PORT_A_write_enable_reg, AE1_q_b[0]_PORT_B_read_enable_reg, , , AE1_q_b[0]_clock_0, AE1_q_b[0]_clock_1, AE1_q_b[0]_clock_enable_0, AE1_q_b[0]_clock_enable_1, , );
AE1_q_b[0] = AE1_q_b[0]_PORT_B_data_out[0];
--QD1_rdata[1] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[1]
--operation mode is normal
QD1_rdata[1] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[1], E1_data_out, QD1L18);
--QD1_td_shift[4] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[4]
--operation mode is normal
QD1_td_shift[4] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1L60, ME4_Q[0], QD1L62, !C1_CLR_SIGNAL, QD1L52);
--QD1L57 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3507
--operation mode is normal
QD1L57 = AMPP_FUNCTION(QD1_rdata[1], QD1_td_shift[4], QD1_count[9]);
--QD1_count[6] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[6]
--operation mode is normal
QD1_count[6] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1_count[5], !C1_CLR_SIGNAL, QD1L52);
--YD2_safe_q[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[0]
--operation mode is arithmetic
YD2_safe_q[0]_lut_out = YD2_safe_q[0] $ T1_fifo_wr;
YD2_safe_q[0] = DFFEAS(YD2_safe_q[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD2L2 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella0~COUT
--operation mode is arithmetic
YD2L2 = CARRY(YD2_safe_q[0]);
--YD2_safe_q[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[1]
--operation mode is arithmetic
YD2_safe_q[1]_carry_eqn = YD2L2;
YD2_safe_q[1]_lut_out = YD2_safe_q[1] $ (T1_fifo_wr & YD2_safe_q[1]_carry_eqn);
YD2_safe_q[1] = DFFEAS(YD2_safe_q[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD2L4 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella1~COUT
--operation mode is arithmetic
YD2L4 = CARRY(!YD2L2 # !YD2_safe_q[1]);
--YD2_safe_q[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[2]
--operation mode is arithmetic
YD2_safe_q[2]_carry_eqn = YD2L4;
YD2_safe_q[2]_lut_out = YD2_safe_q[2] $ (T1_fifo_wr & !YD2_safe_q[2]_carry_eqn);
YD2_safe_q[2] = DFFEAS(YD2_safe_q[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD2L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella2~COUT
--operation mode is arithmetic
YD2L6 = CARRY(YD2_safe_q[2] & (!YD2L4));
--YD2_safe_q[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[3]
--operation mode is arithmetic
YD2_safe_q[3]_carry_eqn = YD2L6;
YD2_safe_q[3]_lut_out = YD2_safe_q[3] $ (T1_fifo_wr & YD2_safe_q[3]_carry_eqn);
YD2_safe_q[3] = DFFEAS(YD2_safe_q[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD2L8 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella3~COUT
--operation mode is arithmetic
YD2L8 = CARRY(!YD2L6 # !YD2_safe_q[3]);
--YD2_safe_q[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[4]
--operation mode is arithmetic
YD2_safe_q[4]_carry_eqn = YD2L8;
YD2_safe_q[4]_lut_out = YD2_safe_q[4] $ (T1_fifo_wr & !YD2_safe_q[4]_carry_eqn);
YD2_safe_q[4] = DFFEAS(YD2_safe_q[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD2L10 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella4~COUT
--operation mode is arithmetic
YD2L10 = CARRY(YD2_safe_q[4] & (!YD2L8));
--YD2_safe_q[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[5]
--operation mode is normal
YD2_safe_q[5]_carry_eqn = YD2L10;
YD2_safe_q[5]_lut_out = YD2_safe_q[5] $ (T1_fifo_wr & YD2_safe_q[5]_carry_eqn);
YD2_safe_q[5] = DFFEAS(YD2_safe_q[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD1_safe_q[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[0]
--operation mode is arithmetic
YD1_safe_q[0]_lut_out = YD1_safe_q[0] $ T1_rd_wfifo;
YD1_safe_q[0] = DFFEAS(YD1_safe_q[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD1L2 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella0~COUT
--operation mode is arithmetic
YD1L2 = CARRY(YD1_safe_q[0]);
--YD1_safe_q[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[1]
--operation mode is arithmetic
YD1_safe_q[1]_carry_eqn = YD1L2;
YD1_safe_q[1]_lut_out = YD1_safe_q[1] $ (T1_rd_wfifo & YD1_safe_q[1]_carry_eqn);
YD1_safe_q[1] = DFFEAS(YD1_safe_q[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD1L4 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella1~COUT
--operation mode is arithmetic
YD1L4 = CARRY(!YD1L2 # !YD1_safe_q[1]);
--YD1_safe_q[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[2]
--operation mode is arithmetic
YD1_safe_q[2]_carry_eqn = YD1L4;
YD1_safe_q[2]_lut_out = YD1_safe_q[2] $ (T1_rd_wfifo & !YD1_safe_q[2]_carry_eqn);
YD1_safe_q[2] = DFFEAS(YD1_safe_q[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD1L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella2~COUT
--operation mode is arithmetic
YD1L6 = CARRY(YD1_safe_q[2] & (!YD1L4));
--YD1_safe_q[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[3]
--operation mode is arithmetic
YD1_safe_q[3]_carry_eqn = YD1L6;
YD1_safe_q[3]_lut_out = YD1_safe_q[3] $ (T1_rd_wfifo & YD1_safe_q[3]_carry_eqn);
YD1_safe_q[3] = DFFEAS(YD1_safe_q[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD1L8 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella3~COUT
--operation mode is arithmetic
YD1L8 = CARRY(!YD1L6 # !YD1_safe_q[3]);
--YD1_safe_q[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[4]
--operation mode is arithmetic
YD1_safe_q[4]_carry_eqn = YD1L8;
YD1_safe_q[4]_lut_out = YD1_safe_q[4] $ (T1_rd_wfifo & !YD1_safe_q[4]_carry_eqn);
YD1_safe_q[4] = DFFEAS(YD1_safe_q[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YD1L10 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella4~COUT
--operation mode is arithmetic
YD1L10 = CARRY(YD1_safe_q[4] & (!YD1L8));
--YD1_safe_q[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[5]
--operation mode is normal
YD1_safe_q[5]_carry_eqn = YD1L10;
YD1_safe_q[5]_lut_out = YD1_safe_q[5] $ (T1_rd_wfifo & YD1_safe_q[5]_carry_eqn);
YD1_safe_q[5] = DFFEAS(YD1_safe_q[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--DD1_internal_jdo1[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[1]
--operation mode is normal
DD1_internal_jdo1[1] = AMPP_FUNCTION(!A1L9, DD1_sr[1], VCC, DD1L144);
--TC1_break_readreg[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[2]
--operation mode is normal
TC1_break_readreg[2] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[2], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L128 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux37~14
--operation mode is normal
DD1L128 = AMPP_FUNCTION(CD1_internal_MonDReg[2], DD1_ir[1], TC1_break_readreg[2], DD1_ir[0]);
--TC1_break_readreg[24] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[24]
--operation mode is normal
TC1_break_readreg[24] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[24], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L34 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19930
--operation mode is normal
DD1L34 = AMPP_FUNCTION(TC1_break_readreg[24], CD1_internal_MonDReg[24], DD1_ir[1]);
--DD1L35 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19931
--operation mode is normal
DD1L35 = AMPP_FUNCTION(DD1L143, DD1_ir[1], DD1L34, DD1_ir[0]);
--GE1_stage_5 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_5
--operation mode is normal
GE1_stage_5_lut_out = GE1_full_6 & GE1_stage_6 # !GE1_full_6 & (GB1L19);
GE1_stage_5 = DFFEAS(GE1_stage_5_lut_out, DE1__clk0, VCC, , GE1L21, , , , );
--GE1_full_5 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_5
--operation mode is normal
GE1_full_5_lut_out = FB1_za_valid & (GB1L28 & GE1_full_4 # !GB1L28 & (GE1_full_6)) # !FB1_za_valid & GE1_full_4;
GE1_full_5 = DFFEAS(GE1_full_5_lut_out, DE1__clk0, E1_data_out, , FE1L13, , , , );
--GE1L22 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process4~1
--operation mode is normal
GE1L22 = FB1_za_valid # GB1L28 & (!GE1_full_4);
--FE1_stage_5 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_5
--operation mode is normal
FE1_stage_5_lut_out = GE1_full_6 & FE1_stage_6 # !GE1_full_6 & (GB1L14);
FE1_stage_5 = DFFEAS(FE1_stage_5_lut_out, DE1__clk0, VCC, , GE1L21, , , , );
--TB1_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_in_d1
--operation mode is normal
TB1_data_in_d1_lut_out = YB1_internal_slave_read_request;
TB1_data_in_d1 = DFFEAS(TB1_data_in_d1_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--UB1_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_in_d1
--operation mode is normal
UB1_data_in_d1_lut_out = YB1_internal_slave_write_request;
UB1_data_in_d1 = DFFEAS(UB1_data_in_d1_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--TC1_break_readreg[23] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[23]
--operation mode is normal
TC1_break_readreg[23] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[23], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L36 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19933
--operation mode is normal
DD1L36 = AMPP_FUNCTION(TC1_break_readreg[23], CD1_internal_MonDReg[23], DD1_ir[1]);
--DD1L37 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19934
--operation mode is normal
DD1L37 = AMPP_FUNCTION(DD1L144, DD1L142, DD1L36, DD1_ir[0]);
--DD1L38 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19935
--operation mode is normal
DD1L38 = AMPP_FUNCTION(DD1L36, DD1L144, A1L5, DD1_ir[0]);
--QD1_rdata[4] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[4]
--operation mode is normal
QD1_rdata[4] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[4], E1_data_out, QD1L18);
--QD1L58 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3510
--operation mode is normal
QD1L58 = AMPP_FUNCTION(QD1_rdata[4], QD1_td_shift[7], QD1_count[9]);
--H1_slave_nativeaddress_d1[0] is std_1s10:inst|clock_0:the_clock_0|slave_nativeaddress_d1[0]
--operation mode is normal
H1_slave_nativeaddress_d1[0]_lut_out = L1_M_alu_result[2];
H1_slave_nativeaddress_d1[0] = DFFEAS(H1_slave_nativeaddress_d1[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_master_writedata[2] is std_1s10:inst|clock_0:the_clock_0|master_writedata[2]
--operation mode is normal
H1_master_writedata[2]_lut_out = H1_slave_writedata_d1[2];
H1_master_writedata[2] = DFFEAS(H1_master_writedata[2]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--H1_master_nativeaddress[1] is std_1s10:inst|clock_0:the_clock_0|master_nativeaddress[1]
--operation mode is normal
H1_master_nativeaddress[1]_lut_out = H1_slave_nativeaddress_d1[1];
H1_master_nativeaddress[1] = DFFEAS(H1_master_nativeaddress[1]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--H1_master_nativeaddress[2] is std_1s10:inst|clock_0:the_clock_0|master_nativeaddress[2]
--operation mode is normal
H1_master_nativeaddress[2]_lut_out = H1_slave_nativeaddress_d1[2];
H1_master_nativeaddress[2] = DFFEAS(H1_master_nativeaddress[2]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--BB1L1 is std_1s10:inst|pll:the_pll|control_reg_en~18
--operation mode is normal
BB1L1 = !H1_master_nativeaddress[1] & !H1_master_nativeaddress[2] & WB1_master_state[2] & H1_master_nativeaddress[0];
--JE1_delayed_unxsync_rxdxx2 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|delayed_unxsync_rxdxx2
--operation mode is normal
JE1_delayed_unxsync_rxdxx2_lut_out = JE1_sync_rxd;
JE1_delayed_unxsync_rxdxx2 = DFFEAS(JE1_delayed_unxsync_rxdxx2_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1_baud_rate_counter[0] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[0]
--operation mode is normal
JE1_baud_rate_counter[0]_lut_out = JE1_baud_rate_counter[0] & (JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2) # !JE1_baud_rate_counter[0] & (JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2 # !JE1L37);
JE1_baud_rate_counter[0] = DFFEAS(JE1_baud_rate_counter[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1_baud_rate_counter[1] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[1]
--operation mode is normal
JE1_baud_rate_counter[1]_lut_out = JE1L2 & (JE1_sync_rxd $ !JE1_delayed_unxsync_rxdxx2) # !JE1L2 & JE1L37 & (JE1_sync_rxd $ !JE1_delayed_unxsync_rxdxx2);
JE1_baud_rate_counter[1] = DFFEAS(JE1_baud_rate_counter[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1_baud_rate_counter[2] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[2]
--operation mode is normal
JE1_baud_rate_counter[2]_lut_out = JE1L4 & !JE1L37 & (JE1_sync_rxd $ !JE1_delayed_unxsync_rxdxx2);
JE1_baud_rate_counter[2] = DFFEAS(JE1_baud_rate_counter[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1_baud_rate_counter[3] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[3]
--operation mode is normal
JE1_baud_rate_counter[3]_lut_out = JE1L6 & (JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2 # !JE1L37) # !JE1L6 & (JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2);
JE1_baud_rate_counter[3] = DFFEAS(JE1_baud_rate_counter[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1L35 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Equal0~166
--operation mode is normal
JE1L35 = !JE1_baud_rate_counter[0] & !JE1_baud_rate_counter[1] & !JE1_baud_rate_counter[2] & !JE1_baud_rate_counter[3];
--JE1_baud_rate_counter[4] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[4]
--operation mode is normal
JE1_baud_rate_counter[4]_lut_out = JE1L8 # JE1L37 # JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2;
JE1_baud_rate_counter[4] = DFFEAS(JE1_baud_rate_counter[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1_baud_rate_counter[5] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[5]
--operation mode is normal
JE1_baud_rate_counter[5]_lut_out = JE1L10 & (JE1_sync_rxd $ !JE1_delayed_unxsync_rxdxx2) # !JE1L10 & JE1L37 & (JE1_sync_rxd $ !JE1_delayed_unxsync_rxdxx2);
JE1_baud_rate_counter[5] = DFFEAS(JE1_baud_rate_counter[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1_baud_rate_counter[6] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[6]
--operation mode is normal
JE1_baud_rate_counter[6]_lut_out = JE1L12 & (JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2 # !JE1L37) # !JE1L12 & (JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2);
JE1_baud_rate_counter[6] = DFFEAS(JE1_baud_rate_counter[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1_baud_rate_counter[7] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[7]
--operation mode is normal
JE1_baud_rate_counter[7]_lut_out = JE1L14 # JE1L37 # JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2;
JE1_baud_rate_counter[7] = DFFEAS(JE1_baud_rate_counter[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1L36 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Equal0~167
--operation mode is normal
JE1L36 = !JE1_baud_rate_counter[4] & !JE1_baud_rate_counter[5] & !JE1_baud_rate_counter[6] & !JE1_baud_rate_counter[7];
--JE1_rxd_edge is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rxd_edge
--operation mode is normal
JE1_rxd_edge = JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2;
--JE1_baud_rate_counter[8] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[8]
--operation mode is normal
JE1_baud_rate_counter[8]_lut_out = JE1L16 & (JE1_sync_rxd $ !JE1_delayed_unxsync_rxdxx2) # !JE1L16 & JE1L37 & (JE1_sync_rxd $ !JE1_delayed_unxsync_rxdxx2);
JE1_baud_rate_counter[8] = DFFEAS(JE1_baud_rate_counter[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1_d1_source_rxd is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|d1_source_rxd
--operation mode is normal
JE1_d1_source_rxd_lut_out = rxd_to_the_uart1;
JE1_d1_source_rxd = DFFEAS(JE1_d1_source_rxd_lut_out, DE1__clk0, E1_data_out, , , , , , );
--CD1L84 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonRd~104
--operation mode is normal
CD1L84 = AMPP_FUNCTION(P1L30, VC1_resetrequest);
--TC1_break_readreg[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[3]
--operation mode is normal
TC1_break_readreg[3] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[3], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L127 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux36~14
--operation mode is normal
DD1L127 = AMPP_FUNCTION(CD1_internal_MonDReg[3], DD1_ir[1], TC1_break_readreg[3], DD1_ir[0]);
--TC1_break_readreg[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[4]
--operation mode is normal
TC1_break_readreg[4] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[4], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L126 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux35~14
--operation mode is normal
DD1L126 = AMPP_FUNCTION(CD1_internal_MonDReg[4], DD1_ir[1], TC1_break_readreg[4], DD1_ir[0]);
--TC1_break_readreg[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[5]
--operation mode is normal
TC1_break_readreg[5] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[5], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L125 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux34~14
--operation mode is normal
DD1L125 = AMPP_FUNCTION(CD1_internal_MonDReg[5], DD1_ir[1], TC1_break_readreg[5], DD1_ir[0]);
--TC1_break_readreg[6] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[6]
--operation mode is normal
TC1_break_readreg[6] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[6], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L124 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux33~12
--operation mode is normal
DD1L124 = AMPP_FUNCTION(CD1_internal_MonDReg[6], DD1_ir[1], TC1_break_readreg[6], DD1_ir[0]);
--DD1L138 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux44~41
--operation mode is normal
DD1L138 = AMPP_FUNCTION(DD1_DRsize[0], DD1_DRsize[1], DD1_DRsize[2]);
--TC1_break_readreg[7] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[7]
--operation mode is normal
TC1_break_readreg[7] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[7], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L123 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux32~14
--operation mode is normal
DD1L123 = AMPP_FUNCTION(CD1_internal_MonDReg[7], DD1_ir[1], TC1_break_readreg[7], DD1_ir[0]);
--TC1_break_readreg[8] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[8]
--operation mode is normal
TC1_break_readreg[8] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[8], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L39 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19941
--operation mode is normal
DD1L39 = AMPP_FUNCTION(TC1_break_readreg[8], CD1_internal_MonDReg[8], DD1_ir[1], DD1_ir[0]);
--TC1_break_readreg[9] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[9]
--operation mode is normal
TC1_break_readreg[9] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[9], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L40 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19943
--operation mode is normal
DD1L40 = AMPP_FUNCTION(TC1_break_readreg[9], CD1_internal_MonDReg[9], DD1_ir[1], DD1_ir[0]);
--TC1_break_readreg[25] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[25]
--operation mode is normal
TC1_break_readreg[25] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[25], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L41 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19945
--operation mode is normal
DD1L41 = AMPP_FUNCTION(TC1_break_readreg[25], CD1_internal_MonDReg[25], DD1_ir[1]);
--DD1L42 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19946
--operation mode is normal
DD1L42 = AMPP_FUNCTION(DD1L144, DD1L142, DD1L41, DD1_ir[0]);
--DD1L43 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19947
--operation mode is normal
DD1L43 = AMPP_FUNCTION(DD1L41, DD1L144, A1L5, DD1_ir[0]);
--TC1_break_readreg[26] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[26]
--operation mode is normal
TC1_break_readreg[26] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[26], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L44 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19949
--operation mode is normal
DD1L44 = AMPP_FUNCTION(TC1_break_readreg[26], CD1_internal_MonDReg[26], DD1_ir[1]);
--DD1L45 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19950
--operation mode is normal
DD1L45 = AMPP_FUNCTION(DD1L144, DD1L142, DD1L44, DD1_ir[0]);
--DD1L46 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19951
--operation mode is normal
DD1L46 = AMPP_FUNCTION(DD1L44, DD1L144, A1L5, DD1_ir[0]);
--TC1_break_readreg[27] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[27]
--operation mode is normal
TC1_break_readreg[27] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[27], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L47 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19953
--operation mode is normal
DD1L47 = AMPP_FUNCTION(TC1_break_readreg[27], CD1_internal_MonDReg[27], DD1_ir[1]);
--DD1L48 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19954
--operation mode is normal
DD1L48 = AMPP_FUNCTION(DD1L143, DD1_ir[1], DD1L47, DD1_ir[0]);
--TC1_break_readreg[28] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[28]
--operation mode is normal
TC1_break_readreg[28] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[28], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L49 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19956
--operation mode is normal
DD1L49 = AMPP_FUNCTION(TC1_break_readreg[28], CD1_internal_MonDReg[28], DD1_ir[1]);
--DD1L50 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19957
--operation mode is normal
DD1L50 = AMPP_FUNCTION(DD1L144, DD1L142, DD1L49, DD1_ir[0]);
--DD1L51 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19958
--operation mode is normal
DD1L51 = AMPP_FUNCTION(DD1L49, DD1L144, A1L5, DD1_ir[0]);
--TC1_break_readreg[29] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[29]
--operation mode is normal
TC1_break_readreg[29] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[29], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L52 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19960
--operation mode is normal
DD1L52 = AMPP_FUNCTION(TC1_break_readreg[29], CD1_internal_MonDReg[29], DD1_ir[1]);
--DD1L53 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19961
--operation mode is normal
DD1L53 = AMPP_FUNCTION(DD1L143, DD1_ir[1], DD1L52, DD1_ir[0]);
--DD1L134 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux42~95
--operation mode is normal
DD1L134 = AMPP_FUNCTION(DD1_DRsize[1], DD1_DRsize[0], altera_internal_jtag, DD1_DRsize[2]);
--DD1L135 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux42~96
--operation mode is normal
DD1L135 = AMPP_FUNCTION(DD1_sr[32], DD1_DRsize[2], DD1_DRsize[1], DD1_DRsize[0]);
--DD1L54 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19963
--operation mode is normal
DD1L54 = AMPP_FUNCTION(DD1L144, DD1L134, DD1L135, A1L5);
--DD1L136 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux42~97
--operation mode is normal
DD1L136 = AMPP_FUNCTION(DD1L134, DD1L135);
--TC1_break_readreg[30] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[30]
--operation mode is normal
TC1_break_readreg[30] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[30], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L55 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19964
--operation mode is normal
DD1L55 = AMPP_FUNCTION(TC1_break_readreg[30], CD1_internal_MonDReg[30], DD1_ir[1]);
--TC1_break_readreg[31] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[31]
--operation mode is normal
TC1_break_readreg[31] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[31], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L56 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19965
--operation mode is normal
DD1L56 = AMPP_FUNCTION(TC1_break_readreg[31], CD1_internal_MonDReg[31], DD1_ir[1]);
--DD1L57 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19966
--operation mode is normal
DD1L57 = AMPP_FUNCTION(DD1L144, DD1L142, DD1L56, DD1_ir[0]);
--DD1L58 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19967
--operation mode is normal
DD1L58 = AMPP_FUNCTION(DD1L56, DD1L144, A1L5, DD1_ir[0]);
--VC1_internal_resetlatch is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_resetlatch
--operation mode is normal
VC1_internal_resetlatch = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[24], DD1L190, VC1_internal_resetlatch, VC1L9, VCC);
--DD1L59 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19969
--operation mode is normal
DD1L59 = AMPP_FUNCTION(VC1_internal_resetlatch, DD1_ir[0], DD1_ir[1]);
--QD1_rdata[5] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[5]
--operation mode is normal
QD1_rdata[5] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[5], E1_data_out, QD1L18);
--QD1L59 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3512
--operation mode is normal
QD1L59 = AMPP_FUNCTION(QD1_rdata[5], QD1_td_shift[8], QD1_count[9]);
--H1_master_writedata[3] is std_1s10:inst|clock_0:the_clock_0|master_writedata[3]
--operation mode is normal
H1_master_writedata[3]_lut_out = H1_slave_writedata_d1[3];
H1_master_writedata[3] = DFFEAS(H1_master_writedata[3]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--H1_master_writedata[7] is std_1s10:inst|clock_0:the_clock_0|master_writedata[7]
--operation mode is normal
H1_master_writedata[7]_lut_out = H1_slave_writedata_d1[7];
H1_master_writedata[7] = DFFEAS(H1_master_writedata[7]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--GC1L11 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~569
--operation mode is arithmetic
GC1L11 = AMPP_FUNCTION(L1L611, L1L677, GC1L13);
--QD1_rdata[6] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[6]
--operation mode is normal
QD1_rdata[6] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[6], E1_data_out, QD1L18);
--H1_master_writedata[4] is std_1s10:inst|clock_0:the_clock_0|master_writedata[4]
--operation mode is normal
H1_master_writedata[4]_lut_out = H1_slave_writedata_d1[4];
H1_master_writedata[4] = DFFEAS(H1_master_writedata[4]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--H1_master_writedata[15] is std_1s10:inst|clock_0:the_clock_0|master_writedata[15]
--operation mode is normal
H1_master_writedata[15]_lut_out = H1_slave_writedata_d1[15];
H1_master_writedata[15] = DFFEAS(H1_master_writedata[15]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--TC1_break_readreg[10] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[10]
--operation mode is normal
TC1_break_readreg[10] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[10], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L60 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19971
--operation mode is normal
DD1L60 = AMPP_FUNCTION(TC1_break_readreg[10], CD1_internal_MonDReg[10], DD1_ir[1], DD1_ir[0]);
--TC1_break_readreg[11] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[11]
--operation mode is normal
TC1_break_readreg[11] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[11], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L61 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19973
--operation mode is normal
DD1L61 = AMPP_FUNCTION(TC1_break_readreg[11], CD1_internal_MonDReg[11], DD1_ir[1], DD1_ir[0]);
--TC1_break_readreg[12] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[12]
--operation mode is normal
TC1_break_readreg[12] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[12], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L62 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19975
--operation mode is normal
DD1L62 = AMPP_FUNCTION(TC1_break_readreg[12], CD1_internal_MonDReg[12], DD1_ir[1], DD1_ir[0]);
--TC1_break_readreg[13] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[13]
--operation mode is normal
TC1_break_readreg[13] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[13], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L63 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19977
--operation mode is normal
DD1L63 = AMPP_FUNCTION(TC1_break_readreg[13], CD1_internal_MonDReg[13], DD1_ir[1], DD1_ir[0]);
--TC1_break_readreg[14] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[14]
--operation mode is normal
TC1_break_readreg[14] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[14], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L122 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux25~50
--operation mode is normal
DD1L122 = AMPP_FUNCTION(TC1_break_readreg[14], CD1_internal_MonDReg[14], DD1_ir[1], DD1_ir[0]);
--DD1L137 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux43~41
--operation mode is normal
DD1L137 = AMPP_FUNCTION(DD1_DRsize[1], DD1_DRsize[2], DD1_DRsize[0]);
--TC1_break_readreg[15] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[15]
--operation mode is normal
TC1_break_readreg[15] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[15], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L64 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19979
--operation mode is normal
DD1L64 = AMPP_FUNCTION(TC1_break_readreg[15], CD1_internal_MonDReg[15], DD1_ir[1]);
--DD1L65 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19980
--operation mode is normal
DD1L65 = AMPP_FUNCTION(DD1L144, DD1L142, DD1L64, DD1_ir[0]);
--DD1L66 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19981
--operation mode is normal
DD1L66 = AMPP_FUNCTION(DD1L64, DD1L144, A1L5, DD1_ir[0]);
--TC1_break_readreg[16] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[16]
--operation mode is normal
TC1_break_readreg[16] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[16], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L67 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19983
--operation mode is normal
DD1L67 = AMPP_FUNCTION(TC1_break_readreg[16], CD1_internal_MonDReg[16], DD1_ir[1]);
--DD1L68 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19984
--operation mode is normal
DD1L68 = AMPP_FUNCTION(DD1L144, DD1L142, DD1L67, DD1_ir[0]);
--DD1L69 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19985
--operation mode is normal
DD1L69 = AMPP_FUNCTION(DD1L67, DD1L144, A1L5, DD1_ir[0]);
--H1_master_writedata[14] is std_1s10:inst|clock_0:the_clock_0|master_writedata[14]
--operation mode is normal
H1_master_writedata[14]_lut_out = H1_slave_writedata_d1[14];
H1_master_writedata[14] = DFFEAS(H1_master_writedata[14]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--H1_master_writedata[13] is std_1s10:inst|clock_0:the_clock_0|master_writedata[13]
--operation mode is normal
H1_master_writedata[13]_lut_out = H1_slave_writedata_d1[13];
H1_master_writedata[13] = DFFEAS(H1_master_writedata[13]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--H1_master_writedata[12] is std_1s10:inst|clock_0:the_clock_0|master_writedata[12]
--operation mode is normal
H1_master_writedata[12]_lut_out = H1_slave_writedata_d1[12];
H1_master_writedata[12] = DFFEAS(H1_master_writedata[12]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--H1_master_writedata[11] is std_1s10:inst|clock_0:the_clock_0|master_writedata[11]
--operation mode is normal
H1_master_writedata[11]_lut_out = H1_slave_writedata_d1[11];
H1_master_writedata[11] = DFFEAS(H1_master_writedata[11]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--H1_master_writedata[10] is std_1s10:inst|clock_0:the_clock_0|master_writedata[10]
--operation mode is normal
H1_master_writedata[10]_lut_out = H1_slave_writedata_d1[10];
H1_master_writedata[10] = DFFEAS(H1_master_writedata[10]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--H1_master_writedata[9] is std_1s10:inst|clock_0:the_clock_0|master_writedata[9]
--operation mode is normal
H1_master_writedata[9]_lut_out = H1_slave_writedata_d1[9];
H1_master_writedata[9] = DFFEAS(H1_master_writedata[9]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--H1_master_writedata[8] is std_1s10:inst|clock_0:the_clock_0|master_writedata[8]
--operation mode is normal
H1_master_writedata[8]_lut_out = H1_slave_writedata_d1[8];
H1_master_writedata[8] = DFFEAS(H1_master_writedata[8]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--H1_master_writedata[5] is std_1s10:inst|clock_0:the_clock_0|master_writedata[5]
--operation mode is normal
H1_master_writedata[5]_lut_out = H1_slave_writedata_d1[5];
H1_master_writedata[5] = DFFEAS(H1_master_writedata[5]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--H1_master_writedata[6] is std_1s10:inst|clock_0:the_clock_0|master_writedata[6]
--operation mode is normal
H1_master_writedata[6]_lut_out = H1_slave_writedata_d1[6];
H1_master_writedata[6] = DFFEAS(H1_master_writedata[6]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--BB1_control_reg_out[0] is std_1s10:inst|pll:the_pll|control_reg_out[0]
--operation mode is normal
BB1_control_reg_out[0]_lut_out = H1_master_writedata[0];
BB1_control_reg_out[0] = DFFEAS(BB1_control_reg_out[0]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--QD1_td_shift[5] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[5]
--operation mode is normal
QD1_td_shift[5] = AMPP_FUNCTION(!A1L6, QD1L53, QD1L63, QD1L61, !C1_CLR_SIGNAL, QD1L52);
--BB1_control_reg_out[1] is std_1s10:inst|pll:the_pll|control_reg_out[1]
--operation mode is normal
BB1_control_reg_out[1]_lut_out = !H1_master_writedata[1];
BB1_control_reg_out[1] = DFFEAS(BB1_control_reg_out[1]_lut_out, PLD_CLOCKINPUT, D1_data_out, , BB1L1, , , , );
--AE1_q_b[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[1]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE1_q_b[1]_PORT_A_data_in = L1_M_st_data[1];
AE1_q_b[1]_PORT_A_data_in_reg = DFFE(AE1_q_b[1]_PORT_A_data_in, AE1_q_b[1]_clock_0, , , AE1_q_b[1]_clock_enable_0);
AE1_q_b[1]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[1]_PORT_A_address_reg = DFFE(AE1_q_b[1]_PORT_A_address, AE1_q_b[1]_clock_0, , , AE1_q_b[1]_clock_enable_0);
AE1_q_b[1]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[1]_PORT_B_address_reg = DFFE(AE1_q_b[1]_PORT_B_address, AE1_q_b[1]_clock_1, , , AE1_q_b[1]_clock_enable_1);
AE1_q_b[1]_PORT_A_write_enable = VCC;
AE1_q_b[1]_PORT_A_write_enable_reg = DFFE(AE1_q_b[1]_PORT_A_write_enable, AE1_q_b[1]_clock_0, , , AE1_q_b[1]_clock_enable_0);
AE1_q_b[1]_PORT_B_read_enable = VCC;
AE1_q_b[1]_PORT_B_read_enable_reg = DFFE(AE1_q_b[1]_PORT_B_read_enable, AE1_q_b[1]_clock_1, , , AE1_q_b[1]_clock_enable_1);
AE1_q_b[1]_clock_0 = DE1__clk0;
AE1_q_b[1]_clock_1 = DE1__clk0;
AE1_q_b[1]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[1]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[1]_PORT_B_data_out = MEMORY(AE1_q_b[1]_PORT_A_data_in_reg, , AE1_q_b[1]_PORT_A_address_reg, AE1_q_b[1]_PORT_B_address_reg, AE1_q_b[1]_PORT_A_write_enable_reg, AE1_q_b[1]_PORT_B_read_enable_reg, , , AE1_q_b[1]_clock_0, AE1_q_b[1]_clock_1, AE1_q_b[1]_clock_enable_0, AE1_q_b[1]_clock_enable_1, , );
AE1_q_b[1] = AE1_q_b[1]_PORT_B_data_out[0];
--QD1_rdata[2] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[2]
--operation mode is normal
QD1_rdata[2] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[2], E1_data_out, QD1L18);
--QD1L60 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3514
--operation mode is normal
QD1L60 = AMPP_FUNCTION(QD1_rdata[2], QD1_td_shift[5], QD1_count[9]);
--QD1_count[5] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[5]
--operation mode is normal
QD1_count[5] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1_count[4], !C1_CLR_SIGNAL, QD1L52);
--DD1_internal_jdo1[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[2]
--operation mode is normal
DD1_internal_jdo1[2] = AMPP_FUNCTION(!A1L9, DD1_sr[2], VCC, DD1L144);
--GE1_stage_6 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_6
--operation mode is normal
GE1_stage_6 = DFFEAS(GE1_stage_6_lut_out, DE1__clk0, VCC, , GE1L20, , , , );
--GE1_full_6 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_6
--operation mode is normal
GE1_full_6_lut_out = GE1_full_5 & (GB1L28 # !FB1_za_valid);
GE1_full_6 = DFFEAS(GE1_full_6_lut_out, DE1__clk0, E1_data_out, , FE1L13, , , , );
--GE1L21 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process2~1
--operation mode is normal
GE1L21 = FB1_za_valid # GB1L28 & (!GE1_full_5);
--FE1_stage_6 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_6
--operation mode is normal
FE1_stage_6 = DFFEAS(FE1_stage_6_lut_out, DE1__clk0, VCC, , GE1L20, , , , );
--YB1_internal_slave_read_request is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_read_request
--operation mode is normal
YB1_internal_slave_read_request_lut_out = YB1_internal_slave_read_request $ (J1L1 & YB1L2);
YB1_internal_slave_read_request = DFFEAS(YB1_internal_slave_read_request_lut_out, DE1__clk0, E1_data_out, , , , , , );
--YB1_internal_slave_write_request is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_write_request
--operation mode is normal
YB1_internal_slave_write_request_lut_out = YB1_internal_slave_write_request $ (YB1L4 & YB1L2);
YB1_internal_slave_write_request = DFFEAS(YB1_internal_slave_write_request_lut_out, DE1__clk0, E1_data_out, , , , , , );
--AE1_q_b[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[4]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE1_q_b[4]_PORT_A_data_in = L1_M_st_data[4];
AE1_q_b[4]_PORT_A_data_in_reg = DFFE(AE1_q_b[4]_PORT_A_data_in, AE1_q_b[4]_clock_0, , , AE1_q_b[4]_clock_enable_0);
AE1_q_b[4]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[4]_PORT_A_address_reg = DFFE(AE1_q_b[4]_PORT_A_address, AE1_q_b[4]_clock_0, , , AE1_q_b[4]_clock_enable_0);
AE1_q_b[4]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[4]_PORT_B_address_reg = DFFE(AE1_q_b[4]_PORT_B_address, AE1_q_b[4]_clock_1, , , AE1_q_b[4]_clock_enable_1);
AE1_q_b[4]_PORT_A_write_enable = VCC;
AE1_q_b[4]_PORT_A_write_enable_reg = DFFE(AE1_q_b[4]_PORT_A_write_enable, AE1_q_b[4]_clock_0, , , AE1_q_b[4]_clock_enable_0);
AE1_q_b[4]_PORT_B_read_enable = VCC;
AE1_q_b[4]_PORT_B_read_enable_reg = DFFE(AE1_q_b[4]_PORT_B_read_enable, AE1_q_b[4]_clock_1, , , AE1_q_b[4]_clock_enable_1);
AE1_q_b[4]_clock_0 = DE1__clk0;
AE1_q_b[4]_clock_1 = DE1__clk0;
AE1_q_b[4]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[4]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[4]_PORT_B_data_out = MEMORY(AE1_q_b[4]_PORT_A_data_in_reg, , AE1_q_b[4]_PORT_A_address_reg, AE1_q_b[4]_PORT_B_address_reg, AE1_q_b[4]_PORT_A_write_enable_reg, AE1_q_b[4]_PORT_B_read_enable_reg, , , AE1_q_b[4]_clock_0, AE1_q_b[4]_clock_1, AE1_q_b[4]_clock_enable_0, AE1_q_b[4]_clock_enable_1, , );
AE1_q_b[4] = AE1_q_b[4]_PORT_B_data_out[0];
--H1_slave_writedata_d1[2] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[2]
--operation mode is normal
H1_slave_writedata_d1[2]_lut_out = L1_M_st_data[2];
H1_slave_writedata_d1[2] = DFFEAS(H1_slave_writedata_d1[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_nativeaddress_d1[1] is std_1s10:inst|clock_0:the_clock_0|slave_nativeaddress_d1[1]
--operation mode is normal
H1_slave_nativeaddress_d1[1]_lut_out = L1_M_alu_result[3];
H1_slave_nativeaddress_d1[1] = DFFEAS(H1_slave_nativeaddress_d1[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_nativeaddress_d1[2] is std_1s10:inst|clock_0:the_clock_0|slave_nativeaddress_d1[2]
--operation mode is normal
H1_slave_nativeaddress_d1[2]_lut_out = L1_M_alu_result[4];
H1_slave_nativeaddress_d1[2] = DFFEAS(H1_slave_nativeaddress_d1[2]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--JE1L37 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Equal0~168
--operation mode is normal
JE1L37 = JE1L35 & JE1L36 & (!JE1_baud_rate_counter[8]);
--JE1L2 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~164
--operation mode is arithmetic
JE1L2 = JE1_baud_rate_counter[1] $ (!JE1L2_carry_eqn);
--JE1L3 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~165
--operation mode is arithmetic
JE1L3 = CARRY(!JE1_baud_rate_counter[1] & (!JE1L18));
--JE1L4 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~166
--operation mode is arithmetic
JE1L4 = JE1_baud_rate_counter[2] $ (JE1L4_carry_eqn);
--JE1L5 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~167
--operation mode is arithmetic
JE1L5 = CARRY(JE1_baud_rate_counter[2] # !JE1L3);
--JE1L6 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~168
--operation mode is arithmetic
JE1L6 = JE1_baud_rate_counter[3] $ (!JE1L6_carry_eqn);
--JE1L7 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~169
--operation mode is arithmetic
JE1L7 = CARRY(!JE1_baud_rate_counter[3] & (!JE1L5));
--JE1L8 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~170
--operation mode is arithmetic
JE1L8 = JE1_baud_rate_counter[4] $ (JE1L8_carry_eqn);
--JE1L9 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~171
--operation mode is arithmetic
JE1L9 = CARRY(JE1_baud_rate_counter[4] # !JE1L7);
--JE1L10 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~172
--operation mode is arithmetic
JE1L10 = JE1_baud_rate_counter[5] $ (!JE1L10_carry_eqn);
--JE1L11 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~173
--operation mode is arithmetic
JE1L11 = CARRY(!JE1_baud_rate_counter[5] & (!JE1L9));
--JE1L12 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~174
--operation mode is arithmetic
JE1L12 = JE1_baud_rate_counter[6] $ (JE1L12_carry_eqn);
--JE1L13 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~175
--operation mode is arithmetic
JE1L13 = CARRY(JE1_baud_rate_counter[6] # !JE1L11);
--JE1L14 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~176
--operation mode is arithmetic
JE1L14 = JE1_baud_rate_counter[7] $ (!JE1L14_carry_eqn);
--JE1L15 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~177
--operation mode is arithmetic
JE1L15 = CARRY(!JE1_baud_rate_counter[7] & (!JE1L13));
--JE1L16 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~178
--operation mode is normal
JE1L16 = JE1_baud_rate_counter[8] $ (JE1L16_carry_eqn);
--VC1L9 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_resetlatch~185
--operation mode is normal
VC1L9 = AMPP_FUNCTION(C1_CLR_SIGNAL, E1_data_out, VC1_internal_resetlatch);
--AE1_q_b[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[5]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE1_q_b[5]_PORT_A_data_in = L1_M_st_data[5];
AE1_q_b[5]_PORT_A_data_in_reg = DFFE(AE1_q_b[5]_PORT_A_data_in, AE1_q_b[5]_clock_0, , , AE1_q_b[5]_clock_enable_0);
AE1_q_b[5]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[5]_PORT_A_address_reg = DFFE(AE1_q_b[5]_PORT_A_address, AE1_q_b[5]_clock_0, , , AE1_q_b[5]_clock_enable_0);
AE1_q_b[5]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[5]_PORT_B_address_reg = DFFE(AE1_q_b[5]_PORT_B_address, AE1_q_b[5]_clock_1, , , AE1_q_b[5]_clock_enable_1);
AE1_q_b[5]_PORT_A_write_enable = VCC;
AE1_q_b[5]_PORT_A_write_enable_reg = DFFE(AE1_q_b[5]_PORT_A_write_enable, AE1_q_b[5]_clock_0, , , AE1_q_b[5]_clock_enable_0);
AE1_q_b[5]_PORT_B_read_enable = VCC;
AE1_q_b[5]_PORT_B_read_enable_reg = DFFE(AE1_q_b[5]_PORT_B_read_enable, AE1_q_b[5]_clock_1, , , AE1_q_b[5]_clock_enable_1);
AE1_q_b[5]_clock_0 = DE1__clk0;
AE1_q_b[5]_clock_1 = DE1__clk0;
AE1_q_b[5]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[5]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[5]_PORT_B_data_out = MEMORY(AE1_q_b[5]_PORT_A_data_in_reg, , AE1_q_b[5]_PORT_A_address_reg, AE1_q_b[5]_PORT_B_address_reg, AE1_q_b[5]_PORT_A_write_enable_reg, AE1_q_b[5]_PORT_B_read_enable_reg, , , AE1_q_b[5]_clock_0, AE1_q_b[5]_clock_1, AE1_q_b[5]_clock_enable_0, AE1_q_b[5]_clock_enable_1, , );
AE1_q_b[5] = AE1_q_b[5]_PORT_B_data_out[0];
--H1_slave_writedata_d1[3] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[3]
--operation mode is normal
H1_slave_writedata_d1[3]_lut_out = L1_M_st_data[3];
H1_slave_writedata_d1[3] = DFFEAS(H1_slave_writedata_d1[3]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_writedata_d1[7] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[7]
--operation mode is normal
H1_slave_writedata_d1[7]_lut_out = L1_M_st_data[7];
H1_slave_writedata_d1[7] = DFFEAS(H1_slave_writedata_d1[7]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--GC1L13 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~571
--operation mode is arithmetic
GC1L13 = AMPP_FUNCTION(L1L610, L1L676, GC1L15);
--AE1_q_b[6] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[6]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE1_q_b[6]_PORT_A_data_in = L1_M_st_data[6];
AE1_q_b[6]_PORT_A_data_in_reg = DFFE(AE1_q_b[6]_PORT_A_data_in, AE1_q_b[6]_clock_0, , , AE1_q_b[6]_clock_enable_0);
AE1_q_b[6]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[6]_PORT_A_address_reg = DFFE(AE1_q_b[6]_PORT_A_address, AE1_q_b[6]_clock_0, , , AE1_q_b[6]_clock_enable_0);
AE1_q_b[6]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[6]_PORT_B_address_reg = DFFE(AE1_q_b[6]_PORT_B_address, AE1_q_b[6]_clock_1, , , AE1_q_b[6]_clock_enable_1);
AE1_q_b[6]_PORT_A_write_enable = VCC;
AE1_q_b[6]_PORT_A_write_enable_reg = DFFE(AE1_q_b[6]_PORT_A_write_enable, AE1_q_b[6]_clock_0, , , AE1_q_b[6]_clock_enable_0);
AE1_q_b[6]_PORT_B_read_enable = VCC;
AE1_q_b[6]_PORT_B_read_enable_reg = DFFE(AE1_q_b[6]_PORT_B_read_enable, AE1_q_b[6]_clock_1, , , AE1_q_b[6]_clock_enable_1);
AE1_q_b[6]_clock_0 = DE1__clk0;
AE1_q_b[6]_clock_1 = DE1__clk0;
AE1_q_b[6]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[6]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[6]_PORT_B_data_out = MEMORY(AE1_q_b[6]_PORT_A_data_in_reg, , AE1_q_b[6]_PORT_A_address_reg, AE1_q_b[6]_PORT_B_address_reg, AE1_q_b[6]_PORT_A_write_enable_reg, AE1_q_b[6]_PORT_B_read_enable_reg, , , AE1_q_b[6]_clock_0, AE1_q_b[6]_clock_1, AE1_q_b[6]_clock_enable_0, AE1_q_b[6]_clock_enable_1, , );
AE1_q_b[6] = AE1_q_b[6]_PORT_B_data_out[0];
--H1_slave_writedata_d1[4] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[4]
--operation mode is normal
H1_slave_writedata_d1[4]_lut_out = L1_M_st_data[4];
H1_slave_writedata_d1[4] = DFFEAS(H1_slave_writedata_d1[4]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_writedata_d1[15] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[15]
--operation mode is normal
H1_slave_writedata_d1[15]_lut_out = L1_M_st_data[15];
H1_slave_writedata_d1[15] = DFFEAS(H1_slave_writedata_d1[15]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_writedata_d1[14] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[14]
--operation mode is normal
H1_slave_writedata_d1[14]_lut_out = L1_M_st_data[14];
H1_slave_writedata_d1[14] = DFFEAS(H1_slave_writedata_d1[14]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_writedata_d1[13] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[13]
--operation mode is normal
H1_slave_writedata_d1[13]_lut_out = L1_M_st_data[13];
H1_slave_writedata_d1[13] = DFFEAS(H1_slave_writedata_d1[13]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_writedata_d1[12] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[12]
--operation mode is normal
H1_slave_writedata_d1[12]_lut_out = L1_M_st_data[12];
H1_slave_writedata_d1[12] = DFFEAS(H1_slave_writedata_d1[12]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_writedata_d1[11] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[11]
--operation mode is normal
H1_slave_writedata_d1[11]_lut_out = L1_M_st_data[11];
H1_slave_writedata_d1[11] = DFFEAS(H1_slave_writedata_d1[11]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_writedata_d1[10] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[10]
--operation mode is normal
H1_slave_writedata_d1[10]_lut_out = L1_M_st_data[10];
H1_slave_writedata_d1[10] = DFFEAS(H1_slave_writedata_d1[10]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_writedata_d1[9] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[9]
--operation mode is normal
H1_slave_writedata_d1[9]_lut_out = L1_M_st_data[9];
H1_slave_writedata_d1[9] = DFFEAS(H1_slave_writedata_d1[9]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_writedata_d1[8] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[8]
--operation mode is normal
H1_slave_writedata_d1[8]_lut_out = L1_M_st_data[8];
H1_slave_writedata_d1[8] = DFFEAS(H1_slave_writedata_d1[8]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_writedata_d1[5] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[5]
--operation mode is normal
H1_slave_writedata_d1[5]_lut_out = L1_M_st_data[5];
H1_slave_writedata_d1[5] = DFFEAS(H1_slave_writedata_d1[5]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_slave_writedata_d1[6] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[6]
--operation mode is normal
H1_slave_writedata_d1[6]_lut_out = L1_M_st_data[6];
H1_slave_writedata_d1[6] = DFFEAS(H1_slave_writedata_d1[6]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--H1_master_writedata[0] is std_1s10:inst|clock_0:the_clock_0|master_writedata[0]
--operation mode is normal
H1_master_writedata[0]_lut_out = H1_slave_writedata_d1[0];
H1_master_writedata[0] = DFFEAS(H1_master_writedata[0]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--QD1_rdata[3] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[3]
--operation mode is normal
QD1_rdata[3] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[3], E1_data_out, QD1L18);
--QD1L61 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3517
--operation mode is normal
QD1L61 = AMPP_FUNCTION(QD1_rdata[3], QD1_td_shift[6], QD1_count[9]);
--H1_master_writedata[1] is std_1s10:inst|clock_0:the_clock_0|master_writedata[1]
--operation mode is normal
H1_master_writedata[1]_lut_out = H1_slave_writedata_d1[1];
H1_master_writedata[1] = DFFEAS(H1_master_writedata[1]_lut_out, PLD_CLOCKINPUT, D1_data_out, , , , , , );
--AE1_q_b[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[2]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE1_q_b[2]_PORT_A_data_in = L1_M_st_data[2];
AE1_q_b[2]_PORT_A_data_in_reg = DFFE(AE1_q_b[2]_PORT_A_data_in, AE1_q_b[2]_clock_0, , , AE1_q_b[2]_clock_enable_0);
AE1_q_b[2]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[2]_PORT_A_address_reg = DFFE(AE1_q_b[2]_PORT_A_address, AE1_q_b[2]_clock_0, , , AE1_q_b[2]_clock_enable_0);
AE1_q_b[2]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[2]_PORT_B_address_reg = DFFE(AE1_q_b[2]_PORT_B_address, AE1_q_b[2]_clock_1, , , AE1_q_b[2]_clock_enable_1);
AE1_q_b[2]_PORT_A_write_enable = VCC;
AE1_q_b[2]_PORT_A_write_enable_reg = DFFE(AE1_q_b[2]_PORT_A_write_enable, AE1_q_b[2]_clock_0, , , AE1_q_b[2]_clock_enable_0);
AE1_q_b[2]_PORT_B_read_enable = VCC;
AE1_q_b[2]_PORT_B_read_enable_reg = DFFE(AE1_q_b[2]_PORT_B_read_enable, AE1_q_b[2]_clock_1, , , AE1_q_b[2]_clock_enable_1);
AE1_q_b[2]_clock_0 = DE1__clk0;
AE1_q_b[2]_clock_1 = DE1__clk0;
AE1_q_b[2]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[2]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[2]_PORT_B_data_out = MEMORY(AE1_q_b[2]_PORT_A_data_in_reg, , AE1_q_b[2]_PORT_A_address_reg, AE1_q_b[2]_PORT_B_address_reg, AE1_q_b[2]_PORT_A_write_enable_reg, AE1_q_b[2]_PORT_B_read_enable_reg, , , AE1_q_b[2]_clock_0, AE1_q_b[2]_clock_1, AE1_q_b[2]_clock_enable_0, AE1_q_b[2]_clock_enable_1, , );
AE1_q_b[2] = AE1_q_b[2]_PORT_B_data_out[0];
--QD1_count[4] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[4]
--operation mode is normal
QD1_count[4] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1_count[3], !C1_CLR_SIGNAL, QD1L52);
--GE1L20 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process0~1
--operation mode is normal
GE1L20 = FB1_za_valid # GB1L28 & (!GE1_full_6);
--YB1L2 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_read_request~29
--operation mode is normal
YB1L2 = !YB1_slave_state[2] & !YB1_slave_state[1] & !YB1_slave_state[0];
--JE1L18 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~181
--operation mode is arithmetic
JE1L18 = CARRY(JE1_baud_rate_counter[0]);
--GC1L15 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~573
--operation mode is arithmetic
GC1L15 = AMPP_FUNCTION(L1L609, L1L675, GC1L17);
--H1_slave_writedata_d1[0] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[0]
--operation mode is normal
H1_slave_writedata_d1[0]_lut_out = L1_M_st_data[0];
H1_slave_writedata_d1[0] = DFFEAS(H1_slave_writedata_d1[0]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--AE1_q_b[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[3]
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE1_q_b[3]_PORT_A_data_in = L1_M_st_data[3];
AE1_q_b[3]_PORT_A_data_in_reg = DFFE(AE1_q_b[3]_PORT_A_data_in, AE1_q_b[3]_clock_0, , , AE1_q_b[3]_clock_enable_0);
AE1_q_b[3]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[3]_PORT_A_address_reg = DFFE(AE1_q_b[3]_PORT_A_address, AE1_q_b[3]_clock_0, , , AE1_q_b[3]_clock_enable_0);
AE1_q_b[3]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[3]_PORT_B_address_reg = DFFE(AE1_q_b[3]_PORT_B_address, AE1_q_b[3]_clock_1, , , AE1_q_b[3]_clock_enable_1);
AE1_q_b[3]_PORT_A_write_enable = VCC;
AE1_q_b[3]_PORT_A_write_enable_reg = DFFE(AE1_q_b[3]_PORT_A_write_enable, AE1_q_b[3]_clock_0, , , AE1_q_b[3]_clock_enable_0);
AE1_q_b[3]_PORT_B_read_enable = VCC;
AE1_q_b[3]_PORT_B_read_enable_reg = DFFE(AE1_q_b[3]_PORT_B_read_enable, AE1_q_b[3]_clock_1, , , AE1_q_b[3]_clock_enable_1);
AE1_q_b[3]_clock_0 = DE1__clk0;
AE1_q_b[3]_clock_1 = DE1__clk0;
AE1_q_b[3]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[3]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[3]_PORT_B_data_out = MEMORY(AE1_q_b[3]_PORT_A_data_in_reg, , AE1_q_b[3]_PORT_A_address_reg, AE1_q_b[3]_PORT_B_address_reg, AE1_q_b[3]_PORT_A_write_enable_reg, AE1_q_b[3]_PORT_B_read_enable_reg, , , AE1_q_b[3]_clock_0, AE1_q_b[3]_clock_1, AE1_q_b[3]_clock_enable_0, AE1_q_b[3]_clock_enable_1, , );
AE1_q_b[3] = AE1_q_b[3]_PORT_B_data_out[0];
--H1_slave_writedata_d1[1] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[1]
--operation mode is normal
H1_slave_writedata_d1[1]_lut_out = L1_M_st_data[1];
H1_slave_writedata_d1[1] = DFFEAS(H1_slave_writedata_d1[1]_lut_out, DE1__clk0, E1_data_out, , , , , , );
--QD1_count[3] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[3]
--operation mode is normal
QD1_count[3] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1_count[2], !C1_CLR_SIGNAL, QD1L52);
--GC1L17 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~575
--operation mode is arithmetic
GC1L17 = AMPP_FUNCTION(L1L608, L1L674, GC1L19);
--QD1_count[2] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[2]
--operation mode is normal
QD1_count[2] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1_count[1], !C1_CLR_SIGNAL, QD1L52);
--GC1L19 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~577
--operation mode is arithmetic
GC1L19 = AMPP_FUNCTION(L1L607, L1L673, GC1L21);
--GC1L21 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~579
--operation mode is arithmetic
GC1L21 = AMPP_FUNCTION(L1L606, L1L672, GC1L23);
--GC1L23 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~581
--operation mode is arithmetic
GC1L23 = AMPP_FUNCTION(L1L605, L1L671, GC1L25);
--GC1L25 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~583
--operation mode is arithmetic
GC1L25 = AMPP_FUNCTION(L1L604, L1L670, GC1L27);
--GC1L27 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~585
--operation mode is arithmetic
GC1L27 = AMPP_FUNCTION(L1L603, L1L669, GC1L29);
--GC1L29 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~587
--operation mode is arithmetic
GC1L29 = AMPP_FUNCTION(L1L602, L1L668, GC1L31);
--GC1L31 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~589
--operation mode is arithmetic
GC1L31 = AMPP_FUNCTION(L1L601, L1L667, GC1L33);
--GC1L33 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~591
--operation mode is arithmetic
GC1L33 = AMPP_FUNCTION(L1L600, L1L666, GC1L35);
--GC1L35 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~593
--operation mode is arithmetic
GC1L35 = AMPP_FUNCTION(L1L599, L1L665, GC1L37);
--GC1L37 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~595
--operation mode is arithmetic
GC1L37 = AMPP_FUNCTION(L1L598, L1L664, GC1L39);
--GC1L39 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~597
--operation mode is arithmetic
GC1L39 = AMPP_FUNCTION(L1L597, L1L663, GC1L41);
--GC1L41 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~599
--operation mode is arithmetic
GC1L41 = AMPP_FUNCTION(L1L596, L1L662, GC1L43);
--GC1L43 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~601
--operation mode is arithmetic
GC1L43 = AMPP_FUNCTION(L1L595, L1L661, GC1L45);
--GC1L45 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~603
--operation mode is arithmetic
GC1L45 = AMPP_FUNCTION(L1L594, L1L660, GC1L47);
--GC1L47 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~605
--operation mode is arithmetic
GC1L47 = AMPP_FUNCTION(L1L593, L1L659, GC1L49);
--GC1L49 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~607
--operation mode is arithmetic
GC1L49 = AMPP_FUNCTION(L1L592, L1L658, GC1L51);
--GC1L51 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~609
--operation mode is arithmetic
GC1L51 = AMPP_FUNCTION(L1L591, L1L657, GC1L53);
--GC1L53 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~611
--operation mode is arithmetic
GC1L53 = AMPP_FUNCTION(L1L590, L1L656, GC1L55);
--GC1L55 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~613
--operation mode is arithmetic
GC1L55 = AMPP_FUNCTION(L1L589, L1L655, GC1L57);
--GC1L57 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~615
--operation mode is arithmetic
GC1L57 = AMPP_FUNCTION(L1L588, L1L654, GC1L59);
--GC1L59 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~617
--operation mode is arithmetic
GC1L59 = AMPP_FUNCTION(L1L587, L1L653, GC1L61);
--GC1L61 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~619
--operation mode is arithmetic
GC1L61 = AMPP_FUNCTION(L1L586, L1L652, GC1L63);
--GC1L63 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~621
--operation mode is arithmetic
GC1L63 = AMPP_FUNCTION(L1L585, L1L651, GC1L65);
--GC1L65 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~623
--operation mode is arithmetic
GC1L65 = AMPP_FUNCTION(L1L584, L1L650);
--EB1L4 is std_1s10:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1~46
--operation mode is normal
EB1L4 = L1_M_alu_result[5] & !L1_M_alu_result[6] & (L1_internal_d_write # L1_internal_d_read);
--W1L30 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|LessThan0~90
--operation mode is normal
W1L30 = !W1_lcd_display_control_slave_wait_counter[5] & !W1_lcd_display_control_slave_wait_counter[4] & W1L28;
--V1L5 is std_1s10:inst|lcd_display:the_lcd_display|LCD_E~445
--operation mode is normal
V1L5 = W1_lcd_display_control_slave_wait_counter[4] & (W1_lcd_display_control_slave_wait_counter[3] & V1L2) # !W1_lcd_display_control_slave_wait_counter[4] & !W1_lcd_display_control_slave_wait_counter[5] & (!V1L2 # !W1_lcd_display_control_slave_wait_counter[3]);
--Q1L71 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_flash_s1~274
--operation mode is normal
Q1L71 = !L1_M_alu_result[24] & !L1_M_alu_result[23] & (L1_internal_d_write # L1_internal_d_read);
--AB1L9 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_requests_onchip_ram_64_kbytes_s1~300
--operation mode is normal
AB1L9 = !L1_M_alu_result[16] & (L1_internal_d_write # L1_internal_d_read);
--Q1_cpu_instruction_master_arbiterlock is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_arbiterlock
--operation mode is normal
Q1_cpu_instruction_master_arbiterlock = Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable & (Q1L79 # Q1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 & Q1L94);
--Q1L48 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_lan91c111_s1~119
--operation mode is normal
Q1L48 = Q1L57 & !Q1_cpu_instruction_master_arbiterlock & (Q1L8 # Q1L10);
--Q1L286 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~39
--operation mode is normal
Q1L286 = !L1_ic_fill_tag[8] & !L1_ic_fill_tag[9] & !L1_ic_fill_tag[10] & AB1L13;
--FB1L171 is std_1s10:inst|sdram:the_sdram|m_cmd~50
--operation mode is normal
FB1L171 = FB1_f_pop & (FB1L554 # !EE1_entries[0] & !EE1_entries[1]);
--FB1L266 is std_1s10:inst|sdram:the_sdram|Mux19~1739
--operation mode is normal
FB1L266 = !FB1_m_state[4] & !FB1_m_state[3] & !FB1_init_done & FB1_i_cmd[1];
--L1_W_stall is std_1s10:inst|cpu:the_cpu|W_stall
--operation mode is normal
L1_W_stall = AMPP_FUNCTION(L1_internal_d_write, M1_internal_cpu_data_master_waitrequest, L1L1443);
--X1L13 is std_1s10:inst|led_pio:the_led_pio|process0~53
--operation mode is normal
X1L13 = L1_M_alu_result[7] & !L1_M_alu_result[5] & P1L7 & NB1L2;
--FB1_f_select is std_1s10:inst|sdram:the_sdram|f_select
--operation mode is normal
FB1_f_select = FB1_f_pop & !FB1L554 & (EE1_entries[0] # EE1_entries[1]);
--FB1L455 is std_1s10:inst|sdram:the_sdram|Mux108~1489
--operation mode is normal
FB1L455 = FB1L451 # FB1_m_addr[7] & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L462 is std_1s10:inst|sdram:the_sdram|Mux109~1355
--operation mode is normal
FB1L462 = FB1L459 # FB1_m_addr[6] & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L469 is std_1s10:inst|sdram:the_sdram|Mux110~1395
--operation mode is normal
FB1L469 = FB1L466 # FB1_m_addr[5] & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L476 is std_1s10:inst|sdram:the_sdram|Mux111~1322
--operation mode is normal
FB1L476 = FB1L473 # FB1_m_addr[4] & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L483 is std_1s10:inst|sdram:the_sdram|Mux112~1354
--operation mode is normal
FB1L483 = FB1L480 # FB1_m_addr[3] & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L490 is std_1s10:inst|sdram:the_sdram|Mux113~1354
--operation mode is normal
FB1L490 = FB1L487 # FB1_m_addr[2] & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L497 is std_1s10:inst|sdram:the_sdram|Mux114~1354
--operation mode is normal
FB1L497 = FB1L494 # FB1_m_addr[1] & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L504 is std_1s10:inst|sdram:the_sdram|Mux115~1354
--operation mode is normal
FB1L504 = FB1L501 # FB1_m_addr[0] & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L511 is std_1s10:inst|sdram:the_sdram|Mux118~1215
--operation mode is normal
FB1L511 = !FB1_m_state[5] & !FB1_m_state[6] & FB1L278 & !FB1_m_state[8];
--GB1L18 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_requests_sdram_s1~431
--operation mode is normal
GB1L18 = L1_M_alu_result[24] & !L1_M_alu_result[25] & (L1_internal_d_write # L1_internal_d_read);
--P1L8 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~308
--operation mode is normal
P1L8 = !L1_M_alu_result[11] & (L1_internal_d_write # L1_internal_d_read);
--P1L14 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~63
--operation mode is normal
P1L14 = !L1_ic_fill_tag[1] & !L1_ic_fill_tag[0] & !L1_ic_fill_line[6] & P1L12;
--L1_D_ic_fill_starting is std_1s10:inst|cpu:the_cpu|D_ic_fill_starting
--operation mode is normal
L1_D_ic_fill_starting = AMPP_FUNCTION(L1_ic_fill_active, L1_M_pipe_flush, L1L240);
--Q1_ext_flash_s1_in_a_read_cycle is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_in_a_read_cycle
--operation mode is normal
Q1_ext_flash_s1_in_a_read_cycle = Q1L63 # N1L146 & (Q1L16 # Q1L18);
--GE1L36 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|updated_one_count~65
--operation mode is normal
GE1L36 = GB1L19 & (EE1_entries[0] # !EE1_entries[1]);
--GE1L5 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1203
--operation mode is normal
GE1L5 = GE1_how_many_ones[1] & GE1_how_many_ones[0] & (!GE1_stage_0 # !FB1_za_valid) # !GE1_how_many_ones[1] & FB1_za_valid & GE1_stage_0 & !GE1_how_many_ones[0];
--GE1L6 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1204
--operation mode is normal
GE1L6 = GE1L36 $ GE1_how_many_ones[0] $ (FB1_za_valid & GE1_stage_0);
--M1L18 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1060
--operation mode is normal
M1L18 = GB1L17 & (EE1_entries[1] & !EE1_entries[0] # !GB1L15);
--Q1L28 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~377
--operation mode is normal
Q1L28 = Q1L71 & Q1L73 & !Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] & !Q1L56;
--P1_cpu_data_master_requests_cpu_jtag_debug_module is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module
--operation mode is normal
P1_cpu_data_master_requests_cpu_jtag_debug_module = !L1_M_alu_result[11] & P1L7 & (L1_internal_d_write # L1_internal_d_read);
--AB1L1 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|Add2~231
--operation mode is normal
AB1L1 = AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (AB1L2 & AB1L11 & !AB1_onchip_ram_64_kbytes_s1_arb_addend[1] # !AB1L2 & !AB1L11) # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (!AB1L11);
--T1L56 is std_1s10:inst|jtag_uart:the_jtag_uart|process2~44
--operation mode is normal
T1L56 = !L1_M_alu_result[7] & !L1_M_alu_result[3] & EB1L2 & T1L54;
--J1L3 is std_1s10:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~363
--operation mode is normal
J1L3 = L1_M_alu_result[6] & (L1_internal_d_write # L1_internal_d_read);
--Q1L242 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_counter_load_value~104
--operation mode is normal
Q1L242 = !Q1_d1_ext_ram_bus_avalon_slave_end_xfer & !Q1L190 & L1_internal_d_write & Q1L48;
--FB1L283 is std_1s10:inst|sdram:the_sdram|Mux24~1464
--operation mode is normal
FB1L283 = !FB1_m_count[2] & !FB1_m_count[1] & FB1L281 & FB1L282;
--FB1L275 is std_1s10:inst|sdram:the_sdram|Mux22~1320
--operation mode is normal
FB1L275 = FB1_m_state[0] & (!FB1_m_state[2] & !FB1L574 # !FB1_m_state[8]);
--FB1L276 is std_1s10:inst|sdram:the_sdram|Mux22~1321
--operation mode is normal
FB1L276 = FB1_m_state[2] & !FB1_m_count[2] & !FB1_m_count[1] & FB1_m_next[1];
--FB1L309 is std_1s10:inst|sdram:the_sdram|Mux28~1612
--operation mode is normal
FB1L309 = FB1_m_count[2] # FB1_m_count[1] # FB1_m_next[1] # !FB1L379;
--FB1L294 is std_1s10:inst|sdram:the_sdram|Mux26~1227
--operation mode is normal
FB1L294 = !FB1L554 & !FB1_refresh_request & (EE1_entries[0] # EE1_entries[1]);
--FB1L298 is std_1s10:inst|sdram:the_sdram|Mux27~1230
--operation mode is normal
FB1L298 = FB1_m_state[0] & !FB1_m_state[2] & FB1L547 & !FB1_m_state[8];
--EE1L62 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56]~56
--operation mode is normal
EE1L62 = FB1L237 & !EE1_wr_address & (EE1_entries[0] # !EE1_entries[1]);
--EE1L123 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[56]~56
--operation mode is normal
EE1L123 = FB1L237 & EE1_wr_address & (EE1_entries[0] # !EE1_entries[1]);
--FB1L221 is std_1s10:inst|sdram:the_sdram|m_next~830
--operation mode is normal
FB1L221 = FB1_refresh_request & !FB1L554 & (EE1_entries[0] # EE1_entries[1]);
--FB1L222 is std_1s10:inst|sdram:the_sdram|m_next~831
--operation mode is normal
FB1L222 = FB1_refresh_request # FB1L554 & (EE1_entries[0] # EE1_entries[1]);
--FB1L335 is std_1s10:inst|sdram:the_sdram|Mux36~1270
--operation mode is normal
FB1L335 = FB1_m_next[3] & (FB1_m_state[4] $ !FB1_m_state[3] # !FB1L221);
--FB1L328 is std_1s10:inst|sdram:the_sdram|Mux35~1200
--operation mode is normal
FB1L328 = FB1_m_next[4] & (FB1_m_state[4] $ !FB1_m_state[3] # !FB1L221);
--L1L1346 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[2]~3709
--operation mode is normal
L1L1346 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[2], L1_M_ctrl_mul_shift_rot, L1L1345);
--L1_D_ctrl_b_not_src is std_1s10:inst|cpu:the_cpu|D_ctrl_b_not_src
--operation mode is normal
L1_D_ctrl_b_not_src = AMPP_FUNCTION(L1_D_iw[4], L1L809, L1_D_iw[5], L1L197);
--L1L219 is std_1s10:inst|cpu:the_cpu|D_ctrl_jmp_indirect~38
--operation mode is normal
L1L219 = AMPP_FUNCTION(L1_D_iw[4], L1_D_iw[5], L1L808, L1_D_iw[12]);
--L1L1349 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[3]~3710
--operation mode is normal
L1L1349 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[3], L1_M_ctrl_mul_shift_rot, L1L1348);
--L1L1361 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[7]~3711
--operation mode is normal
L1L1361 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[7], L1_M_ctrl_mul_shift_rot, L1L1360);
--L1_E_hbreak_req is std_1s10:inst|cpu:the_cpu|E_hbreak_req
--operation mode is normal
L1_E_hbreak_req = AMPP_FUNCTION(L1_E_iw[13], L1_E_iw[14], L1L968, L1L483);
--L1L80 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogic~268
--operation mode is normal
L1L80 = AMPP_FUNCTION(L1_internal_d_write, M1_internal_cpu_data_master_waitrequest, L1L1443, L1L799);
--L1L1352 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[4]~3712
--operation mode is normal
L1L1352 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[4], L1_M_ctrl_mul_shift_rot, L1L1351);
--L1L1406 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[22]~3713
--operation mode is normal
L1L1406 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[22], L1_M_ctrl_mul_shift_rot, L1L1405);
--L1L1403 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[21]~3714
--operation mode is normal
L1L1403 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[21], L1_M_ctrl_mul_shift_rot, L1L1402);
--L1L1412 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[24]~3715
--operation mode is normal
L1L1412 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[24], L1_M_ctrl_mul_shift_rot, L1L1411);
--L1L1397 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[19]~3716
--operation mode is normal
L1L1397 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[19], L1_M_ctrl_mul_shift_rot, L1L1396);
--L1L1394 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[18]~3717
--operation mode is normal
L1L1394 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[18], L1_M_ctrl_mul_shift_rot, L1L1393);
--L1L1391 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[17]~3718
--operation mode is normal
L1L1391 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[17], L1_M_ctrl_mul_shift_rot, L1L1390);
--L1L1388 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[16]~3719
--operation mode is normal
L1L1388 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[16], L1_M_ctrl_mul_shift_rot, L1L1387);
--L1L1409 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[23]~3720
--operation mode is normal
L1L1409 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[23], L1_M_ctrl_mul_shift_rot, L1L1408);
--L1L1415 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[25]~3721
--operation mode is normal
L1L1415 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[25], L1_M_ctrl_mul_shift_rot, L1L1414);
--L1L1400 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[20]~3722
--operation mode is normal
L1L1400 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[20], L1_M_ctrl_mul_shift_rot, L1L1399);
--L1L1385 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[15]~3723
--operation mode is normal
L1L1385 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[15], L1_M_ctrl_mul_shift_rot, L1L1384);
--L1L1382 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[14]~3724
--operation mode is normal
L1L1382 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[14], L1_M_ctrl_mul_shift_rot, L1L1381);
--L1L1379 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[13]~3725
--operation mode is normal
L1L1379 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[13], L1_M_ctrl_mul_shift_rot, L1L1378);
--L1L1376 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[12]~3726
--operation mode is normal
L1L1376 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[12], L1_M_ctrl_mul_shift_rot, L1L1375);
--L1L1373 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[11]~3727
--operation mode is normal
L1L1373 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[11], L1_M_ctrl_mul_shift_rot, L1L1372);
--L1L1370 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[10]~3728
--operation mode is normal
L1L1370 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[10], L1_M_ctrl_mul_shift_rot, L1L1369);
--L1L1367 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[9]~3729
--operation mode is normal
L1L1367 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[9], L1_M_ctrl_mul_shift_rot, L1L1366);
--L1L1364 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[8]~3730
--operation mode is normal
L1L1364 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[8], L1_M_ctrl_mul_shift_rot, L1L1363);
--L1L1355 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[5]~3731
--operation mode is normal
L1L1355 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[5], L1_M_ctrl_mul_shift_rot, L1L1354);
--L1L1358 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[6]~3732
--operation mode is normal
L1L1358 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[6], L1_M_ctrl_mul_shift_rot, L1L1357);
--L1L1343 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[1]~3733
--operation mode is normal
L1L1343 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[1], L1_M_ctrl_mul_shift_rot, L1L1342);
--L1L1340 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[0]~3734
--operation mode is normal
L1L1340 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[0], L1_M_ctrl_mul_shift_rot, L1L1339);
--FE1L5 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1196
--operation mode is normal
FE1L5 = FE1_how_many_ones[1] & FE1_how_many_ones[0] & (!FE1_stage_0 # !FB1_za_valid) # !FE1_how_many_ones[1] & FB1_za_valid & FE1_stage_0 & !FE1_how_many_ones[0];
--FE1L6 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1197
--operation mode is normal
FE1L6 = FE1L21 $ FE1_how_many_ones[0] $ (FB1_za_valid & FE1_stage_0);
--GB1L75 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_end_xfer~18
--operation mode is normal
GB1L75 = EE1_entries[1] & !EE1_entries[0] & FB1L237;
--FB1L364 is std_1s10:inst|sdram:the_sdram|Mux40~1452
--operation mode is normal
FB1L364 = !FB1_m_state[4] & !FB1_m_state[3] & FB1L350;
--FB1L377 is std_1s10:inst|sdram:the_sdram|Mux41~1461
--operation mode is normal
FB1L377 = FB1_m_state[0] & !FB1_m_state[3] & FB1L350;
--FB1L378 is std_1s10:inst|sdram:the_sdram|Mux41~1462
--operation mode is normal
FB1L378 = FB1_m_count[1] & (!FB1L350 # !FB1_refresh_request # !FB1_init_done);
--L1L229 is std_1s10:inst|cpu:the_cpu|D_ctrl_wrctl_inst~24
--operation mode is normal
L1L229 = AMPP_FUNCTION(L1_D_iw[4], L1_D_iw[5], L1_D_iw[12], L1L808);
--U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave is std_1s10:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave|cpu_data_master_requests_jtag_uart_avalon_jtag_slave
--operation mode is normal
U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave = !L1_M_alu_result[7] & !L1_M_alu_result[3] & EB1L2;
--S1_cpu_data_master_requests_high_res_timer_s1 is std_1s10:inst|high_res_timer_s1_arbitrator:the_high_res_timer_s1|cpu_data_master_requests_high_res_timer_s1
--operation mode is normal
S1_cpu_data_master_requests_high_res_timer_s1 = L1_M_alu_result[6] & L1_M_alu_result[5] & LB1L2;
--M1L45 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5018
--operation mode is normal
M1L45 = M1L42 & (Q1_internal_incoming_ext_ram_bus_data[2] # !Q1L73 # !Q1L71);
--QB1_cpu_data_master_granted_uart1_s1 is std_1s10:inst|uart1_s1_arbitrator:the_uart1_s1|cpu_data_master_granted_uart1_s1
--operation mode is normal
QB1_cpu_data_master_granted_uart1_s1 = L1_M_alu_result[6] & !L1_M_alu_result[5] & LB1L2;
--LB1_cpu_data_master_requests_sys_clk_timer_s1 is std_1s10:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1
--operation mode is normal
LB1_cpu_data_master_requests_sys_clk_timer_s1 = !L1_M_alu_result[6] & !L1_M_alu_result[5] & LB1L2;
--M1L226 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~327
--operation mode is normal
M1L226 = R1_readdata[3] # !LB1L2 # !L1_M_alu_result[5] # !L1_M_alu_result[6];
--M1L54 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5019
--operation mode is normal
M1L54 = M1L51 & (Q1_internal_incoming_ext_ram_bus_data[3] # !Q1L73 # !Q1L71);
--M1L88 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5020
--operation mode is normal
M1L88 = M1L84 & (Q1_internal_incoming_ext_ram_bus_data[7] # !Q1L73 # !Q1L71);
--L1L214 is std_1s10:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~734
--operation mode is normal
L1L214 = AMPP_FUNCTION(L1_D_iw[4], L1_D_iw[5], L1L815, L1L812);
--L1L817 is std_1s10:inst|cpu:the_cpu|Equal53~790
--operation mode is normal
L1L817 = AMPP_FUNCTION(L1_D_iw[4], L1_D_iw[5], L1L808);
--M1L62 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5021
--operation mode is normal
M1L62 = M1L58 & (Q1_internal_incoming_ext_ram_bus_data[4] # !Q1L73 # !Q1L71);
--M1L180 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5022
--operation mode is normal
M1L180 = M1L178 & (Q1_internal_incoming_ext_ram_bus_data[22] # !Q1L73 # !Q1L71);
--M1L112 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5023
--operation mode is normal
M1L112 = !QB1_cpu_data_master_granted_uart1_s1 & (!L1_M_alu_result[7] & !L1_M_alu_result[4] # !EB1L3);
--M1L230 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~339
--operation mode is normal
M1L230 = R1_readdata[15] # !LB1L2 # !L1_M_alu_result[5] # !L1_M_alu_result[6];
--M1L175 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~5024
--operation mode is normal
M1L175 = M1L145 & M1L174 & (!NB1_cpu_data_master_granted_sysid_control_slave # !L1_M_alu_result[2]);
--M1L150 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5025
--operation mode is normal
M1L150 = M1L145 & M1L149 & (!NB1_cpu_data_master_granted_sysid_control_slave # !L1_M_alu_result[2]);
--M1L138 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~5026
--operation mode is normal
M1L138 = M1L135 & (Q1_internal_incoming_ext_ram_bus_data[14] # !Q1L73 # !Q1L71);
--M1L220 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~5027
--operation mode is normal
M1L220 = M1L218 & (Q1_internal_incoming_ext_ram_bus_data[30] # !Q1L73 # !Q1L71);
--M1L229 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~337
--operation mode is normal
M1L229 = R1_readdata[13] # !LB1L2 # !L1_M_alu_result[5] # !L1_M_alu_result[6];
--M1L215 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~5028
--operation mode is normal
M1L215 = M1L145 & M1L214 & (!NB1_cpu_data_master_granted_sysid_control_slave # !L1_M_alu_result[2]);
--M1L228 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~335
--operation mode is normal
M1L228 = R1_readdata[11] # !LB1L2 # !L1_M_alu_result[5] # !L1_M_alu_result[6];
--M1L205 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~5029
--operation mode is normal
M1L205 = M1L145 & M1L204 & (!NB1_cpu_data_master_granted_sysid_control_slave # !L1_M_alu_result[2]);
--M1L227 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~333
--operation mode is normal
M1L227 = R1_readdata[9] # !LB1L2 # !L1_M_alu_result[5] # !L1_M_alu_result[6];
--M1L104 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5030
--operation mode is normal
M1L104 = M1L101 & (Q1_internal_incoming_ext_ram_bus_data[9] # !Q1L73 # !Q1L71);
--M1L95 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5031
--operation mode is normal
M1L95 = M1L92 & (Q1_internal_incoming_ext_ram_bus_data[8] # !Q1L73 # !Q1L71);
--M1L96 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5032
--operation mode is normal
M1L96 = L1_M_alu_result[7] & !G1L1 & (HE1_readdata[8] # !QB1_cpu_data_master_granted_uart1_s1) # !L1_M_alu_result[7] & (HE1_readdata[8] # !QB1_cpu_data_master_granted_uart1_s1);
--M1L231 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~642
--operation mode is normal
M1L231 = L1_M_alu_result[6] # L1_M_alu_result[5] # KB1_readdata[5] # !LB1L2;
--M1L71 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5033
--operation mode is normal
M1L71 = M1L69 & (Q1_internal_incoming_ext_ram_bus_data[5] # !Q1L73 # !Q1L71);
--M1L79 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5034
--operation mode is normal
M1L79 = M1L75 & (Q1_internal_incoming_ext_ram_bus_data[6] # !Q1L73 # !Q1L71);
--C1L5 is sld_hub:sld_hub_inst|comb~97
--operation mode is normal
C1L5 = AMPP_FUNCTION(altera_internal_jtag, ME3_Q[6], C1L4, A1L8);
--QD1L62 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3523
--operation mode is normal
QD1L62 = AMPP_FUNCTION(QD1_state, QD1_count[1], QD1_td_shift[9], QD1_user_saw_rvalid);
--DD1L141 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process2~2
--operation mode is normal
DD1L141 = AMPP_FUNCTION(A1L5, DD1_in_between_shiftdr_and_updatedr, DD1L144);
--DB1L3 is std_1s10:inst|reconfig_request_pio:the_reconfig_request_pio|process2~24
--operation mode is normal
DB1L3 = L1_internal_d_write & !M1_internal_cpu_data_master_waitrequest & L1_M_alu_result[7] & EB1L2;
--GB1L73 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_winner~0
--operation mode is normal
GB1L73 = GB1_WideOr1 & (!GB1L13 & !GB1L70 # !GB1_sdram_s1_slavearbiterlockenable);
--GB1L58 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_counter_enable~43
--operation mode is normal
GB1L58 = GB1L57 & (EE1_entries[0] # !FB1L237 # !EE1_entries[1]);
--L1L865 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[0]~4256
--operation mode is normal
L1L865 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1L863, L1_D_pc[3]);
--L1L868 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[1]~4257
--operation mode is normal
L1L868 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1L866, L1_D_pc[4]);
--L1L871 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[2]~4258
--operation mode is normal
L1L871 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1L869, L1_D_pc[5]);
--L1L874 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[3]~4259
--operation mode is normal
L1L874 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1L872, L1_D_pc[6]);
--L1L877 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[4]~4260
--operation mode is normal
L1L877 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1L875, L1_D_pc[7]);
--L1L880 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~4261
--operation mode is normal
L1L880 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1L878, L1_D_pc[8]);
--L1L883 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[6]~4262
--operation mode is normal
L1L883 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1L881, L1_D_pc[9]);
--L1L839 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[2]~1824
--operation mode is normal
L1L839 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1L837, L1_D_pc[2]);
--L1L836 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[1]~1825
--operation mode is normal
L1L836 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1L834, L1_D_pc[1]);
--L1L833 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[0]~1826
--operation mode is normal
L1L833 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1L831, L1_D_pc[0]);
--L1L1333 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie~155
--operation mode is normal
L1L1333 = AMPP_FUNCTION(L1_E_ctrl_break, L1_E_ctrl_exception, L1L548, L1_E_wrctl_status);
--L1L1334 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie~156
--operation mode is normal
L1L1334 = AMPP_FUNCTION(L1_E_ctrl_break, L1_E_ctrl_exception, L1L800, L1_W_stall);
--M1L308 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|process3~0
--operation mode is normal
M1L308 = !M1_internal_cpu_data_master_dbs_address[1] & !M1_internal_cpu_data_master_dbs_address[0] & M1L307;
--CD1L62 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|module_input6~23
--operation mode is normal
CD1L62 = AMPP_FUNCTION(L1_internal_d_write, L1_hbreak_enabled, P1L3, L1_M_alu_result[10]);
--T1L38 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~317
--operation mode is normal
T1L38 = L1_M_alu_result[7] # L1_M_alu_result[3] # T1L34 # !EB1L2;
--T1L39 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~318
--operation mode is normal
T1L39 = L1_M_alu_result[7] # L1_M_alu_result[3] # T1L35 # !EB1L2;
--M1L27 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5035
--operation mode is normal
M1L27 = M1L22 & (Q1_internal_incoming_ext_ram_bus_data[0] # !Q1L73 # !Q1L71);
--M1L36 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5036
--operation mode is normal
M1L36 = M1L31 & (Q1_internal_incoming_ext_ram_bus_data[1] # !Q1L73 # !Q1L71);
--L1L1335 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie~157
--operation mode is normal
L1L1335 = AMPP_FUNCTION(L1_internal_d_write, M1_internal_cpu_data_master_waitrequest, L1L1443, L1L800);
--WD2L1 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|_~28
--operation mode is normal
WD2L1 = QD1L37Q & (WD2_b_full $ (!T1L43 # !WD2_b_non_empty)) # !QD1L37Q & (WD2_b_non_empty & T1L43);
--L1L1418 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[26]~3735
--operation mode is normal
L1L1418 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[26], L1_M_ctrl_mul_shift_rot, L1L1417);
--L1L1421 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[27]~3736
--operation mode is normal
L1L1421 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[27], L1_M_ctrl_mul_shift_rot, L1L1420);
--L1L1424 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[28]~3737
--operation mode is normal
L1L1424 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[28], L1_M_ctrl_mul_shift_rot, L1L1423);
--L1L1427 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[29]~3738
--operation mode is normal
L1L1427 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[29], L1_M_ctrl_mul_shift_rot, L1L1426);
--L1L1430 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3739
--operation mode is normal
L1L1430 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[30], L1_M_ctrl_mul_shift_rot, L1L1429);
--L1L1433 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3740
--operation mode is normal
L1L1433 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[31], L1_M_ctrl_mul_shift_rot, L1L1432);
--DD1L70 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19987
--operation mode is normal
DD1L70 = AMPP_FUNCTION(A1L5, DD1_in_between_shiftdr_and_updatedr, DD1L144, DD1_ir[0]);
--DD1L71 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19988
--operation mode is normal
DD1L71 = AMPP_FUNCTION(DD1L134, DD1L135, DD1L55, DD1L143);
--L1L193 is std_1s10:inst|cpu:the_cpu|D_ctrl_alu_subtract~411
--operation mode is normal
L1L193 = AMPP_FUNCTION(L1_D_iw[15], L1_D_iw[14], L1_D_iw[13]);
--L1L206 is std_1s10:inst|cpu:the_cpu|D_ctrl_dst_data_sel_cmp~275
--operation mode is normal
L1L206 = AMPP_FUNCTION(L1_D_iw[15], L1_D_iw[14], L1_D_iw[13]);
--L1L215 is std_1s10:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~735
--operation mode is normal
L1L215 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[11]);
--L1L208 is std_1s10:inst|cpu:the_cpu|D_ctrl_dst_data_sel_pc_plus_one~92
--operation mode is normal
L1L208 = AMPP_FUNCTION(L1_D_iw[13], L1_D_iw[16]);
--L1L222 is std_1s10:inst|cpu:the_cpu|D_ctrl_mul_shift_rot~229
--operation mode is normal
L1L222 = AMPP_FUNCTION(L1_D_iw[13], L1_D_iw[11]);
--L1L194 is std_1s10:inst|cpu:the_cpu|D_ctrl_alu_subtract~412
--operation mode is normal
L1L194 = AMPP_FUNCTION(L1_D_iw[1], L1_D_iw[2], L1_D_iw[3], L1_D_iw[0]);
--QD1L63 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3524
--operation mode is normal
QD1L63 = AMPP_FUNCTION(QD1L51, QD1_state, RE1_state[4], ME4_Q[0]);
--QD1L51 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3485
--operation mode is normal
QD1L51 = AMPP_FUNCTION(QD1_user_saw_rvalid, QD1_td_shift[9], QD1_count[1]);
--L1L818 is std_1s10:inst|cpu:the_cpu|Equal53~791
--operation mode is normal
L1L818 = AMPP_FUNCTION(L1_D_iw[0], L1_D_iw[1], L1_D_iw[2], L1_D_iw[3]);
--L1L202 is std_1s10:inst|cpu:the_cpu|D_ctrl_br~19
--operation mode is normal
L1L202 = AMPP_FUNCTION(L1_D_iw[1], L1_D_iw[2], L1_D_iw[0]);
--L1L400 is std_1s10:inst|cpu:the_cpu|D_wr_dst_reg~83
--operation mode is normal
L1L400 = AMPP_FUNCTION(L1_D_iw[0], L1_D_iw[1], L1_D_iw[2]);
--L1L401 is std_1s10:inst|cpu:the_cpu|D_wr_dst_reg~88
--operation mode is normal
L1L401 = AMPP_FUNCTION(L1L400, L1_D_issue, L1_M_pipe_flush);
--L1L402 is std_1s10:inst|cpu:the_cpu|D_wr_dst_reg~89
--operation mode is normal
L1L402 = AMPP_FUNCTION(L1_D_iw[1], L1_D_iw[0]);
--L1L226 is std_1s10:inst|cpu:the_cpu|D_ctrl_unsigned_lo_imm~281
--operation mode is normal
L1L226 = AMPP_FUNCTION(L1_D_iw[2], L1_D_iw[3], L1_D_iw[4], L1_D_iw[5]);
--L1L227 is std_1s10:inst|cpu:the_cpu|D_ctrl_unsigned_lo_imm~284
--operation mode is normal
L1L227 = AMPP_FUNCTION(L1L226, L1_D_iw[1], L1_D_iw[0]);
--FB1L389 is std_1s10:inst|sdram:the_sdram|Mux42~1477
--operation mode is normal
FB1L389 = FB1_m_state[3] & FB1_m_count[0] & (FB1_m_state[4] # !FB1L383) # !FB1_m_state[3] & (FB1_m_count[0] # FB1L383 # !FB1_m_state[4]);
--FB1L390 is std_1s10:inst|sdram:the_sdram|Mux42~1478
--operation mode is normal
FB1L390 = FB1L389 & (FB1_m_state[3] # FB1_m_state[4] # FB1L387);
--A1L275 is ~GND
--operation mode is normal
A1L275 = GND;
--PLD_CLOCKINPUT is PLD_CLOCKINPUT
--operation mode is input
PLD_CLOCKINPUT = INPUT();
--PLD_CLEAR_N is PLD_CLEAR_N
--operation mode is input
PLD_CLEAR_N = INPUT();
--in_port_to_the_button_pio[2] is in_port_to_the_button_pio[2]
--operation mode is input
in_port_to_the_button_pio[2] = INPUT();
--in_port_to_the_button_pio[3] is in_port_to_the_button_pio[3]
--operation mode is input
in_port_to_the_button_pio[3] = INPUT();
--irq_from_the_lan91c111 is irq_from_the_lan91c111
--operation mode is input
irq_from_the_lan91c111 = INPUT();
--in_port_to_the_button_pio[1] is in_port_to_the_button_pio[1]
--operation mode is input
in_port_to_the_button_pio[1] = INPUT();
--in_port_to_the_button_pio[0] is in_port_to_the_button_pio[0]
--operation mode is input
in_port_to_the_button_pio[0] = INPUT();
--rxd_to_the_uart1 is rxd_to_the_uart1
--operation mode is input
rxd_to_the_uart1 = INPUT();
--ENET_ADS_N is ENET_ADS_N
--operation mode is output
ENET_ADS_N = OUTPUT(GND);
--ENET_AEN is ENET_AEN
--operation mode is output
ENET_AEN = OUTPUT(GND);
--ior_n_to_the_lan91c111 is ior_n_to_the_lan91c111
--operation mode is output
ior_n_to_the_lan91c111 = OUTPUT(!Q1_ior_n_to_the_lan91c111);
--write_n_to_the_ext_flash is write_n_to_the_ext_flash
--operation mode is output
write_n_to_the_ext_flash = OUTPUT(!Q1_write_n_to_the_ext_flash);
--iow_n_to_the_lan91c111 is iow_n_to_the_lan91c111
--operation mode is output
iow_n_to_the_lan91c111 = OUTPUT(!Q1_iow_n_to_the_lan91c111);
--read_n_to_the_ext_flash is read_n_to_the_ext_flash
--operation mode is output
read_n_to_the_ext_flash = OUTPUT(!Q1_read_n_to_the_ext_flash);
--read_n_to_the_ext_ram is read_n_to_the_ext_ram
--operation mode is output
read_n_to_the_ext_ram = OUTPUT(!Q1_read_n_to_the_ext_ram);
--select_n_to_the_ext_ram is select_n_to_the_ext_ram
--operation mode is output
select_n_to_the_ext_ram = OUTPUT(!Q1_select_n_to_the_ext_ram);
--write_n_to_the_ext_ram is write_n_to_the_ext_ram
--operation mode is output
write_n_to_the_ext_ram = OUTPUT(!Q1L301);
--zs_cas_n_from_the_sdram is zs_cas_n_from_the_sdram
--operation mode is output
zs_cas_n_from_the_sdram = OUTPUT(!FB1_m_cmd[1]);
--zs_cke_from_the_sdram is zs_cke_from_the_sdram
--operation mode is output
zs_cke_from_the_sdram = OUTPUT(VCC);
--zs_cs_n_from_the_sdram is zs_cs_n_from_the_sdram
--operation mode is output
zs_cs_n_from_the_sdram = OUTPUT(!FB1_m_cmd[3]);
--zs_ras_n_from_the_sdram is zs_ras_n_from_the_sdram
--operation mode is output
zs_ras_n_from_the_sdram = OUTPUT(!FB1_m_cmd[2]);
--zs_we_n_from_the_sdram is zs_we_n_from_the_sdram
--operation mode is output
zs_we_n_from_the_sdram = OUTPUT(!FB1_m_cmd[0]);
--LCD_RW_from_the_lcd_display is LCD_RW_from_the_lcd_display
--operation mode is output
LCD_RW_from_the_lcd_display = OUTPUT(L1_M_alu_result[2]);
--LCD_RS_from_the_lcd_display is LCD_RS_from_the_lcd_display
--operation mode is output
LCD_RS_from_the_lcd_display = OUTPUT(L1_M_alu_result[3]);
--LCD_E_from_the_lcd_display is LCD_E_from_the_lcd_display
--operation mode is output
LCD_E_from_the_lcd_display = OUTPUT(V1L4);
--txd_from_the_uart1 is txd_from_the_uart1
--operation mode is output
txd_from_the_uart1 = OUTPUT(!KE1_txd);
--select_n_to_the_ext_flash is select_n_to_the_ext_flash
--operation mode is output
select_n_to_the_ext_flash = OUTPUT(!Q1_select_n_to_the_ext_flash);
--SDRAM_CLKOUT is SDRAM_CLKOUT
--operation mode is output
SDRAM_CLKOUT = OUTPUT(DE1__extclk0);
--be_n_to_the_ext_ram[3] is be_n_to_the_ext_ram[3]
--operation mode is output
be_n_to_the_ext_ram[3] = OUTPUT(!Q1_be_n_to_the_ext_ram[3]);
--be_n_to_the_ext_ram[2] is be_n_to_the_ext_ram[2]
--operation mode is output
be_n_to_the_ext_ram[2] = OUTPUT(!Q1_be_n_to_the_ext_ram[2]);
--be_n_to_the_ext_ram[1] is be_n_to_the_ext_ram[1]
--operation mode is output
be_n_to_the_ext_ram[1] = OUTPUT(!Q1_be_n_to_the_ext_ram[1]);
--be_n_to_the_ext_ram[0] is be_n_to_the_ext_ram[0]
--operation mode is output
be_n_to_the_ext_ram[0] = OUTPUT(!Q1_be_n_to_the_ext_ram[0]);
--byteenablen_to_the_lan91c111[3] is byteenablen_to_the_lan91c111[3]
--operation mode is output
byteenablen_to_the_lan91c111[3] = OUTPUT(!Q1_byteenablen_to_the_lan91c111[3]);
--byteenablen_to_the_lan91c111[2] is byteenablen_to_the_lan91c111[2]
--operation mode is output
byteenablen_to_the_lan91c111[2] = OUTPUT(!Q1_byteenablen_to_the_lan91c111[2]);
--byteenablen_to_the_lan91c111[1] is byteenablen_to_the_lan91c111[1]
--operation mode is output
byteenablen_to_the_lan91c111[1] = OUTPUT(!Q1_byteenablen_to_the_lan91c111[1]);
--byteenablen_to_the_lan91c111[0] is byteenablen_to_the_lan91c111[0]
--operation mode is output
byteenablen_to_the_lan91c111[0] = OUTPUT(!Q1_byteenablen_to_the_lan91c111[0]);
--ext_ram_bus_address[22] is ext_ram_bus_address[22]
--operation mode is output
ext_ram_bus_address[22] = OUTPUT(Q1_ext_ram_bus_address[22]);
--ext_ram_bus_address[21] is ext_ram_bus_address[21]
--operation mode is output
ext_ram_bus_address[21] = OUTPUT(Q1_ext_ram_bus_address[21]);
--ext_ram_bus_address[20] is ext_ram_bus_address[20]
--operation mode is output
ext_ram_bus_address[20] = OUTPUT(Q1_ext_ram_bus_address[20]);
--ext_ram_bus_address[19] is ext_ram_bus_address[19]
--operation mode is output
ext_ram_bus_address[19] = OUTPUT(Q1_ext_ram_bus_address[19]);
--ext_ram_bus_address[18] is ext_ram_bus_address[18]
--operation mode is output
ext_ram_bus_address[18] = OUTPUT(Q1_ext_ram_bus_address[18]);
--ext_ram_bus_address[17] is ext_ram_bus_address[17]
--operation mode is output
ext_ram_bus_address[17] = OUTPUT(Q1_ext_ram_bus_address[17]);
--ext_ram_bus_address[16] is ext_ram_bus_address[16]
--operation mode is output
ext_ram_bus_address[16] = OUTPUT(Q1_ext_ram_bus_address[16]);
--ext_ram_bus_address[15] is ext_ram_bus_address[15]
--operation mode is output
ext_ram_bus_address[15] = OUTPUT(Q1_ext_ram_bus_address[15]);
--ext_ram_bus_address[14] is ext_ram_bus_address[14]
--operation mode is output
ext_ram_bus_address[14] = OUTPUT(Q1_ext_ram_bus_address[14]);
--ext_ram_bus_address[13] is ext_ram_bus_address[13]
--operation mode is output
ext_ram_bus_address[13] = OUTPUT(Q1_ext_ram_bus_address[13]);
--ext_ram_bus_address[12] is ext_ram_bus_address[12]
--operation mode is output
ext_ram_bus_address[12] = OUTPUT(Q1_ext_ram_bus_address[12]);
--ext_ram_bus_address[11] is ext_ram_bus_address[11]
--operation mode is output
ext_ram_bus_address[11] = OUTPUT(Q1_ext_ram_bus_address[11]);
--ext_ram_bus_address[10] is ext_ram_bus_address[10]
--operation mode is output
ext_ram_bus_address[10] = OUTPUT(Q1_ext_ram_bus_address[10]);
--ext_ram_bus_address[9] is ext_ram_bus_address[9]
--operation mode is output
ext_ram_bus_address[9] = OUTPUT(Q1_ext_ram_bus_address[9]);
--ext_ram_bus_address[8] is ext_ram_bus_address[8]
--operation mode is output
ext_ram_bus_address[8] = OUTPUT(Q1_ext_ram_bus_address[8]);
--ext_ram_bus_address[7] is ext_ram_bus_address[7]
--operation mode is output
ext_ram_bus_address[7] = OUTPUT(Q1_ext_ram_bus_address[7]);
--ext_ram_bus_address[6] is ext_ram_bus_address[6]
--operation mode is output
ext_ram_bus_address[6] = OUTPUT(Q1_ext_ram_bus_address[6]);
--ext_ram_bus_address[5] is ext_ram_bus_address[5]
--operation mode is output
ext_ram_bus_address[5] = OUTPUT(Q1_ext_ram_bus_address[5]);
--ext_ram_bus_address[4] is ext_ram_bus_address[4]
--operation mode is output
ext_ram_bus_address[4] = OUTPUT(Q1_ext_ram_bus_address[4]);
--ext_ram_bus_address[3] is ext_ram_bus_address[3]
--operation mode is output
ext_ram_bus_address[3] = OUTPUT(Q1_ext_ram_bus_address[3]);
--ext_ram_bus_address[2] is ext_ram_bus_address[2]
--operation mode is output
ext_ram_bus_address[2] = OUTPUT(Q1_ext_ram_bus_address[2]);
--ext_ram_bus_address[1] is ext_ram_bus_address[1]
--operation mode is output
ext_ram_bus_address[1] = OUTPUT(Q1_ext_ram_bus_address[1]);
--ext_ram_bus_address[0] is ext_ram_bus_address[0]
--operation mode is output
ext_ram_bus_address[0] = OUTPUT(Q1_ext_ram_bus_address[0]);
--out_port_from_the_led_pio[7] is out_port_from_the_led_pio[7]
--operation mode is output
out_port_from_the_led_pio[7] = OUTPUT(X1_data_out[7]);
--out_port_from_the_led_pio[6] is out_port_from_the_led_pio[6]
--operation mode is output
out_port_from_the_led_pio[6] = OUTPUT(X1_data_out[6]);
--out_port_from_the_led_pio[5] is out_port_from_the_led_pio[5]
--operation mode is output
out_port_from_the_led_pio[5] = OUTPUT(X1_data_out[5]);
--out_port_from_the_led_pio[4] is out_port_from_the_led_pio[4]
--operation mode is output
out_port_from_the_led_pio[4] = OUTPUT(X1_data_out[4]);
--out_port_from_the_led_pio[3] is out_port_from_the_led_pio[3]
--operation mode is output
out_port_from_the_led_pio[3] = OUTPUT(X1_data_out[3]);
--out_port_from_the_led_pio[2] is out_port_from_the_led_pio[2]
--operation mode is output
out_port_from_the_led_pio[2] = OUTPUT(X1_data_out[2]);
--out_port_from_the_led_pio[1] is out_port_from_the_led_pio[1]
--operation mode is output
out_port_from_the_led_pio[1] = OUTPUT(X1_data_out[1]);
--out_port_from_the_led_pio[0] is out_port_from_the_led_pio[0]
--operation mode is output
out_port_from_the_led_pio[0] = OUTPUT(X1_data_out[0]);
--out_port_from_the_seven_seg_pio[15] is out_port_from_the_seven_seg_pio[15]
--operation mode is output
out_port_from_the_seven_seg_pio[15] = OUTPUT(HB1_data_out[15]);
--out_port_from_the_seven_seg_pio[14] is out_port_from_the_seven_seg_pio[14]
--operation mode is output
out_port_from_the_seven_seg_pio[14] = OUTPUT(HB1_data_out[14]);
--out_port_from_the_seven_seg_pio[13] is out_port_from_the_seven_seg_pio[13]
--operation mode is output
out_port_from_the_seven_seg_pio[13] = OUTPUT(HB1_data_out[13]);
--out_port_from_the_seven_seg_pio[12] is out_port_from_the_seven_seg_pio[12]
--operation mode is output
out_port_from_the_seven_seg_pio[12] = OUTPUT(HB1_data_out[12]);
--out_port_from_the_seven_seg_pio[11] is out_port_from_the_seven_seg_pio[11]
--operation mode is output
out_port_from_the_seven_seg_pio[11] = OUTPUT(HB1_data_out[11]);
--out_port_from_the_seven_seg_pio[10] is out_port_from_the_seven_seg_pio[10]
--operation mode is output
out_port_from_the_seven_seg_pio[10] = OUTPUT(HB1_data_out[10]);
--out_port_from_the_seven_seg_pio[9] is out_port_from_the_seven_seg_pio[9]
--operation mode is output
out_port_from_the_seven_seg_pio[9] = OUTPUT(HB1_data_out[9]);
--out_port_from_the_seven_seg_pio[8] is out_port_from_the_seven_seg_pio[8]
--operation mode is output
out_port_from_the_seven_seg_pio[8] = OUTPUT(HB1_data_out[8]);
--out_port_from_the_seven_seg_pio[7] is out_port_from_the_seven_seg_pio[7]
--operation mode is output
out_port_from_the_seven_seg_pio[7] = OUTPUT(HB1_data_out[7]);
--out_port_from_the_seven_seg_pio[6] is out_port_from_the_seven_seg_pio[6]
--operation mode is output
out_port_from_the_seven_seg_pio[6] = OUTPUT(HB1_data_out[6]);
--out_port_from_the_seven_seg_pio[5] is out_port_from_the_seven_seg_pio[5]
--operation mode is output
out_port_from_the_seven_seg_pio[5] = OUTPUT(HB1_data_out[5]);
--out_port_from_the_seven_seg_pio[4] is out_port_from_the_seven_seg_pio[4]
--operation mode is output
out_port_from_the_seven_seg_pio[4] = OUTPUT(HB1_data_out[4]);
--out_port_from_the_seven_seg_pio[3] is out_port_from_the_seven_seg_pio[3]
--operation mode is output
out_port_from_the_seven_seg_pio[3] = OUTPUT(HB1_data_out[3]);
--out_port_from_the_seven_seg_pio[2] is out_port_from_the_seven_seg_pio[2]
--operation mode is output
out_port_from_the_seven_seg_pio[2] = OUTPUT(HB1_data_out[2]);
--out_port_from_the_seven_seg_pio[1] is out_port_from_the_seven_seg_pio[1]
--operation mode is output
out_port_from_the_seven_seg_pio[1] = OUTPUT(HB1_data_out[1]);
--out_port_from_the_seven_seg_pio[0] is out_port_from_the_seven_seg_pio[0]
--operation mode is output
out_port_from_the_seven_seg_pio[0] = OUTPUT(HB1_data_out[0]);
--zs_addr_from_the_sdram[11] is zs_addr_from_the_sdram[11]
--operation mode is output
zs_addr_from_the_sdram[11] = OUTPUT(FB1_m_addr[11]);
--zs_addr_from_the_sdram[10] is zs_addr_from_the_sdram[10]
--operation mode is output
zs_addr_from_the_sdram[10] = OUTPUT(FB1_m_addr[10]);
--zs_addr_from_the_sdram[9] is zs_addr_from_the_sdram[9]
--operation mode is output
zs_addr_from_the_sdram[9] = OUTPUT(FB1_m_addr[9]);
--zs_addr_from_the_sdram[8] is zs_addr_from_the_sdram[8]
--operation mode is output
zs_addr_from_the_sdram[8] = OUTPUT(FB1_m_addr[8]);
--zs_addr_from_the_sdram[7] is zs_addr_from_the_sdram[7]
--operation mode is output
zs_addr_from_the_sdram[7] = OUTPUT(FB1_m_addr[7]);
--zs_addr_from_the_sdram[6] is zs_addr_from_the_sdram[6]
--operation mode is output
zs_addr_from_the_sdram[6] = OUTPUT(FB1_m_addr[6]);
--zs_addr_from_the_sdram[5] is zs_addr_from_the_sdram[5]
--operation mode is output
zs_addr_from_the_sdram[5] = OUTPUT(FB1_m_addr[5]);
--zs_addr_from_the_sdram[4] is zs_addr_from_the_sdram[4]
--operation mode is output
zs_addr_from_the_sdram[4] = OUTPUT(FB1_m_addr[4]);
--zs_addr_from_the_sdram[3] is zs_addr_from_the_sdram[3]
--operation mode is output
zs_addr_from_the_sdram[3] = OUTPUT(FB1_m_addr[3]);
--zs_addr_from_the_sdram[2] is zs_addr_from_the_sdram[2]
--operation mode is output
zs_addr_from_the_sdram[2] = OUTPUT(FB1_m_addr[2]);
--zs_addr_from_the_sdram[1] is zs_addr_from_the_sdram[1]
--operation mode is output
zs_addr_from_the_sdram[1] = OUTPUT(FB1_m_addr[1]);
--zs_addr_from_the_sdram[0] is zs_addr_from_the_sdram[0]
--operation mode is output
zs_addr_from_the_sdram[0] = OUTPUT(FB1_m_addr[0]);
--zs_ba_from_the_sdram[1] is zs_ba_from_the_sdram[1]
--operation mode is output
zs_ba_from_the_sdram[1] = OUTPUT(FB1_m_bank[1]);
--zs_ba_from_the_sdram[0] is zs_ba_from_the_sdram[0]
--operation mode is output
zs_ba_from_the_sdram[0] = OUTPUT(FB1_m_bank[0]);
--zs_dqm_from_the_sdram[3] is zs_dqm_from_the_sdram[3]
--operation mode is output
zs_dqm_from_the_sdram[3] = OUTPUT(FB1_m_dqm[3]);
--zs_dqm_from_the_sdram[2] is zs_dqm_from_the_sdram[2]
--operation mode is output
zs_dqm_from_the_sdram[2] = OUTPUT(FB1_m_dqm[2]);
--zs_dqm_from_the_sdram[1] is zs_dqm_from_the_sdram[1]
--operation mode is output
zs_dqm_from_the_sdram[1] = OUTPUT(FB1_m_dqm[1]);
--zs_dqm_from_the_sdram[0] is zs_dqm_from_the_sdram[0]
--operation mode is output
zs_dqm_from_the_sdram[0] = OUTPUT(FB1_m_dqm[0]);
--A1L22 is bidir_port_to_and_from_the_reconfig_request_pio~0
--operation mode is bidir
A1L22 = bidir_port_to_and_from_the_reconfig_request_pio;
--bidir_port_to_and_from_the_reconfig_request_pio is bidir_port_to_and_from_the_reconfig_request_pio
--operation mode is bidir
bidir_port_to_and_from_the_reconfig_request_pio_tri_out = TRI(DB1_data_out, DB1_data_dir);
bidir_port_to_and_from_the_reconfig_request_pio = BIDIR(bidir_port_to_and_from_the_reconfig_request_pio_tri_out);
--A1L87 is ext_ram_bus_data~0
--operation mode is bidir
--ext_ram_bus_data[31] is ext_ram_bus_data[31]
--operation mode is bidir
ext_ram_bus_data[31]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[31], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[31] = BIDIR(ext_ram_bus_data[31]_tri_out);
--A1L88 is ext_ram_bus_data~1
--operation mode is bidir
--ext_ram_bus_data[30] is ext_ram_bus_data[30]
--operation mode is bidir
ext_ram_bus_data[30]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[30], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[30] = BIDIR(ext_ram_bus_data[30]_tri_out);
--A1L89 is ext_ram_bus_data~2
--operation mode is bidir
--ext_ram_bus_data[29] is ext_ram_bus_data[29]
--operation mode is bidir
ext_ram_bus_data[29]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[29], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[29] = BIDIR(ext_ram_bus_data[29]_tri_out);
--A1L90 is ext_ram_bus_data~3
--operation mode is bidir
--ext_ram_bus_data[28] is ext_ram_bus_data[28]
--operation mode is bidir
ext_ram_bus_data[28]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[28], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[28] = BIDIR(ext_ram_bus_data[28]_tri_out);
--A1L91 is ext_ram_bus_data~4
--operation mode is bidir
--ext_ram_bus_data[27] is ext_ram_bus_data[27]
--operation mode is bidir
ext_ram_bus_data[27]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[27], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[27] = BIDIR(ext_ram_bus_data[27]_tri_out);
--A1L92 is ext_ram_bus_data~5
--operation mode is bidir
--ext_ram_bus_data[26] is ext_ram_bus_data[26]
--operation mode is bidir
ext_ram_bus_data[26]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[26], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[26] = BIDIR(ext_ram_bus_data[26]_tri_out);
--A1L93 is ext_ram_bus_data~6
--operation mode is bidir
--ext_ram_bus_data[25] is ext_ram_bus_data[25]
--operation mode is bidir
ext_ram_bus_data[25]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[25], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[25] = BIDIR(ext_ram_bus_data[25]_tri_out);
--A1L94 is ext_ram_bus_data~7
--operation mode is bidir
--ext_ram_bus_data[24] is ext_ram_bus_data[24]
--operation mode is bidir
ext_ram_bus_data[24]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[24], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[24] = BIDIR(ext_ram_bus_data[24]_tri_out);
--A1L95 is ext_ram_bus_data~8
--operation mode is bidir
--ext_ram_bus_data[23] is ext_ram_bus_data[23]
--operation mode is bidir
ext_ram_bus_data[23]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[23], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[23] = BIDIR(ext_ram_bus_data[23]_tri_out);
--A1L96 is ext_ram_bus_data~9
--operation mode is bidir
--ext_ram_bus_data[22] is ext_ram_bus_data[22]
--operation mode is bidir
ext_ram_bus_data[22]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[22], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[22] = BIDIR(ext_ram_bus_data[22]_tri_out);
--A1L97 is ext_ram_bus_data~10
--operation mode is bidir
--ext_ram_bus_data[21] is ext_ram_bus_data[21]
--operation mode is bidir
ext_ram_bus_data[21]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[21], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[21] = BIDIR(ext_ram_bus_data[21]_tri_out);
--A1L98 is ext_ram_bus_data~11
--operation mode is bidir
--ext_ram_bus_data[20] is ext_ram_bus_data[20]
--operation mode is bidir
ext_ram_bus_data[20]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[20], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[20] = BIDIR(ext_ram_bus_data[20]_tri_out);
--A1L99 is ext_ram_bus_data~12
--operation mode is bidir
--ext_ram_bus_data[19] is ext_ram_bus_data[19]
--operation mode is bidir
ext_ram_bus_data[19]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[19], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[19] = BIDIR(ext_ram_bus_data[19]_tri_out);
--A1L100 is ext_ram_bus_data~13
--operation mode is bidir
A1L100 = ext_ram_bus_data[18];
--ext_ram_bus_data[18] is ext_ram_bus_data[18]
--operation mode is bidir
ext_ram_bus_data[18]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[18], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[18] = BIDIR(ext_ram_bus_data[18]_tri_out);
--A1L101 is ext_ram_bus_data~14
--operation mode is bidir
A1L101 = ext_ram_bus_data[17];
--ext_ram_bus_data[17] is ext_ram_bus_data[17]
--operation mode is bidir
ext_ram_bus_data[17]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[17], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[17] = BIDIR(ext_ram_bus_data[17]_tri_out);
--A1L102 is ext_ram_bus_data~15
--operation mode is bidir
A1L102 = ext_ram_bus_data[16];
--ext_ram_bus_data[16] is ext_ram_bus_data[16]
--operation mode is bidir
ext_ram_bus_data[16]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[16], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[16] = BIDIR(ext_ram_bus_data[16]_tri_out);
--A1L103 is ext_ram_bus_data~16
--operation mode is bidir
A1L103 = ext_ram_bus_data[15];
--ext_ram_bus_data[15] is ext_ram_bus_data[15]
--operation mode is bidir
ext_ram_bus_data[15]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[15], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[15] = BIDIR(ext_ram_bus_data[15]_tri_out);
--A1L104 is ext_ram_bus_data~17
--operation mode is bidir
A1L104 = ext_ram_bus_data[14];
--ext_ram_bus_data[14] is ext_ram_bus_data[14]
--operation mode is bidir
ext_ram_bus_data[14]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[14], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[14] = BIDIR(ext_ram_bus_data[14]_tri_out);
--A1L105 is ext_ram_bus_data~18
--operation mode is bidir
A1L105 = ext_ram_bus_data[13];
--ext_ram_bus_data[13] is ext_ram_bus_data[13]
--operation mode is bidir
ext_ram_bus_data[13]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[13], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[13] = BIDIR(ext_ram_bus_data[13]_tri_out);
--A1L106 is ext_ram_bus_data~19
--operation mode is bidir
A1L106 = ext_ram_bus_data[12];
--ext_ram_bus_data[12] is ext_ram_bus_data[12]
--operation mode is bidir
ext_ram_bus_data[12]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[12], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[12] = BIDIR(ext_ram_bus_data[12]_tri_out);
--A1L107 is ext_ram_bus_data~20
--operation mode is bidir
A1L107 = ext_ram_bus_data[11];
--ext_ram_bus_data[11] is ext_ram_bus_data[11]
--operation mode is bidir
ext_ram_bus_data[11]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[11], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[11] = BIDIR(ext_ram_bus_data[11]_tri_out);
--A1L108 is ext_ram_bus_data~21
--operation mode is bidir
A1L108 = ext_ram_bus_data[10];
--ext_ram_bus_data[10] is ext_ram_bus_data[10]
--operation mode is bidir
ext_ram_bus_data[10]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[10], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[10] = BIDIR(ext_ram_bus_data[10]_tri_out);
--A1L109 is ext_ram_bus_data~22
--operation mode is bidir
--ext_ram_bus_data[9] is ext_ram_bus_data[9]
--operation mode is bidir
ext_ram_bus_data[9]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[9], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[9] = BIDIR(ext_ram_bus_data[9]_tri_out);
--A1L110 is ext_ram_bus_data~23
--operation mode is bidir
--ext_ram_bus_data[8] is ext_ram_bus_data[8]
--operation mode is bidir
ext_ram_bus_data[8]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[8], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[8] = BIDIR(ext_ram_bus_data[8]_tri_out);
--A1L111 is ext_ram_bus_data~24
--operation mode is bidir
--ext_ram_bus_data[7] is ext_ram_bus_data[7]
--operation mode is bidir
ext_ram_bus_data[7]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[7], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[7] = BIDIR(ext_ram_bus_data[7]_tri_out);
--A1L112 is ext_ram_bus_data~25
--operation mode is bidir
--ext_ram_bus_data[6] is ext_ram_bus_data[6]
--operation mode is bidir
ext_ram_bus_data[6]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[6], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[6] = BIDIR(ext_ram_bus_data[6]_tri_out);
--A1L113 is ext_ram_bus_data~26
--operation mode is bidir
--ext_ram_bus_data[5] is ext_ram_bus_data[5]
--operation mode is bidir
ext_ram_bus_data[5]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[5], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[5] = BIDIR(ext_ram_bus_data[5]_tri_out);
--A1L114 is ext_ram_bus_data~27
--operation mode is bidir
--ext_ram_bus_data[4] is ext_ram_bus_data[4]
--operation mode is bidir
ext_ram_bus_data[4]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[4], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[4] = BIDIR(ext_ram_bus_data[4]_tri_out);
--A1L115 is ext_ram_bus_data~28
--operation mode is bidir
--ext_ram_bus_data[3] is ext_ram_bus_data[3]
--operation mode is bidir
ext_ram_bus_data[3]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[3], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[3] = BIDIR(ext_ram_bus_data[3]_tri_out);
--A1L116 is ext_ram_bus_data~29
--operation mode is bidir
--ext_ram_bus_data[2] is ext_ram_bus_data[2]
--operation mode is bidir
ext_ram_bus_data[2]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[2], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[2] = BIDIR(ext_ram_bus_data[2]_tri_out);
--A1L117 is ext_ram_bus_data~30
--operation mode is bidir
--ext_ram_bus_data[1] is ext_ram_bus_data[1]
--operation mode is bidir
ext_ram_bus_data[1]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[1], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[1] = BIDIR(ext_ram_bus_data[1]_tri_out);
--A1L118 is ext_ram_bus_data~31
--operation mode is bidir
--ext_ram_bus_data[0] is ext_ram_bus_data[0]
--operation mode is bidir
ext_ram_bus_data[0]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[0], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[0] = BIDIR(ext_ram_bus_data[0]_tri_out);
--A1L136 is LCD_data_to_and_from_the_lcd_display~0
--operation mode is bidir
A1L136 = LCD_data_to_and_from_the_lcd_display[7];
--LCD_data_to_and_from_the_lcd_display[7] is LCD_data_to_and_from_the_lcd_display[7]
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[7]_tri_out = TRI(L1_M_st_data[7], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[7] = BIDIR(LCD_data_to_and_from_the_lcd_display[7]_tri_out);
--A1L137 is LCD_data_to_and_from_the_lcd_display~1
--operation mode is bidir
A1L137 = LCD_data_to_and_from_the_lcd_display[6];
--LCD_data_to_and_from_the_lcd_display[6] is LCD_data_to_and_from_the_lcd_display[6]
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[6]_tri_out = TRI(L1_M_st_data[6], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[6] = BIDIR(LCD_data_to_and_from_the_lcd_display[6]_tri_out);
--A1L138 is LCD_data_to_and_from_the_lcd_display~2
--operation mode is bidir
A1L138 = LCD_data_to_and_from_the_lcd_display[5];
--LCD_data_to_and_from_the_lcd_display[5] is LCD_data_to_and_from_the_lcd_display[5]
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[5]_tri_out = TRI(L1_M_st_data[5], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[5] = BIDIR(LCD_data_to_and_from_the_lcd_display[5]_tri_out);
--A1L139 is LCD_data_to_and_from_the_lcd_display~3
--operation mode is bidir
A1L139 = LCD_data_to_and_from_the_lcd_display[4];
--LCD_data_to_and_from_the_lcd_display[4] is LCD_data_to_and_from_the_lcd_display[4]
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[4]_tri_out = TRI(L1_M_st_data[4], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[4] = BIDIR(LCD_data_to_and_from_the_lcd_display[4]_tri_out);
--A1L140 is LCD_data_to_and_from_the_lcd_display~4
--operation mode is bidir
A1L140 = LCD_data_to_and_from_the_lcd_display[3];
--LCD_data_to_and_from_the_lcd_display[3] is LCD_data_to_and_from_the_lcd_display[3]
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[3]_tri_out = TRI(L1_M_st_data[3], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[3] = BIDIR(LCD_data_to_and_from_the_lcd_display[3]_tri_out);
--A1L141 is LCD_data_to_and_from_the_lcd_display~5
--operation mode is bidir
A1L141 = LCD_data_to_and_from_the_lcd_display[2];
--LCD_data_to_and_from_the_lcd_display[2] is LCD_data_to_and_from_the_lcd_display[2]
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[2]_tri_out = TRI(L1_M_st_data[2], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[2] = BIDIR(LCD_data_to_and_from_the_lcd_display[2]_tri_out);
--A1L142 is LCD_data_to_and_from_the_lcd_display~6
--operation mode is bidir
A1L142 = LCD_data_to_and_from_the_lcd_display[1];
--LCD_data_to_and_from_the_lcd_display[1] is LCD_data_to_and_from_the_lcd_display[1]
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[1]_tri_out = TRI(L1_M_st_data[1], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[1] = BIDIR(LCD_data_to_and_from_the_lcd_display[1]_tri_out);
--A1L143 is LCD_data_to_and_from_the_lcd_display~7
--operation mode is bidir
A1L143 = LCD_data_to_and_from_the_lcd_display[0];
--LCD_data_to_and_from_the_lcd_display[0] is LCD_data_to_and_from_the_lcd_display[0]
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[0]_tri_out = TRI(L1_M_st_data[0], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[0] = BIDIR(LCD_data_to_and_from_the_lcd_display[0]_tri_out);
--A1L236 is zs_dq_to_and_from_the_sdram~0
--operation mode is bidir
A1L236 = zs_dq_to_and_from_the_sdram[31];
--zs_dq_to_and_from_the_sdram[31] is zs_dq_to_and_from_the_sdram[31]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[31]_tri_out = TRI(FB1_m_data[31], FB1_oe);
zs_dq_to_and_from_the_sdram[31] = BIDIR(zs_dq_to_and_from_the_sdram[31]_tri_out);
--A1L237 is zs_dq_to_and_from_the_sdram~1
--operation mode is bidir
A1L237 = zs_dq_to_and_from_the_sdram[30];
--zs_dq_to_and_from_the_sdram[30] is zs_dq_to_and_from_the_sdram[30]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[30]_tri_out = TRI(FB1_m_data[30], FB1_oe);
zs_dq_to_and_from_the_sdram[30] = BIDIR(zs_dq_to_and_from_the_sdram[30]_tri_out);
--A1L238 is zs_dq_to_and_from_the_sdram~2
--operation mode is bidir
A1L238 = zs_dq_to_and_from_the_sdram[29];
--zs_dq_to_and_from_the_sdram[29] is zs_dq_to_and_from_the_sdram[29]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[29]_tri_out = TRI(FB1_m_data[29], FB1_oe);
zs_dq_to_and_from_the_sdram[29] = BIDIR(zs_dq_to_and_from_the_sdram[29]_tri_out);
--A1L239 is zs_dq_to_and_from_the_sdram~3
--operation mode is bidir
A1L239 = zs_dq_to_and_from_the_sdram[28];
--zs_dq_to_and_from_the_sdram[28] is zs_dq_to_and_from_the_sdram[28]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[28]_tri_out = TRI(FB1_m_data[28], FB1_oe);
zs_dq_to_and_from_the_sdram[28] = BIDIR(zs_dq_to_and_from_the_sdram[28]_tri_out);
--A1L240 is zs_dq_to_and_from_the_sdram~4
--operation mode is bidir
A1L240 = zs_dq_to_and_from_the_sdram[27];
--zs_dq_to_and_from_the_sdram[27] is zs_dq_to_and_from_the_sdram[27]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[27]_tri_out = TRI(FB1_m_data[27], FB1_oe);
zs_dq_to_and_from_the_sdram[27] = BIDIR(zs_dq_to_and_from_the_sdram[27]_tri_out);
--A1L241 is zs_dq_to_and_from_the_sdram~5
--operation mode is bidir
A1L241 = zs_dq_to_and_from_the_sdram[26];
--zs_dq_to_and_from_the_sdram[26] is zs_dq_to_and_from_the_sdram[26]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[26]_tri_out = TRI(FB1_m_data[26], FB1_oe);
zs_dq_to_and_from_the_sdram[26] = BIDIR(zs_dq_to_and_from_the_sdram[26]_tri_out);
--A1L242 is zs_dq_to_and_from_the_sdram~6
--operation mode is bidir
A1L242 = zs_dq_to_and_from_the_sdram[25];
--zs_dq_to_and_from_the_sdram[25] is zs_dq_to_and_from_the_sdram[25]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[25]_tri_out = TRI(FB1_m_data[25], FB1_oe);
zs_dq_to_and_from_the_sdram[25] = BIDIR(zs_dq_to_and_from_the_sdram[25]_tri_out);
--A1L243 is zs_dq_to_and_from_the_sdram~7
--operation mode is bidir
A1L243 = zs_dq_to_and_from_the_sdram[24];
--zs_dq_to_and_from_the_sdram[24] is zs_dq_to_and_from_the_sdram[24]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[24]_tri_out = TRI(FB1_m_data[24], FB1_oe);
zs_dq_to_and_from_the_sdram[24] = BIDIR(zs_dq_to_and_from_the_sdram[24]_tri_out);
--A1L244 is zs_dq_to_and_from_the_sdram~8
--operation mode is bidir
A1L244 = zs_dq_to_and_from_the_sdram[23];
--zs_dq_to_and_from_the_sdram[23] is zs_dq_to_and_from_the_sdram[23]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[23]_tri_out = TRI(FB1_m_data[23], FB1_oe);
zs_dq_to_and_from_the_sdram[23] = BIDIR(zs_dq_to_and_from_the_sdram[23]_tri_out);
--A1L245 is zs_dq_to_and_from_the_sdram~9
--operation mode is bidir
A1L245 = zs_dq_to_and_from_the_sdram[22];
--zs_dq_to_and_from_the_sdram[22] is zs_dq_to_and_from_the_sdram[22]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[22]_tri_out = TRI(FB1_m_data[22], FB1_oe);
zs_dq_to_and_from_the_sdram[22] = BIDIR(zs_dq_to_and_from_the_sdram[22]_tri_out);
--A1L246 is zs_dq_to_and_from_the_sdram~10
--operation mode is bidir
A1L246 = zs_dq_to_and_from_the_sdram[21];
--zs_dq_to_and_from_the_sdram[21] is zs_dq_to_and_from_the_sdram[21]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[21]_tri_out = TRI(FB1_m_data[21], FB1_oe);
zs_dq_to_and_from_the_sdram[21] = BIDIR(zs_dq_to_and_from_the_sdram[21]_tri_out);
--A1L247 is zs_dq_to_and_from_the_sdram~11
--operation mode is bidir
A1L247 = zs_dq_to_and_from_the_sdram[20];
--zs_dq_to_and_from_the_sdram[20] is zs_dq_to_and_from_the_sdram[20]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[20]_tri_out = TRI(FB1_m_data[20], FB1_oe);
zs_dq_to_and_from_the_sdram[20] = BIDIR(zs_dq_to_and_from_the_sdram[20]_tri_out);
--A1L248 is zs_dq_to_and_from_the_sdram~12
--operation mode is bidir
A1L248 = zs_dq_to_and_from_the_sdram[19];
--zs_dq_to_and_from_the_sdram[19] is zs_dq_to_and_from_the_sdram[19]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[19]_tri_out = TRI(FB1_m_data[19], FB1_oe);
zs_dq_to_and_from_the_sdram[19] = BIDIR(zs_dq_to_and_from_the_sdram[19]_tri_out);
--A1L249 is zs_dq_to_and_from_the_sdram~13
--operation mode is bidir
A1L249 = zs_dq_to_and_from_the_sdram[18];
--zs_dq_to_and_from_the_sdram[18] is zs_dq_to_and_from_the_sdram[18]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[18]_tri_out = TRI(FB1_m_data[18], FB1_oe);
zs_dq_to_and_from_the_sdram[18] = BIDIR(zs_dq_to_and_from_the_sdram[18]_tri_out);
--A1L250 is zs_dq_to_and_from_the_sdram~14
--operation mode is bidir
A1L250 = zs_dq_to_and_from_the_sdram[17];
--zs_dq_to_and_from_the_sdram[17] is zs_dq_to_and_from_the_sdram[17]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[17]_tri_out = TRI(FB1_m_data[17], FB1_oe);
zs_dq_to_and_from_the_sdram[17] = BIDIR(zs_dq_to_and_from_the_sdram[17]_tri_out);
--A1L251 is zs_dq_to_and_from_the_sdram~15
--operation mode is bidir
A1L251 = zs_dq_to_and_from_the_sdram[16];
--zs_dq_to_and_from_the_sdram[16] is zs_dq_to_and_from_the_sdram[16]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[16]_tri_out = TRI(FB1_m_data[16], FB1_oe);
zs_dq_to_and_from_the_sdram[16] = BIDIR(zs_dq_to_and_from_the_sdram[16]_tri_out);
--A1L252 is zs_dq_to_and_from_the_sdram~16
--operation mode is bidir
A1L252 = zs_dq_to_and_from_the_sdram[15];
--zs_dq_to_and_from_the_sdram[15] is zs_dq_to_and_from_the_sdram[15]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[15]_tri_out = TRI(FB1_m_data[15], FB1_oe);
zs_dq_to_and_from_the_sdram[15] = BIDIR(zs_dq_to_and_from_the_sdram[15]_tri_out);
--A1L253 is zs_dq_to_and_from_the_sdram~17
--operation mode is bidir
A1L253 = zs_dq_to_and_from_the_sdram[14];
--zs_dq_to_and_from_the_sdram[14] is zs_dq_to_and_from_the_sdram[14]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[14]_tri_out = TRI(FB1_m_data[14], FB1_oe);
zs_dq_to_and_from_the_sdram[14] = BIDIR(zs_dq_to_and_from_the_sdram[14]_tri_out);
--A1L254 is zs_dq_to_and_from_the_sdram~18
--operation mode is bidir
A1L254 = zs_dq_to_and_from_the_sdram[13];
--zs_dq_to_and_from_the_sdram[13] is zs_dq_to_and_from_the_sdram[13]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[13]_tri_out = TRI(FB1_m_data[13], FB1_oe);
zs_dq_to_and_from_the_sdram[13] = BIDIR(zs_dq_to_and_from_the_sdram[13]_tri_out);
--A1L255 is zs_dq_to_and_from_the_sdram~19
--operation mode is bidir
A1L255 = zs_dq_to_and_from_the_sdram[12];
--zs_dq_to_and_from_the_sdram[12] is zs_dq_to_and_from_the_sdram[12]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[12]_tri_out = TRI(FB1_m_data[12], FB1_oe);
zs_dq_to_and_from_the_sdram[12] = BIDIR(zs_dq_to_and_from_the_sdram[12]_tri_out);
--A1L256 is zs_dq_to_and_from_the_sdram~20
--operation mode is bidir
A1L256 = zs_dq_to_and_from_the_sdram[11];
--zs_dq_to_and_from_the_sdram[11] is zs_dq_to_and_from_the_sdram[11]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[11]_tri_out = TRI(FB1_m_data[11], FB1_oe);
zs_dq_to_and_from_the_sdram[11] = BIDIR(zs_dq_to_and_from_the_sdram[11]_tri_out);
--A1L257 is zs_dq_to_and_from_the_sdram~21
--operation mode is bidir
A1L257 = zs_dq_to_and_from_the_sdram[10];
--zs_dq_to_and_from_the_sdram[10] is zs_dq_to_and_from_the_sdram[10]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[10]_tri_out = TRI(FB1_m_data[10], FB1_oe);
zs_dq_to_and_from_the_sdram[10] = BIDIR(zs_dq_to_and_from_the_sdram[10]_tri_out);
--A1L258 is zs_dq_to_and_from_the_sdram~22
--operation mode is bidir
A1L258 = zs_dq_to_and_from_the_sdram[9];
--zs_dq_to_and_from_the_sdram[9] is zs_dq_to_and_from_the_sdram[9]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[9]_tri_out = TRI(FB1_m_data[9], FB1_oe);
zs_dq_to_and_from_the_sdram[9] = BIDIR(zs_dq_to_and_from_the_sdram[9]_tri_out);
--A1L259 is zs_dq_to_and_from_the_sdram~23
--operation mode is bidir
A1L259 = zs_dq_to_and_from_the_sdram[8];
--zs_dq_to_and_from_the_sdram[8] is zs_dq_to_and_from_the_sdram[8]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[8]_tri_out = TRI(FB1_m_data[8], FB1_oe);
zs_dq_to_and_from_the_sdram[8] = BIDIR(zs_dq_to_and_from_the_sdram[8]_tri_out);
--A1L260 is zs_dq_to_and_from_the_sdram~24
--operation mode is bidir
A1L260 = zs_dq_to_and_from_the_sdram[7];
--zs_dq_to_and_from_the_sdram[7] is zs_dq_to_and_from_the_sdram[7]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[7]_tri_out = TRI(FB1_m_data[7], FB1_oe);
zs_dq_to_and_from_the_sdram[7] = BIDIR(zs_dq_to_and_from_the_sdram[7]_tri_out);
--A1L261 is zs_dq_to_and_from_the_sdram~25
--operation mode is bidir
A1L261 = zs_dq_to_and_from_the_sdram[6];
--zs_dq_to_and_from_the_sdram[6] is zs_dq_to_and_from_the_sdram[6]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[6]_tri_out = TRI(FB1_m_data[6], FB1_oe);
zs_dq_to_and_from_the_sdram[6] = BIDIR(zs_dq_to_and_from_the_sdram[6]_tri_out);
--A1L262 is zs_dq_to_and_from_the_sdram~26
--operation mode is bidir
A1L262 = zs_dq_to_and_from_the_sdram[5];
--zs_dq_to_and_from_the_sdram[5] is zs_dq_to_and_from_the_sdram[5]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[5]_tri_out = TRI(FB1_m_data[5], FB1_oe);
zs_dq_to_and_from_the_sdram[5] = BIDIR(zs_dq_to_and_from_the_sdram[5]_tri_out);
--A1L263 is zs_dq_to_and_from_the_sdram~27
--operation mode is bidir
A1L263 = zs_dq_to_and_from_the_sdram[4];
--zs_dq_to_and_from_the_sdram[4] is zs_dq_to_and_from_the_sdram[4]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[4]_tri_out = TRI(FB1_m_data[4], FB1_oe);
zs_dq_to_and_from_the_sdram[4] = BIDIR(zs_dq_to_and_from_the_sdram[4]_tri_out);
--A1L264 is zs_dq_to_and_from_the_sdram~28
--operation mode is bidir
A1L264 = zs_dq_to_and_from_the_sdram[3];
--zs_dq_to_and_from_the_sdram[3] is zs_dq_to_and_from_the_sdram[3]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[3]_tri_out = TRI(FB1_m_data[3], FB1_oe);
zs_dq_to_and_from_the_sdram[3] = BIDIR(zs_dq_to_and_from_the_sdram[3]_tri_out);
--A1L265 is zs_dq_to_and_from_the_sdram~29
--operation mode is bidir
A1L265 = zs_dq_to_and_from_the_sdram[2];
--zs_dq_to_and_from_the_sdram[2] is zs_dq_to_and_from_the_sdram[2]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[2]_tri_out = TRI(FB1_m_data[2], FB1_oe);
zs_dq_to_and_from_the_sdram[2] = BIDIR(zs_dq_to_and_from_the_sdram[2]_tri_out);
--A1L266 is zs_dq_to_and_from_the_sdram~30
--operation mode is bidir
A1L266 = zs_dq_to_and_from_the_sdram[1];
--zs_dq_to_and_from_the_sdram[1] is zs_dq_to_and_from_the_sdram[1]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[1]_tri_out = TRI(FB1_m_data[1], FB1_oe);
zs_dq_to_and_from_the_sdram[1] = BIDIR(zs_dq_to_and_from_the_sdram[1]_tri_out);
--A1L267 is zs_dq_to_and_from_the_sdram~31
--operation mode is bidir
A1L267 = zs_dq_to_and_from_the_sdram[0];
--zs_dq_to_and_from_the_sdram[0] is zs_dq_to_and_from_the_sdram[0]
--operation mode is bidir
zs_dq_to_and_from_the_sdram[0]_tri_out = TRI(FB1_m_data[0], FB1_oe);
zs_dq_to_and_from_the_sdram[0] = BIDIR(zs_dq_to_and_from_the_sdram[0]_tri_out);
--A1L2 is altera_internal_jtag~$wirecell
--operation mode is normal
--L1L1013 is std_1s10:inst|cpu:the_cpu|ic_fill_ap_offset[0]~$wirecell
--operation mode is normal
L1L1013 = AMPP_FUNCTION(L1_ic_fill_ap_offset[0]);