Fitter report for standard

1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Netlist Optimizations
5. Fitter Equations
6. Pin-Out File
7. Fitter Resource Usage Summary
8. Input Pins
9. Output Pins
10. Bidir Pins
11. I/O Bank Usage
12. All Package Pins
13. PLL Summary
14. PLL Usage
15. Output Pin Default Load For Reported TCO
16. Fitter Resource Utilization by Entity
17. Delay Chain Summary
18. Pad To Core Delay Chain Fanout
19. Control Signals
20. Global & Other Fast Signals
21. Non-Global High Fan-Out Signals
22. Fitter RAM Summary
23. Fitter DSP Block Usage Summary
24. DSP Block Details
25. Interconnect Usage Summary
26. LAB Logic Elements
27. LAB-wide Signals
28. LAB Signals Sourced
29. LAB Signals Sourced Out
30. LAB Distinct Inputs
31. Fitter Device Options
32. Fitter Messages
33. Fitter Suppressed Messages

Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.