Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
inst|std_1s10_reset_clk_domain_synch 3 1 0 1 1 1 1 1 0 0 0 0 0
inst|std_1s10_reset_sys_clk_domain_synch 3 1 0 1 1 1 1 1 0 0 0 0 0
inst|the_uart0|the_uart0_regs 41 10 6 10 40 10 10 10 0 0 0 0 0
inst|the_uart0|the_uart0_rx|the_uart0_rx_stimulus_source 14 0 13 0 1 0 0 0 0 0 0 0 0
inst|the_uart0|the_uart0_rx 16 2 0 2 13 2 2 2 0 0 0 0 0
inst|the_uart0|the_uart0_tx 24 1 0 1 4 1 1 1 0 0 0 0 0
inst|the_uart0 26 0 0 0 20 0 0 0 0 0 0 0 0
inst|the_uart0_s1 84 2 18 2 48 2 2 2 0 0 0 0 0
inst|the_sysid 1 20 0 20 32 20 20 20 0 0 0 0 0
inst|the_sysid_control_slave 65 0 2 0 38 0 0 0 0 0 0 0 0
inst|the_sys_clk_timer 23 0 0 0 17 0 0 0 0 0 0 0 0
inst|the_sys_clk_timer_s1 82 0 18 0 44 0 0 0 0 0 0 0 0
inst|the_std_1s10_clock_0|endofpacket_bit_pipe 5 0 0 0 1 0 0 0 0 0 0 0 0
inst|the_std_1s10_clock_0|master_FSM 5 0 0 0 4 0 0 0 0 0 0 0 0
inst|the_std_1s10_clock_0|write_request_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
inst|the_std_1s10_clock_0|read_request_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
inst|the_std_1s10_clock_0|slave_FSM 6 0 0 0 3 0 0 0 0 0 0 0 0
inst|the_std_1s10_clock_0|write_done_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
inst|the_std_1s10_clock_0|read_done_edge_to_pulse 3 0 0 0 1 0 0 0 0 0 0 0 0
inst|the_std_1s10_clock_0 49 1 0 1 45 1 1 1 0 0 0 0 0
inst|the_std_1s10_clock_0_out 47 0 22 0 22 0 0 0 0 0 0 0 0
inst|the_std_1s10_clock_0_in 87 1 20 1 51 1 1 1 0 0 0 0 0
inst|the_seven_seg_pio 22 0 0 0 32 0 0 0 0 0 0 0 0
inst|the_seven_seg_pio_s1 81 0 18 0 42 0 0 0 0 0 0 0 0
inst|the_sdram|the_sdram_input_efifo_module 63 2 0 2 63 2 2 2 0 0 0 0 0
inst|the_sdram 63 1 1 1 57 1 1 1 32 0 0 0 0
inst|the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1 7 4 0 4 4 4 4 4 0 0 0 0 0
inst|the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1 7 4 0 4 4 4 4 4 0 0 0 0 0
inst|the_sdram_s1 131 0 4 0 106 0 0 0 0 0 0 0 0
inst|the_reconfig_request_pio 7 0 0 0 1 0 0 0 1 0 0 0 0
inst|the_reconfig_request_pio_s1 66 0 33 0 12 0 0 0 0 0 0 0 0
inst|the_pll|the_pll 1 0 0 0 2 0 0 0 0 0 0 0 0
inst|the_pll 24 0 1 0 19 0 0 0 0 0 0 0 0
inst|the_pll_s1 44 0 4 0 45 0 0 0 0 0 0 0 0
inst|the_led_pio 14 0 0 0 16 0 0 0 0 0 0 0 0
inst|the_led_pio_s1 77 0 29 0 26 0 0 0 0 0 0 0 0
inst|the_lcd_display 13 0 1 0 11 0 0 0 8 0 0 0 0
inst|the_lcd_display_control_slave 77 0 29 0 27 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 24 0 0 0 8 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_r|rfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_r 13 0 1 0 16 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 24 0 0 0 8 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_w|wfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
inst|the_jtag_uart|the_jtag_uart_scfifo_w 12 0 0 0 16 0 0 0 0 0 0 0 0
inst|the_jtag_uart 38 9 23 9 36 9 9 9 0 0 0 0 0
inst|the_jtag_uart_avalon_jtag_slave 101 2 2 2 78 2 2 2 0 0 0 0 0
inst|the_hrclock 24 0 0 0 17 0 0 0 0 0 0 0 0
inst|the_hrclock_s1 82 0 18 0 45 0 0 0 0 0 0 0 0
inst|the_fast_tlb_miss_ram_1k|the_altsyncram|auto_generated 92 0 0 0 64 0 0 0 0 0 0 0 0
inst|the_fast_tlb_miss_ram_1k 94 0 0 0 64 0 0 0 0 0 0 0 0
inst|the_fast_tlb_miss_ram_1k_s2 100 0 3 0 83 0 0 0 0 0 0 0 0
inst|the_fast_tlb_miss_ram_1k_s1 63 5 3 5 83 5 5 5 0 0 0 0 0
inst|the_ext_ram_bus_avalon_slave 112 0 0 0 109 0 0 0 32 0 0 0 0
inst|the_cpu 219 40 30 40 218 40 40 40 0 0 0 0 0
inst|the_cpu_tightly_coupled_instruction_master_0 67 18 23 18 61 18 18 18 0 0 0 0 0
inst|the_cpu_tightly_coupled_data_master_0 104 18 59 18 61 18 18 18 0 0 0 0 0
inst|the_cpu_instruction_master 152 0 2 0 64 0 0 0 0 0 0 0 0
inst|the_cpu_data_master 427 26 8 26 104 26 26 26 0 0 0 0 0
inst|the_cpu_jtag_debug_module 133 0 4 0 92 0 0 0 0 0 0 0 0
inst|the_button_pio 14 0 0 0 5 0 0 0 0 0 0 0 0
inst|the_button_pio_s1 70 0 30 0 19 0 0 0 0 0 0 0 0
inst 8 2 0 2 93 2 2 2 73 0 0 0 0