std_1s10



2010.07.17.12:47:30 Datasheet
Overview
  clk  std_1s10
   uart0
 rxd  
 txd  
 in_port  
 out_port  
 out_port  
 bidir_port  
   sdram
 zs_addr  
 zs_ba  
 zs_cas_n  
 zs_cke  
 zs_cs_n  
 zs_dq  
 zs_dqm  
 zs_ras_n  
 zs_we_n  
   lcd_display
 LCD_data  
 LCD_E  
 LCD_RS  
 LCD_RW  
Processor

   cpu Nios II 9.1

Peripherals

   pll altera_avalon_pll 9.1

   cpu altera_nios2 9.1

   ext_ram_bus altera_avalon_tri_state_bridge 9.1

   fast_tlb_miss_ram_1k altera_avalon_onchip_memory2 9.1

   sys_clk_timer altera_avalon_timer 9.1

   jtag_uart altera_avalon_jtag_uart 9.1

   uart0 altera_avalon_uart 9.1

   button_pio altera_avalon_pio 9.1

   led_pio altera_avalon_pio 9.1

   seven_seg_pio altera_avalon_pio 9.1

   reconfig_request_pio altera_avalon_pio 9.1

   sdram altera_avalon_new_sdram_controller 9.1

   sysid altera_avalon_sysid 9.1

   lcd_display altera_avalon_lcd_16207 9.1

   hrclock altera_avalon_timer 9.1
Memory Map
cpu
 instruction_master  tightly_coupled_instruction_master_0  data_master  tightly_coupled_data_master_0
  pll
s1  0x008108c0
  cpu
jtag_debug_module  0x00810000 0x00810000
  ext_flash
s1  0x00000000 0x00000000
  ext_ram
s1  0x02000000 0x02000000
  fast_tlb_miss_ram_1k
s1  0x02100000
s2  0x02100000
  sys_clk_timer
s1  0x00810800
  jtag_uart
avalon_jtag_slave  0x00810820
  uart0
s1  0x00810840
  button_pio
s1  0x00810830
  led_pio
s1  0x00810880
  seven_seg_pio
s1  0x00810890
  reconfig_request_pio
s1  0x008108a0
  sdram
s1  0x01000000 0x01000000
  sysid
control_slave  0x00810828
  lcd_display
control_slave  0x008108b0
  lan91c111_0
s1  0x00800000 0x00800000
  hrclock
s1  0x00810900

clk

clock_source v9.1





Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

pll

altera_avalon_pll v9.1

clk clk   pll
  inclk0
cpu data_master  
  s1
c0   cpu
  clk
c0   ext_ram_bus
  clk
c0   ext_flash
  clk
c0   ext_ram
  clk
c0   fast_tlb_miss_ram_1k
  clk1
c0  
  clk2
c0   sys_clk_timer
  clk
c0   jtag_uart
  clk
c0   uart0
  clk
c0   button_pio
  clk
c0   led_pio
  clk
c0   seven_seg_pio
  clk
c0   reconfig_request_pio
  clk
c0   sdram
  clk
c0   sysid
  clk
c0   lcd_display
  clk
c0   lan91c111_0
  clk
c0   hrclock
  clk




Parameters

c0
c1
c2
c3
c4
c5
c6
c7
c8
c9
deviceFamily STRATIX
e0
e1
e2
e3
inputClockFrequency 50000000
inputClockRate 50000000
lockedOutputPortOption Export
pfdenaInputPortOption Register
pllHdl
resetInputPortOption Register
generateLegacySim false
  

Software Assignments

ARESET "None"
PFDENA "None"
LOCKED "None"
PLLENA "None"
SCANCLK "None"
SCANDATA "None"
SCANREAD "None"
SCANWRITE "None"
SCANCLKENA "None"
SCANACLR "None"
SCANDATAOUT "None"
SCANDONE "None"
CONFIGUPDATE "None"
PHASECOUNTERSELECT "None"
PHASEDONE "None"
PHASEUPDOWN "None"
PHASESTEP "None"

cpu

altera_nios2 v9.1

pll c0   cpu
  clk
instruction_master   ext_ram_bus
  avalon_slave
data_master  
  avalon_slave
data_master   sys_clk_timer
  s1
d_irq  
  irq
data_master   jtag_uart
  avalon_jtag_slave
d_irq  
  irq
data_master   uart0
  s1
d_irq  
  irq
data_master   button_pio
  s1
d_irq  
  irq
data_master   led_pio
  s1
data_master   seven_seg_pio
  s1
data_master   reconfig_request_pio
  s1
instruction_master   sdram
  s1
data_master  
  s1
data_master   sysid
  control_slave
data_master   pll
  s1
data_master   lcd_display
  control_slave
d_irq   lan91c111_0
  irq
tightly_coupled_data_master_0   fast_tlb_miss_ram_1k
  s2
tightly_coupled_instruction_master_0  
  s1
data_master   hrclock
  s1
d_irq  
  irq




Parameters

userDefinedSettings
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSets 0
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_interruptControllerType Internal
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Static
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave ext_flash.s1
resetOffset 0
muldiv_multiplierType DSPBlock
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _10
mmu_enabled true
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave fast_tlb_miss_ram_1k.s1
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
impl Fast
icache_size _8192
icache_ramBlockType Automatic
icache_numTCIM _1
icache_burstType None
exceptionSlave sdram.s1
exceptionOffset 32
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _4096
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _1
dcache_lineSize _32
dcache_bursts false
cpuReset false
cpuID 0
clockFrequency 50000000
breakSlave cpu.jtag_debug_module
breakOffset 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CPU_IMPLEMENTATION "fast"
BIG_ENDIAN 0
CPU_FREQ 50000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 8192
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 4096
INITDA_SUPPORTED
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
MMU_PRESENT
KERNEL_REGION_BASE 0xc0000000
IO_REGION_BASE 0xe0000000
KERNEL_MMU_REGION_BASE 0x80000000
USER_REGION_BASE 0x0
PROCESS_ID_NUM_BITS 10
TLB_NUM_WAYS 16
TLB_NUM_WAYS_LOG2 4
TLB_PTR_SZ 7
TLB_NUM_ENTRIES 128
FAST_TLB_MISS_EXCEPTION_ADDR 0xc2100000
EXCEPTION_ADDR 0xc1000020
RESET_ADDR 0xc0000000
BREAK_ADDR 0xc0810020
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
HAS_ILLEGAL_INSTRUCTION_EXCEPTION
HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION
HAS_EXTRA_EXCEPTION_INFO
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 1
INST_ADDR_WIDTH 26
DATA_ADDR_WIDTH 26
NUM_OF_SHADOW_REG_SETS 0

ext_ram_bus

altera_avalon_tri_state_bridge v9.1

pll c0   ext_ram_bus
  clk
cpu instruction_master  
  avalon_slave
data_master  
  avalon_slave
tristate_master   ext_flash
  s1
tristate_master   ext_ram
  s1
tristate_master   lan91c111_0
  s1




Parameters

registerIncomingSignals true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ext_flash

altera_avalon_cfi_flash v9.1

pll c0   ext_flash
  clk
ext_ram_bus tristate_master  
  s1




Parameters

actualHoldTime 40.0
actualSetupTime 40.0
actualWaitTime 160.0
addressWidth 23
clockRate 50000000
corePreset CUSTOM
dataWidth 8
holdTime 40
setupTime 40
sharedPorts s1/data,s1/address
timingUnits NS
waitTime 160
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

SETUP_VALUE 40
WAIT_VALUE 160
HOLD_VALUE 40
TIMING_UNITS "ns"
SIZE 8388608u

ext_ram

altera_nios_dev_kit_stratix_edition_sram2 v9.1

pll c0   ext_ram
  clk
ext_ram_bus tristate_master  
  s1




Parameters

sharedPorts s1/data,s1/address
simMakeModel true
size 1048576
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

SRAM_MEMORY_SIZE 1048576
SRAM_MEMORY_UNITS 1
SRAM_DATA_WIDTH 32

fast_tlb_miss_ram_1k

altera_avalon_onchip_memory2 v9.1

pll c0   fast_tlb_miss_ram_1k
  clk1
c0  
  clk2
cpu tightly_coupled_data_master_0  
  s2
tightly_coupled_instruction_master_0  
  s1




Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
deviceFamily Stratix
dualPort true
initMemContent true
initializationFileName fast_tlb_miss_ram_1k
instanceID NONE
memorySize 512
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "fast_tlb_miss_ram_1k"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 1
SIZE_VALUE 512u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

sys_clk_timer

altera_avalon_timer v9.1

pll c0   sys_clk_timer
  clk
cpu data_master  
  s1
d_irq  
  irq




Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 10
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 50000000
timeoutPulseOutput false
timerPreset CUSTOM
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 10
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 50000000u
LOAD_VALUE 499999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 100u

jtag_uart

altera_avalon_jtag_uart v9.1

pll c0   jtag_uart
  clk
cpu data_master  
  avalon_jtag_slave
d_irq  
  irq




Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

uart0

altera_avalon_uart v9.1

pll c0   uart0
  clk
cpu data_master  
  s1
d_irq  
  irq




Parameters

baud 115200
baudError 0.01
clockRate 50000000
dataBits 8
fixedBaud true
parity NONE
simCharStream
simInteractiveInputEnable false
simInteractiveOutputEnable false
simTrueBaud false
stopBits 1
syncRegDepth 2
useCtsRts false
useEopRegister false
useRelativePathForSimFile false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BAUD 115200
DATA_BITS 8
FIXED_BAUD 1
PARITY 'N'
STOP_BITS 1
SYNC_REG_DEPTH 2
USE_CTS_RTS 0
USE_EOP_REGISTER 0
SIM_TRUE_BAUD 0
SIM_CHAR_STREAM ""
FREQ 50000000u

button_pio

altera_avalon_pio v9.1

pll c0   button_pio
  clk
cpu data_master  
  s1
d_irq  
  irq




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 50000000
direction Input
edgeType ANY
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring true
simDrivenValue 15
width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0xf
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 4
RESET_VALUE 0x0
EDGE_TYPE "ANY"
IRQ_TYPE "EDGE"
FREQ 50000000u

led_pio

altera_avalon_pio v9.1

pll c0   led_pio
  clk
cpu data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

seven_seg_pio

altera_avalon_pio v9.1

pll c0   seven_seg_pio
  clk
cpu data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 16
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 16
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

reconfig_request_pio

altera_avalon_pio v9.1

pll c0   reconfig_request_pio
  clk
cpu data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

sdram

altera_avalon_new_sdram_controller v9.1

pll c0   sdram
  clk
cpu instruction_master  
  s1
data_master  
  s1




Parameters

TAC 5.5
TMRD 3
TRCD 20.0
TRFC 70.0
TRP 20.0
TWR 14.0
casLatency 3
clockRate 50000000
columnWidth 8
dataWidth 32
generateSimulationModel true
initNOPDelay 0.0
initRefreshCommands 2
masteredTristateBridgeSlave
model custom
numberOfBanks 4
numberOfChipSelects 1
pinsSharedViaTriState false
powerUpDelay 100.0
refreshPeriod 15.625
registerDataIn true
rowWidth 12
size 16777216
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

REGISTER_DATA_IN 1
SIM_MODEL_BASE 1
SDRAM_DATA_WIDTH 32
SDRAM_ADDR_WIDTH 22
SDRAM_ROW_WIDTH 12
SDRAM_COL_WIDTH 8
SDRAM_NUM_CHIPSELECTS 1
SDRAM_NUM_BANKS 4
REFRESH_PERIOD 15.625
POWERUP_DELAY 100.0
CAS_LATENCY 3
T_RFC 70.0
T_RP 20.0
T_MRD 3
T_RCD 20.0
T_AC 5.5
T_WR 14.0
INIT_REFRESH_COMMANDS 2
INIT_NOP_DELAY 0.0
SHARED_DATA 0
STARVATION_INDICATOR 0
TRISTATE_BRIDGE_SLAVE ""
IS_INITIALIZED 1
SDRAM_BANK_WIDTH 2
CONTENTS_INFO ""

sysid

altera_avalon_sysid v9.1

pll c0   sysid
  clk
cpu data_master  
  control_slave




Parameters

id 2098993396
timestamp 1279363320
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ID 2098993396u
TIMESTAMP 1279363320u

lcd_display

altera_avalon_lcd_16207 v9.1

pll c0   lcd_display
  clk
cpu data_master  
  control_slave




Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

lan91c111_0

altera_avalon_lan91c111 v9.1

pll c0   lan91c111_0
  clk
ext_ram_bus tristate_master  
  s1
cpu d_irq  
  irq




Parameters

ethernetPeripheralLocation DEV_BOARD
registerOffset 768
sharedPorts s1/address,s1/data
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

IS_ETHERNET_MAC 1
LAN91C111_REGISTERS_OFFSET 768
LAN91C111_DATA_BUS_WIDTH 32

hrclock

altera_avalon_timer v9.1

pll c0   hrclock
  clk
cpu data_master  
  s1
d_irq  
  irq




Parameters

alwaysRun false
counterSize 64
fixedPeriod false
period 1
periodUnits USEC
resetOutput false
snapshot true
systemFrequency 50000000
timeoutPulseOutput false
timerPreset CUSTOM
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 1
PERIOD_UNITS "us"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 50000000u
LOAD_VALUE 49ULL
COUNTER_SIZE 64
MULT 1.0E-6
TICKS_PER_SEC 1000000u
generation took 0.01 seconds rendering took 16.46 seconds