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--Q1L396 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ior_n_to_the_lan91c111~COMB_OUT at LC_X36_Y16_N4
--operation mode is normal
Q1L396 = !Q1_ext_ram_bus_avalon_slave_begins_xfer & (Q1L106 # L1_internal_d_read & Q1L72);
--Q1L465 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_flash~COMB_OUT at LC_X41_Y17_N0
--operation mode is normal
Q1L465 = !Q1_ext_ram_bus_avalon_slave_begins_xfer & Q1L249 & (Q1_ext_flash_s1_wait_counter[3] $ !Q1L447);
--Q1L399 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|iow_n_to_the_lan91c111~COMB_OUT at LC_X36_Y11_N5
--operation mode is normal
Q1L399 = Q1L415 & L1_internal_d_write & !Q1_ext_ram_bus_avalon_slave_begins_xfer & Q1L72;
--Q1L453 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_flash~COMB_OUT at LC_X41_Y17_N7
--operation mode is normal
Q1L453 = !Q1_ext_flash_s1_wait_counter[3] & !Q1_ext_ram_bus_avalon_slave_begins_xfer & (Q1L104 # Q1L87);
--Q1L456 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram~COMB_OUT at LC_X39_Y17_N8
--operation mode is normal
Q1L456 = Q1L105 # L1_internal_d_read & Q1L71;
--Q1L460 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram~COMB_OUT at LC_X36_Y17_N3
--operation mode is normal
Q1L460 = Q1L105 # Q1L80 & (Q1L32 # Q1L34);
--Q1_write_n_to_the_ext_ram_local is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_local at LC_X36_Y17_N1
--operation mode is normal
Q1_write_n_to_the_ext_ram_local_lut_out = L1_internal_d_write & Q1L80 & (Q1L32 # Q1L34);
Q1_write_n_to_the_ext_ram_local = DFFEAS(Q1_write_n_to_the_ext_ram_local_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L468 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram~0 at LC_X36_Y17_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
Q1_write_n_to_the_ext_ram_mask_qfbk = Q1_write_n_to_the_ext_ram_mask;
Q1L468 = Q1_write_n_to_the_ext_ram_local & (!Q1_write_n_to_the_ext_ram_mask_qfbk);
--Q1_write_n_to_the_ext_ram_mask is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_ram_mask at LC_X36_Y17_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
Q1_write_n_to_the_ext_ram_mask = DFFEAS(Q1L468, !GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , Q1_write_n_to_the_ext_ram_local, , , VCC);
--FB1L224 is std_1s10:inst|sdram:the_sdram|m_cmd[1]~COMB_OUT at LC_X35_Y2_N8
--operation mode is normal
FB1L224 = !FB1L432 & (FB1_m_state[7] & FB1L433 # !FB1_m_state[7] & (FB1L435));
--FB1L223Q is std_1s10:inst|sdram:the_sdram|m_cmd[1]~_Duplicate_1 at LC_X35_Y2_N8
--operation mode is normal
FB1L223Q = DFFEAS(FB1L224, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L232 is std_1s10:inst|sdram:the_sdram|m_cmd[3]~COMB_OUT at LC_X32_Y4_N7
--operation mode is normal
FB1L232 = FB1_m_state[7] & FB1L426 & FB1L427 # !FB1_m_state[7] & (!FB1L425);
--FB1L228 is std_1s10:inst|sdram:the_sdram|m_cmd[2]~COMB_OUT at LC_X35_Y1_N8
--operation mode is normal
FB1L228 = !FB1L428 & !FB1L429 & (FB1L431 # !FB1L430);
--FB1L227Q is std_1s10:inst|sdram:the_sdram|m_cmd[2]~_Duplicate_1 at LC_X35_Y1_N8
--operation mode is normal
FB1L227Q = DFFEAS(FB1L228, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L220 is std_1s10:inst|sdram:the_sdram|m_cmd[0]~COMB_OUT at LC_X35_Y2_N0
--operation mode is normal
FB1L220 = FB1L437 & FB1L439 & (!FB1L233 # !FB1L438);
--FB1L219Q is std_1s10:inst|sdram:the_sdram|m_cmd[0]~_Duplicate_1 at LC_X35_Y2_N0
--operation mode is normal
FB1L219Q = DFFEAS(FB1L220, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--L1_M_alu_result[7] is std_1s10:inst|cpu:the_cpu|M_alu_result[7] at LC_X33_Y13_N6
--operation mode is normal
L1_M_alu_result[7] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L539, A1L275, L1L7, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_internal_d_read is std_1s10:inst|cpu:the_cpu|internal_d_read at LC_X34_Y13_N8
--operation mode is normal
L1_internal_d_read = AMPP_FUNCTION(DE1__clk0, L1_W_stall, L1_E_ctrl_ld, L1L819, L1L347, E1_data_out);
--L1_M_alu_result[22] is std_1s10:inst|cpu:the_cpu|M_alu_result[22] at LC_X33_Y13_N2
--operation mode is normal
L1_M_alu_result[22] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L554, A1L275, L1L11, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[21] is std_1s10:inst|cpu:the_cpu|M_alu_result[21] at LC_X33_Y13_N3
--operation mode is normal
L1_M_alu_result[21] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L553, A1L275, L1L12, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[24] is std_1s10:inst|cpu:the_cpu|M_alu_result[24] at LC_X34_Y13_N3
--operation mode is normal
L1_M_alu_result[24] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L556, A1L275, L1L13, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[19] is std_1s10:inst|cpu:the_cpu|M_alu_result[19] at LC_X22_Y20_N7
--operation mode is normal
L1_M_alu_result[19] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L551, A1L275, L1L14, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--AB1L6 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_requests_onchip_ram_64_kbytes_s1~297 at LC_X36_Y13_N3
--operation mode is normal
AB1L6 = !L1_M_alu_result[22] & !L1_M_alu_result[24] & !L1_M_alu_result[21] & !L1_M_alu_result[19];
--L1_M_alu_result[18] is std_1s10:inst|cpu:the_cpu|M_alu_result[18] at LC_X33_Y13_N9
--operation mode is normal
L1_M_alu_result[18] = AMPP_FUNCTION(DE1__clk0, L1L15, L1L550, A1L275, L1_E_ctrl_dst_data_sel_logic_result, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[17] is std_1s10:inst|cpu:the_cpu|M_alu_result[17] at LC_X33_Y13_N7
--operation mode is normal
L1_M_alu_result[17] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L549, A1L275, L1L16, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--AB1L7 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_requests_onchip_ram_64_kbytes_s1~298 at LC_X33_Y13_N5
--operation mode is normal
AB1L7 = !L1_M_alu_result[17] & !L1_M_alu_result[18];
--L1_M_alu_result[16] is std_1s10:inst|cpu:the_cpu|M_alu_result[16] at LC_X22_Y20_N9
--operation mode is normal
L1_M_alu_result[16] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L548, A1L275, L1L17, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[23] is std_1s10:inst|cpu:the_cpu|M_alu_result[23] at LC_X34_Y13_N4
--operation mode is normal
L1_M_alu_result[23] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L18, A1L275, L1L555, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[25] is std_1s10:inst|cpu:the_cpu|M_alu_result[25] at LC_X33_Y13_N0
--operation mode is normal
L1_M_alu_result[25] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L557, A1L275, L1L19, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[20] is std_1s10:inst|cpu:the_cpu|M_alu_result[20] at LC_X33_Y13_N4
--operation mode is normal
L1_M_alu_result[20] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L552, A1L275, L1L20, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--P1L5 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~305 at LC_X35_Y12_N4
--operation mode is normal
P1L5 = L1_M_alu_result[23] & !L1_M_alu_result[25] & L1_M_alu_result[16] & !L1_M_alu_result[20];
--L1_M_alu_result[15] is std_1s10:inst|cpu:the_cpu|M_alu_result[15] at LC_X22_Y20_N2
--operation mode is normal
L1_M_alu_result[15] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L547, A1L275, L1L21, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[14] is std_1s10:inst|cpu:the_cpu|M_alu_result[14] at LC_X22_Y20_N4
--operation mode is normal
L1_M_alu_result[14] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L22, A1L275, L1L546, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[13] is std_1s10:inst|cpu:the_cpu|M_alu_result[13] at LC_X22_Y20_N1
--operation mode is normal
L1_M_alu_result[13] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L23, A1L275, L1L545, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[12] is std_1s10:inst|cpu:the_cpu|M_alu_result[12] at LC_X22_Y20_N5
--operation mode is normal
L1_M_alu_result[12] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L24, A1L275, L1L544, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--P1L6 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~306 at LC_X22_Y20_N0
--operation mode is normal
P1L6 = !L1_M_alu_result[14] & !L1_M_alu_result[13] & !L1_M_alu_result[12] & !L1_M_alu_result[15];
--P1L7 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~307 at LC_X39_Y12_N9
--operation mode is normal
P1L7 = AB1L7 & AB1L6 & P1L5 & P1L6;
--L1_M_alu_result[11] is std_1s10:inst|cpu:the_cpu|M_alu_result[11] at LC_X22_Y20_N6
--operation mode is normal
L1_M_alu_result[11] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L543, A1L275, L1L25, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[10] is std_1s10:inst|cpu:the_cpu|M_alu_result[10] at LC_X19_Y13_N5
--operation mode is normal
L1_M_alu_result[10] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L542, A1L275, L1L26, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[9] is std_1s10:inst|cpu:the_cpu|M_alu_result[9] at LC_X19_Y13_N0
--operation mode is normal
L1_M_alu_result[9] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L27, A1L275, L1L541, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1_M_alu_result[8] is std_1s10:inst|cpu:the_cpu|M_alu_result[8] at LC_X19_Y13_N3
--operation mode is normal
L1_M_alu_result[8] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L540, A1L275, L1L28, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--NB1L2 is std_1s10:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~58 at LC_X39_Y20_N4
--operation mode is normal
NB1L2 = L1_M_alu_result[11] & !L1_M_alu_result[9] & !L1_M_alu_result[8] & !L1_M_alu_result[10];
--L1_internal_d_write is std_1s10:inst|cpu:the_cpu|internal_d_write at LC_X34_Y13_N0
--operation mode is normal
L1_internal_d_write = AMPP_FUNCTION(DE1__clk0, L1L819, KB1L7, L1_E_ctrl_st, L1L1480, E1_data_out);
--QB1L4 is std_1s10:inst|uart1_s1_arbitrator:the_uart1_s1|internal_cpu_data_master_requests_uart1_s1~0 at LC_X34_Y13_N6
--operation mode is normal
QB1L4 = L1_internal_d_write # L1_internal_d_read;
--L1_M_alu_result[6] is std_1s10:inst|cpu:the_cpu|M_alu_result[6] at LC_X19_Y13_N6
--operation mode is normal
L1_M_alu_result[6] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L538, A1L275, L1L32, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--G1L1 is std_1s10:inst|button_pio_s1_arbitrator:the_button_pio_s1|cpu_data_master_requests_button_pio_s1~52 at LC_X40_Y12_N0
--operation mode is normal
G1L1 = L1_M_alu_result[4] & EB1L4 & P1L7 & NB1L2;
--W1_lcd_display_control_slave_wait_counter[1] is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[1] at LC_X40_Y18_N9
--operation mode is normal
W1_lcd_display_control_slave_wait_counter[1]_lut_out = !W1L21 & W1L1 & (!QB1L4 # !W1L22);
W1_lcd_display_control_slave_wait_counter[1] = DFFEAS(W1_lcd_display_control_slave_wait_counter[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--W1_lcd_display_control_slave_wait_counter[0] is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[0] at LC_X40_Y19_N9
--operation mode is normal
W1_lcd_display_control_slave_wait_counter[0]_lut_out = W1L25 # !W1L21 & W1L4 & W1L23;
W1_lcd_display_control_slave_wait_counter[0] = DFFEAS(W1_lcd_display_control_slave_wait_counter[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--W1_lcd_display_control_slave_wait_counter[3] is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[3] at LC_X40_Y19_N5
--operation mode is normal
W1_lcd_display_control_slave_wait_counter[3]_lut_out = !W1L25 & (!W1L21 & W1L7 # !W1L23);
W1_lcd_display_control_slave_wait_counter[3] = DFFEAS(W1_lcd_display_control_slave_wait_counter[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--W1_lcd_display_control_slave_wait_counter[2] is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[2] at LC_X40_Y19_N2
--operation mode is normal
W1_lcd_display_control_slave_wait_counter[2]_lut_out = W1L25 # !W1L21 & W1L23 & W1L11;
W1_lcd_display_control_slave_wait_counter[2] = DFFEAS(W1_lcd_display_control_slave_wait_counter[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--W1L34 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|LessThan0~88 at LC_X39_Y18_N2
--operation mode is normal
W1L34 = !W1_lcd_display_control_slave_wait_counter[0] & !W1_lcd_display_control_slave_wait_counter[1] # !W1_lcd_display_control_slave_wait_counter[2] # !W1_lcd_display_control_slave_wait_counter[3];
--W1_lcd_display_control_slave_wait_counter[5] is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[5] at LC_X40_Y19_N6
--operation mode is normal
W1_lcd_display_control_slave_wait_counter[5]_lut_out = W1L25 # !W1L21 & W1L14 & W1L23;
W1_lcd_display_control_slave_wait_counter[5] = DFFEAS(W1_lcd_display_control_slave_wait_counter[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--W1_lcd_display_control_slave_wait_counter[4] is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[4] at LC_X40_Y19_N4
--operation mode is normal
W1_lcd_display_control_slave_wait_counter[4]_lut_out = !W1L25 & (!W1L21 & W1L15 # !W1L23);
W1_lcd_display_control_slave_wait_counter[4] = DFFEAS(W1_lcd_display_control_slave_wait_counter[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--W1L35 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|LessThan0~89 at LC_X39_Y18_N0
--operation mode is normal
W1L35 = !W1_lcd_display_control_slave_wait_counter[4] & !W1_lcd_display_control_slave_wait_counter[5];
--V1L1 is std_1s10:inst|lcd_display:the_lcd_display|LCD_E~441 at LC_X40_Y18_N1
--operation mode is normal
V1L1 = L1_M_alu_result[7] & G1L1 & L1_internal_d_read & W1L36;
--W1L24 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_in_a_write_cycle~36 at LC_X40_Y18_N6
--operation mode is normal
W1L24 = G1L1 & (L1_M_alu_result[7] & L1_internal_d_write);
--L1_M_mem_byte_en[0] is std_1s10:inst|cpu:the_cpu|M_mem_byte_en[0] at LC_X34_Y21_N5
--operation mode is normal
L1_M_mem_byte_en[0] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[3], L1_E_iw[4], HC1_result[0], HC1_result[1], E1_data_out, L1_W_stall);
--V1L2 is std_1s10:inst|lcd_display:the_lcd_display|LCD_E~442 at LC_X39_Y18_N9
--operation mode is normal
V1L2 = W1_lcd_display_control_slave_wait_counter[2] & (W1_lcd_display_control_slave_wait_counter[0] # W1_lcd_display_control_slave_wait_counter[4] # W1_lcd_display_control_slave_wait_counter[1]) # !W1_lcd_display_control_slave_wait_counter[2] & (W1_lcd_display_control_slave_wait_counter[4] & W1_lcd_display_control_slave_wait_counter[1]);
--V1L3 is std_1s10:inst|lcd_display:the_lcd_display|LCD_E~443 at LC_X40_Y19_N8
--operation mode is normal
V1L3 = L1_M_mem_byte_en[0] & !W1_lcd_display_control_slave_wait_counter[5] & !V1L5;
--W1_d1_reasons_to_wait is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|d1_reasons_to_wait at LC_X40_Y18_N0
--operation mode is normal
W1_d1_reasons_to_wait_lut_out = L1_M_alu_result[7] & G1L1 & (!W1_d1_reasons_to_wait # !W1L21);
W1_d1_reasons_to_wait = DFFEAS(W1_d1_reasons_to_wait_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--W1L22 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_begintransfer~38 at LC_X40_Y18_N7
--operation mode is normal
W1L22 = L1_M_alu_result[7] & G1L1 & (!W1_d1_reasons_to_wait);
--V1L4 is std_1s10:inst|lcd_display:the_lcd_display|LCD_E~444 at LC_X40_Y18_N2
--operation mode is normal
V1L4 = !W1L22 & (V1L1 # V1L3 & W1L24);
--KE1_txd is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|txd at LC_X50_Y9_N1
--operation mode is normal
KE1_txd_lut_out = HE1_control_reg[9] # KE1_pre_txd;
KE1_txd = DFFEAS(KE1_txd_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--DE1__clk0 is std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0 at PLL_5
DE1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(PLD_CLOCKINPUT), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());
--DE1__extclk0 is std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_extclk0 at PLL_5
DE1__extclk0 = PLL.EXTCLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(PLD_CLOCKINPUT), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());
--Q1L52 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[3]~COMB_OUT at LC_X36_Y17_N6
--operation mode is normal
Q1L52 = L1_M_mem_byte_en[3] # !Q1L32 & !Q1L34 # !Q1L80;
--Q1L49 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[2]~COMB_OUT at LC_X36_Y17_N5
--operation mode is normal
Q1L49 = L1_M_mem_byte_en[2] # !Q1L34 & !Q1L32 # !Q1L80;
--Q1L46 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[1]~COMB_OUT at LC_X36_Y17_N9
--operation mode is normal
Q1L46 = L1_M_mem_byte_en[1] # !Q1L32 & !Q1L34 # !Q1L80;
--Q1L43 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[0]~COMB_OUT at LC_X36_Y17_N2
--operation mode is normal
Q1L43 = L1_M_mem_byte_en[0] # !Q1L32 & !Q1L34 # !Q1L80;
--Q1L65 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[3]~COMB_OUT at LC_X35_Y10_N2
--operation mode is normal
Q1L65 = L1_M_mem_byte_en[3] # !Q1L12 & !Q1L9 # !Q1L82;
--Q1L62 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[2]~COMB_OUT at LC_X35_Y10_N8
--operation mode is normal
Q1L62 = L1_M_mem_byte_en[2] # !Q1L12 & !Q1L9 # !Q1L82;
--Q1L59 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[1]~COMB_OUT at LC_X35_Y10_N6
--operation mode is normal
Q1L59 = L1_M_mem_byte_en[1] # !Q1L9 & !Q1L12 # !Q1L82;
--Q1L56 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[0]~COMB_OUT at LC_X35_Y10_N3
--operation mode is normal
Q1L56 = L1_M_mem_byte_en[0] # !Q1L9 & !Q1L12 # !Q1L82;
--Q1L323 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22]~COMB_OUT at LC_X35_Y11_N7
--operation mode is normal
Q1L323 = Q1L440 & (Q1L441 # L1_M_alu_result[22] & Q1L70);
--Q1L320 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21]~COMB_OUT at LC_X35_Y11_N3
--operation mode is normal
Q1L320 = Q1L440 & (Q1L439 # Q1L70 & L1_M_alu_result[21]);
--Q1L317 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20]~COMB_OUT at LC_X35_Y12_N8
--operation mode is normal
Q1L317 = Q1L440 & (Q1L438 # L1_M_alu_result[20] & Q1L70);
--Q1L314 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[19]~COMB_OUT at LC_X35_Y14_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[7]_qfbk = L1_ic_fill_tag[7];
Q1L314 = Q1L440 & (Q1L442 & (L1_ic_fill_tag[7]_qfbk) # !Q1L442 & L1_M_alu_result[19]);
--L1_ic_fill_tag[7] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[7] at LC_X35_Y14_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[7] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[17], E1_data_out, GND, L1_D_ic_fill_starting);
--Q1L312 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[18]~COMB_OUT at LC_X35_Y14_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[6]_qfbk = L1_ic_fill_tag[6];
Q1L312 = Q1L440 & (Q1L442 & (L1_ic_fill_tag[6]_qfbk) # !Q1L442 & L1_M_alu_result[18]);
--L1_ic_fill_tag[6] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[6] at LC_X35_Y14_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[6] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[16], E1_data_out, GND, L1_D_ic_fill_starting);
--Q1L310 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17]~COMB_OUT at LC_X35_Y14_N4
--operation mode is normal
Q1L310 = Q1L440 & (Q1L442 & L1_ic_fill_tag[5] # !Q1L442 & (L1_M_alu_result[17]));
--Q1L307 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[16]~COMB_OUT at LC_X35_Y14_N8
--operation mode is normal
Q1L307 = Q1L440 & (Q1L442 & L1_ic_fill_tag[4] # !Q1L442 & (L1_M_alu_result[16]));
--Q1L304 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[15]~COMB_OUT at LC_X35_Y13_N5
--operation mode is normal
Q1L304 = Q1L72 & L1_M_alu_result[15] # !Q1L72 & (Q1L437 & (L1_ic_fill_tag[3]) # !Q1L437 & L1_M_alu_result[15]);
--Q1L301 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[14]~COMB_OUT at LC_X39_Y17_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[2]_qfbk = L1_ic_fill_tag[2];
Q1L301 = Q1L437 & (Q1L72 & L1_M_alu_result[14] # !Q1L72 & (L1_ic_fill_tag[2]_qfbk)) # !Q1L437 & L1_M_alu_result[14];
--L1_ic_fill_tag[2] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[2] at LC_X39_Y17_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[2] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[12], E1_data_out, GND, L1_D_ic_fill_starting);
--Q1L299 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[13]~COMB_OUT at LC_X35_Y9_N1
--operation mode is normal
Q1L299 = Q1L72 & L1_M_alu_result[13] # !Q1L72 & (Q1L437 & (L1_ic_fill_tag[1]) # !Q1L437 & L1_M_alu_result[13]);
--Q1L296 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[12]~COMB_OUT at LC_X33_Y11_N3
--operation mode is normal
Q1L296 = Q1L72 & L1_M_alu_result[12] # !Q1L72 & (Q1L437 & (L1_ic_fill_tag[0]) # !Q1L437 & L1_M_alu_result[12]);
--Q1L293 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[11]~COMB_OUT at LC_X35_Y13_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_line[6]_qfbk = L1_ic_fill_line[6];
Q1L293 = Q1L72 & L1_M_alu_result[11] # !Q1L72 & (Q1L437 & (L1_ic_fill_line[6]_qfbk) # !Q1L437 & L1_M_alu_result[11]);
--L1_ic_fill_line[6] is std_1s10:inst|cpu:the_cpu|ic_fill_line[6] at LC_X35_Y13_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_line[6] = AMPP_FUNCTION(DE1__clk0, L1L1126, E1_data_out, GND);
--Q1L291 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[10]~COMB_OUT at LC_X39_Y20_N0
--operation mode is normal
Q1L291 = Q1L437 & (Q1L72 & L1_M_alu_result[10] # !Q1L72 & (L1_ic_fill_line[5])) # !Q1L437 & L1_M_alu_result[10];
--Q1L288 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[9]~COMB_OUT at LC_X39_Y20_N3
--operation mode is normal
Q1L288 = Q1L437 & (Q1L72 & L1_M_alu_result[9] # !Q1L72 & (L1_ic_fill_line[4])) # !Q1L437 & L1_M_alu_result[9];
--Q1L285 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[8]~COMB_OUT at LC_X39_Y20_N9
--operation mode is normal
Q1L285 = Q1L437 & (Q1L72 & L1_M_alu_result[8] # !Q1L72 & (L1_ic_fill_line[3])) # !Q1L437 & L1_M_alu_result[8];
--Q1L282 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[7]~COMB_OUT at LC_X39_Y20_N5
--operation mode is normal
Q1L282 = Q1L72 & (L1_M_alu_result[7]) # !Q1L72 & (Q1L437 & L1_ic_fill_line[2] # !Q1L437 & (L1_M_alu_result[7]));
--Q1L279 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[6]~COMB_OUT at LC_X39_Y20_N2
--operation mode is normal
Q1L279 = Q1L72 & L1_M_alu_result[6] # !Q1L72 & (Q1L437 & (L1_ic_fill_line[1]) # !Q1L437 & L1_M_alu_result[6]);
--Q1L276 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[5]~COMB_OUT at LC_X39_Y20_N7
--operation mode is normal
Q1L276 = Q1L72 & L1_M_alu_result[5] # !Q1L72 & (Q1L437 & (L1_ic_fill_line[0]) # !Q1L437 & L1_M_alu_result[5]);
--Q1L273 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[4]~COMB_OUT at LC_X39_Y20_N1
--operation mode is normal
Q1L273 = Q1L72 & L1_M_alu_result[4] # !Q1L72 & (Q1L437 & (L1_ic_fill_ap_offset[2]) # !Q1L437 & L1_M_alu_result[4]);
--Q1L270 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[3]~COMB_OUT at LC_X39_Y20_N8
--operation mode is normal
Q1L270 = Q1L437 & (Q1L72 & (L1_M_alu_result[3]) # !Q1L72 & L1_ic_fill_ap_offset[1]) # !Q1L437 & (L1_M_alu_result[3]);
--Q1L267 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[2]~COMB_OUT at LC_X40_Y13_N7
--operation mode is normal
Q1L267 = Q1L72 & (L1_M_alu_result[2]) # !Q1L72 & (Q1L437 & L1_ic_fill_ap_offset[0] # !Q1L437 & (L1_M_alu_result[2]));
--Q1L264 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[1]~COMB_OUT at LC_X40_Y17_N5
--operation mode is normal
Q1L264 = L1_M_alu_result[1] & (Q1L433 # Q1L440 & Q1L436) # !L1_M_alu_result[1] & Q1L440 & Q1L436;
--Q1L261 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[0]~COMB_OUT at LC_X40_Y17_N9
--operation mode is normal
Q1L261 = Q1L440 & (Q1L434 # Q1L433 & L1_M_alu_result[0]) # !Q1L440 & Q1L433 & L1_M_alu_result[0];
--X1_data_out[7] is std_1s10:inst|led_pio:the_led_pio|data_out[7] at LC_X22_Y27_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
X1_data_out[7]_lut_out = GND;
X1_data_out[7] = DFFEAS(X1_data_out[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , X1L10, L1_M_st_data[7], , , VCC);
--X1_data_out[6] is std_1s10:inst|led_pio:the_led_pio|data_out[6] at LC_X22_Y27_N7
--operation mode is normal
X1_data_out[6]_lut_out = L1_M_st_data[6];
X1_data_out[6] = DFFEAS(X1_data_out[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , X1L10, , , , );
--X1_data_out[5] is std_1s10:inst|led_pio:the_led_pio|data_out[5] at LC_X22_Y27_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
X1_data_out[5]_lut_out = GND;
X1_data_out[5] = DFFEAS(X1_data_out[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , X1L10, L1_M_st_data[5], , , VCC);
--X1_data_out[4] is std_1s10:inst|led_pio:the_led_pio|data_out[4] at LC_X22_Y27_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
X1_data_out[4]_lut_out = GND;
X1_data_out[4] = DFFEAS(X1_data_out[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , X1L10, L1_M_st_data[4], , , VCC);
--X1_data_out[3] is std_1s10:inst|led_pio:the_led_pio|data_out[3] at LC_X22_Y27_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
X1_data_out[3]_lut_out = GND;
X1_data_out[3] = DFFEAS(X1_data_out[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , X1L10, L1_M_st_data[3], , , VCC);
--X1_data_out[2] is std_1s10:inst|led_pio:the_led_pio|data_out[2] at LC_X22_Y27_N8
--operation mode is normal
X1_data_out[2]_lut_out = L1_M_st_data[2];
X1_data_out[2] = DFFEAS(X1_data_out[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , X1L10, , , , );
--X1_data_out[1] is std_1s10:inst|led_pio:the_led_pio|data_out[1] at LC_X22_Y27_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
X1_data_out[1]_lut_out = GND;
X1_data_out[1] = DFFEAS(X1_data_out[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , X1L10, L1_M_st_data[1], , , VCC);
--X1_data_out[0] is std_1s10:inst|led_pio:the_led_pio|data_out[0] at LC_X22_Y27_N3
--operation mode is normal
X1_data_out[0]_lut_out = L1_M_st_data[0];
X1_data_out[0] = DFFEAS(X1_data_out[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , X1L10, , , , );
--HB1_data_out[15] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[15] at LC_X21_Y22_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HB1_data_out[15]_lut_out = GND;
HB1_data_out[15] = DFFEAS(HB1_data_out[15]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, L1_M_st_data[15], , , VCC);
--HB1_data_out[14] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[14] at LC_X21_Y22_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HB1_data_out[14]_lut_out = GND;
HB1_data_out[14] = DFFEAS(HB1_data_out[14]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, L1_M_st_data[14], , , VCC);
--HB1_data_out[13] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[13] at LC_X21_Y22_N1
--operation mode is normal
HB1_data_out[13]_lut_out = L1_M_st_data[13];
HB1_data_out[13] = DFFEAS(HB1_data_out[13]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, , , , );
--HB1_data_out[12] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[12] at LC_X21_Y22_N2
--operation mode is normal
HB1_data_out[12]_lut_out = L1_M_st_data[12];
HB1_data_out[12] = DFFEAS(HB1_data_out[12]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, , , , );
--HB1_data_out[11] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[11] at LC_X21_Y22_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HB1_data_out[11]_lut_out = GND;
HB1_data_out[11] = DFFEAS(HB1_data_out[11]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, L1_M_st_data[11], , , VCC);
--HB1_data_out[10] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[10] at LC_X21_Y22_N6
--operation mode is normal
HB1_data_out[10]_lut_out = L1_M_st_data[10];
HB1_data_out[10] = DFFEAS(HB1_data_out[10]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, , , , );
--HB1_data_out[9] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[9] at LC_X21_Y22_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HB1_data_out[9]_lut_out = GND;
HB1_data_out[9] = DFFEAS(HB1_data_out[9]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, L1_M_st_data[9], , , VCC);
--HB1_data_out[8] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[8] at LC_X36_Y8_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HB1_data_out[8]_lut_out = GND;
HB1_data_out[8] = DFFEAS(HB1_data_out[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, L1_M_st_data[8], , , VCC);
--HB1_data_out[7] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[7] at LC_X21_Y22_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HB1_data_out[7]_lut_out = GND;
HB1_data_out[7] = DFFEAS(HB1_data_out[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, L1_M_st_data[7], , , VCC);
--HB1_data_out[6] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[6] at LC_X21_Y28_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HB1_data_out[6]_lut_out = GND;
HB1_data_out[6] = DFFEAS(HB1_data_out[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, L1_M_st_data[6], , , VCC);
--HB1_data_out[5] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[5] at LC_X21_Y28_N6
--operation mode is normal
HB1_data_out[5]_lut_out = L1_M_st_data[5];
HB1_data_out[5] = DFFEAS(HB1_data_out[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, , , , );
--HB1_data_out[4] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[4] at LC_X21_Y28_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HB1_data_out[4]_lut_out = GND;
HB1_data_out[4] = DFFEAS(HB1_data_out[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, L1_M_st_data[4], , , VCC);
--HB1_data_out[3] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[3] at LC_X21_Y28_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HB1_data_out[3]_lut_out = GND;
HB1_data_out[3] = DFFEAS(HB1_data_out[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, L1_M_st_data[3], , , VCC);
--HB1_data_out[2] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[2] at LC_X21_Y28_N7
--operation mode is normal
HB1_data_out[2]_lut_out = L1_M_st_data[2];
HB1_data_out[2] = DFFEAS(HB1_data_out[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, , , , );
--HB1_data_out[1] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[1] at LC_X21_Y28_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HB1_data_out[1]_lut_out = GND;
HB1_data_out[1] = DFFEAS(HB1_data_out[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, L1_M_st_data[1], , , VCC);
--HB1_data_out[0] is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|data_out[0] at LC_X21_Y28_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HB1_data_out[0]_lut_out = GND;
HB1_data_out[0] = DFFEAS(HB1_data_out[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HB1L18, L1_M_st_data[0], , , VCC);
--FB1L206 is std_1s10:inst|sdram:the_sdram|m_addr[11]~COMB_OUT at LC_X39_Y2_N2
--operation mode is normal
FB1L206 = FB1L602 & FB1L205Q # !FB1L602 & (FB1L600 # FB1L205Q & FB1L601);
--FB1L205Q is std_1s10:inst|sdram:the_sdram|m_addr[11]~_Duplicate_1 at LC_X39_Y2_N2
--operation mode is normal
FB1L205Q = DFFEAS(FB1L206, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L202 is std_1s10:inst|sdram:the_sdram|m_addr[10]~COMB_OUT at LC_X39_Y2_N5
--operation mode is normal
FB1L202 = FB1L602 & (FB1L201Q) # !FB1L602 & (FB1L607 # FB1L601 & FB1L201Q);
--FB1L201Q is std_1s10:inst|sdram:the_sdram|m_addr[10]~_Duplicate_1 at LC_X39_Y2_N5
--operation mode is normal
FB1L201Q = DFFEAS(FB1L202, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L198 is std_1s10:inst|sdram:the_sdram|m_addr[9]~COMB_OUT at LC_X39_Y2_N0
--operation mode is normal
FB1L198 = FB1L602 & (FB1L197Q) # !FB1L602 & (FB1L612 # FB1L197Q & FB1L601);
--FB1L197Q is std_1s10:inst|sdram:the_sdram|m_addr[9]~_Duplicate_1 at LC_X39_Y2_N0
--operation mode is normal
FB1L197Q = DFFEAS(FB1L198, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L194 is std_1s10:inst|sdram:the_sdram|m_addr[8]~COMB_OUT at LC_X39_Y2_N6
--operation mode is normal
FB1L194 = FB1L602 & (FB1L193Q) # !FB1L602 & (FB1L617 # FB1L601 & FB1L193Q);
--FB1L193Q is std_1s10:inst|sdram:the_sdram|m_addr[8]~_Duplicate_1 at LC_X39_Y2_N6
--operation mode is normal
FB1L193Q = DFFEAS(FB1L194, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L190 is std_1s10:inst|sdram:the_sdram|m_addr[7]~COMB_OUT at LC_X33_Y6_N0
--operation mode is normal
FB1L190 = FB1L602 & (FB1L189Q) # !FB1L602 & (FB1L624 # FB1_m_state[6] & FB1L189Q);
--FB1L189Q is std_1s10:inst|sdram:the_sdram|m_addr[7]~_Duplicate_1 at LC_X33_Y6_N0
--operation mode is normal
FB1L189Q = DFFEAS(FB1L190, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L186 is std_1s10:inst|sdram:the_sdram|m_addr[6]~COMB_OUT at LC_X34_Y6_N7
--operation mode is normal
FB1L186 = FB1L626 # FB1L631 & !FB1L602 & !FB1_m_state[6];
--FB1L185Q is std_1s10:inst|sdram:the_sdram|m_addr[6]~_Duplicate_1 at LC_X34_Y6_N7
--operation mode is normal
FB1L185Q = DFFEAS(FB1L186, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L182 is std_1s10:inst|sdram:the_sdram|m_addr[5]~COMB_OUT at LC_X34_Y3_N9
--operation mode is normal
FB1L182 = FB1L633 # !FB1L602 & !FB1_m_state[6] & FB1L638;
--FB1L181Q is std_1s10:inst|sdram:the_sdram|m_addr[5]~_Duplicate_1 at LC_X34_Y3_N9
--operation mode is normal
FB1L181Q = DFFEAS(FB1L182, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L178 is std_1s10:inst|sdram:the_sdram|m_addr[4]~COMB_OUT at LC_X34_Y5_N9
--operation mode is normal
FB1L178 = FB1L640 # !FB1L602 & !FB1_m_state[6] & FB1L645;
--FB1L177Q is std_1s10:inst|sdram:the_sdram|m_addr[4]~_Duplicate_1 at LC_X34_Y5_N9
--operation mode is normal
FB1L177Q = DFFEAS(FB1L178, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L174 is std_1s10:inst|sdram:the_sdram|m_addr[3]~COMB_OUT at LC_X33_Y5_N0
--operation mode is normal
FB1L174 = FB1L647 # !FB1L602 & !FB1_m_state[6] & FB1L652;
--FB1L173Q is std_1s10:inst|sdram:the_sdram|m_addr[3]~_Duplicate_1 at LC_X33_Y5_N0
--operation mode is normal
FB1L173Q = DFFEAS(FB1L174, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L170 is std_1s10:inst|sdram:the_sdram|m_addr[2]~COMB_OUT at LC_X33_Y5_N9
--operation mode is normal
FB1L170 = FB1L654 # !FB1L602 & !FB1_m_state[6] & FB1L659;
--FB1L169Q is std_1s10:inst|sdram:the_sdram|m_addr[2]~_Duplicate_1 at LC_X33_Y5_N9
--operation mode is normal
FB1L169Q = DFFEAS(FB1L170, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L166 is std_1s10:inst|sdram:the_sdram|m_addr[1]~COMB_OUT at LC_X35_Y5_N9
--operation mode is normal
FB1L166 = FB1L661 # !FB1_m_state[6] & !FB1L602 & FB1L666;
--FB1L165Q is std_1s10:inst|sdram:the_sdram|m_addr[1]~_Duplicate_1 at LC_X35_Y5_N9
--operation mode is normal
FB1L165Q = DFFEAS(FB1L166, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L162 is std_1s10:inst|sdram:the_sdram|m_addr[0]~COMB_OUT at LC_X36_Y5_N2
--operation mode is normal
FB1L162 = FB1L668 # !FB1_m_state[6] & FB1L673 & !FB1L602;
--FB1L161Q is std_1s10:inst|sdram:the_sdram|m_addr[0]~_Duplicate_1 at LC_X36_Y5_N2
--operation mode is normal
FB1L161Q = DFFEAS(FB1L162, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L215 is std_1s10:inst|sdram:the_sdram|m_bank[1]~COMB_OUT at LC_X39_Y3_N2
--operation mode is normal
FB1L215 = FB1L676 & (FB1L681 & FB1L675 # !FB1L681 & (FB1L214Q)) # !FB1L676 & (FB1L214Q);
--FB1L214Q is std_1s10:inst|sdram:the_sdram|m_bank[1]~_Duplicate_1 at LC_X39_Y3_N2
--operation mode is normal
FB1L214Q = DFFEAS(FB1L215, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L211 is std_1s10:inst|sdram:the_sdram|m_bank[0]~COMB_OUT at LC_X35_Y6_N6
--operation mode is normal
FB1L211 = FB1L681 & (FB1L676 & FB1L677 # !FB1L676 & (FB1L210Q)) # !FB1L681 & (FB1L210Q);
--FB1L210Q is std_1s10:inst|sdram:the_sdram|m_bank[0]~_Duplicate_1 at LC_X35_Y6_N6
--operation mode is normal
FB1L210Q = DFFEAS(FB1L211, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L383 is std_1s10:inst|sdram:the_sdram|m_dqm[3]~COMB_OUT at LC_X39_Y3_N9
--operation mode is normal
FB1L383 = FB1L676 & (FB1L681 & FB1L713 # !FB1L681 & (FB1L382Q)) # !FB1L676 & (FB1L382Q);
--FB1L382Q is std_1s10:inst|sdram:the_sdram|m_dqm[3]~_Duplicate_1 at LC_X39_Y3_N9
--operation mode is normal
FB1L382Q = DFFEAS(FB1L383, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L379 is std_1s10:inst|sdram:the_sdram|m_dqm[2]~COMB_OUT at LC_X39_Y3_N5
--operation mode is normal
FB1L379 = FB1L676 & (FB1L681 & (FB1L714) # !FB1L681 & FB1L378Q) # !FB1L676 & (FB1L378Q);
--FB1L378Q is std_1s10:inst|sdram:the_sdram|m_dqm[2]~_Duplicate_1 at LC_X39_Y3_N5
--operation mode is normal
FB1L378Q = DFFEAS(FB1L379, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L375 is std_1s10:inst|sdram:the_sdram|m_dqm[1]~COMB_OUT at LC_X39_Y3_N0
--operation mode is normal
FB1L375 = FB1L676 & (FB1L681 & FB1L715 # !FB1L681 & (FB1L374Q)) # !FB1L676 & (FB1L374Q);
--FB1L374Q is std_1s10:inst|sdram:the_sdram|m_dqm[1]~_Duplicate_1 at LC_X39_Y3_N0
--operation mode is normal
FB1L374Q = DFFEAS(FB1L375, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L371 is std_1s10:inst|sdram:the_sdram|m_dqm[0]~COMB_OUT at LC_X39_Y3_N8
--operation mode is normal
FB1L371 = FB1L676 & (FB1L681 & FB1L716 # !FB1L681 & (FB1L370Q)) # !FB1L676 & (FB1L370Q);
--FB1L370Q is std_1s10:inst|sdram:the_sdram|m_dqm[0]~_Duplicate_1 at LC_X39_Y3_N8
--operation mode is normal
FB1L370Q = DFFEAS(FB1L371, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--A1L7 is altera_internal_jtag~TDO at ELA_X0_Y15_N0
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);
--A1L8 is altera_internal_jtag~TMSUTAP at ELA_X0_Y15_N0
A1L8 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);
--A1L6 is altera_internal_jtag~TCKUTAP at ELA_X0_Y15_N0
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);
--altera_internal_jtag is altera_internal_jtag at ELA_X0_Y15_N0
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);
--A1L5 is altera_internal_jtag~SHIFTUSER at ELA_X0_Y15_N0
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);
--A1L9 is altera_internal_jtag~UPDATEUSER at ELA_X0_Y15_N0
A1L9 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);
--A1L4 is altera_internal_jtag~RUNIDLEUSER at ELA_X0_Y15_N0
A1L4 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, altera_reserved_ntrst, , !C1_hub_tdo);
--L1_internal_i_read is std_1s10:inst|cpu:the_cpu|internal_i_read at LC_X40_Y11_N8
--operation mode is normal
L1_internal_i_read = AMPP_FUNCTION(DE1__clk0, L1_ic_fill_ap_cnt[3], L1_D_ic_fill_starting, N1L114, L1_internal_i_read, E1_data_out);
--Q1L244 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal3~112 at LC_X36_Y14_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[11]_qfbk = L1_ic_fill_tag[11];
Q1L244 = !L1_ic_fill_tag[8] & !L1_ic_fill_tag[10] & L1_ic_fill_tag[11]_qfbk & !L1_ic_fill_tag[9];
--L1_ic_fill_tag[11] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[11] at LC_X36_Y14_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[11] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[21], E1_data_out, GND, L1_D_ic_fill_starting);
--Q1L245 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal3~113 at LC_X36_Y14_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[12]_qfbk = L1_ic_fill_tag[12];
Q1L245 = !L1_ic_fill_tag[7] & !L1_ic_fill_tag[5] & !L1_ic_fill_tag[12]_qfbk & !L1_ic_fill_tag[6];
--L1_ic_fill_tag[12] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[12] at LC_X36_Y14_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[12] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[22], E1_data_out, GND, L1_D_ic_fill_starting);
--Q1L246 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal3~114 at LC_X36_Y14_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[4]_qfbk = L1_ic_fill_tag[4];
Q1L246 = !L1_ic_fill_tag[13] & Q1L245 & !L1_ic_fill_tag[4]_qfbk & Q1L244;
--L1_ic_fill_tag[4] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[4] at LC_X36_Y14_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[4] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[14], E1_data_out, GND, L1_D_ic_fill_starting);
--Q1L402 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_in_a_read_cycle~50 at LC_X36_Y14_N9
--operation mode is normal
Q1L402 = L1_internal_i_read & (Q1L246);
--Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable at LC_X39_Y16_N4
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable_lut_out = Q1L450 & (Q1L347 & Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable # !Q1L347 & (Q1L358)) # !Q1L450 & Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable;
Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable = DFFEAS(Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_ram_s1 at LC_X39_Y15_N1
--operation mode is normal
Q1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1_lut_out = Q1_cpu_data_master_requests_ext_ram_s1 & (Q1L1 # !Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal & Q1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1);
Q1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1 = DFFEAS(Q1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L97 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_ram_s1~274 at LC_X33_Y13_N1
--operation mode is normal
Q1L97 = !L1_M_alu_result[20] & L1_M_alu_result[25] & !L1_M_alu_result[21] & !L1_M_alu_result[22];
--Q1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_ext_flash_s1 at LC_X39_Y14_N8
--operation mode is normal
Q1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1_lut_out = Q1_cpu_data_master_requests_ext_flash_s1 & (Q1L333 # Q1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1 & !Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);
Q1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1 = DFFEAS(Q1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1_cpu_data_master_requests_ext_flash_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_flash_s1 at LC_X36_Y13_N0
--operation mode is normal
Q1_cpu_data_master_requests_ext_flash_s1 = !L1_M_alu_result[23] & !L1_M_alu_result[24] & !L1_M_alu_result[25] & QB1L4;
--Q1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_data_master_granted_slave_lan91c111_s1 at LC_X39_Y15_N8
--operation mode is normal
Q1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1_lut_out = Q1_cpu_data_master_requests_lan91c111_s1 & (Q1L329 # Q1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1 & !Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);
Q1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1 = DFFEAS(Q1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L99 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1~271 at LC_X36_Y13_N1
--operation mode is normal
Q1L99 = !L1_M_alu_result[20] & !L1_M_alu_result[25] & L1_M_alu_result[23];
--Q1_cpu_data_master_requests_lan91c111_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1 at LC_X36_Y13_N6
--operation mode is normal
Q1_cpu_data_master_requests_lan91c111_s1 = AB1L7 & Q1L99 & AB1L6 & AB1L9;
--Q1L68 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~108 at LC_X36_Y13_N7
--operation mode is normal
Q1L68 = Q1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1 & (Q1_cpu_data_master_requests_lan91c111_s1 # Q1_cpu_data_master_requests_ext_flash_s1 & Q1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1) # !Q1_last_cycle_cpu_data_master_granted_slave_lan91c111_s1 & Q1_cpu_data_master_requests_ext_flash_s1 & Q1_last_cycle_cpu_data_master_granted_slave_ext_flash_s1;
--Q1L69 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_continuerequest~109 at LC_X36_Y13_N8
--operation mode is normal
Q1L69 = Q1L68 # Q1_last_cycle_cpu_data_master_granted_slave_ext_ram_s1 & Q1L95 & Q1L97;
--GE1_fifo_contains_ones_n is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|fifo_contains_ones_n at LC_X40_Y11_N9
--operation mode is normal
GE1_fifo_contains_ones_n_lut_out = GE1L4 # GE1L6 # GE1L3 # GE1L2;
GE1_fifo_contains_ones_n = DFFEAS(GE1_fifo_contains_ones_n_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GE1L27, , , , );
--N1_internal_cpu_instruction_master_latency_counter[0] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[0] at LC_X40_Y11_N6
--operation mode is normal
N1_internal_cpu_instruction_master_latency_counter[0]_lut_out = N1L153 & AB1L16 # !N1L153 & (N1_internal_cpu_instruction_master_latency_counter[1] & !N1_internal_cpu_instruction_master_latency_counter[0]);
N1_internal_cpu_instruction_master_latency_counter[0] = DFFEAS(N1_internal_cpu_instruction_master_latency_counter[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--N1_internal_cpu_instruction_master_latency_counter[1] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_latency_counter[1] at LC_X40_Y11_N5
--operation mode is normal
N1_internal_cpu_instruction_master_latency_counter[1]_lut_out = N1L153 & (N1L152) # !N1L153 & N1_internal_cpu_instruction_master_latency_counter[1] & (N1_internal_cpu_instruction_master_latency_counter[0]);
N1_internal_cpu_instruction_master_latency_counter[1] = DFFEAS(N1_internal_cpu_instruction_master_latency_counter[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L359 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_cpu_instruction_master_qualified_request_ext_ram_s1~90 at LC_X40_Y11_N7
--operation mode is normal
Q1L359 = L1_internal_i_read & (GE1_fifo_contains_ones_n # N1_internal_cpu_instruction_master_latency_counter[0] & N1_internal_cpu_instruction_master_latency_counter[1]);
--Q1L403 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_in_a_read_cycle~51 at LC_X36_Y14_N6
--operation mode is normal
Q1L403 = Q1L402 & !Q1L359 & (!Q1L69 # !Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable);
--Q1L4 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~352 at LC_X40_Y15_N4
--operation mode is arithmetic
Q1L4 = Q1_ext_ram_bus_avalon_slave_arb_addend[0] $ Q1L403;
--Q1L5 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~353 at LC_X40_Y15_N4
--operation mode is arithmetic
Q1L5 = CARRY(!Q1_ext_ram_bus_avalon_slave_arb_addend[0] & !Q1L403);
--Q1L6 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~354 at LC_X40_Y14_N0
--operation mode is arithmetic
Q1L6 = Q1L6_carry_eqn $ (Q1L402 & !Q1L360);
--Q1L7 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~355 at LC_X40_Y14_N0
--operation mode is arithmetic
Q1L7_cout_0 = !Q1L33 & (Q1L360 # !Q1L402);
Q1L7 = CARRY(Q1L7_cout_0);
--Q1L8 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~355COUT1_428 at LC_X40_Y14_N0
--operation mode is arithmetic
Q1L8_cout_1 = !Q1L33 & (Q1L360 # !Q1L402);
Q1L8 = CARRY(Q1L8_cout_1);
--Q1L106 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_granted_lan91c111_s1~66 at LC_X40_Y14_N8
--operation mode is normal
Q1L106 = Q1L403 & (Q1L4 # Q1L6);
--Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[0] at LC_X40_Y14_N8
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[0] = DFFEAS(Q1L106, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1L342, , , , );
--Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] at LC_X40_Y18_N3
--operation mode is normal
Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0]_lut_out = Q1L117 & L1_internal_d_read & Q1L72;
Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] = DFFEAS(Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L81 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~69 at LC_X36_Y13_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1]_qfbk = Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1];
Q1L81 = Q1_cpu_data_master_requests_lan91c111_s1 & (!Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] & !Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1]_qfbk # !L1_internal_d_read);
--Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1] at LC_X36_Y13_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[1] = DFFEAS(Q1L81, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0], , , VCC);
--Q1L443 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~37 at LC_X36_Y14_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[8]_qfbk = L1_ic_fill_tag[8];
Q1L443 = !L1_ic_fill_tag[10] & !L1_ic_fill_tag[8]_qfbk & !L1_ic_fill_tag[9];
--L1_ic_fill_tag[8] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[8] at LC_X36_Y14_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[8] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[18], E1_data_out, GND, L1_D_ic_fill_starting);
--Q1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1 at LC_X39_Y14_N1
--operation mode is normal
Q1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1_lut_out = Q1L445 & (Q1L335 # !Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal & Q1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1);
Q1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1 = DFFEAS(Q1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--AB1L13 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_requests_onchip_ram_64_kbytes_s1~48 at LC_X36_Y14_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[13]_qfbk = L1_ic_fill_tag[13];
AB1L13 = !L1_ic_fill_tag[12] & !L1_ic_fill_tag[11] & L1_ic_fill_tag[13]_qfbk & L1_internal_i_read;
--L1_ic_fill_tag[13] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[13] at LC_X36_Y14_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[13] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[23], E1_data_out, GND, L1_D_ic_fill_starting);
--Q1L102 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~3 at LC_X36_Y14_N4
--operation mode is normal
Q1L102 = Q1_last_cycle_cpu_instruction_master_granted_slave_ext_ram_s1 & Q1L443 & AB1L13;
--Q1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1 at LC_X39_Y15_N4
--operation mode is normal
Q1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1_lut_out = Q1L402 & (Q1L327 # Q1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1 & !Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);
Q1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1 = DFFEAS(Q1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L103 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~54 at LC_X40_Y15_N1
--operation mode is normal
Q1L103 = Q1L102 # L1_internal_i_read & Q1_last_cycle_cpu_instruction_master_granted_slave_lan91c111_s1 & Q1L246;
--Q1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 at LC_X39_Y14_N3
--operation mode is normal
Q1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1_lut_out = Q1L118 & (Q1L331 # Q1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 & !Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal);
Q1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 = DFFEAS(Q1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L118 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_requests_ext_flash_s1~26 at LC_X40_Y11_N2
--operation mode is normal
Q1L118 = L1_internal_i_read & !L1_ic_fill_tag[12] & !L1_ic_fill_tag[13] & !L1_ic_fill_tag[11];
--Q1L101 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~1 at LC_X34_Y13_N1
--operation mode is normal
Q1L101 = Q1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 & Q1L118;
--Q1L82 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~70 at LC_X40_Y15_N2
--operation mode is normal
Q1L82 = !Q1_cpu_instruction_master_arbiterlock & Q1L81;
--Q1L9 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~356 at LC_X40_Y15_N5
--operation mode is arithmetic
Q1L9 = Q1L82 $ Q1_ext_ram_bus_avalon_slave_arb_addend[1] $ !Q1L9_carry_eqn;
--Q1L10 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~357 at LC_X40_Y15_N5
--operation mode is arithmetic
Q1L10_cout_0 = Q1L82 & (!Q1L5 # !Q1_ext_ram_bus_avalon_slave_arb_addend[1]) # !Q1L82 & !Q1_ext_ram_bus_avalon_slave_arb_addend[1] & !Q1L5;
Q1L10 = CARRY(Q1L10_cout_0);
--Q1L11 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~357COUT1_420 at LC_X40_Y15_N5
--operation mode is arithmetic
Q1L11_cout_1 = Q1L82 & (!Q1L5 # !Q1_ext_ram_bus_avalon_slave_arb_addend[1]) # !Q1L82 & !Q1_ext_ram_bus_avalon_slave_arb_addend[1] & !Q1L5;
Q1L11 = CARRY(Q1L11_cout_1);
--Q1L12 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~358 at LC_X40_Y14_N1
--operation mode is arithmetic
Q1L12_carry_eqn = (!Q1L33 & Q1L7) # (Q1L33 & Q1L8);
Q1L12 = Q1L82 $ (!Q1L12_carry_eqn);
--Q1L13 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~359 at LC_X40_Y14_N1
--operation mode is arithmetic
Q1L13_cout_0 = Q1L82 # !Q1L7;
Q1L13 = CARRY(Q1L13_cout_0);
--Q1L14 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~359COUT1_430 at LC_X40_Y14_N1
--operation mode is arithmetic
Q1L14_cout_1 = Q1L82 # !Q1L8;
Q1L14 = CARRY(Q1L14_cout_1);
--Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] at LC_X40_Y16_N0
--operation mode is normal
Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0]_lut_out = Q1L247 & Q1L87 & (Q1L345 # Q1_d1_ext_ram_bus_avalon_slave_end_xfer);
Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] = DFFEAS(Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L73 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~143 at LC_X36_Y15_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1]_qfbk = Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1];
Q1L73 = !Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1]_qfbk & !Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] # !L1_internal_d_read;
--Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] at LC_X36_Y15_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] = DFFEAS(Q1L73, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0], , , VCC);
--M1_internal_cpu_data_master_dbs_address[1] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[1] at LC_X34_Y21_N6
--operation mode is normal
M1_internal_cpu_data_master_dbs_address[1]_lut_out = M1_internal_cpu_data_master_dbs_address[1] $ (M1_internal_cpu_data_master_dbs_address[0] & M1L307 & Q1_cpu_data_master_requests_ext_flash_s1);
M1_internal_cpu_data_master_dbs_address[1] = DFFEAS(M1_internal_cpu_data_master_dbs_address[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--L1_M_mem_byte_en[3] is std_1s10:inst|cpu:the_cpu|M_mem_byte_en[3] at LC_X34_Y21_N9
--operation mode is normal
L1_M_mem_byte_en[3] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[3], L1_E_iw[4], HC1_result[0], HC1_result[1], E1_data_out, L1_W_stall);
--L1_M_mem_byte_en[2] is std_1s10:inst|cpu:the_cpu|M_mem_byte_en[2] at LC_X34_Y21_N1
--operation mode is normal
L1_M_mem_byte_en[2] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[3], L1_E_iw[4], HC1_result[0], HC1_result[1], E1_data_out, L1_W_stall);
--M1_internal_cpu_data_master_dbs_address[0] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_dbs_address[0] at LC_X34_Y21_N3
--operation mode is normal
M1_internal_cpu_data_master_dbs_address[0]_lut_out = M1_internal_cpu_data_master_dbs_address[0] $ (M1L307 & Q1_cpu_data_master_requests_ext_flash_s1);
M1_internal_cpu_data_master_dbs_address[0] = DFFEAS(M1_internal_cpu_data_master_dbs_address[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L66 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_byteenable_ext_flash_s1~310 at LC_X34_Y21_N2
--operation mode is normal
Q1L66 = M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & L1_M_mem_byte_en[3] # !M1_internal_cpu_data_master_dbs_address[0] & (L1_M_mem_byte_en[2]));
--L1_M_mem_byte_en[1] is std_1s10:inst|cpu:the_cpu|M_mem_byte_en[1] at LC_X34_Y21_N4
--operation mode is normal
L1_M_mem_byte_en[1] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[3], L1_E_iw[4], HC1_result[0], HC1_result[1], E1_data_out, L1_W_stall);
--Q1L67 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_byteenable_ext_flash_s1~311 at LC_X34_Y21_N7
--operation mode is normal
Q1L67 = !M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & (L1_M_mem_byte_en[1]) # !M1_internal_cpu_data_master_dbs_address[0] & L1_M_mem_byte_en[0]);
--M1_internal_cpu_data_master_no_byte_enables_and_last_term is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_no_byte_enables_and_last_term at LC_X34_Y21_N0
--operation mode is normal
M1_internal_cpu_data_master_no_byte_enables_and_last_term_lut_out = !L1_M_mem_byte_en[3] & M1_internal_cpu_data_master_dbs_address[0] & M1_internal_cpu_data_master_dbs_address[1] & L1_internal_d_write;
M1_internal_cpu_data_master_no_byte_enables_and_last_term = DFFEAS(M1_internal_cpu_data_master_no_byte_enables_and_last_term_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L74 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~144 at LC_X34_Y21_N8
--operation mode is normal
Q1L74 = !M1_internal_cpu_data_master_no_byte_enables_and_last_term & (Q1L66 # Q1L67);
--Q1L75 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~145 at LC_X34_Y13_N7
--operation mode is normal
Q1L75 = Q1_cpu_data_master_requests_ext_flash_s1 & Q1L73 & (Q1L74 # !L1_internal_d_write);
--Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] at LC_X39_Y13_N0
--operation mode is normal
Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]_lut_out = !Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] & L1_internal_d_read & !Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] & Q1L71;
Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] = DFFEAS(Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L77 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~127 at LC_X39_Y13_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1]_qfbk = Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1];
Q1L77 = !Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1]_qfbk & !Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] # !L1_internal_d_read;
--Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] at LC_X39_Y13_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[1] = DFFEAS(Q1L77, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0], , , VCC);
--M1_internal_cpu_data_master_waitrequest is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|internal_cpu_data_master_waitrequest at LC_X36_Y17_N8
--operation mode is normal
M1_internal_cpu_data_master_waitrequest_lut_out = !M1L9 & !M1L17 & !M1L3 & !M1L8;
M1_internal_cpu_data_master_waitrequest = DFFEAS(M1_internal_cpu_data_master_waitrequest_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L78 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~128 at LC_X36_Y17_N7
--operation mode is normal
Q1L78 = !M1_internal_cpu_data_master_waitrequest & !Q1_write_n_to_the_ext_ram_local # !L1_internal_d_write;
--Q1L79 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~129 at LC_X33_Y13_N8
--operation mode is normal
Q1L79 = Q1L77 & Q1L95 & Q1L97 & Q1L78;
--M1L1 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1042 at LC_X40_Y16_N3
--operation mode is normal
M1L1 = Q1_cpu_instruction_master_arbiterlock # !Q1L79 & !Q1L75 & !Q1L81;
--Q1L444 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~38 at LC_X36_Y13_N9
--operation mode is normal
Q1L444 = Q1L445 & !Q1L359 & (!Q1L69 # !Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable);
--N1L146 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]~36 at LC_X40_Y15_N0
--operation mode is normal
N1L146 = Q1L118 & !Q1L359 & (!Q1L69 # !Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable);
--Q1L345 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_begins_xfer~52 at LC_X40_Y16_N4
--operation mode is normal
Q1L345 = !N1L146 & !Q1L403 & !Q1L444 & M1L1;
--Q1_ext_ram_bus_avalon_slave_begins_xfer is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_begins_xfer at LC_X40_Y16_N7
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_begins_xfer = !Q1_d1_ext_ram_bus_avalon_slave_end_xfer & (!Q1L345);
--Q1L76 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~146 at LC_X34_Y13_N5
--operation mode is normal
Q1L76 = Q1L75 & (!Q1L101 & !Q1L103 # !Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable);
--Q1L15 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~360 at LC_X40_Y15_N7
--operation mode is arithmetic
Q1L15_carry_eqn = (!Q1L5 & Q1L22) # (Q1L5 & Q1L23);
Q1L15 = Q1_ext_ram_bus_avalon_slave_arb_addend[3] $ Q1L76 $ !Q1L15_carry_eqn;
--Q1L16 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~361 at LC_X40_Y15_N7
--operation mode is arithmetic
Q1L16_cout_0 = Q1_ext_ram_bus_avalon_slave_arb_addend[3] & Q1L76 & !Q1L22 # !Q1_ext_ram_bus_avalon_slave_arb_addend[3] & (Q1L76 # !Q1L22);
Q1L16 = CARRY(Q1L16_cout_0);
--Q1L17 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~361COUT1_424 at LC_X40_Y15_N7
--operation mode is arithmetic
Q1L17_cout_1 = Q1_ext_ram_bus_avalon_slave_arb_addend[3] & Q1L76 & !Q1L23 # !Q1_ext_ram_bus_avalon_slave_arb_addend[3] & (Q1L76 # !Q1L23);
Q1L17 = CARRY(Q1L17_cout_1);
--Q1L18 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~362 at LC_X40_Y14_N3
--operation mode is arithmetic
Q1L18_carry_eqn = (!Q1L33 & Q1L25) # (Q1L33 & Q1L26);
Q1L18 = Q1L76 $ !Q1L18_carry_eqn;
--Q1L19 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~363 at LC_X40_Y14_N3
--operation mode is arithmetic
Q1L19_cout_0 = Q1L76 # !Q1L25;
Q1L19 = CARRY(Q1L19_cout_0);
--Q1L20 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~363COUT1_434 at LC_X40_Y14_N3
--operation mode is arithmetic
Q1L20_cout_1 = Q1L76 # !Q1L26;
Q1L20 = CARRY(Q1L20_cout_1);
--Q1L249 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_counter_load_value[1]~149 at LC_X41_Y17_N1
--operation mode is normal
Q1L249 = L1_internal_d_write & Q1L76 & (Q1L15 # Q1L18);
--Q1_ext_flash_s1_wait_counter[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[3] at LC_X41_Y17_N2
--operation mode is normal
Q1_ext_flash_s1_wait_counter[3]_lut_out = Q1L251 # Q1_ext_flash_s1_wait_counter[3] & (Q1_ext_flash_s1_wait_counter[0] # !Q1L447);
Q1_ext_flash_s1_wait_counter[3] = DFFEAS(Q1_ext_flash_s1_wait_counter[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1_ext_flash_s1_wait_counter[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[2] at LC_X41_Y17_N8
--operation mode is normal
Q1_ext_flash_s1_wait_counter[2]_lut_out = !Q1L247 & !Q1L251 & (Q1L39 $ !Q1_ext_flash_s1_wait_counter[2]);
Q1_ext_flash_s1_wait_counter[2] = DFFEAS(Q1_ext_flash_s1_wait_counter[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1_ext_flash_s1_wait_counter[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[1] at LC_X41_Y18_N2
--operation mode is normal
Q1_ext_flash_s1_wait_counter[1]_lut_out = Q1_ext_ram_bus_avalon_slave_begins_xfer & !Q1_ext_flash_s1_in_a_read_cycle & (Q1L250 # Q1L249) # !Q1_ext_ram_bus_avalon_slave_begins_xfer & Q1L250;
Q1_ext_flash_s1_wait_counter[1] = DFFEAS(Q1_ext_flash_s1_wait_counter[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L447 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_write_n_to_the_ext_flash~108 at LC_X41_Y18_N4
--operation mode is normal
Q1L447 = !Q1_ext_flash_s1_wait_counter[1] & (!Q1_ext_flash_s1_wait_counter[2]);
--Q1_lan91c111_s1_wait_counter[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[0] at LC_X40_Y16_N1
--operation mode is normal
Q1_lan91c111_s1_wait_counter[0]_lut_out = Q1L401 # !Q1_lan91c111_s1_wait_counter[0] & !Q1L2 & Q1L415;
Q1_lan91c111_s1_wait_counter[0] = DFFEAS(Q1_lan91c111_s1_wait_counter[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1_lan91c111_s1_wait_counter[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[3] at LC_X36_Y16_N6
--operation mode is normal
Q1_lan91c111_s1_wait_counter[3]_lut_out = Q1L37 # Q1_ext_ram_bus_avalon_slave_begins_xfer & (Q1L106 # Q1L348);
Q1_lan91c111_s1_wait_counter[3] = DFFEAS(Q1_lan91c111_s1_wait_counter[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1_lan91c111_s1_wait_counter[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[2] at LC_X36_Y16_N9
--operation mode is normal
Q1_lan91c111_s1_wait_counter[2]_lut_out = Q1L415 & !Q1L400 & (Q1L38 $ Q1_lan91c111_s1_wait_counter[2]);
Q1_lan91c111_s1_wait_counter[2] = DFFEAS(Q1_lan91c111_s1_wait_counter[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1_lan91c111_s1_wait_counter[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_wait_counter[1] at LC_X36_Y16_N3
--operation mode is normal
Q1_lan91c111_s1_wait_counter[1]_lut_out = Q1L415 & !Q1L400 & (Q1_lan91c111_s1_wait_counter[0] $ !Q1_lan91c111_s1_wait_counter[1]);
Q1_lan91c111_s1_wait_counter[1] = DFFEAS(Q1_lan91c111_s1_wait_counter[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L415 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|LessThan1~82 at LC_X36_Y16_N8
--operation mode is normal
Q1L415 = Q1_lan91c111_s1_wait_counter[1] # Q1_lan91c111_s1_wait_counter[2] # Q1_lan91c111_s1_wait_counter[0] # Q1_lan91c111_s1_wait_counter[3];
--Q1L87 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_read_data_valid_ext_flash_s1_shift_register_in~13 at LC_X39_Y17_N9
--operation mode is normal
Q1L87 = Q1L76 & L1_internal_d_read & (Q1L15 # Q1L18);
--Q1L21 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~364 at LC_X40_Y15_N6
--operation mode is arithmetic
Q1L21_carry_eqn = (!Q1L5 & Q1L10) # (Q1L5 & Q1L11);
Q1L21 = Q1_ext_ram_bus_avalon_slave_arb_addend[2] $ N1L146 $ Q1L21_carry_eqn;
--Q1L22 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~365 at LC_X40_Y15_N6
--operation mode is arithmetic
Q1L22_cout_0 = Q1_ext_ram_bus_avalon_slave_arb_addend[2] & (!Q1L10 # !N1L146) # !Q1_ext_ram_bus_avalon_slave_arb_addend[2] & !N1L146 & !Q1L10;
Q1L22 = CARRY(Q1L22_cout_0);
--Q1L23 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~365COUT1_422 at LC_X40_Y15_N6
--operation mode is arithmetic
Q1L23_cout_1 = Q1_ext_ram_bus_avalon_slave_arb_addend[2] & (!Q1L11 # !N1L146) # !Q1_ext_ram_bus_avalon_slave_arb_addend[2] & !N1L146 & !Q1L11;
Q1L23 = CARRY(Q1L23_cout_1);
--Q1L24 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~366 at LC_X40_Y14_N2
--operation mode is arithmetic
Q1L24_carry_eqn = (!Q1L33 & Q1L13) # (Q1L33 & Q1L14);
Q1L24 = Q1L24_carry_eqn $ (Q1L118 & !Q1L360);
--Q1L25 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~367 at LC_X40_Y14_N2
--operation mode is arithmetic
Q1L25_cout_0 = !Q1L13 & (Q1L360 # !Q1L118);
Q1L25 = CARRY(Q1L25_cout_0);
--Q1L26 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~367COUT1_432 at LC_X40_Y14_N2
--operation mode is arithmetic
Q1L26_cout_1 = !Q1L14 & (Q1L360 # !Q1L118);
Q1L26 = CARRY(Q1L26_cout_1);
--Q1L104 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_granted_ext_flash_s1~38 at LC_X40_Y17_N3
--operation mode is normal
Q1L104 = N1L146 & (Q1L21 # Q1L24);
--Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[2] at LC_X40_Y17_N3
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[2] = DFFEAS(Q1L104, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1L342, , , , );
--Q1L27 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~368 at LC_X40_Y15_N8
--operation mode is arithmetic
Q1L27_carry_eqn = (!Q1L5 & Q1L16) # (Q1L5 & Q1L17);
Q1L27 = Q1_ext_ram_bus_avalon_slave_arb_addend[4] $ Q1L444 $ Q1L27_carry_eqn;
--Q1L28 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~369 at LC_X40_Y15_N8
--operation mode is arithmetic
Q1L28_cout_0 = Q1_ext_ram_bus_avalon_slave_arb_addend[4] & (!Q1L16 # !Q1L444) # !Q1_ext_ram_bus_avalon_slave_arb_addend[4] & !Q1L444 & !Q1L16;
Q1L28 = CARRY(Q1L28_cout_0);
--Q1L29 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~369COUT1_426 at LC_X40_Y15_N8
--operation mode is arithmetic
Q1L29_cout_1 = Q1_ext_ram_bus_avalon_slave_arb_addend[4] & (!Q1L17 # !Q1L444) # !Q1_ext_ram_bus_avalon_slave_arb_addend[4] & !Q1L444 & !Q1L17;
Q1L29 = CARRY(Q1L29_cout_1);
--Q1L30 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~370 at LC_X40_Y14_N4
--operation mode is arithmetic
Q1L30_carry_eqn = (!Q1L33 & Q1L19) # (Q1L33 & Q1L20);
Q1L30 = Q1L30_carry_eqn $ (!Q1L360 & Q1L445);
--Q1L31 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~371 at LC_X40_Y14_N4
--operation mode is arithmetic
Q1L31 = CARRY(!Q1L20 & (Q1L360 # !Q1L445));
--Q1L105 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_granted_ext_ram_s1~31 at LC_X39_Y17_N7
--operation mode is normal
Q1L105 = Q1L444 & (Q1L30 # Q1L27);
--Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[4] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[4] at LC_X39_Y17_N7
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[4] = DFFEAS(Q1L105, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1L342, , , , );
--Q1L80 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_ram_s1~130 at LC_X39_Y16_N5
--operation mode is normal
Q1L80 = Q1L79 & (!Q1L103 & !Q1L101 # !Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable);
--Q1L32 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~372 at LC_X40_Y15_N9
--operation mode is arithmetic
Q1L32_carry_eqn = (!Q1L5 & Q1L28) # (Q1L5 & Q1L29);
Q1L32 = Q1L80 $ Q1_ext_ram_bus_avalon_slave_arb_addend[5] $ !Q1L32_carry_eqn;
--Q1L33 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~373 at LC_X40_Y15_N9
--operation mode is arithmetic
Q1L33 = CARRY(Q1L80 & (!Q1L29 # !Q1_ext_ram_bus_avalon_slave_arb_addend[5]) # !Q1L80 & !Q1_ext_ram_bus_avalon_slave_arb_addend[5] & !Q1L29);
--Q1L34 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~374 at LC_X40_Y14_N5
--operation mode is normal
Q1L34 = Q1L80 $ !Q1L34_carry_eqn;
--Q1L71 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_ext_ram_s1~76 at LC_X40_Y14_N9
--operation mode is normal
Q1L71 = Q1L80 & (Q1L32 # Q1L34);
--Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[5] at LC_X40_Y14_N9
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5] = DFFEAS(Q1L71, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1L342, , , , );
--FB1_m_state[6] is std_1s10:inst|sdram:the_sdram|m_state[6] at LC_X36_Y2_N5
--operation mode is normal
FB1_m_state[6]_lut_out = FB1L449 # FB1L469 & (FB1L453 # FB1L450);
FB1_m_state[6] = DFFEAS(FB1_m_state[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_m_state[1] is std_1s10:inst|sdram:the_sdram|m_state[1] at LC_X35_Y1_N7
--operation mode is normal
FB1_m_state[1]_lut_out = FB1L481 # FB1L482 & (FB1L455 # FB1L484);
FB1_m_state[1] = DFFEAS(FB1_m_state[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_m_state[8] is std_1s10:inst|sdram:the_sdram|m_state[8] at LC_X31_Y2_N9
--operation mode is normal
FB1_m_state[8]_lut_out = FB1_m_state[8] $ (FB1L444 & FB1L445 & FB1L717);
FB1_m_state[8] = DFFEAS(FB1_m_state[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_m_state[5] is std_1s10:inst|sdram:the_sdram|m_state[5] at LC_X34_Y2_N9
--operation mode is normal
FB1_m_state[5]_lut_out = FB1L457 # FB1L454 & (FB1L455 # FB1L458);
FB1_m_state[5] = DFFEAS(FB1_m_state[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_m_state[2] is std_1s10:inst|sdram:the_sdram|m_state[2] at LC_X33_Y3_N4
--operation mode is normal
FB1_m_state[2]_lut_out = FB1L470 # FB1L471 & (FB1L475 # FB1L478);
FB1_m_state[2] = DFFEAS(FB1_m_state[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L594 is std_1s10:inst|sdram:the_sdram|Mux104~1565 at LC_X33_Y2_N0
--operation mode is normal
FB1L594 = !FB1_m_state[8] & !FB1_m_state[5] & (!FB1_m_state[2]);
--FB1L432 is std_1s10:inst|sdram:the_sdram|Mux19~1734 at LC_X32_Y3_N4
--operation mode is normal
FB1L432 = FB1_m_state[6] # FB1_m_state[1] # !FB1L594;
--FB1_m_state[7] is std_1s10:inst|sdram:the_sdram|m_state[7] at LC_X35_Y3_N4
--operation mode is normal
FB1_m_state[7]_lut_out = FB1L447 # FB1_m_state[7] & (!FB1L426 # !FB1L427);
FB1_m_state[7] = DFFEAS(FB1_m_state[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_m_state[4] is std_1s10:inst|sdram:the_sdram|m_state[4] at LC_X36_Y1_N6
--operation mode is normal
FB1_m_state[4]_lut_out = FB1L459 # FB1L717 & FB1L463 & FB1L535;
FB1_m_state[4] = DFFEAS(FB1_m_state[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_m_state[3] is std_1s10:inst|sdram:the_sdram|m_state[3] at LC_X36_Y1_N3
--operation mode is normal
FB1_m_state[3]_lut_out = FB1L465 # FB1L717 & FB1L466 & FB1L467;
FB1_m_state[3] = DFFEAS(FB1_m_state[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_m_state[0] is std_1s10:inst|sdram:the_sdram|m_state[0] at LC_X31_Y2_N6
--operation mode is normal
FB1_m_state[0]_lut_out = !FB1L485 & (FB1_m_state[0] # FB1L30 & !FB1L744);
FB1_m_state[0] = DFFEAS(FB1_m_state[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L433 is std_1s10:inst|sdram:the_sdram|Mux19~1735 at LC_X35_Y2_N3
--operation mode is normal
FB1L433 = FB1_m_state[0] & (!FB1_m_state[4] & !FB1_m_state[3] # !FB1_m_state[7]);
--FB1_f_pop is std_1s10:inst|sdram:the_sdram|f_pop at LC_X34_Y4_N8
--operation mode is normal
FB1_f_pop_lut_out = FB1L562 & (FB1L564 # FB1L474 & FB1_m_state[0]);
FB1_f_pop = DFFEAS(FB1_f_pop_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--EE1_rd_address is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_address at LC_X35_Y7_N0
--operation mode is normal
EE1_rd_address_lut_out = EE1_rd_address $ (!FB1L724 & FB1_f_pop & EE1L127);
EE1_rd_address = DFFEAS(EE1_rd_address_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_active_addr[9] is std_1s10:inst|sdram:the_sdram|active_addr[9] at LC_X35_Y7_N4
--operation mode is normal
FB1_active_addr[9]_lut_out = FB1L565 & (E1_data_out & (FB1L592) # !E1_data_out & FB1_active_addr[9]) # !FB1L565 & FB1_active_addr[9];
FB1_active_addr[9] = DFFEAS(FB1_active_addr[9]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L115 is std_1s10:inst|sdram:the_sdram|Equal4~447 at LC_X35_Y7_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[45]_qfbk = EE1_entry_0[45];
FB1L115 = FB1_active_addr[9] $ (EE1_rd_address & EE1_entry_1[45] # !EE1_rd_address & (EE1_entry_0[45]_qfbk));
--EE1_entry_0[45] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[45] at LC_X35_Y7_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[45] = DFFEAS(FB1L115, GLOBAL(DE1__clk0), VCC, , EE1L62, GB1L45, , , VCC);
--FB1_active_addr[8] is std_1s10:inst|sdram:the_sdram|active_addr[8] at LC_X35_Y6_N7
--operation mode is normal
FB1_active_addr[8]_lut_out = FB1L14 & (FB1L12 & EE1L173 # !FB1L12 & (FB1_active_addr[8])) # !FB1L14 & (FB1_active_addr[8]);
FB1_active_addr[8] = DFFEAS(FB1_active_addr[8]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L113 is std_1s10:inst|sdram:the_sdram|Equal3~74 at LC_X35_Y7_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[44]_qfbk = EE1_entry_0[44];
FB1L113 = FB1_active_addr[8] $ (EE1_rd_address & EE1_entry_1[44] # !EE1_rd_address & (EE1_entry_0[44]_qfbk));
--EE1_entry_0[44] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[44] at LC_X35_Y7_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[44] = DFFEAS(FB1L113, GLOBAL(DE1__clk0), VCC, , EE1L62, GB1L44, , , VCC);
--FB1_active_addr[14] is std_1s10:inst|sdram:the_sdram|active_addr[14] at LC_X36_Y6_N3
--operation mode is normal
FB1_active_addr[14]_lut_out = E1_data_out & (FB1L565 & (FB1L580) # !FB1L565 & FB1_active_addr[14]) # !E1_data_out & FB1_active_addr[14];
FB1_active_addr[14] = DFFEAS(FB1_active_addr[14]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L116 is std_1s10:inst|sdram:the_sdram|Equal4~448 at LC_X35_Y7_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[50]_qfbk = EE1_entry_0[50];
FB1L116 = FB1_active_addr[14] $ (EE1_rd_address & EE1_entry_1[50] # !EE1_rd_address & (EE1_entry_0[50]_qfbk));
--EE1_entry_0[50] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[50] at LC_X35_Y7_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[50] = DFFEAS(FB1L116, GLOBAL(DE1__clk0), VCC, , EE1L62, GB1L50, , , VCC);
--FB1_active_addr[13] is std_1s10:inst|sdram:the_sdram|active_addr[13] at LC_X34_Y5_N5
--operation mode is normal
FB1_active_addr[13]_lut_out = FB1L565 & (E1_data_out & (FB1L582) # !E1_data_out & FB1_active_addr[13]) # !FB1L565 & FB1_active_addr[13];
FB1_active_addr[13] = DFFEAS(FB1_active_addr[13]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L117 is std_1s10:inst|sdram:the_sdram|Equal4~449 at LC_X35_Y7_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[49]_qfbk = EE1_entry_0[49];
FB1L117 = FB1_active_addr[13] $ (EE1_rd_address & EE1_entry_1[49] # !EE1_rd_address & (EE1_entry_0[49]_qfbk));
--EE1_entry_0[49] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[49] at LC_X35_Y7_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[49] = DFFEAS(FB1L117, GLOBAL(DE1__clk0), VCC, , EE1L62, GB1L49, , , VCC);
--FB1L720 is std_1s10:inst|sdram:the_sdram|pending~245 at LC_X35_Y7_N8
--operation mode is normal
FB1L720 = FB1L115 # FB1L113 # FB1L116 # FB1L117;
--FB1_active_addr[11] is std_1s10:inst|sdram:the_sdram|active_addr[11] at LC_X34_Y4_N1
--operation mode is normal
FB1_active_addr[11]_lut_out = E1_data_out & (FB1L565 & (FB1L586) # !FB1L565 & FB1_active_addr[11]) # !E1_data_out & FB1_active_addr[11];
FB1_active_addr[11] = DFFEAS(FB1_active_addr[11]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L118 is std_1s10:inst|sdram:the_sdram|Equal4~450 at LC_X35_Y9_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[47]_qfbk = EE1_entry_0[47];
FB1L118 = FB1_active_addr[11] $ (EE1_rd_address & EE1_entry_1[47] # !EE1_rd_address & (EE1_entry_0[47]_qfbk));
--EE1_entry_0[47] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[47] at LC_X35_Y9_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[47] = DFFEAS(FB1L118, GLOBAL(DE1__clk0), VCC, , EE1L62, GB1L47, , , VCC);
--FB1_active_addr[21] is std_1s10:inst|sdram:the_sdram|active_addr[21] at LC_X35_Y6_N5
--operation mode is normal
FB1_active_addr[21]_lut_out = FB1L14 & (FB1L12 & (EE1L174) # !FB1L12 & FB1_active_addr[21]) # !FB1L14 & FB1_active_addr[21];
FB1_active_addr[21] = DFFEAS(FB1_active_addr[21]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L114 is std_1s10:inst|sdram:the_sdram|Equal3~75 at LC_X35_Y9_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[57]_qfbk = EE1_entry_0[57];
FB1L114 = FB1_active_addr[21] $ (EE1_rd_address & EE1_entry_1[57] # !EE1_rd_address & (EE1_entry_0[57]_qfbk));
--EE1_entry_0[57] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[57] at LC_X35_Y9_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[57] = DFFEAS(FB1L114, GLOBAL(DE1__clk0), VCC, , EE1L62, GB1L57, , , VCC);
--FB1_active_addr[16] is std_1s10:inst|sdram:the_sdram|active_addr[16] at LC_X33_Y9_N6
--operation mode is normal
FB1_active_addr[16]_lut_out = FB1L565 & (E1_data_out & (FB1L576) # !E1_data_out & FB1_active_addr[16]) # !FB1L565 & FB1_active_addr[16];
FB1_active_addr[16] = DFFEAS(FB1_active_addr[16]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L119 is std_1s10:inst|sdram:the_sdram|Equal4~451 at LC_X35_Y9_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[52]_qfbk = EE1_entry_0[52];
FB1L119 = FB1_active_addr[16] $ (EE1_rd_address & EE1_entry_1[52] # !EE1_rd_address & (EE1_entry_0[52]_qfbk));
--EE1_entry_0[52] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[52] at LC_X35_Y9_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[52] = DFFEAS(FB1L119, GLOBAL(DE1__clk0), VCC, , EE1L62, GB1L52, , , VCC);
--FB1_active_addr[15] is std_1s10:inst|sdram:the_sdram|active_addr[15] at LC_X34_Y6_N8
--operation mode is normal
FB1_active_addr[15]_lut_out = E1_data_out & (FB1L565 & (FB1L578) # !FB1L565 & FB1_active_addr[15]) # !E1_data_out & FB1_active_addr[15];
FB1_active_addr[15] = DFFEAS(FB1_active_addr[15]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L120 is std_1s10:inst|sdram:the_sdram|Equal4~452 at LC_X34_Y6_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[51]_qfbk = EE1_entry_0[51];
FB1L120 = FB1_active_addr[15] $ (EE1_rd_address & EE1_entry_1[51] # !EE1_rd_address & (EE1_entry_0[51]_qfbk));
--EE1_entry_0[51] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[51] at LC_X34_Y6_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[51] = DFFEAS(FB1L120, GLOBAL(DE1__clk0), VCC, , EE1L62, GB1L51, , , VCC);
--FB1L721 is std_1s10:inst|sdram:the_sdram|pending~246 at LC_X35_Y9_N9
--operation mode is normal
FB1L721 = FB1L119 # FB1L120 # FB1L118 # FB1L114;
--FB1_active_addr[17] is std_1s10:inst|sdram:the_sdram|active_addr[17] at LC_X33_Y9_N7
--operation mode is normal
FB1_active_addr[17]_lut_out = FB1L565 & (E1_data_out & (FB1L574) # !E1_data_out & FB1_active_addr[17]) # !FB1L565 & FB1_active_addr[17];
FB1_active_addr[17] = DFFEAS(FB1_active_addr[17]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L121 is std_1s10:inst|sdram:the_sdram|Equal4~453 at LC_X33_Y11_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[53]_qfbk = EE1_entry_0[53];
FB1L121 = FB1_active_addr[17] $ (EE1_rd_address & EE1_entry_1[53] # !EE1_rd_address & (EE1_entry_0[53]_qfbk));
--EE1_entry_0[53] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[53] at LC_X33_Y11_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[53] = DFFEAS(FB1L121, GLOBAL(DE1__clk0), VCC, , EE1L62, GB1L53, , , VCC);
--FB1_active_addr[10] is std_1s10:inst|sdram:the_sdram|active_addr[10] at LC_X33_Y9_N8
--operation mode is normal
FB1_active_addr[10]_lut_out = FB1L565 & (E1_data_out & (FB1L588) # !E1_data_out & FB1_active_addr[10]) # !FB1L565 & FB1_active_addr[10];
FB1_active_addr[10] = DFFEAS(FB1_active_addr[10]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L122 is std_1s10:inst|sdram:the_sdram|Equal4~454 at LC_X33_Y11_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[46]_qfbk = EE1_entry_0[46];
FB1L122 = FB1_active_addr[10] $ (EE1_rd_address & EE1_entry_1[46] # !EE1_rd_address & (EE1_entry_0[46]_qfbk));
--EE1_entry_0[46] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[46] at LC_X33_Y11_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[46] = DFFEAS(FB1L122, GLOBAL(DE1__clk0), VCC, , EE1L62, GB1L46, , , VCC);
--EE1_entry_0[58] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[58] at LC_X33_Y4_N6
--operation mode is normal
EE1_entry_0[58]_lut_out = !GB1_sdram_s1_in_a_write_cycle;
EE1_entry_0[58] = DFFEAS(EE1_entry_0[58]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1_entry_1[58] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[58] at LC_X35_Y15_N8
--operation mode is normal
EE1_entry_1[58]_lut_out = !GB1_sdram_s1_in_a_write_cycle;
EE1_entry_1[58] = DFFEAS(EE1_entry_1[58]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--FB1_active_rnw is std_1s10:inst|sdram:the_sdram|active_rnw at LC_X33_Y4_N0
--operation mode is normal
FB1_active_rnw_lut_out = FB1L14 & (FB1L12 & EE1L175 # !FB1L12 & (FB1_active_rnw)) # !FB1L14 & (FB1_active_rnw);
FB1_active_rnw = DFFEAS(FB1_active_rnw_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L745 is std_1s10:inst|sdram:the_sdram|rnw_match~0 at LC_X33_Y4_N7
--operation mode is normal
FB1L745 = FB1_active_rnw $ (EE1_rd_address & EE1_entry_1[58] # !EE1_rd_address & (EE1_entry_0[58]));
--FB1_active_addr[20] is std_1s10:inst|sdram:the_sdram|active_addr[20] at LC_X33_Y9_N4
--operation mode is normal
FB1_active_addr[20]_lut_out = FB1L565 & (E1_data_out & (FB1L568) # !E1_data_out & FB1_active_addr[20]) # !FB1L565 & FB1_active_addr[20];
FB1_active_addr[20] = DFFEAS(FB1_active_addr[20]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L123 is std_1s10:inst|sdram:the_sdram|Equal4~455 at LC_X33_Y11_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[56]_qfbk = EE1_entry_0[56];
FB1L123 = FB1_active_addr[20] $ (EE1_rd_address & (EE1_entry_1[56]) # !EE1_rd_address & EE1_entry_0[56]_qfbk);
--EE1_entry_0[56] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56] at LC_X33_Y11_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[56] = DFFEAS(FB1L123, GLOBAL(DE1__clk0), VCC, , EE1L62, GB1L56, , , VCC);
--FB1L722 is std_1s10:inst|sdram:the_sdram|pending~247 at LC_X33_Y11_N2
--operation mode is normal
FB1L722 = FB1L122 # FB1L121 # FB1L745 # FB1L123;
--FB1_active_addr[18] is std_1s10:inst|sdram:the_sdram|active_addr[18] at LC_X39_Y4_N3
--operation mode is normal
FB1_active_addr[18]_lut_out = FB1L565 & (E1_data_out & FB1L572 # !E1_data_out & (FB1_active_addr[18])) # !FB1L565 & (FB1_active_addr[18]);
FB1_active_addr[18] = DFFEAS(FB1_active_addr[18]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L124 is std_1s10:inst|sdram:the_sdram|Equal4~456 at LC_X35_Y12_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[54]_qfbk = EE1_entry_0[54];
FB1L124 = FB1_active_addr[18] $ (EE1_rd_address & EE1_entry_1[54] # !EE1_rd_address & (EE1_entry_0[54]_qfbk));
--EE1_entry_0[54] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[54] at LC_X35_Y12_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[54] = DFFEAS(FB1L124, GLOBAL(DE1__clk0), VCC, , EE1L62, GB1L54, , , VCC);
--FB1_active_addr[12] is std_1s10:inst|sdram:the_sdram|active_addr[12] at LC_X33_Y9_N9
--operation mode is normal
FB1_active_addr[12]_lut_out = FB1L565 & (E1_data_out & (FB1L584) # !E1_data_out & FB1_active_addr[12]) # !FB1L565 & FB1_active_addr[12];
FB1_active_addr[12] = DFFEAS(FB1_active_addr[12]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L125 is std_1s10:inst|sdram:the_sdram|Equal4~457 at LC_X34_Y8_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[48]_qfbk = EE1_entry_0[48];
FB1L125 = FB1_active_addr[12] $ (EE1_rd_address & (EE1_entry_1[48]) # !EE1_rd_address & EE1_entry_0[48]_qfbk);
--EE1_entry_0[48] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[48] at LC_X34_Y8_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[48] = DFFEAS(FB1L125, GLOBAL(DE1__clk0), VCC, , EE1L62, GB1L48, , , VCC);
--FB1_active_cs_n is std_1s10:inst|sdram:the_sdram|active_cs_n at LC_X2_Y12_N0
--operation mode is normal
FB1_active_cs_n_lut_out = FB1L32 & (FB1_refresh_request # !EE1L127 & FB1_active_cs_n) # !FB1L32 & (FB1_active_cs_n);
FB1_active_cs_n = DFFEAS(FB1_active_cs_n_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1_active_addr[19] is std_1s10:inst|sdram:the_sdram|active_addr[19] at LC_X35_Y8_N2
--operation mode is normal
FB1_active_addr[19]_lut_out = FB1L565 & (E1_data_out & (FB1L570) # !E1_data_out & FB1_active_addr[19]) # !FB1L565 & FB1_active_addr[19];
FB1_active_addr[19] = DFFEAS(FB1_active_addr[19]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L126 is std_1s10:inst|sdram:the_sdram|Equal4~458 at LC_X35_Y11_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[55]_qfbk = EE1_entry_0[55];
FB1L126 = FB1_active_addr[19] $ (EE1_rd_address & EE1_entry_1[55] # !EE1_rd_address & (EE1_entry_0[55]_qfbk));
--EE1_entry_0[55] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[55] at LC_X35_Y11_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[55] = DFFEAS(FB1L126, GLOBAL(DE1__clk0), VCC, , EE1L62, GB1L55, , , VCC);
--FB1L723 is std_1s10:inst|sdram:the_sdram|pending~248 at LC_X35_Y11_N8
--operation mode is normal
FB1L723 = FB1L125 # FB1L124 # FB1_active_cs_n # FB1L126;
--FB1L724 is std_1s10:inst|sdram:the_sdram|pending~249 at LC_X35_Y11_N9
--operation mode is normal
FB1L724 = FB1L722 # FB1L721 # FB1L720 # FB1L723;
--EE1_entries[0] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entries[0] at LC_X36_Y4_N2
--operation mode is normal
EE1_entries[0]_lut_out = FB1_f_select $ (FB1L407 & !EE1_entries[1] & !EE1_entries[0] # !FB1L407 & (EE1_entries[0]));
EE1_entries[0] = DFFEAS(EE1_entries[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--EE1_entries[1] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entries[1] at LC_X36_Y4_N7
--operation mode is normal
EE1_entries[1]_lut_out = FB1_f_select & (EE1_entries[1] & (EE1_entries[0]) # !EE1_entries[1] & !FB1L407 & !EE1_entries[0]) # !FB1_f_select & (EE1_entries[1] $ (FB1L407 & EE1_entries[0]));
EE1_entries[1] = DFFEAS(EE1_entries[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--EE1L127 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|Equal1~94 at LC_X39_Y10_N2
--operation mode is normal
EE1L127 = EE1_entries[0] # EE1_entries[1];
--FB1L434 is std_1s10:inst|sdram:the_sdram|Mux19~1736 at LC_X35_Y2_N9
--operation mode is normal
FB1L434 = FB1_m_state[3] $ (FB1_m_state[4]);
--FB1_init_done is std_1s10:inst|sdram:the_sdram|init_done at LC_X40_Y2_N1
--operation mode is normal
FB1_init_done_lut_out = FB1_init_done # FB1_i_state[0] & !FB1_i_state[1] & FB1_i_state[2];
FB1_init_done = DFFEAS(FB1_init_done_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_i_cmd[1] is std_1s10:inst|sdram:the_sdram|i_cmd[1] at LC_X40_Y2_N7
--operation mode is normal
FB1_i_cmd[1]_lut_out = FB1_i_state[2] # FB1_i_state[1] & !FB1_i_state[0];
FB1_i_cmd[1] = DFFEAS(FB1_i_cmd[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FB1L134, , , , );
--FB1L518 is std_1s10:inst|sdram:the_sdram|Mux40~1435 at LC_X33_Y3_N3
--operation mode is normal
FB1L518 = !FB1_m_state[3] & !FB1_m_state[4];
--FB1L435 is std_1s10:inst|sdram:the_sdram|Mux19~1737 at LC_X35_Y2_N6
--operation mode is normal
FB1L435 = FB1L433 & FB1L434 & !FB1L233 # !FB1L433 & (FB1L436);
--FB1_i_cmd[3] is std_1s10:inst|sdram:the_sdram|i_cmd[3] at LC_X40_Y2_N9
--operation mode is normal
FB1_i_cmd[3]_lut_out = FB1_i_state[1] # FB1_i_state[0] # FB1_i_state[2];
FB1_i_cmd[3] = DFFEAS(FB1_i_cmd[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FB1L134, , , , );
--FB1_refresh_request is std_1s10:inst|sdram:the_sdram|refresh_request at LC_X35_Y3_N7
--operation mode is normal
FB1_refresh_request_lut_out = FB1_init_done & !FB1_ack_refresh_request & (FB1L112 # FB1_refresh_request);
FB1_refresh_request = DFFEAS(FB1_refresh_request_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L415 is std_1s10:inst|sdram:the_sdram|Mux17~1798 at LC_X2_Y12_N7
--operation mode is normal
FB1L415 = FB1_init_done & (!FB1_refresh_request) # !FB1_init_done & !FB1_i_cmd[3];
--FB1L416 is std_1s10:inst|sdram:the_sdram|Mux17~1799 at LC_X33_Y2_N6
--operation mode is normal
FB1L416 = !FB1_m_state[8] & !FB1_m_state[3] & !FB1_m_state[1] & !FB1_m_state[5];
--FB1L417 is std_1s10:inst|sdram:the_sdram|Mux17~1800 at LC_X2_Y12_N4
--operation mode is normal
FB1L417 = FB1_m_state[0] & !FB1L416 & (FB1_m_state[4]) # !FB1_m_state[0] & (FB1L415 # FB1_m_state[4] # !FB1L416);
--FB1L418 is std_1s10:inst|sdram:the_sdram|Mux17~1801 at LC_X33_Y2_N1
--operation mode is normal
FB1L418 = FB1_m_state[8] & !FB1_m_state[3] & !FB1_m_state[1] & !FB1_m_state[5] # !FB1_m_state[8] & (FB1_m_state[3] & !FB1_m_state[1] & !FB1_m_state[5] # !FB1_m_state[3] & (FB1_m_state[1] $ FB1_m_state[5]));
--FB1L419 is std_1s10:inst|sdram:the_sdram|Mux17~1802 at LC_X2_Y12_N5
--operation mode is normal
FB1L419 = FB1_m_state[0] & (FB1_active_cs_n # !FB1L418 & !FB1_m_state[4]);
--FB1L420 is std_1s10:inst|sdram:the_sdram|Mux17~1803 at LC_X2_Y12_N8
--operation mode is normal
FB1L420 = !FB1_m_state[2] & !FB1_m_state[6] & (FB1L417 # FB1L419);
--FB1L421 is std_1s10:inst|sdram:the_sdram|Mux17~1804 at LC_X2_Y12_N9
--operation mode is normal
FB1L421 = !FB1_m_state[2] & FB1_m_state[0] & (FB1_refresh_request # !FB1_active_cs_n);
--FB1L422 is std_1s10:inst|sdram:the_sdram|Mux17~1805 at LC_X2_Y12_N2
--operation mode is normal
FB1L422 = FB1_m_state[6] & (FB1_m_state[4] # !FB1L416 # !FB1L421);
--FB1_m_next[7] is std_1s10:inst|sdram:the_sdram|m_next[7] at LC_X31_Y3_N6
--operation mode is normal
FB1_m_next[7]_lut_out = FB1_m_state[8] & FB1_m_next[7] & (FB1L491 # !FB1L511) # !FB1_m_state[8] & (FB1L491);
FB1_m_next[7] = DFFEAS(FB1_m_next[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FB1L512, , , , );
--FB1_m_next[0] is std_1s10:inst|sdram:the_sdram|m_next[0] at LC_X31_Y3_N7
--operation mode is normal
FB1_m_next[0]_lut_out = FB1_m_state[8] & FB1_m_next[0] & (FB1L517 # !FB1L511) # !FB1_m_state[8] & !FB1L517;
FB1_m_next[0] = DFFEAS(FB1_m_next[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FB1L512, , , , );
--FB1_m_next[1] is std_1s10:inst|sdram:the_sdram|m_next[1] at LC_X31_Y3_N1
--operation mode is normal
FB1_m_next[1]_lut_out = FB1_m_state[8] & FB1_m_next[1] & (FB1L510 # !FB1L511) # !FB1_m_state[8] & FB1L510;
FB1_m_next[1] = DFFEAS(FB1_m_next[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FB1L512, , , , );
--FB1_m_next[3] is std_1s10:inst|sdram:the_sdram|m_next[3] at LC_X32_Y4_N6
--operation mode is normal
FB1_m_next[3]_lut_out = FB1_m_state[7] & FB1_m_next[3] & (FB1L504 # !FB1L618) # !FB1_m_state[7] & (FB1L504);
FB1_m_next[3] = DFFEAS(FB1_m_next[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FB1L512, , , , );
--FB1_m_next[4] is std_1s10:inst|sdram:the_sdram|m_next[4] at LC_X32_Y4_N8
--operation mode is normal
FB1_m_next[4]_lut_out = FB1_m_state[7] & FB1_m_next[4] & (FB1L497 # !FB1L618) # !FB1_m_state[7] & (FB1L497);
FB1_m_next[4] = DFFEAS(FB1_m_next[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FB1L512, , , , );
--FB1L127 is std_1s10:inst|sdram:the_sdram|Equal5~50 at LC_X32_Y4_N1
--operation mode is normal
FB1L127 = !FB1_m_next[4] & !FB1_m_next[1] & FB1_m_next[0] & !FB1_m_next[3];
--FB1L423 is std_1s10:inst|sdram:the_sdram|Mux17~1806 at LC_X35_Y3_N3
--operation mode is normal
FB1L423 = !FB1_m_state[4] & FB1L416 & FB1_m_state[0];
--FB1L424 is std_1s10:inst|sdram:the_sdram|Mux17~1807 at LC_X32_Y4_N0
--operation mode is normal
FB1L424 = FB1_active_cs_n & (!FB1_m_next[7] # !FB1L127) # !FB1L423;
--FB1L425 is std_1s10:inst|sdram:the_sdram|Mux17~1808 at LC_X32_Y4_N2
--operation mode is normal
FB1L425 = FB1L422 # FB1L420 # FB1_m_state[2] & FB1L424;
--FB1L426 is std_1s10:inst|sdram:the_sdram|Mux17~1809 at LC_X32_Y3_N0
--operation mode is normal
FB1L426 = !FB1_m_state[2] & FB1_m_state[0];
--FB1L427 is std_1s10:inst|sdram:the_sdram|Mux17~1810 at LC_X35_Y3_N0
--operation mode is normal
FB1L427 = !FB1_m_state[4] & FB1L416 & !FB1_m_state[6];
--FB1_i_cmd[2] is std_1s10:inst|sdram:the_sdram|i_cmd[2] at LC_X40_Y2_N6
--operation mode is normal
FB1_i_cmd[2]_lut_out = FB1_i_state[2] # FB1_i_state[1] $ FB1_i_state[0];
FB1_i_cmd[2] = DFFEAS(FB1_i_cmd[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FB1L134, , , , );
--FB1L454 is std_1s10:inst|sdram:the_sdram|Mux25~1249 at LC_X34_Y2_N3
--operation mode is normal
FB1L454 = !FB1_m_state[6] & !FB1_m_state[1] & !FB1_m_state[7];
--FB1L428 is std_1s10:inst|sdram:the_sdram|Mux18~1358 at LC_X34_Y2_N4
--operation mode is normal
FB1L428 = !FB1_m_state[0] & (FB1_init_done # !FB1_i_cmd[2] # !FB1L454);
--FB1L469 is std_1s10:inst|sdram:the_sdram|Mux28~1601 at LC_X35_Y1_N5
--operation mode is normal
FB1L469 = !FB1_m_state[1] & !FB1_m_state[7];
--FB1L429 is std_1s10:inst|sdram:the_sdram|Mux18~1359 at LC_X36_Y2_N0
--operation mode is normal
FB1L429 = !FB1L469 & FB1_m_state[6] # !FB1L594 # !FB1L518;
--FB1L430 is std_1s10:inst|sdram:the_sdram|Mux18~1360 at LC_X35_Y1_N4
--operation mode is normal
FB1L430 = FB1_m_state[0] & (!FB1_m_state[6]);
--FB1L431 is std_1s10:inst|sdram:the_sdram|Mux18~1361 at LC_X35_Y1_N9
--operation mode is normal
FB1L431 = FB1_m_state[1] $ FB1_m_state[7];
--FB1L437 is std_1s10:inst|sdram:the_sdram|Mux20~1311 at LC_X35_Y2_N7
--operation mode is normal
FB1L437 = !FB1_m_state[7] & !FB1_m_state[2] & FB1L416;
--FB1L438 is std_1s10:inst|sdram:the_sdram|Mux20~1312 at LC_X35_Y2_N1
--operation mode is normal
FB1L438 = FB1_m_state[4] # FB1_init_done & !FB1_m_state[0];
--FB1_i_cmd[0] is std_1s10:inst|sdram:the_sdram|i_cmd[0] at LC_X40_Y2_N2
--operation mode is normal
FB1_i_cmd[0]_lut_out = FB1_i_state[2] # !FB1_i_state[1] & FB1_i_state[0];
FB1_i_cmd[0] = DFFEAS(FB1_i_cmd[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FB1L134, , , , );
--FB1L439 is std_1s10:inst|sdram:the_sdram|Mux20~1313 at LC_X35_Y2_N2
--operation mode is normal
FB1L439 = FB1_m_state[0] & (FB1_m_state[6] $ FB1L438) # !FB1_m_state[0] & !FB1_m_state[6] & !FB1L438 & FB1_i_cmd[0];
--L1_E_control_rd_data_without_mmu_regs[2] is std_1s10:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[2] at LC_X30_Y21_N5
--operation mode is normal
L1_E_control_rd_data_without_mmu_regs[2] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[8], L1_M_ipending_reg[2], L1L205, L1_M_ienable_reg[2], E1_data_out, L1_W_stall);
--L1_E_logic_op[1] is std_1s10:inst|cpu:the_cpu|E_logic_op[1] at LC_X22_Y6_N7
--operation mode is normal
L1_E_logic_op[1] = AMPP_FUNCTION(DE1__clk0, L1L827, L1_D_iw[15], L1_D_iw[4], L1_D_iw[5], E1_data_out, L1_W_stall);
--L1_E_src1_prelim[2] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[2] at LC_X18_Y21_N3
--operation mode is normal
L1_E_src1_prelim[2] = AMPP_FUNCTION(DE1__clk0, L1_D_src1_hazard_W, MC1_q_b[2], L1L1383, L1_W_wr_data[2], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_E_src1_hazard_M is std_1s10:inst|cpu:the_cpu|E_src1_hazard_M at LC_X19_Y19_N7
--operation mode is normal
L1_E_src1_hazard_M = AMPP_FUNCTION(DE1__clk0, L1L384, L1L383, L1L822, L1L207, E1_data_out, L1_W_stall);
--L1_M_mul_shift_rot_result[2] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[2] at LC_X13_Y16_N8
--operation mode is normal
L1_M_mul_shift_rot_result[2] = AMPP_FUNCTION(DE1__clk0, L1L1284, QC1_result[34], L1L1255, QC1_result[2], E1_data_out, L1_M_ctrl_rot);
--L1L1381 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[2]~3645 at LC_X18_Y21_N4
--operation mode is normal
L1L1381 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[2], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[2] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[2] at LC_X24_Y21_N8
--operation mode is normal
L1_av_ld_data_aligned_or_div[2] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[18], L1_d_readdata_d1[2], L1L141, L1_M_ld_align_sh16, E1_data_out, L1_M_ld_align_sh8);
--L1L1382 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[2]~3646 at LC_X27_Y21_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L1382 = AMPP_FUNCTION(L1_M_alu_result[2], L1_av_ld_or_div_done, L1_av_ld_data_aligned_or_div[2]);
--L1_M_ctrl_mul_shift_rot is std_1s10:inst|cpu:the_cpu|M_ctrl_mul_shift_rot at LC_X27_Y21_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_ctrl_mul_shift_rot = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_mul_shift_rot, E1_data_out, GND, L1_W_stall);
--L1L605 is std_1s10:inst|cpu:the_cpu|E_src1[2]~1965 at LC_X18_Y21_N5
--operation mode is normal
L1L605 = AMPP_FUNCTION(L1_E_src1_prelim[2], L1L1382, L1_E_src1_hazard_M, L1L1381);
--L1_E_src2_imm[2] is std_1s10:inst|cpu:the_cpu|E_src2_imm[2] at LC_X19_Y12_N9
--operation mode is normal
L1_E_src2_imm[2] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[2], L1_D_iw[5], L1_D_iw[8], L1L235, E1_data_out, L1_W_stall);
--L1L1329 is std_1s10:inst|cpu:the_cpu|M_st_data[10]~COMBOUT at LC_X19_Y20_N6
--operation mode is normal
L1L1329 = AMPP_FUNCTION(L1_E_src2_prelim[2], L1_E_src2_hazard_M, L1L1383);
--L1_M_st_data[10] is std_1s10:inst|cpu:the_cpu|M_st_data[10] at LC_X19_Y20_N6
--operation mode is normal
L1_M_st_data[10] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[2], L1_E_src2_hazard_M, L1L811, L1L1383, E1_data_out, L1L845, L1_W_stall);
--L1_E_ctrl_src2_is_imm is std_1s10:inst|cpu:the_cpu|E_ctrl_src2_is_imm at LC_X19_Y8_N3
--operation mode is normal
L1_E_ctrl_src2_is_imm = AMPP_FUNCTION(DE1__clk0, L1L421, L1L222, L1_D_ctrl_b_not_src, L1L247, E1_data_out, L1_W_stall);
--L1L671 is std_1s10:inst|cpu:the_cpu|E_src2[2]~1491 at LC_X19_Y12_N7
--operation mode is normal
L1L671 = AMPP_FUNCTION(L1_E_src2_imm[2], L1_E_ctrl_src2_is_imm, L1L1329);
--L1_E_logic_op[0] is std_1s10:inst|cpu:the_cpu|E_logic_op[0] at LC_X19_Y7_N4
--operation mode is normal
L1_E_logic_op[0] = AMPP_FUNCTION(DE1__clk0, L1L827, L1_D_iw[14], L1_D_iw[3], L1L830, E1_data_out, L1_W_stall);
--L1L1 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12881 at LC_X28_Y21_N1
--operation mode is normal
L1L1 = AMPP_FUNCTION(L1_E_logic_op[1], L1L605, L1_E_logic_op[0], L1L671);
--L1_E_extra_pc[0] is std_1s10:inst|cpu:the_cpu|E_extra_pc[0] at LC_X34_Y20_N2
--operation mode is normal
L1_E_extra_pc[0] = AMPP_FUNCTION(DE1__clk0, L1L218, L1_D_iw[21], L1_D_pc_plus_one[0], L1_D_br_taken_waddr_partial[0], E1_data_out, L1_W_stall);
--HC1_result[2] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[2] at LC_X18_Y12_N2
--operation mode is arithmetic
HC1_result[2] = AMPP_FUNCTION(L1L671, L1L605, HC1L6, HC1L7, L1_E_ctrl_alu_subtract);
--HC1L9 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT at LC_X18_Y12_N2
--operation mode is arithmetic
HC1L9 = AMPP_FUNCTION(L1L671, L1L605, HC1L6, L1_E_ctrl_alu_subtract);
--HC1L10 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUTCOUT1_151 at LC_X18_Y12_N2
--operation mode is arithmetic
HC1L10 = AMPP_FUNCTION(L1L671, L1L605, HC1L7, L1_E_ctrl_alu_subtract);
--L1_E_ctrl_dst_data_sel_pc_plus_one is std_1s10:inst|cpu:the_cpu|E_ctrl_dst_data_sel_pc_plus_one at LC_X18_Y7_N4
--operation mode is normal
L1_E_ctrl_dst_data_sel_pc_plus_one = AMPP_FUNCTION(DE1__clk0, L1L238, L1L841, L1L227, L1L207, E1_data_out, L1_W_stall);
--L1L2 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12882 at LC_X28_Y21_N8
--operation mode is normal
L1L2 = AMPP_FUNCTION(L1_E_extra_pc[0], L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[2]);
--L1_E_ctrl_dst_data_sel_logic_result is std_1s10:inst|cpu:the_cpu|E_ctrl_dst_data_sel_logic_result at LC_X22_Y21_N4
--operation mode is normal
L1_E_ctrl_dst_data_sel_logic_result = AMPP_FUNCTION(DE1__clk0, L1L247, L1_D_iw[16], L1_D_iw[13], L1L226, E1_data_out, L1_W_stall);
--L1L3 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12883 at LC_X28_Y21_N2
--operation mode is normal
L1L3 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_logic_result, L1L1, L1L2);
--L1_E_ctrl_rdctl_inst is std_1s10:inst|cpu:the_cpu|E_ctrl_rdctl_inst at LC_X22_Y20_N8
--operation mode is normal
L1_E_ctrl_rdctl_inst = AMPP_FUNCTION(DE1__clk0, L1L842, L1L247, E1_data_out, L1_W_stall);
--L1_E_ctrl_dst_data_sel_cmp is std_1s10:inst|cpu:the_cpu|E_ctrl_dst_data_sel_cmp at LC_X22_Y6_N3
--operation mode is normal
L1_E_ctrl_dst_data_sel_cmp = AMPP_FUNCTION(DE1__clk0, L1L212, L1L224, L1L225, L1L223, E1_data_out, L1_W_stall);
--L1L429 is std_1s10:inst|cpu:the_cpu|E_alu_result[2]~2246 at LC_X28_Y21_N6
--operation mode is normal
L1L429 = AMPP_FUNCTION(L1_E_control_rd_data_without_mmu_regs[2], L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1L3);
--L1_M_alu_result[2] is std_1s10:inst|cpu:the_cpu|M_alu_result[2] at LC_X28_Y21_N6
--operation mode is normal
L1_M_alu_result[2] = AMPP_FUNCTION(DE1__clk0, L1_E_control_rd_data_without_mmu_regs[2], L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1L3, E1_data_out, L1_W_stall);
--L1_M_mul_shift_rot_stall is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_stall at LC_X27_Y22_N8
--operation mode is normal
L1_M_mul_shift_rot_stall = AMPP_FUNCTION(DE1__clk0, L1_W_stall, L1L819, L1_E_ctrl_mul_shift_rot, L1_M_valid_mul_shift_rot_entered_M, E1_data_out);
--L1L1480 is std_1s10:inst|cpu:the_cpu|W_stall~19 at LC_X27_Y22_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L1480 = AMPP_FUNCTION(L1_M_valid_from_E, L1_av_ld_or_div_done, L1_M_mul_shift_rot_stall);
--L1_M_ctrl_ld is std_1s10:inst|cpu:the_cpu|M_ctrl_ld at LC_X27_Y22_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_ctrl_ld = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_ld, E1_data_out, GND, L1_W_stall);
--KB1L7 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|control_wr_strobe~28 at LC_X41_Y15_N3
--operation mode is normal
KB1L7 = !M1_internal_cpu_data_master_waitrequest & L1_internal_d_write;
--L1_E_control_rd_data_without_mmu_regs[3] is std_1s10:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[3] at LC_X29_Y21_N7
--operation mode is normal
L1_E_control_rd_data_without_mmu_regs[3] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[8], L1L205, L1_M_ienable_reg[3], L1_M_ipending_reg[3], E1_data_out, L1_W_stall);
--L1_E_src1_prelim[3] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[3] at LC_X18_Y21_N7
--operation mode is normal
L1_E_src1_prelim[3] = AMPP_FUNCTION(DE1__clk0, L1_D_src1_hazard_W, MC1_q_b[3], L1L1386, L1_W_wr_data[3], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[3] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[3] at LC_X13_Y16_N9
--operation mode is normal
L1_M_mul_shift_rot_result[3] = AMPP_FUNCTION(DE1__clk0, QC1_result[3], L1L1284, L1L1256, QC1_result[35], E1_data_out, L1_M_ctrl_rot);
--L1L1384 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[3]~3647 at LC_X19_Y21_N7
--operation mode is normal
L1L1384 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[3]);
--L1_av_ld_data_aligned_or_div[3] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[3] at LC_X24_Y21_N3
--operation mode is normal
L1_av_ld_data_aligned_or_div[3] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[19], L1_M_ld_align_sh16, L1L143, L1_d_readdata_d1[3], E1_data_out, L1_M_ld_align_sh8);
--L1L1385 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[3]~3648 at LC_X19_Y21_N1
--operation mode is normal
L1L1385 = AMPP_FUNCTION(L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot, L1_av_ld_data_aligned_or_div[3], L1_M_alu_result[3]);
--L1L606 is std_1s10:inst|cpu:the_cpu|E_src1[3]~1966 at LC_X18_Y21_N1
--operation mode is normal
L1L606 = AMPP_FUNCTION(L1_E_src1_prelim[3], L1_E_src1_hazard_M, L1L1384, L1L1385);
--L1_E_src2_imm[3] is std_1s10:inst|cpu:the_cpu|E_src2_imm[3] at LC_X19_Y12_N8
--operation mode is normal
L1_E_src2_imm[3] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[2], L1_D_iw[5], L1_D_iw[9], L1L235, E1_data_out, L1_W_stall);
--L1L1331 is std_1s10:inst|cpu:the_cpu|M_st_data[11]~COMBOUT at LC_X19_Y20_N0
--operation mode is normal
L1L1331 = AMPP_FUNCTION(L1_E_src2_prelim[3], L1_E_src2_hazard_M, L1L1386);
--L1_M_st_data[11] is std_1s10:inst|cpu:the_cpu|M_st_data[11] at LC_X19_Y20_N0
--operation mode is normal
L1_M_st_data[11] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[3], L1_E_src2_hazard_M, L1L812, L1L1386, E1_data_out, L1L845, L1_W_stall);
--L1L672 is std_1s10:inst|cpu:the_cpu|E_src2[3]~1492 at LC_X19_Y12_N3
--operation mode is normal
L1L672 = AMPP_FUNCTION(L1_E_src2_imm[3], L1_E_ctrl_src2_is_imm, L1L1331);
--L1L4 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12884 at LC_X19_Y11_N7
--operation mode is normal
L1L4 = AMPP_FUNCTION(L1_E_logic_op[0], L1L606, L1_E_logic_op[1], L1L672);
--L1_E_extra_pc[1] is std_1s10:inst|cpu:the_cpu|E_extra_pc[1] at LC_X34_Y20_N0
--operation mode is normal
L1_E_extra_pc[1] = AMPP_FUNCTION(DE1__clk0, L1L218, L1_D_iw[21], L1_D_br_taken_waddr_partial[1], L1_D_pc_plus_one[1], E1_data_out, L1_W_stall);
--HC1_result[3] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[3] at LC_X18_Y12_N3
--operation mode is arithmetic
HC1_result[3] = AMPP_FUNCTION(L1L672, L1L606, HC1L9, HC1L10, L1_E_ctrl_alu_subtract);
--HC1L12 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT at LC_X18_Y12_N3
--operation mode is arithmetic
HC1L12 = AMPP_FUNCTION(L1L672, L1L606, HC1L9, L1_E_ctrl_alu_subtract);
--HC1L13 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUTCOUT1_153 at LC_X18_Y12_N3
--operation mode is arithmetic
HC1L13 = AMPP_FUNCTION(L1L672, L1L606, HC1L10, L1_E_ctrl_alu_subtract);
--L1L5 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12885 at LC_X34_Y20_N1
--operation mode is normal
L1L5 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, L1_E_extra_pc[1], HC1_result[3]);
--L1L6 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12886 at LC_X29_Y21_N3
--operation mode is normal
L1L6 = AMPP_FUNCTION(L1L4, L1_E_ctrl_dst_data_sel_logic_result, L1L5);
--L1L430 is std_1s10:inst|cpu:the_cpu|E_alu_result[3]~2247 at LC_X29_Y21_N4
--operation mode is normal
L1L430 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_E_control_rd_data_without_mmu_regs[3], L1L6);
--L1_M_alu_result[3] is std_1s10:inst|cpu:the_cpu|M_alu_result[3] at LC_X29_Y21_N4
--operation mode is normal
L1_M_alu_result[3] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_E_control_rd_data_without_mmu_regs[3], L1L6, E1_data_out, L1_W_stall);
--L1_E_extra_pc[5] is std_1s10:inst|cpu:the_cpu|E_extra_pc[5] at LC_X33_Y18_N3
--operation mode is normal
L1_E_extra_pc[5] = AMPP_FUNCTION(DE1__clk0, L1_D_br_taken_waddr_partial[5], L1L218, L1_D_iw[21], L1_D_pc_plus_one[5], E1_data_out, L1_W_stall);
--HC1_result[7] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[7] at LC_X18_Y12_N7
--operation mode is arithmetic
HC1_result[7] = AMPP_FUNCTION(L1L676, L1L610, HC1L15, HC1L20, HC1L21, L1_E_ctrl_alu_subtract);
--HC1L23 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[7]~COUT at LC_X18_Y12_N7
--operation mode is arithmetic
HC1L23 = AMPP_FUNCTION(L1L676, L1L610, HC1L20, L1_E_ctrl_alu_subtract);
--HC1L24 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[7]~COUTCOUT1_159 at LC_X18_Y12_N7
--operation mode is arithmetic
HC1L24 = AMPP_FUNCTION(L1L676, L1L610, HC1L21, L1_E_ctrl_alu_subtract);
--L1L7 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12887 at LC_X28_Y20_N2
--operation mode is normal
L1L7 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[7], L1_E_extra_pc[5]);
--L1_E_src1_prelim[7] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[7] at LC_X13_Y17_N3
--operation mode is normal
L1_E_src1_prelim[7] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[7], L1_D_src1_hazard_W, L1L1398, L1_W_wr_data[7], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[7] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[7] at LC_X13_Y16_N6
--operation mode is normal
L1_M_mul_shift_rot_result[7] = AMPP_FUNCTION(DE1__clk0, QC1_result[39], L1L1284, L1L1260, QC1_result[7], E1_data_out, L1_M_ctrl_rot);
--L1L1396 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[7]~3649 at LC_X13_Y17_N1
--operation mode is normal
L1L1396 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[7], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[7] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[7] at LC_X24_Y21_N2
--operation mode is normal
L1_av_ld_data_aligned_or_div[7] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[23], L1_d_readdata_d1[7], L1L151, L1_M_ld_align_sh16, E1_data_out, L1_M_ld_align_sh8);
--L1L1397 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[7]~3650 at LC_X13_Y17_N4
--operation mode is normal
L1L1397 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_av_ld_or_div_done, L1_M_alu_result[7], L1_av_ld_data_aligned_or_div[7]);
--L1L610 is std_1s10:inst|cpu:the_cpu|E_src1[7]~1967 at LC_X13_Y17_N2
--operation mode is normal
L1L610 = AMPP_FUNCTION(L1_E_src1_prelim[7], L1L1396, L1_E_src1_hazard_M, L1L1397);
--L1_E_src2_imm[7] is std_1s10:inst|cpu:the_cpu|E_src2_imm[7] at LC_X19_Y12_N0
--operation mode is normal
L1_E_src2_imm[7] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[2], L1_D_iw[5], L1_D_iw[13], L1L235, E1_data_out, L1_W_stall);
--L1L1339 is std_1s10:inst|cpu:the_cpu|M_st_data[15]~COMBOUT at LC_X18_Y17_N2
--operation mode is normal
L1L1339 = AMPP_FUNCTION(L1_E_src2_hazard_M, L1L1398, L1_E_src2_prelim[7]);
--L1_M_st_data[15] is std_1s10:inst|cpu:the_cpu|M_st_data[15] at LC_X18_Y17_N2
--operation mode is normal
L1_M_st_data[15] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_hazard_M, L1L1398, L1L816, L1_E_src2_prelim[7], E1_data_out, L1L845, L1_W_stall);
--L1L676 is std_1s10:inst|cpu:the_cpu|E_src2[7]~1493 at LC_X19_Y12_N1
--operation mode is normal
L1L676 = AMPP_FUNCTION(L1_E_src2_imm[7], L1_E_ctrl_src2_is_imm, L1L1339);
--L1L539 is std_1s10:inst|cpu:the_cpu|E_logic_result[7]~16117 at LC_X19_Y11_N0
--operation mode is normal
L1L539 = AMPP_FUNCTION(L1L610, L1_E_logic_op[1], L1L676, L1_E_logic_op[0]);
--L1L347 is std_1s10:inst|cpu:the_cpu|d_read_nxt~0 at LC_X34_Y13_N2
--operation mode is normal
L1L347 = AMPP_FUNCTION(M1_internal_cpu_data_master_waitrequest, L1_internal_d_read);
--L1_E_valid_from_D is std_1s10:inst|cpu:the_cpu|E_valid_from_D at LC_X33_Y16_N6
--operation mode is normal
L1_E_valid_from_D = AMPP_FUNCTION(DE1__clk0, L1_M_pipe_flush, L1_D_issue, E1_data_out, L1_W_stall);
--L1_M_pipe_flush is std_1s10:inst|cpu:the_cpu|M_pipe_flush at LC_X27_Y21_N6
--operation mode is normal
L1_M_pipe_flush = AMPP_FUNCTION(DE1__clk0, L1L818, L1_E_hbreak_req, L1_E_ctrl_flush_pipe_always, L1L1288, E1_data_out, L1_W_stall);
--L1L818 is std_1s10:inst|cpu:the_cpu|E_valid~28 at LC_X33_Y21_N0
--operation mode is normal
L1L818 = AMPP_FUNCTION(L1_E_valid_from_D, L1_M_pipe_flush);
--L1_E_iw[5] is std_1s10:inst|cpu:the_cpu|E_iw[5] at LC_X17_Y15_N7
--operation mode is normal
L1_E_iw[5] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[5], E1_data_out, L1_W_stall);
--L1L564 is std_1s10:inst|cpu:the_cpu|E_op_eret~64 at LC_X25_Y22_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L564 = AMPP_FUNCTION(L1_E_iw[5], L1_E_iw[12], L1_E_iw[3]);
--L1_E_iw[4] is std_1s10:inst|cpu:the_cpu|E_iw[4] at LC_X25_Y22_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[4] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[4], E1_data_out, GND, L1_W_stall);
--L1_E_iw[2] is std_1s10:inst|cpu:the_cpu|E_iw[2] at LC_X14_Y17_N9
--operation mode is normal
L1_E_iw[2] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[2], E1_data_out, L1_W_stall);
--L1_E_iw[0] is std_1s10:inst|cpu:the_cpu|E_iw[0] at LC_X17_Y16_N7
--operation mode is normal
L1_E_iw[0] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[0], E1_data_out, L1_W_stall);
--L1L565 is std_1s10:inst|cpu:the_cpu|E_op_eret~65 at LC_X25_Y22_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L565 = AMPP_FUNCTION(L1_E_iw[2], L1_E_iw[0]);
--L1_E_iw[1] is std_1s10:inst|cpu:the_cpu|E_iw[1] at LC_X25_Y22_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[1] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[1], E1_data_out, GND, L1_W_stall);
--L1L501 is std_1s10:inst|cpu:the_cpu|E_hbreak_req~62 at LC_X25_Y22_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L501 = AMPP_FUNCTION(L1_M_pipe_flush, L1_E_valid_from_D, L1_E_iw[15]);
--L1_E_iw[16] is std_1s10:inst|cpu:the_cpu|E_iw[16] at LC_X25_Y22_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[16] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[16], E1_data_out, GND, L1_W_stall);
--L1L502 is std_1s10:inst|cpu:the_cpu|E_hbreak_req~63 at LC_X25_Y22_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L502 = AMPP_FUNCTION(L1L564, L1L565, L1L501);
--L1_E_iw[11] is std_1s10:inst|cpu:the_cpu|E_iw[11] at LC_X25_Y22_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[11] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[11], E1_data_out, GND, L1_W_stall);
--L1L503 is std_1s10:inst|cpu:the_cpu|E_hbreak_req~64 at LC_X27_Y22_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L503 = AMPP_FUNCTION(L1_E_iw[14]);
--L1_E_iw[13] is std_1s10:inst|cpu:the_cpu|E_iw[13] at LC_X27_Y22_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[13] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[13], E1_data_out, GND, L1_W_stall);
--VC1_jtag_break is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|jtag_break at LC_X33_Y24_N1
--operation mode is normal
VC1_jtag_break = AMPP_FUNCTION(DE1__clk0, E1_data_out, VC1_jtag_break, VC1L1, VC1_probepresent, !C1_CLR_SIGNAL, DD1L190);
--L1_latched_oci_tb_hbreak_req is std_1s10:inst|cpu:the_cpu|latched_oci_tb_hbreak_req at LC_X27_Y22_N7
--operation mode is normal
L1_latched_oci_tb_hbreak_req = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1L1005, L1_hbreak_enabled, L1L818, E1_data_out);
--L1_hbreak_enabled is std_1s10:inst|cpu:the_cpu|hbreak_enabled at LC_X27_Y22_N4
--operation mode is normal
L1_hbreak_enabled = AMPP_FUNCTION(DE1__clk0, L1_hbreak_enabled, L1L1003, L1L1004, L1L1000, E1_data_out);
--L1_wait_for_one_post_bret_inst is std_1s10:inst|cpu:the_cpu|wait_for_one_post_bret_inst at LC_X44_Y21_N6
--operation mode is normal
L1_wait_for_one_post_bret_inst = AMPP_FUNCTION(DE1__clk0, L1_hbreak_enabled, L1_wait_for_one_post_bret_inst, L1L80, SC1_internal_oci_single_step_mode1, E1_data_out);
--L1L1005 is std_1s10:inst|cpu:the_cpu|hbreak_req~30 at LC_X32_Y24_N0
--operation mode is normal
L1L1005 = AMPP_FUNCTION(VC1_jtag_break, L1_wait_for_one_post_bret_inst, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled);
--L1L819 is std_1s10:inst|cpu:the_cpu|E_valid~29 at LC_X27_Y22_N2
--operation mode is normal
L1L819 = AMPP_FUNCTION(L1L503, L1L818, L1L502, L1L1005);
--L1_M_valid_from_E is std_1s10:inst|cpu:the_cpu|M_valid_from_E at LC_X27_Y22_N2
--operation mode is normal
L1_M_valid_from_E = AMPP_FUNCTION(DE1__clk0, L1L503, L1L818, L1L502, L1L1005, E1_data_out, L1_W_stall);
--L1_E_ctrl_ld is std_1s10:inst|cpu:the_cpu|E_ctrl_ld at LC_X21_Y6_N2
--operation mode is normal
L1_E_ctrl_ld = AMPP_FUNCTION(DE1__clk0, L1_D_iw[2], L1_D_iw[0], L1_D_iw[4], L1_D_iw[1], E1_data_out, L1_W_stall);
--L1_E_control_rd_data_without_mmu_regs[4] is std_1s10:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[4] at LC_X29_Y20_N3
--operation mode is normal
L1_E_control_rd_data_without_mmu_regs[4] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[8], L1L205, L1_M_ipending_reg[4], L1_M_ienable_reg[4], E1_data_out, L1_W_stall);
--L1_E_src1_prelim[4] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[4] at LC_X13_Y17_N8
--operation mode is normal
L1_E_src1_prelim[4] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[4], L1_D_src1_hazard_W, L1L1389, L1_W_wr_data[4], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[4] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[4] at LC_X14_Y15_N6
--operation mode is normal
L1_M_mul_shift_rot_result[4] = AMPP_FUNCTION(DE1__clk0, QC1_result[4], QC1_result[36], L1L1257, L1L1284, E1_data_out, L1_M_ctrl_rot);
--L1L1387 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[4]~3651 at LC_X14_Y19_N4
--operation mode is normal
L1L1387 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[4], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[4] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[4] at LC_X24_Y21_N5
--operation mode is normal
L1_av_ld_data_aligned_or_div[4] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[20], L1_M_ld_align_sh16, L1L145, L1_d_readdata_d1[4], E1_data_out, L1_M_ld_align_sh8);
--L1L1388 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[4]~3652 at LC_X14_Y19_N5
--operation mode is normal
L1L1388 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_av_ld_or_div_done, L1_M_alu_result[4], L1_av_ld_data_aligned_or_div[4]);
--L1L607 is std_1s10:inst|cpu:the_cpu|E_src1[4]~1968 at LC_X14_Y19_N2
--operation mode is normal
L1L607 = AMPP_FUNCTION(L1L1387, L1_E_src1_hazard_M, L1L1388, L1_E_src1_prelim[4]);
--L1_E_src2_imm[4] is std_1s10:inst|cpu:the_cpu|E_src2_imm[4] at LC_X19_Y12_N6
--operation mode is normal
L1_E_src2_imm[4] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[2], L1_D_iw[10], L1_D_iw[5], L1L235, E1_data_out, L1_W_stall);
--L1L1333 is std_1s10:inst|cpu:the_cpu|M_st_data[12]~COMBOUT at LC_X19_Y20_N5
--operation mode is normal
L1L1333 = AMPP_FUNCTION(L1L1389, L1_E_src2_prelim[4], L1_E_src2_hazard_M);
--L1_M_st_data[12] is std_1s10:inst|cpu:the_cpu|M_st_data[12] at LC_X19_Y20_N5
--operation mode is normal
L1_M_st_data[12] = AMPP_FUNCTION(DE1__clk0, L1L1389, L1_E_src2_prelim[4], L1L813, L1_E_src2_hazard_M, E1_data_out, L1L845, L1_W_stall);
--L1L673 is std_1s10:inst|cpu:the_cpu|E_src2[4]~1494 at LC_X19_Y12_N5
--operation mode is normal
L1L673 = AMPP_FUNCTION(L1_E_ctrl_src2_is_imm, L1L1333, L1_E_src2_imm[4]);
--L1L8 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12888 at LC_X29_Y20_N1
--operation mode is normal
L1L8 = AMPP_FUNCTION(L1_E_logic_op[1], L1L607, L1_E_logic_op[0], L1L673);
--L1_E_extra_pc[2] is std_1s10:inst|cpu:the_cpu|E_extra_pc[2] at LC_X29_Y20_N8
--operation mode is normal
L1_E_extra_pc[2] = AMPP_FUNCTION(DE1__clk0, L1_D_br_taken_waddr_partial[2], L1_D_iw[21], L1L218, L1_D_pc_plus_one[2], E1_data_out, L1_W_stall);
--HC1_result[4] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[4] at LC_X18_Y12_N4
--operation mode is arithmetic
HC1_result[4] = AMPP_FUNCTION(L1L673, L1L607, HC1L12, HC1L13, L1_E_ctrl_alu_subtract);
--HC1L15 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT at LC_X18_Y12_N4
--operation mode is arithmetic
HC1L15 = AMPP_FUNCTION(L1L673, L1L607, HC1L12, HC1L13, L1_E_ctrl_alu_subtract);
--L1L9 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12889 at LC_X29_Y20_N5
--operation mode is normal
L1L9 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[4], L1_E_extra_pc[2]);
--L1L10 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12890 at LC_X29_Y20_N6
--operation mode is normal
L1L10 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_logic_result, L1L8, L1L9);
--L1L431 is std_1s10:inst|cpu:the_cpu|E_alu_result[4]~2248 at LC_X29_Y20_N4
--operation mode is normal
L1L431 = AMPP_FUNCTION(L1_E_ctrl_rdctl_inst, L1_E_ctrl_dst_data_sel_cmp, L1_E_control_rd_data_without_mmu_regs[4], L1L10);
--L1_M_alu_result[4] is std_1s10:inst|cpu:the_cpu|M_alu_result[4] at LC_X29_Y20_N4
--operation mode is normal
L1_M_alu_result[4] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_rdctl_inst, L1_E_ctrl_dst_data_sel_cmp, L1_E_control_rd_data_without_mmu_regs[4], L1L10, E1_data_out, L1_W_stall);
--L1_E_extra_pc[20] is std_1s10:inst|cpu:the_cpu|E_extra_pc[20] at LC_X34_Y18_N7
--operation mode is normal
L1_E_extra_pc[20] = AMPP_FUNCTION(DE1__clk0, L1L81, L1_D_iw[21], L1_D_pc_plus_one[20], L1L218, E1_data_out, L1_W_stall);
--HC1_result[22] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[22] at LC_X18_Y10_N2
--operation mode is arithmetic
HC1_result[22] = AMPP_FUNCTION(L1L691, L1L625, HC1L57, HC1L62, HC1L63, L1_E_ctrl_alu_subtract);
--HC1L65 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[22]~COUT at LC_X18_Y10_N2
--operation mode is arithmetic
HC1L65 = AMPP_FUNCTION(L1L691, L1L625, HC1L62, L1_E_ctrl_alu_subtract);
--HC1L66 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[22]~COUTCOUT1_183 at LC_X18_Y10_N2
--operation mode is arithmetic
HC1L66 = AMPP_FUNCTION(L1L691, L1L625, HC1L63, L1_E_ctrl_alu_subtract);
--L1L11 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12891 at LC_X34_Y18_N9
--operation mode is normal
L1L11 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, L1_E_extra_pc[20], HC1_result[22]);
--L1_E_src1_prelim[22] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[22] at LC_X19_Y15_N8
--operation mode is normal
L1_E_src1_prelim[22] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[22], L1_W_wr_data[22], L1L1443, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[22] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[22] at LC_X14_Y15_N0
--operation mode is normal
L1_M_mul_shift_rot_result[22] = AMPP_FUNCTION(DE1__clk0, L1L1284, QC1_result[54], L1L1275, QC1_result[22], E1_data_out, L1_M_ctrl_rot);
--L1L1441 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[22]~3653 at LC_X19_Y15_N7
--operation mode is normal
L1L1441 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[22], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[22] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[22] at LC_X23_Y21_N4
--operation mode is normal
L1_av_ld_data_aligned_or_div[22] = AMPP_FUNCTION(DE1__clk0, L1L171, L1_M_iw[4], L1_d_readdata_d1[22], L1_M_ctrl_ld_signed, E1_data_out);
--L1L1442 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[22]~3654 at LC_X19_Y15_N2
--operation mode is normal
L1L1442 = AMPP_FUNCTION(L1_M_alu_result[22], L1_av_ld_or_div_done, L1_av_ld_data_aligned_or_div[22], L1_M_ctrl_mul_shift_rot);
--L1L625 is std_1s10:inst|cpu:the_cpu|E_src1[22]~1969 at LC_X19_Y15_N0
--operation mode is normal
L1L625 = AMPP_FUNCTION(L1L1442, L1_E_src1_hazard_M, L1L1441, L1_E_src1_prelim[22]);
--L1_E_src2_imm[22] is std_1s10:inst|cpu:the_cpu|E_src2_imm[22] at LC_X19_Y8_N0
--operation mode is normal
L1_E_src2_imm[22] = AMPP_FUNCTION(DE1__clk0, L1L246, L1L247, L1L410, L1L222, E1_data_out, L1_W_stall);
--L1L1353 is std_1s10:inst|cpu:the_cpu|M_st_data[22]~COMBOUT at LC_X19_Y8_N9
--operation mode is normal
L1L1353 = AMPP_FUNCTION(L1_E_src2_prelim[22], L1L1443, L1_E_src2_hazard_M);
--L1_M_st_data[22] is std_1s10:inst|cpu:the_cpu|M_st_data[22] at LC_X19_Y8_N9
--operation mode is normal
L1_M_st_data[22] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[22], L1L1443, L1L1337, L1_E_src2_hazard_M, E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L691 is std_1s10:inst|cpu:the_cpu|E_src2[22]~1495 at LC_X19_Y8_N7
--operation mode is normal
L1L691 = AMPP_FUNCTION(L1_E_src2_imm[22], L1_E_ctrl_src2_is_imm, L1L1353);
--L1L554 is std_1s10:inst|cpu:the_cpu|E_logic_result[22]~16118 at LC_X19_Y11_N8
--operation mode is normal
L1L554 = AMPP_FUNCTION(L1L691, L1_E_logic_op[1], L1L625, L1_E_logic_op[0]);
--L1_E_extra_pc[19] is std_1s10:inst|cpu:the_cpu|E_extra_pc[19] at LC_X33_Y18_N0
--operation mode is normal
L1_E_extra_pc[19] = AMPP_FUNCTION(DE1__clk0, L1L83, L1L218, L1_D_iw[21], L1_D_pc_plus_one[19], E1_data_out, L1_W_stall);
--HC1_result[21] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[21] at LC_X18_Y10_N1
--operation mode is arithmetic
HC1_result[21] = AMPP_FUNCTION(L1L690, L1L624, HC1L57, HC1L59, HC1L60, L1_E_ctrl_alu_subtract);
--HC1L62 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[21]~COUT at LC_X18_Y10_N1
--operation mode is arithmetic
HC1L62 = AMPP_FUNCTION(L1L690, L1L624, HC1L59, L1_E_ctrl_alu_subtract);
--HC1L63 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[21]~COUTCOUT1_181 at LC_X18_Y10_N1
--operation mode is arithmetic
HC1L63 = AMPP_FUNCTION(L1L690, L1L624, HC1L60, L1_E_ctrl_alu_subtract);
--L1L12 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12892 at LC_X33_Y18_N4
--operation mode is normal
L1L12 = AMPP_FUNCTION(HC1_result[21], L1_E_extra_pc[19], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src1_prelim[21] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[21] at LC_X17_Y21_N9
--operation mode is normal
L1_E_src1_prelim[21] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[21], MC1_q_b[21], L1L1440, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[21] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[21] at LC_X14_Y15_N4
--operation mode is normal
L1_M_mul_shift_rot_result[21] = AMPP_FUNCTION(DE1__clk0, QC1_result[53], L1L1284, L1L1274, QC1_result[21], E1_data_out, L1_M_ctrl_rot);
--L1L1438 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[21]~3655 at LC_X17_Y21_N1
--operation mode is normal
L1L1438 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[21]);
--L1_av_ld_data_aligned_or_div[21] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[21] at LC_X23_Y21_N1
--operation mode is normal
L1_av_ld_data_aligned_or_div[21] = AMPP_FUNCTION(DE1__clk0, L1L171, L1_M_iw[4], L1_d_readdata_d1[21], L1_M_ctrl_ld_signed, E1_data_out);
--L1L1439 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[21]~3656 at LC_X17_Y21_N4
--operation mode is normal
L1L1439 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_av_ld_data_aligned_or_div[21], L1_av_ld_or_div_done, L1_M_alu_result[21]);
--L1L624 is std_1s10:inst|cpu:the_cpu|E_src1[21]~1970 at LC_X17_Y21_N5
--operation mode is normal
L1L624 = AMPP_FUNCTION(L1_E_src1_hazard_M, L1L1439, L1L1438, L1_E_src1_prelim[21]);
--L1_E_src2_imm[21] is std_1s10:inst|cpu:the_cpu|E_src2_imm[21] at LC_X17_Y10_N6
--operation mode is normal
L1_E_src2_imm[21] = AMPP_FUNCTION(DE1__clk0, L1L246, L1L222, L1L247, L1L409, E1_data_out, L1_W_stall);
--L1L1351 is std_1s10:inst|cpu:the_cpu|M_st_data[21]~COMBOUT at LC_X17_Y10_N3
--operation mode is normal
L1L1351 = AMPP_FUNCTION(L1L1440, L1_E_src2_hazard_M, L1_E_src2_prelim[21]);
--L1_M_st_data[21] is std_1s10:inst|cpu:the_cpu|M_st_data[21] at LC_X17_Y10_N3
--operation mode is normal
L1_M_st_data[21] = AMPP_FUNCTION(DE1__clk0, L1L1440, L1_E_src2_hazard_M, L1L1335, L1_E_src2_prelim[21], E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L690 is std_1s10:inst|cpu:the_cpu|E_src2[21]~1496 at LC_X17_Y10_N7
--operation mode is normal
L1L690 = AMPP_FUNCTION(L1L1351, L1_E_src2_imm[21], L1_E_ctrl_src2_is_imm);
--L1L553 is std_1s10:inst|cpu:the_cpu|E_logic_result[21]~16119 at LC_X19_Y11_N3
--operation mode is normal
L1L553 = AMPP_FUNCTION(L1_E_logic_op[0], L1L690, L1_E_logic_op[1], L1L624);
--L1_E_extra_pc[22] is std_1s10:inst|cpu:the_cpu|E_extra_pc[22] at LC_X33_Y15_N0
--operation mode is normal
L1_E_extra_pc[22] = AMPP_FUNCTION(DE1__clk0, L1L218, L1L86, L1_D_iw[21], L1_D_pc_plus_one[22], E1_data_out, L1_W_stall);
--HC1_result[24] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[24] at LC_X18_Y10_N4
--operation mode is arithmetic
HC1_result[24] = AMPP_FUNCTION(L1L693, L1L627, HC1L57, HC1L68, HC1L69, L1_E_ctrl_alu_subtract);
--HC1L71 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[24]~COUT at LC_X18_Y10_N4
--operation mode is arithmetic
HC1L71 = AMPP_FUNCTION(L1L693, L1L627, HC1L57, HC1L68, HC1L69, L1_E_ctrl_alu_subtract);
--L1L13 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12893 at LC_X33_Y15_N1
--operation mode is normal
L1L13 = AMPP_FUNCTION(L1_E_extra_pc[22], HC1_result[24], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src2_imm[24] is std_1s10:inst|cpu:the_cpu|E_src2_imm[24] at LC_X17_Y10_N0
--operation mode is normal
L1_E_src2_imm[24] = AMPP_FUNCTION(DE1__clk0, L1L246, L1L222, L1L247, L1L412, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[24] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[24] at LC_X19_Y21_N9
--operation mode is normal
L1_E_src2_prelim[24] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[24], L1L403, L1L1449, L1_W_wr_data[24], E1_data_out, L1L399, L1_W_stall);
--L1_E_src2_hazard_M is std_1s10:inst|cpu:the_cpu|E_src2_hazard_M at LC_X19_Y17_N8
--operation mode is normal
L1_E_src2_hazard_M = AMPP_FUNCTION(DE1__clk0, L1_D_iw[24], L1L395, L1L822, L1_E_dst_regnum[2], E1_data_out, L1_W_stall);
--L1_M_mul_shift_rot_result[24] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[24] at LC_X13_Y14_N9
--operation mode is normal
L1_M_mul_shift_rot_result[24] = AMPP_FUNCTION(DE1__clk0, L1L1284, QC1_result[56], L1L1277, QC1_result[24], E1_data_out, L1_M_ctrl_rot);
--L1L1447 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[24]~3657 at LC_X19_Y21_N0
--operation mode is normal
L1L1447 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[24]);
--L1_av_ld_data_aligned_or_div[24] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[24] at LC_X23_Y21_N9
--operation mode is normal
L1_av_ld_data_aligned_or_div[24] = AMPP_FUNCTION(DE1__clk0, L1L171, L1_M_iw[4], L1_d_readdata_d1[24], L1_M_ctrl_ld_signed, E1_data_out);
--L1L1448 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[24]~3658 at LC_X19_Y21_N5
--operation mode is normal
L1L1448 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[24], L1_M_ctrl_mul_shift_rot, L1_av_ld_or_div_done, L1_M_alu_result[24]);
--L1L801 is std_1s10:inst|cpu:the_cpu|E_src2_reg[24]~472 at LC_X19_Y21_N3
--operation mode is normal
L1L801 = AMPP_FUNCTION(L1L1448, L1_E_src2_prelim[24], L1_E_src2_hazard_M, L1L1447);
--L1L693 is std_1s10:inst|cpu:the_cpu|E_src2[24]~1497 at LC_X17_Y10_N8
--operation mode is normal
L1L693 = AMPP_FUNCTION(L1_E_ctrl_src2_is_imm, L1L801, L1_E_src2_imm[24]);
--L1_E_src1_prelim[24] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[24] at LC_X18_Y16_N6
--operation mode is normal
L1_E_src1_prelim[24] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[24], L1_D_src1_hazard_W, L1L1449, L1_W_wr_data[24], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L627 is std_1s10:inst|cpu:the_cpu|E_src1[24]~1971 at LC_X19_Y21_N8
--operation mode is normal
L1L627 = AMPP_FUNCTION(L1L1448, L1_E_src1_hazard_M, L1_E_src1_prelim[24], L1L1447);
--L1L556 is std_1s10:inst|cpu:the_cpu|E_logic_result[24]~16120 at LC_X19_Y11_N5
--operation mode is normal
L1L556 = AMPP_FUNCTION(L1L693, L1_E_logic_op[0], L1_E_logic_op[1], L1L627);
--L1_E_extra_pc[17] is std_1s10:inst|cpu:the_cpu|E_extra_pc[17] at LC_X33_Y17_N9
--operation mode is normal
L1_E_extra_pc[17] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[21], L1L218, L1L89, L1_D_pc_plus_one[17], E1_data_out, L1_W_stall);
--HC1_result[19] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[19] at LC_X18_Y11_N9
--operation mode is arithmetic
HC1_result[19] = AMPP_FUNCTION(L1L688, L1L622, HC1L43, HC1L54, HC1L55, L1_E_ctrl_alu_subtract);
--HC1L57 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[19]~COUT at LC_X18_Y11_N9
--operation mode is arithmetic
HC1L57 = AMPP_FUNCTION(L1L688, L1L622, HC1L43, HC1L54, HC1L55, L1_E_ctrl_alu_subtract);
--L1L14 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12894 at LC_X33_Y17_N5
--operation mode is normal
L1L14 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, L1_E_extra_pc[17], HC1_result[19]);
--L1_E_src1_prelim[19] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[19] at LC_X18_Y16_N0
--operation mode is normal
L1_E_src1_prelim[19] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[19], L1_D_src1_hazard_W, L1L1434, L1_W_wr_data[19], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[19] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[19] at LC_X13_Y14_N0
--operation mode is normal
L1_M_mul_shift_rot_result[19] = AMPP_FUNCTION(DE1__clk0, QC1_result[51], L1L1284, L1L1272, QC1_result[19], E1_data_out, L1_M_ctrl_rot);
--L1L1432 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[19]~3659 at LC_X13_Y14_N8
--operation mode is normal
L1L1432 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[19]);
--L1_av_ld_data_aligned_or_div[19] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[19] at LC_X23_Y21_N8
--operation mode is normal
L1_av_ld_data_aligned_or_div[19] = AMPP_FUNCTION(DE1__clk0, L1L171, L1_M_iw[4], L1_d_readdata_d1[19], L1_M_ctrl_ld_signed, E1_data_out);
--L1L1433 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[19]~3660 at LC_X23_Y21_N3
--operation mode is normal
L1L1433 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[19], L1_M_ctrl_mul_shift_rot, L1_av_ld_or_div_done, L1_M_alu_result[19]);
--L1L622 is std_1s10:inst|cpu:the_cpu|E_src1[19]~1972 at LC_X18_Y16_N9
--operation mode is normal
L1L622 = AMPP_FUNCTION(L1L1433, L1L1432, L1_E_src1_hazard_M, L1_E_src1_prelim[19]);
--L1_E_src2_imm[19] is std_1s10:inst|cpu:the_cpu|E_src2_imm[19] at LC_X17_Y10_N5
--operation mode is normal
L1_E_src2_imm[19] = AMPP_FUNCTION(DE1__clk0, L1L222, L1L247, L1L407, L1L246, E1_data_out, L1_W_stall);
--L1L1347 is std_1s10:inst|cpu:the_cpu|M_st_data[19]~COMBOUT at LC_X21_Y21_N0
--operation mode is normal
L1L1347 = AMPP_FUNCTION(L1_E_src2_prelim[19], L1_E_src2_hazard_M, L1L1434);
--L1_M_st_data[19] is std_1s10:inst|cpu:the_cpu|M_st_data[19] at LC_X21_Y21_N0
--operation mode is normal
L1_M_st_data[19] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[19], L1_E_src2_hazard_M, L1L1331, L1L1434, E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L688 is std_1s10:inst|cpu:the_cpu|E_src2[19]~1498 at LC_X17_Y10_N2
--operation mode is normal
L1L688 = AMPP_FUNCTION(L1_E_src2_imm[19], L1_E_ctrl_src2_is_imm, L1L1347);
--L1L551 is std_1s10:inst|cpu:the_cpu|E_logic_result[19]~16121 at LC_X19_Y11_N4
--operation mode is normal
L1L551 = AMPP_FUNCTION(L1_E_logic_op[0], L1L688, L1_E_logic_op[1], L1L622);
--L1_E_extra_pc[16] is std_1s10:inst|cpu:the_cpu|E_extra_pc[16] at LC_X33_Y17_N2
--operation mode is normal
L1_E_extra_pc[16] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[21], L1L92, L1L218, L1_D_pc_plus_one[16], E1_data_out, L1_W_stall);
--HC1_result[18] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[18] at LC_X18_Y11_N8
--operation mode is arithmetic
HC1_result[18] = AMPP_FUNCTION(L1L687, L1L621, HC1L43, HC1L51, HC1L52, L1_E_ctrl_alu_subtract);
--HC1L54 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[18]~COUT at LC_X18_Y11_N8
--operation mode is arithmetic
HC1L54 = AMPP_FUNCTION(L1L687, L1L621, HC1L51, L1_E_ctrl_alu_subtract);
--HC1L55 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[18]~COUTCOUT1_177 at LC_X18_Y11_N8
--operation mode is arithmetic
HC1L55 = AMPP_FUNCTION(L1L687, L1L621, HC1L52, L1_E_ctrl_alu_subtract);
--L1L15 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12895 at LC_X28_Y20_N8
--operation mode is normal
L1L15 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, L1_E_extra_pc[16], HC1_result[18]);
--L1_E_src1_prelim[18] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[18] at LC_X18_Y14_N2
--operation mode is normal
L1_E_src1_prelim[18] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[18], L1_D_src1_hazard_W, L1L1431, L1_W_wr_data[18], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[18] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[18] at LC_X13_Y14_N6
--operation mode is normal
L1_M_mul_shift_rot_result[18] = AMPP_FUNCTION(DE1__clk0, L1L1284, QC1_result[18], L1L1271, QC1_result[50], E1_data_out, L1_M_ctrl_rot);
--L1L1429 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[18]~3661 at LC_X18_Y14_N6
--operation mode is normal
L1L1429 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[18], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[18] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[18] at LC_X23_Y21_N7
--operation mode is normal
L1_av_ld_data_aligned_or_div[18] = AMPP_FUNCTION(DE1__clk0, L1L171, L1_M_iw[4], L1_d_readdata_d1[18], L1_M_ctrl_ld_signed, E1_data_out);
--L1L1430 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[18]~3662 at LC_X23_Y21_N6
--operation mode is normal
L1L1430 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_alu_result[18], L1_av_ld_data_aligned_or_div[18], L1_av_ld_or_div_done);
--L1L621 is std_1s10:inst|cpu:the_cpu|E_src1[18]~1973 at LC_X18_Y14_N7
--operation mode is normal
L1L621 = AMPP_FUNCTION(L1L1430, L1L1429, L1_E_src1_hazard_M, L1_E_src1_prelim[18]);
--L1_E_src2_imm[18] is std_1s10:inst|cpu:the_cpu|E_src2_imm[18] at LC_X18_Y8_N6
--operation mode is normal
L1_E_src2_imm[18] = AMPP_FUNCTION(DE1__clk0, L1L406, L1L222, L1L246, L1L247, E1_data_out, L1_W_stall);
--L1L1345 is std_1s10:inst|cpu:the_cpu|M_st_data[18]~COMBOUT at LC_X18_Y8_N2
--operation mode is normal
L1L1345 = AMPP_FUNCTION(L1L1431, L1_E_src2_hazard_M, L1_E_src2_prelim[18]);
--L1_M_st_data[18] is std_1s10:inst|cpu:the_cpu|M_st_data[18] at LC_X18_Y8_N2
--operation mode is normal
L1_M_st_data[18] = AMPP_FUNCTION(DE1__clk0, L1L1431, L1_E_src2_hazard_M, L1L1329, L1_E_src2_prelim[18], E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L687 is std_1s10:inst|cpu:the_cpu|E_src2[18]~1499 at LC_X18_Y8_N3
--operation mode is normal
L1L687 = AMPP_FUNCTION(L1_E_ctrl_src2_is_imm, L1_E_src2_imm[18], L1L1345);
--L1L550 is std_1s10:inst|cpu:the_cpu|E_logic_result[18]~16122 at LC_X19_Y11_N9
--operation mode is normal
L1L550 = AMPP_FUNCTION(L1_E_logic_op[1], L1_E_logic_op[0], L1L621, L1L687);
--L1_E_extra_pc[15] is std_1s10:inst|cpu:the_cpu|E_extra_pc[15] at LC_X33_Y18_N9
--operation mode is normal
L1_E_extra_pc[15] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[21], L1L218, L1_D_pc_plus_one[15], L1L95, E1_data_out, L1_W_stall);
--HC1_result[17] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[17] at LC_X18_Y11_N7
--operation mode is arithmetic
HC1_result[17] = AMPP_FUNCTION(L1L686, L1L620, HC1L43, HC1L48, HC1L49, L1_E_ctrl_alu_subtract);
--HC1L51 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[17]~COUT at LC_X18_Y11_N7
--operation mode is arithmetic
HC1L51 = AMPP_FUNCTION(L1L686, L1L620, HC1L48, L1_E_ctrl_alu_subtract);
--HC1L52 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[17]~COUTCOUT1_175 at LC_X18_Y11_N7
--operation mode is arithmetic
HC1L52 = AMPP_FUNCTION(L1L686, L1L620, HC1L49, L1_E_ctrl_alu_subtract);
--L1L16 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12896 at LC_X33_Y18_N5
--operation mode is normal
L1L16 = AMPP_FUNCTION(L1_E_extra_pc[15], HC1_result[17], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src1_prelim[17] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[17] at LC_X17_Y14_N6
--operation mode is normal
L1_E_src1_prelim[17] = AMPP_FUNCTION(DE1__clk0, L1_D_src1_hazard_W, MC1_q_b[17], L1L1428, L1_W_wr_data[17], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[17] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[17] at LC_X12_Y14_N6
--operation mode is normal
L1_M_mul_shift_rot_result[17] = AMPP_FUNCTION(DE1__clk0, L1L1284, QC1_result[49], L1L1270, QC1_result[17], E1_data_out, L1_M_ctrl_rot);
--L1L1426 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[17]~3663 at LC_X17_Y14_N1
--operation mode is normal
L1L1426 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[17], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[17] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[17] at LC_X17_Y14_N9
--operation mode is normal
L1_av_ld_data_aligned_or_div[17] = AMPP_FUNCTION(DE1__clk0, L1L171, L1_M_iw[4], L1_d_readdata_d1[17], L1_M_ctrl_ld_signed, E1_data_out);
--L1L1427 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[17]~3664 at LC_X17_Y14_N7
--operation mode is normal
L1L1427 = AMPP_FUNCTION(L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot, L1_M_alu_result[17], L1_av_ld_data_aligned_or_div[17]);
--L1L620 is std_1s10:inst|cpu:the_cpu|E_src1[17]~1974 at LC_X17_Y14_N8
--operation mode is normal
L1L620 = AMPP_FUNCTION(L1_E_src1_hazard_M, L1L1427, L1L1426, L1_E_src1_prelim[17]);
--L1_E_src2_imm[17] is std_1s10:inst|cpu:the_cpu|E_src2_imm[17] at LC_X17_Y8_N1
--operation mode is normal
L1_E_src2_imm[17] = AMPP_FUNCTION(DE1__clk0, L1L222, L1L247, L1L405, L1L246, E1_data_out, L1_W_stall);
--L1L1343 is std_1s10:inst|cpu:the_cpu|M_st_data[17]~COMBOUT at LC_X17_Y8_N8
--operation mode is normal
L1L1343 = AMPP_FUNCTION(L1L1428, L1_E_src2_prelim[17], L1_E_src2_hazard_M);
--L1_M_st_data[17] is std_1s10:inst|cpu:the_cpu|M_st_data[17] at LC_X17_Y8_N8
--operation mode is normal
L1_M_st_data[17] = AMPP_FUNCTION(DE1__clk0, L1L1428, L1_E_src2_prelim[17], L1L1327, L1_E_src2_hazard_M, E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L686 is std_1s10:inst|cpu:the_cpu|E_src2[17]~1500 at LC_X17_Y8_N9
--operation mode is normal
L1L686 = AMPP_FUNCTION(L1_E_src2_imm[17], L1_E_ctrl_src2_is_imm, L1L1343);
--L1L549 is std_1s10:inst|cpu:the_cpu|E_logic_result[17]~16123 at LC_X19_Y11_N6
--operation mode is normal
L1L549 = AMPP_FUNCTION(L1_E_logic_op[0], L1L686, L1_E_logic_op[1], L1L620);
--L1_E_extra_pc[14] is std_1s10:inst|cpu:the_cpu|E_extra_pc[14] at LC_X28_Y20_N1
--operation mode is normal
L1_E_extra_pc[14] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[14], L1L97, L1_D_iw[21], L1L218, E1_data_out, L1_W_stall);
--HC1_result[16] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[16] at LC_X18_Y11_N6
--operation mode is arithmetic
HC1_result[16] = AMPP_FUNCTION(L1L685, L1L619, HC1L43, HC1L45, HC1L46, L1_E_ctrl_alu_subtract);
--HC1L48 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[16]~COUT at LC_X18_Y11_N6
--operation mode is arithmetic
HC1L48 = AMPP_FUNCTION(L1L685, L1L619, HC1L45, L1_E_ctrl_alu_subtract);
--HC1L49 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[16]~COUTCOUT1_173 at LC_X18_Y11_N6
--operation mode is arithmetic
HC1L49 = AMPP_FUNCTION(L1L685, L1L619, HC1L46, L1_E_ctrl_alu_subtract);
--L1L17 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12897 at LC_X28_Y20_N0
--operation mode is normal
L1L17 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, L1_E_extra_pc[14], HC1_result[16]);
--L1_E_src1_prelim[16] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[16] at LC_X18_Y16_N3
--operation mode is normal
L1_E_src1_prelim[16] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[16], L1_D_src1_hazard_W, L1L1425, MC1_q_b[16], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[16] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[16] at LC_X12_Y14_N4
--operation mode is normal
L1_M_mul_shift_rot_result[16] = AMPP_FUNCTION(DE1__clk0, QC1_result[48], L1L1284, L1L1269, QC1_result[16], E1_data_out, L1_M_ctrl_rot);
--L1L1423 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[16]~3665 at LC_X18_Y16_N5
--operation mode is normal
L1L1423 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[16], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[16] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[16] at LC_X18_Y16_N8
--operation mode is normal
L1_av_ld_data_aligned_or_div[16] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_ld_signed, L1_M_iw[4], L1_d_readdata_d1[16], L1L171, E1_data_out);
--L1L1424 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[16]~3666 at LC_X18_Y16_N4
--operation mode is normal
L1L1424 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[16], L1_M_ctrl_mul_shift_rot, L1_M_alu_result[16], L1_av_ld_or_div_done);
--L1L619 is std_1s10:inst|cpu:the_cpu|E_src1[16]~1975 at LC_X18_Y16_N1
--operation mode is normal
L1L619 = AMPP_FUNCTION(L1_E_src1_prelim[16], L1_E_src1_hazard_M, L1L1423, L1L1424);
--L1_E_src2_imm[16] is std_1s10:inst|cpu:the_cpu|E_src2_imm[16] at LC_X17_Y10_N9
--operation mode is normal
L1_E_src2_imm[16] = AMPP_FUNCTION(DE1__clk0, L1L222, L1L247, L1L404, L1L246, E1_data_out, L1_W_stall);
--L1L1341 is std_1s10:inst|cpu:the_cpu|M_st_data[16]~COMBOUT at LC_X17_Y10_N4
--operation mode is normal
L1L1341 = AMPP_FUNCTION(L1L1425, L1_E_src2_prelim[16], L1_E_src2_hazard_M);
--L1_M_st_data[16] is std_1s10:inst|cpu:the_cpu|M_st_data[16] at LC_X17_Y10_N4
--operation mode is normal
L1_M_st_data[16] = AMPP_FUNCTION(DE1__clk0, L1L1425, L1_E_src2_prelim[16], L1L1325, L1_E_src2_hazard_M, E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L685 is std_1s10:inst|cpu:the_cpu|E_src2[16]~1501 at LC_X17_Y10_N1
--operation mode is normal
L1L685 = AMPP_FUNCTION(L1_E_src2_imm[16], L1_E_ctrl_src2_is_imm, L1L1341);
--L1L548 is std_1s10:inst|cpu:the_cpu|E_logic_result[16]~16124 at LC_X19_Y11_N1
--operation mode is normal
L1L548 = AMPP_FUNCTION(L1L685, L1_E_logic_op[1], L1L619, L1_E_logic_op[0]);
--L1_E_extra_pc[21] is std_1s10:inst|cpu:the_cpu|E_extra_pc[21] at LC_X33_Y15_N5
--operation mode is normal
L1_E_extra_pc[21] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[21], L1L100, L1_D_pc_plus_one[21], L1L218, E1_data_out, L1_W_stall);
--HC1_result[23] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[23] at LC_X18_Y10_N3
--operation mode is arithmetic
HC1_result[23] = AMPP_FUNCTION(L1L692, L1L626, HC1L57, HC1L65, HC1L66, L1_E_ctrl_alu_subtract);
--HC1L68 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[23]~COUT at LC_X18_Y10_N3
--operation mode is arithmetic
HC1L68 = AMPP_FUNCTION(L1L692, L1L626, HC1L65, L1_E_ctrl_alu_subtract);
--HC1L69 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[23]~COUTCOUT1_185 at LC_X18_Y10_N3
--operation mode is arithmetic
HC1L69 = AMPP_FUNCTION(L1L692, L1L626, HC1L66, L1_E_ctrl_alu_subtract);
--L1L18 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12898 at LC_X33_Y15_N6
--operation mode is normal
L1L18 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, L1_E_extra_pc[21], HC1_result[23]);
--L1_E_src1_prelim[23] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[23] at LC_X17_Y14_N5
--operation mode is normal
L1_E_src1_prelim[23] = AMPP_FUNCTION(DE1__clk0, L1_D_src1_hazard_W, MC1_q_b[23], L1L1446, L1_W_wr_data[23], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[23] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[23] at LC_X12_Y14_N2
--operation mode is normal
L1_M_mul_shift_rot_result[23] = AMPP_FUNCTION(DE1__clk0, QC1_result[55], QC1_result[23], L1L1276, L1L1284, E1_data_out, L1_M_ctrl_rot);
--L1L1444 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[23]~3667 at LC_X17_Y14_N3
--operation mode is normal
L1L1444 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[23]);
--L1_av_ld_data_aligned_or_div[23] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[23] at LC_X23_Y21_N5
--operation mode is normal
L1_av_ld_data_aligned_or_div[23] = AMPP_FUNCTION(DE1__clk0, L1L171, L1_M_iw[4], L1_d_readdata_d1[23], L1_M_ctrl_ld_signed, E1_data_out);
--L1L1445 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[23]~3668 at LC_X23_Y21_N2
--operation mode is normal
L1L1445 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_av_ld_data_aligned_or_div[23], L1_av_ld_or_div_done, L1_M_alu_result[23]);
--L1L626 is std_1s10:inst|cpu:the_cpu|E_src1[23]~1976 at LC_X17_Y14_N4
--operation mode is normal
L1L626 = AMPP_FUNCTION(L1_E_src1_hazard_M, L1L1445, L1L1444, L1_E_src1_prelim[23]);
--L1_E_src2_imm[23] is std_1s10:inst|cpu:the_cpu|E_src2_imm[23] at LC_X17_Y8_N6
--operation mode is normal
L1_E_src2_imm[23] = AMPP_FUNCTION(DE1__clk0, L1L411, L1L247, L1L222, L1L246, E1_data_out, L1_W_stall);
--L1L1355 is std_1s10:inst|cpu:the_cpu|M_st_data[23]~COMBOUT at LC_X17_Y8_N5
--operation mode is normal
L1L1355 = AMPP_FUNCTION(L1_E_src2_prelim[23], L1_E_src2_hazard_M, L1L1446);
--L1_M_st_data[23] is std_1s10:inst|cpu:the_cpu|M_st_data[23] at LC_X17_Y8_N5
--operation mode is normal
L1_M_st_data[23] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[23], L1_E_src2_hazard_M, L1L1339, L1L1446, E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L692 is std_1s10:inst|cpu:the_cpu|E_src2[23]~1502 at LC_X17_Y8_N2
--operation mode is normal
L1L692 = AMPP_FUNCTION(L1_E_src2_imm[23], L1_E_ctrl_src2_is_imm, L1L1355);
--L1L555 is std_1s10:inst|cpu:the_cpu|E_logic_result[23]~16125 at LC_X19_Y11_N2
--operation mode is normal
L1L555 = AMPP_FUNCTION(L1_E_logic_op[0], L1L626, L1_E_logic_op[1], L1L692);
--L1_E_extra_pc[23] is std_1s10:inst|cpu:the_cpu|E_extra_pc[23] at LC_X33_Y19_N8
--operation mode is normal
L1_E_extra_pc[23] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[21], L1L218, L1_D_pc_plus_one[23], L1L103, E1_data_out, L1_W_stall);
--HC1_result[25] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[25] at LC_X18_Y10_N5
--operation mode is arithmetic
HC1_result[25] = AMPP_FUNCTION(L1L694, L1L628, HC1L71, L1_E_ctrl_alu_subtract);
--HC1L73 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[25]~COUT at LC_X18_Y10_N5
--operation mode is arithmetic
HC1L73 = AMPP_FUNCTION(L1L694, L1L628, L1_E_ctrl_alu_subtract);
--HC1L74 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[25]~COUTCOUT1_187 at LC_X18_Y10_N5
--operation mode is arithmetic
HC1L74 = AMPP_FUNCTION(L1L694, L1L628, L1_E_ctrl_alu_subtract);
--L1L19 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12899 at LC_X33_Y19_N9
--operation mode is normal
L1L19 = AMPP_FUNCTION(L1_E_extra_pc[23], L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[25]);
--L1_E_src2_imm[25] is std_1s10:inst|cpu:the_cpu|E_src2_imm[25] at LC_X17_Y8_N0
--operation mode is normal
L1_E_src2_imm[25] = AMPP_FUNCTION(DE1__clk0, L1L413, L1L247, L1L222, L1L246, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[25] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[25] at LC_X14_Y19_N9
--operation mode is normal
L1_E_src2_prelim[25] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[25], L1L403, L1L1452, NC1_q_b[25], E1_data_out, L1L399, L1_W_stall);
--L1_M_mul_shift_rot_result[25] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[25] at LC_X12_Y14_N8
--operation mode is normal
L1_M_mul_shift_rot_result[25] = AMPP_FUNCTION(DE1__clk0, QC1_result[57], L1L1284, L1L1278, QC1_result[25], E1_data_out, L1_M_ctrl_rot);
--L1L1450 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[25]~3669 at LC_X14_Y19_N0
--operation mode is normal
L1L1450 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[25], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[25] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[25] at LC_X23_Y21_N0
--operation mode is normal
L1_av_ld_data_aligned_or_div[25] = AMPP_FUNCTION(DE1__clk0, L1L171, L1_M_iw[4], L1_d_readdata_d1[25], L1_M_ctrl_ld_signed, E1_data_out);
--L1L1451 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[25]~3670 at LC_X21_Y20_N8
--operation mode is normal
L1L1451 = AMPP_FUNCTION(L1_M_alu_result[25], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot, L1_av_ld_data_aligned_or_div[25]);
--L1L802 is std_1s10:inst|cpu:the_cpu|E_src2_reg[25]~473 at LC_X14_Y19_N8
--operation mode is normal
L1L802 = AMPP_FUNCTION(L1L1451, L1_E_src2_prelim[25], L1_E_src2_hazard_M, L1L1450);
--L1L694 is std_1s10:inst|cpu:the_cpu|E_src2[25]~1503 at LC_X17_Y8_N4
--operation mode is normal
L1L694 = AMPP_FUNCTION(L1_E_src2_imm[25], L1_E_ctrl_src2_is_imm, L1L802);
--L1_E_src1_prelim[25] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[25] at LC_X14_Y17_N3
--operation mode is normal
L1_E_src1_prelim[25] = AMPP_FUNCTION(DE1__clk0, L1_D_src1_hazard_W, L1_W_wr_data[25], L1L1452, MC1_q_b[25], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L628 is std_1s10:inst|cpu:the_cpu|E_src1[25]~1977 at LC_X14_Y19_N1
--operation mode is normal
L1L628 = AMPP_FUNCTION(L1_E_src1_prelim[25], L1_E_src1_hazard_M, L1L1451, L1L1450);
--L1L557 is std_1s10:inst|cpu:the_cpu|E_logic_result[25]~16126 at LC_X18_Y13_N9
--operation mode is normal
L1L557 = AMPP_FUNCTION(L1_E_logic_op[1], L1L694, L1_E_logic_op[0], L1L628);
--L1_E_extra_pc[18] is std_1s10:inst|cpu:the_cpu|E_extra_pc[18] at LC_X33_Y17_N8
--operation mode is normal
L1_E_extra_pc[18] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[21], L1_D_pc_plus_one[18], L1L218, L1L104, E1_data_out, L1_W_stall);
--HC1_result[20] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[20] at LC_X18_Y10_N0
--operation mode is arithmetic
HC1_result[20] = AMPP_FUNCTION(L1L689, L1L623, HC1L57, L1_E_ctrl_alu_subtract);
--HC1L59 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[20]~COUT at LC_X18_Y10_N0
--operation mode is arithmetic
HC1L59 = AMPP_FUNCTION(L1L689, L1L623, L1_E_ctrl_alu_subtract);
--HC1L60 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[20]~COUTCOUT1_179 at LC_X18_Y10_N0
--operation mode is arithmetic
HC1L60 = AMPP_FUNCTION(L1L689, L1L623, L1_E_ctrl_alu_subtract);
--L1L20 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12900 at LC_X33_Y17_N1
--operation mode is normal
L1L20 = AMPP_FUNCTION(L1_E_extra_pc[18], L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[20]);
--L1_E_src1_prelim[20] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[20] at LC_X18_Y14_N1
--operation mode is normal
L1_E_src1_prelim[20] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[20], L1_D_src1_hazard_W, L1L1437, L1_W_wr_data[20], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[20] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[20] at LC_X12_Y14_N9
--operation mode is normal
L1_M_mul_shift_rot_result[20] = AMPP_FUNCTION(DE1__clk0, QC1_result[52], L1L1284, L1L1273, QC1_result[20], E1_data_out, L1_M_ctrl_rot);
--L1L1435 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[20]~3671 at LC_X18_Y14_N4
--operation mode is normal
L1L1435 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[20]);
--L1_av_ld_data_aligned_or_div[20] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[20] at LC_X18_Y14_N3
--operation mode is normal
L1_av_ld_data_aligned_or_div[20] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[20], L1_M_iw[4], L1_M_ctrl_ld_signed, L1L171, E1_data_out);
--L1L1436 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[20]~3672 at LC_X18_Y14_N8
--operation mode is normal
L1L1436 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[20], L1_M_ctrl_mul_shift_rot, L1_M_alu_result[20], L1_av_ld_or_div_done);
--L1L623 is std_1s10:inst|cpu:the_cpu|E_src1[20]~1978 at LC_X18_Y14_N5
--operation mode is normal
L1L623 = AMPP_FUNCTION(L1L1436, L1_E_src1_prelim[20], L1_E_src1_hazard_M, L1L1435);
--L1_E_src2_imm[20] is std_1s10:inst|cpu:the_cpu|E_src2_imm[20] at LC_X18_Y8_N5
--operation mode is normal
L1_E_src2_imm[20] = AMPP_FUNCTION(DE1__clk0, L1L247, L1L222, L1L246, L1L408, E1_data_out, L1_W_stall);
--L1L1349 is std_1s10:inst|cpu:the_cpu|M_st_data[20]~COMBOUT at LC_X18_Y8_N8
--operation mode is normal
L1L1349 = AMPP_FUNCTION(L1_E_src2_prelim[20], L1_E_src2_hazard_M, L1L1437);
--L1_M_st_data[20] is std_1s10:inst|cpu:the_cpu|M_st_data[20] at LC_X18_Y8_N8
--operation mode is normal
L1_M_st_data[20] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[20], L1_E_src2_hazard_M, L1L1333, L1L1437, E1_data_out, !L1_E_iw[4], L1_W_stall);
--L1L689 is std_1s10:inst|cpu:the_cpu|E_src2[20]~1504 at LC_X18_Y8_N7
--operation mode is normal
L1L689 = AMPP_FUNCTION(L1_E_ctrl_src2_is_imm, L1_E_src2_imm[20], L1L1349);
--L1L552 is std_1s10:inst|cpu:the_cpu|E_logic_result[20]~16127 at LC_X17_Y11_N0
--operation mode is normal
L1L552 = AMPP_FUNCTION(L1L689, L1L623, L1_E_logic_op[1], L1_E_logic_op[0]);
--L1_E_extra_pc[13] is std_1s10:inst|cpu:the_cpu|E_extra_pc[13] at LC_X33_Y20_N1
--operation mode is normal
L1_E_extra_pc[13] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[13], L1_D_iw[21], L1L107, L1L218, E1_data_out, L1_W_stall);
--HC1_result[15] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[15] at LC_X18_Y11_N5
--operation mode is arithmetic
HC1_result[15] = AMPP_FUNCTION(L1L684, L1L618, HC1L43, L1_E_ctrl_alu_subtract);
--HC1L45 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[15]~COUT at LC_X18_Y11_N5
--operation mode is arithmetic
HC1L45 = AMPP_FUNCTION(L1L684, L1L618, L1_E_ctrl_alu_subtract);
--HC1L46 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[15]~COUTCOUT1_171 at LC_X18_Y11_N5
--operation mode is arithmetic
HC1L46 = AMPP_FUNCTION(L1L684, L1L618, L1_E_ctrl_alu_subtract);
--L1L21 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12901 at LC_X33_Y20_N2
--operation mode is normal
L1L21 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, L1_E_extra_pc[13], HC1_result[15]);
--L1_E_src2_imm[15] is std_1s10:inst|cpu:the_cpu|E_src2_imm[15] at LC_X17_Y12_N0
--operation mode is normal
L1_E_src2_imm[15] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[2], L1_D_iw[5], L1_D_iw[21], L1L235, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[15] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[15] at LC_X17_Y17_N0
--operation mode is normal
L1_E_src2_prelim[15] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[15], L1_W_wr_data[15], L1L1422, L1L403, E1_data_out, L1L399, L1_W_stall);
--L1_M_mul_shift_rot_result[15] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[15] at LC_X12_Y16_N8
--operation mode is normal
L1_M_mul_shift_rot_result[15] = AMPP_FUNCTION(DE1__clk0, QC1_result[47], L1L1284, L1L1268, QC1_result[15], E1_data_out, L1_M_ctrl_rot);
--L1L1420 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[15]~3673 at LC_X17_Y17_N9
--operation mode is normal
L1L1420 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[15]);
--L1L151 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[15]~COMBOUT at LC_X24_Y20_N3
--operation mode is normal
L1L151 = AMPP_FUNCTION(L1_M_ld_align_sh16, L1_d_readdata_d1[15], L1_d_readdata_d1[31]);
--L1_av_ld_data_aligned_or_div[15] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[15] at LC_X24_Y20_N3
--operation mode is normal
L1_av_ld_data_aligned_or_div[15] = AMPP_FUNCTION(DE1__clk0, L1_M_ld_align_sh16, L1_d_readdata_d1[15], L1_av_fill_bit, L1_d_readdata_d1[31], E1_data_out, L1L846);
--L1L1421 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[15]~3674 at LC_X17_Y17_N8
--operation mode is normal
L1L1421 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_av_ld_or_div_done, L1_av_ld_data_aligned_or_div[15], L1_M_alu_result[15]);
--L1L816 is std_1s10:inst|cpu:the_cpu|E_sth_data[15]~472 at LC_X18_Y17_N3
--operation mode is normal
L1L816 = AMPP_FUNCTION(L1_E_src2_hazard_M, L1L1421, L1L1420, L1_E_src2_prelim[15]);
--L1L684 is std_1s10:inst|cpu:the_cpu|E_src2[15]~1505 at LC_X17_Y12_N3
--operation mode is normal
L1L684 = AMPP_FUNCTION(L1_E_ctrl_src2_is_imm, L1L816, L1_E_src2_imm[15]);
--L1_E_src1_prelim[15] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[15] at LC_X14_Y17_N5
--operation mode is normal
L1_E_src1_prelim[15] = AMPP_FUNCTION(DE1__clk0, L1_D_src1_hazard_W, MC1_q_b[15], L1L1422, L1_W_wr_data[15], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L618 is std_1s10:inst|cpu:the_cpu|E_src1[15]~1979 at LC_X18_Y17_N4
--operation mode is normal
L1L618 = AMPP_FUNCTION(L1L1421, L1_E_src1_prelim[15], L1L1420, L1_E_src1_hazard_M);
--L1L547 is std_1s10:inst|cpu:the_cpu|E_logic_result[15]~16128 at LC_X18_Y13_N5
--operation mode is normal
L1L547 = AMPP_FUNCTION(L1_E_logic_op[1], L1L684, L1_E_logic_op[0], L1L618);
--L1_E_extra_pc[12] is std_1s10:inst|cpu:the_cpu|E_extra_pc[12] at LC_X27_Y20_N7
--operation mode is normal
L1_E_extra_pc[12] = AMPP_FUNCTION(DE1__clk0, L1L110, L1L218, L1_D_iw[21], L1_D_pc_plus_one[12], E1_data_out, L1_W_stall);
--HC1_result[14] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[14] at LC_X18_Y11_N4
--operation mode is arithmetic
HC1_result[14] = AMPP_FUNCTION(L1L683, L1L617, HC1L29, HC1L40, HC1L41, L1_E_ctrl_alu_subtract);
--HC1L43 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[14]~COUT at LC_X18_Y11_N4
--operation mode is arithmetic
HC1L43 = AMPP_FUNCTION(L1L683, L1L617, HC1L29, HC1L40, HC1L41, L1_E_ctrl_alu_subtract);
--L1L22 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12902 at LC_X27_Y20_N4
--operation mode is normal
L1L22 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, L1_E_extra_pc[12], HC1_result[14]);
--L1_E_src2_imm[14] is std_1s10:inst|cpu:the_cpu|E_src2_imm[14] at LC_X17_Y12_N1
--operation mode is normal
L1_E_src2_imm[14] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[2], L1_D_iw[5], L1_D_iw[20], L1L235, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[14] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[14] at LC_X14_Y18_N4
--operation mode is normal
L1_E_src2_prelim[14] = AMPP_FUNCTION(DE1__clk0, L1L403, NC1_q_b[14], L1L1419, L1_W_wr_data[14], E1_data_out, L1L399, L1_W_stall);
--L1_M_mul_shift_rot_result[14] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[14] at LC_X14_Y15_N2
--operation mode is normal
L1_M_mul_shift_rot_result[14] = AMPP_FUNCTION(DE1__clk0, QC1_result[46], L1L1284, L1L1267, QC1_result[14], E1_data_out, L1_M_ctrl_rot);
--L1L1417 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[14]~3675 at LC_X14_Y15_N9
--operation mode is normal
L1L1417 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[14], L1_M_ctrl_mul_shift_rot);
--L1L149 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[14]~COMBOUT at LC_X24_Y20_N6
--operation mode is normal
L1L149 = AMPP_FUNCTION(L1_M_ld_align_sh16, L1_d_readdata_d1[30], L1_d_readdata_d1[14]);
--L1_av_ld_data_aligned_or_div[14] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[14] at LC_X24_Y20_N6
--operation mode is normal
L1_av_ld_data_aligned_or_div[14] = AMPP_FUNCTION(DE1__clk0, L1_M_ld_align_sh16, L1_d_readdata_d1[30], L1_av_fill_bit, L1_d_readdata_d1[14], E1_data_out, L1L846);
--L1L1418 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[14]~3676 at LC_X14_Y15_N7
--operation mode is normal
L1L1418 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[14], L1_M_alu_result[14], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L815 is std_1s10:inst|cpu:the_cpu|E_sth_data[14]~473 at LC_X14_Y18_N6
--operation mode is normal
L1L815 = AMPP_FUNCTION(L1_E_src2_prelim[14], L1_E_src2_hazard_M, L1L1418, L1L1417);
--L1L683 is std_1s10:inst|cpu:the_cpu|E_src2[14]~1506 at LC_X17_Y12_N9
--operation mode is normal
L1L683 = AMPP_FUNCTION(L1L815, L1_E_src2_imm[14], L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[14] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[14] at LC_X14_Y17_N4
--operation mode is normal
L1_E_src1_prelim[14] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[14], L1_D_src1_hazard_W, L1L1419, MC1_q_b[14], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L617 is std_1s10:inst|cpu:the_cpu|E_src1[14]~1980 at LC_X14_Y15_N8
--operation mode is normal
L1L617 = AMPP_FUNCTION(L1L1418, L1_E_src1_prelim[14], L1_E_src1_hazard_M, L1L1417);
--L1L546 is std_1s10:inst|cpu:the_cpu|E_logic_result[14]~16129 at LC_X18_Y13_N4
--operation mode is normal
L1L546 = AMPP_FUNCTION(L1_E_logic_op[1], L1L683, L1_E_logic_op[0], L1L617);
--L1_E_extra_pc[11] is std_1s10:inst|cpu:the_cpu|E_extra_pc[11] at LC_X27_Y20_N1
--operation mode is normal
L1_E_extra_pc[11] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[11], L1L218, L1_D_iw[21], L1L113, E1_data_out, L1_W_stall);
--HC1_result[13] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[13] at LC_X18_Y11_N3
--operation mode is arithmetic
HC1_result[13] = AMPP_FUNCTION(L1L682, L1L616, HC1L29, HC1L37, HC1L38, L1_E_ctrl_alu_subtract);
--HC1L40 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[13]~COUT at LC_X18_Y11_N3
--operation mode is arithmetic
HC1L40 = AMPP_FUNCTION(L1L682, L1L616, HC1L37, L1_E_ctrl_alu_subtract);
--HC1L41 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[13]~COUTCOUT1_169 at LC_X18_Y11_N3
--operation mode is arithmetic
HC1L41 = AMPP_FUNCTION(L1L682, L1L616, HC1L38, L1_E_ctrl_alu_subtract);
--L1L23 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12903 at LC_X25_Y21_N6
--operation mode is normal
L1L23 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, L1_E_extra_pc[11], HC1_result[13]);
--L1_E_src2_imm[13] is std_1s10:inst|cpu:the_cpu|E_src2_imm[13] at LC_X17_Y12_N8
--operation mode is normal
L1_E_src2_imm[13] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[5], L1_D_iw[19], L1_D_iw[2], L1L235, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[13] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[13] at LC_X17_Y17_N4
--operation mode is normal
L1_E_src2_prelim[13] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[13], L1_W_wr_data[13], L1L1416, L1L403, E1_data_out, L1L399, L1_W_stall);
--L1_M_mul_shift_rot_result[13] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[13] at LC_X12_Y16_N6
--operation mode is normal
L1_M_mul_shift_rot_result[13] = AMPP_FUNCTION(DE1__clk0, QC1_result[45], QC1_result[13], L1L1266, L1L1284, E1_data_out, L1_M_ctrl_rot);
--L1L1414 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[13]~3677 at LC_X18_Y17_N5
--operation mode is normal
L1L1414 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[13]);
--L1L147 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[13]~COMBOUT at LC_X24_Y20_N2
--operation mode is normal
L1L147 = AMPP_FUNCTION(L1_M_ld_align_sh16, L1_d_readdata_d1[13], L1_d_readdata_d1[29]);
--L1_av_ld_data_aligned_or_div[13] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[13] at LC_X24_Y20_N2
--operation mode is normal
L1_av_ld_data_aligned_or_div[13] = AMPP_FUNCTION(DE1__clk0, L1_M_ld_align_sh16, L1_d_readdata_d1[13], L1_av_fill_bit, L1_d_readdata_d1[29], E1_data_out, L1L846);
--L1L1415 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[13]~3678 at LC_X18_Y17_N6
--operation mode is normal
L1L1415 = AMPP_FUNCTION(L1_av_ld_or_div_done, L1_M_alu_result[13], L1_M_ctrl_mul_shift_rot, L1_av_ld_data_aligned_or_div[13]);
--L1L814 is std_1s10:inst|cpu:the_cpu|E_sth_data[13]~474 at LC_X18_Y17_N0
--operation mode is normal
L1L814 = AMPP_FUNCTION(L1_E_src2_hazard_M, L1_E_src2_prelim[13], L1L1414, L1L1415);
--L1L682 is std_1s10:inst|cpu:the_cpu|E_src2[13]~1507 at LC_X17_Y12_N5
--operation mode is normal
L1L682 = AMPP_FUNCTION(L1_E_src2_imm[13], L1_E_ctrl_src2_is_imm, L1L814);
--L1_E_src1_prelim[13] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[13] at LC_X14_Y17_N8
--operation mode is normal
L1_E_src1_prelim[13] = AMPP_FUNCTION(DE1__clk0, L1_D_src1_hazard_W, MC1_q_b[13], L1L1416, L1_W_wr_data[13], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L616 is std_1s10:inst|cpu:the_cpu|E_src1[13]~1981 at LC_X18_Y17_N9
--operation mode is normal
L1L616 = AMPP_FUNCTION(L1_E_src1_hazard_M, L1L1414, L1_E_src1_prelim[13], L1L1415);
--L1L545 is std_1s10:inst|cpu:the_cpu|E_logic_result[13]~16130 at LC_X18_Y13_N2
--operation mode is normal
L1L545 = AMPP_FUNCTION(L1_E_logic_op[1], L1L682, L1_E_logic_op[0], L1L616);
--L1_E_extra_pc[10] is std_1s10:inst|cpu:the_cpu|E_extra_pc[10] at LC_X33_Y20_N0
--operation mode is normal
L1_E_extra_pc[10] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[10], L1L218, L1L116, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[12] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[12] at LC_X18_Y11_N2
--operation mode is arithmetic
HC1_result[12] = AMPP_FUNCTION(L1L681, L1L615, HC1L29, HC1L34, HC1L35, L1_E_ctrl_alu_subtract);
--HC1L37 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[12]~COUT at LC_X18_Y11_N2
--operation mode is arithmetic
HC1L37 = AMPP_FUNCTION(L1L681, L1L615, HC1L34, L1_E_ctrl_alu_subtract);
--HC1L38 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[12]~COUTCOUT1_167 at LC_X18_Y11_N2
--operation mode is arithmetic
HC1L38 = AMPP_FUNCTION(L1L681, L1L615, HC1L35, L1_E_ctrl_alu_subtract);
--L1L24 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12904 at LC_X25_Y21_N7
--operation mode is normal
L1L24 = AMPP_FUNCTION(L1_E_extra_pc[10], HC1_result[12], L1_E_ctrl_dst_data_sel_pc_plus_one);
--L1_E_src2_imm[12] is std_1s10:inst|cpu:the_cpu|E_src2_imm[12] at LC_X17_Y12_N6
--operation mode is normal
L1_E_src2_imm[12] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[5], L1_D_iw[18], L1_D_iw[2], L1L235, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[12] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[12] at LC_X14_Y16_N2
--operation mode is normal
L1_E_src2_prelim[12] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[12], L1_W_wr_data[12], L1L1413, L1L403, E1_data_out, L1L399, L1_W_stall);
--L1_M_mul_shift_rot_result[12] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[12] at LC_X13_Y16_N2
--operation mode is normal
L1_M_mul_shift_rot_result[12] = AMPP_FUNCTION(DE1__clk0, QC1_result[12], L1L1284, L1L1265, QC1_result[44], E1_data_out, L1_M_ctrl_rot);
--L1L1411 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[12]~3679 at LC_X13_Y16_N4
--operation mode is normal
L1L1411 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[12]);
--L1L145 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[12]~COMBOUT at LC_X24_Y20_N5
--operation mode is normal
L1L145 = AMPP_FUNCTION(L1_M_ld_align_sh16, L1_d_readdata_d1[12], L1_d_readdata_d1[28]);
--L1_av_ld_data_aligned_or_div[12] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[12] at LC_X24_Y20_N5
--operation mode is normal
L1_av_ld_data_aligned_or_div[12] = AMPP_FUNCTION(DE1__clk0, L1_M_ld_align_sh16, L1_d_readdata_d1[12], L1_av_fill_bit, L1_d_readdata_d1[28], E1_data_out, L1L846);
--L1L1412 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[12]~3680 at LC_X13_Y16_N0
--operation mode is normal
L1L1412 = AMPP_FUNCTION(L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot, L1_M_alu_result[12], L1_av_ld_data_aligned_or_div[12]);
--L1L813 is std_1s10:inst|cpu:the_cpu|E_sth_data[12]~475 at LC_X14_Y16_N9
--operation mode is normal
L1L813 = AMPP_FUNCTION(L1L1412, L1L1411, L1_E_src2_hazard_M, L1_E_src2_prelim[12]);
--L1L681 is std_1s10:inst|cpu:the_cpu|E_src2[12]~1508 at LC_X17_Y12_N4
--operation mode is normal
L1L681 = AMPP_FUNCTION(L1L813, L1_E_src2_imm[12], L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[12] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[12] at LC_X14_Y17_N7
--operation mode is normal
L1_E_src1_prelim[12] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[12], MC1_q_b[12], L1L1413, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L615 is std_1s10:inst|cpu:the_cpu|E_src1[12]~1982 at LC_X13_Y16_N5
--operation mode is normal
L1L615 = AMPP_FUNCTION(L1L1411, L1_E_src1_hazard_M, L1_E_src1_prelim[12], L1L1412);
--L1L544 is std_1s10:inst|cpu:the_cpu|E_logic_result[12]~16131 at LC_X17_Y11_N1
--operation mode is normal
L1L544 = AMPP_FUNCTION(L1L681, L1_E_logic_op[0], L1_E_logic_op[1], L1L615);
--L1_E_extra_pc[9] is std_1s10:inst|cpu:the_cpu|E_extra_pc[9] at LC_X30_Y20_N0
--operation mode is normal
L1_E_extra_pc[9] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[9], L1_D_br_taken_waddr_partial[9], L1L218, L1_D_iw[21], E1_data_out, L1_W_stall);
--HC1_result[11] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[11] at LC_X18_Y11_N1
--operation mode is arithmetic
HC1_result[11] = AMPP_FUNCTION(L1L680, L1L614, HC1L29, HC1L31, HC1L32, L1_E_ctrl_alu_subtract);
--HC1L34 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[11]~COUT at LC_X18_Y11_N1
--operation mode is arithmetic
HC1L34 = AMPP_FUNCTION(L1L680, L1L614, HC1L31, L1_E_ctrl_alu_subtract);
--HC1L35 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[11]~COUTCOUT1_165 at LC_X18_Y11_N1
--operation mode is arithmetic
HC1L35 = AMPP_FUNCTION(L1L680, L1L614, HC1L32, L1_E_ctrl_alu_subtract);
--L1L25 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12905 at LC_X30_Y20_N6
--operation mode is normal
L1L25 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[11], L1_E_extra_pc[9]);
--L1_E_src2_imm[11] is std_1s10:inst|cpu:the_cpu|E_src2_imm[11] at LC_X17_Y9_N3
--operation mode is normal
L1_E_src2_imm[11] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[5], L1_D_iw[2], L1_D_iw[17], L1L235, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[11] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[11] at LC_X14_Y18_N1
--operation mode is normal
L1_E_src2_prelim[11] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[11], L1_W_wr_data[11], L1L1410, L1L403, E1_data_out, L1L399, L1_W_stall);
--L1_M_mul_shift_rot_result[11] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[11] at LC_X12_Y16_N9
--operation mode is normal
L1_M_mul_shift_rot_result[11] = AMPP_FUNCTION(DE1__clk0, L1L1284, QC1_result[43], L1L1264, QC1_result[11], E1_data_out, L1_M_ctrl_rot);
--L1L1408 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[11]~3681 at LC_X14_Y18_N2
--operation mode is normal
L1L1408 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[11]);
--L1L143 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[11]~COMBOUT at LC_X24_Y20_N0
--operation mode is normal
L1L143 = AMPP_FUNCTION(L1_M_ld_align_sh16, L1_d_readdata_d1[27], L1_d_readdata_d1[11]);
--L1_av_ld_data_aligned_or_div[11] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[11] at LC_X24_Y20_N0
--operation mode is normal
L1_av_ld_data_aligned_or_div[11] = AMPP_FUNCTION(DE1__clk0, L1_M_ld_align_sh16, L1_d_readdata_d1[27], L1_av_fill_bit, L1_d_readdata_d1[11], E1_data_out, L1L846);
--L1L1409 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[11]~3682 at LC_X14_Y18_N9
--operation mode is normal
L1L1409 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[11], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot, L1_M_alu_result[11]);
--L1L812 is std_1s10:inst|cpu:the_cpu|E_sth_data[11]~476 at LC_X14_Y18_N8
--operation mode is normal
L1L812 = AMPP_FUNCTION(L1L1408, L1_E_src2_prelim[11], L1_E_src2_hazard_M, L1L1409);
--L1L680 is std_1s10:inst|cpu:the_cpu|E_src2[11]~1509 at LC_X17_Y9_N9
--operation mode is normal
L1L680 = AMPP_FUNCTION(L1_E_src2_imm[11], L1_E_ctrl_src2_is_imm, L1L812);
--L1_E_src1_prelim[11] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[11] at LC_X14_Y17_N0
--operation mode is normal
L1_E_src1_prelim[11] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[11], L1_W_wr_data[11], L1L1410, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L614 is std_1s10:inst|cpu:the_cpu|E_src1[11]~1983 at LC_X14_Y18_N3
--operation mode is normal
L1L614 = AMPP_FUNCTION(L1L1408, L1_E_src1_prelim[11], L1_E_src1_hazard_M, L1L1409);
--L1L543 is std_1s10:inst|cpu:the_cpu|E_logic_result[11]~16132 at LC_X14_Y18_N7
--operation mode is normal
L1L543 = AMPP_FUNCTION(L1L614, L1_E_logic_op[1], L1_E_logic_op[0], L1L680);
--L1_E_extra_pc[8] is std_1s10:inst|cpu:the_cpu|E_extra_pc[8] at LC_X30_Y20_N5
--operation mode is normal
L1_E_extra_pc[8] = AMPP_FUNCTION(DE1__clk0, L1_D_br_taken_waddr_partial[8], L1_D_iw[21], L1_D_pc_plus_one[8], L1L218, E1_data_out, L1_W_stall);
--HC1_result[10] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[10] at LC_X18_Y11_N0
--operation mode is arithmetic
HC1_result[10] = AMPP_FUNCTION(L1L679, L1L613, HC1L29, L1_E_ctrl_alu_subtract);
--HC1L31 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[10]~COUT at LC_X18_Y11_N0
--operation mode is arithmetic
HC1L31 = AMPP_FUNCTION(L1L679, L1L613, L1_E_ctrl_alu_subtract);
--HC1L32 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[10]~COUTCOUT1_163 at LC_X18_Y11_N0
--operation mode is arithmetic
HC1L32 = AMPP_FUNCTION(L1L679, L1L613, L1_E_ctrl_alu_subtract);
--L1L26 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12906 at LC_X30_Y20_N4
--operation mode is normal
L1L26 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, L1_E_extra_pc[8], HC1_result[10]);
--L1_E_src2_imm[10] is std_1s10:inst|cpu:the_cpu|E_src2_imm[10] at LC_X17_Y9_N5
--operation mode is normal
L1_E_src2_imm[10] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[5], L1_D_iw[16], L1L235, L1_D_iw[2], E1_data_out, L1_W_stall);
--L1_E_src2_prelim[10] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[10] at LC_X19_Y17_N0
--operation mode is normal
L1_E_src2_prelim[10] = AMPP_FUNCTION(DE1__clk0, L1L403, NC1_q_b[10], L1L1407, L1_W_wr_data[10], E1_data_out, L1L399, L1_W_stall);
--L1_M_mul_shift_rot_result[10] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[10] at LC_X12_Y16_N4
--operation mode is normal
L1_M_mul_shift_rot_result[10] = AMPP_FUNCTION(DE1__clk0, L1L1284, QC1_result[42], L1L1263, QC1_result[10], E1_data_out, L1_M_ctrl_rot);
--L1L1405 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[10]~3683 at LC_X19_Y17_N7
--operation mode is normal
L1L1405 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[10]);
--L1L141 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[10]~COMBOUT at LC_X24_Y20_N1
--operation mode is normal
L1L141 = AMPP_FUNCTION(L1_M_ld_align_sh16, L1_d_readdata_d1[26], L1_d_readdata_d1[10]);
--L1_av_ld_data_aligned_or_div[10] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[10] at LC_X24_Y20_N1
--operation mode is normal
L1_av_ld_data_aligned_or_div[10] = AMPP_FUNCTION(DE1__clk0, L1_M_ld_align_sh16, L1_d_readdata_d1[26], L1_av_fill_bit, L1_d_readdata_d1[10], E1_data_out, L1L846);
--L1L1406 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[10]~3684 at LC_X19_Y17_N4
--operation mode is normal
L1L1406 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_av_ld_data_aligned_or_div[10], L1_av_ld_or_div_done, L1_M_alu_result[10]);
--L1L811 is std_1s10:inst|cpu:the_cpu|E_sth_data[10]~477 at LC_X19_Y17_N2
--operation mode is normal
L1L811 = AMPP_FUNCTION(L1_E_src2_hazard_M, L1L1406, L1L1405, L1_E_src2_prelim[10]);
--L1L679 is std_1s10:inst|cpu:the_cpu|E_src2[10]~1510 at LC_X17_Y9_N1
--operation mode is normal
L1L679 = AMPP_FUNCTION(L1_E_src2_imm[10], L1L811, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[10] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[10] at LC_X17_Y16_N2
--operation mode is normal
L1_E_src1_prelim[10] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[10], L1_D_src1_hazard_W, L1L1407, MC1_q_b[10], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L613 is std_1s10:inst|cpu:the_cpu|E_src1[10]~1984 at LC_X19_Y17_N5
--operation mode is normal
L1L613 = AMPP_FUNCTION(L1_E_src1_hazard_M, L1_E_src1_prelim[10], L1L1405, L1L1406);
--L1L542 is std_1s10:inst|cpu:the_cpu|E_logic_result[10]~16133 at LC_X19_Y17_N3
--operation mode is normal
L1L542 = AMPP_FUNCTION(L1_E_logic_op[1], L1L679, L1L613, L1_E_logic_op[0]);
--L1_E_extra_pc[7] is std_1s10:inst|cpu:the_cpu|E_extra_pc[7] at LC_X32_Y20_N9
--operation mode is normal
L1_E_extra_pc[7] = AMPP_FUNCTION(DE1__clk0, L1_D_pc_plus_one[7], L1_D_iw[21], L1_D_br_taken_waddr_partial[7], L1L218, E1_data_out, L1_W_stall);
--HC1_result[9] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[9] at LC_X18_Y12_N9
--operation mode is arithmetic
HC1_result[9] = AMPP_FUNCTION(L1L678, L1L612, HC1L15, HC1L26, HC1L27, L1_E_ctrl_alu_subtract);
--HC1L29 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[9]~COUT at LC_X18_Y12_N9
--operation mode is arithmetic
HC1L29 = AMPP_FUNCTION(L1L678, L1L612, HC1L15, HC1L26, HC1L27, L1_E_ctrl_alu_subtract);
--L1L27 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12907 at LC_X32_Y20_N3
--operation mode is normal
L1L27 = AMPP_FUNCTION(L1_E_extra_pc[7], L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[9]);
--L1_E_src2_imm[9] is std_1s10:inst|cpu:the_cpu|E_src2_imm[9] at LC_X17_Y9_N0
--operation mode is normal
L1_E_src2_imm[9] = AMPP_FUNCTION(DE1__clk0, L1L235, L1_D_iw[2], L1_D_iw[15], L1_D_iw[5], E1_data_out, L1_W_stall);
--L1_E_src2_prelim[9] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[9] at LC_X14_Y14_N9
--operation mode is normal
L1_E_src2_prelim[9] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[9], L1L403, L1L1404, L1_W_wr_data[9], E1_data_out, L1L399, L1_W_stall);
--L1_M_mul_shift_rot_result[9] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[9] at LC_X12_Y15_N0
--operation mode is normal
L1_M_mul_shift_rot_result[9] = AMPP_FUNCTION(DE1__clk0, QC1_result[9], L1L1284, L1L1262, QC1_result[41], E1_data_out, L1_M_ctrl_rot);
--L1L1402 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[9]~3685 at LC_X14_Y14_N3
--operation mode is normal
L1L1402 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[9]);
--L1L139 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[9]~COMBOUT at LC_X24_Y20_N7
--operation mode is normal
L1L139 = AMPP_FUNCTION(L1_d_readdata_d1[9], L1_d_readdata_d1[25], L1_M_ld_align_sh16);
--L1_av_ld_data_aligned_or_div[9] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[9] at LC_X24_Y20_N7
--operation mode is normal
L1_av_ld_data_aligned_or_div[9] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[9], L1_d_readdata_d1[25], L1_av_fill_bit, L1_M_ld_align_sh16, E1_data_out, L1L846);
--L1L1403 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[9]~3686 at LC_X14_Y14_N7
--operation mode is normal
L1L1403 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_av_ld_or_div_done, L1_M_alu_result[9], L1_av_ld_data_aligned_or_div[9]);
--L1L810 is std_1s10:inst|cpu:the_cpu|E_sth_data[9]~478 at LC_X14_Y14_N4
--operation mode is normal
L1L810 = AMPP_FUNCTION(L1_E_src2_hazard_M, L1_E_src2_prelim[9], L1L1403, L1L1402);
--L1L678 is std_1s10:inst|cpu:the_cpu|E_src2[9]~1511 at LC_X17_Y9_N8
--operation mode is normal
L1L678 = AMPP_FUNCTION(L1_E_src2_imm[9], L1L810, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[9] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[9] at LC_X17_Y16_N1
--operation mode is normal
L1_E_src1_prelim[9] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[9], L1_D_src1_hazard_W, L1L1404, MC1_q_b[9], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L612 is std_1s10:inst|cpu:the_cpu|E_src1[9]~1985 at LC_X14_Y14_N8
--operation mode is normal
L1L612 = AMPP_FUNCTION(L1_E_src1_prelim[9], L1_E_src1_hazard_M, L1L1402, L1L1403);
--L1L541 is std_1s10:inst|cpu:the_cpu|E_logic_result[9]~16134 at LC_X14_Y14_N1
--operation mode is normal
L1L541 = AMPP_FUNCTION(L1L612, L1_E_logic_op[0], L1L678, L1_E_logic_op[1]);
--L1_E_extra_pc[6] is std_1s10:inst|cpu:the_cpu|E_extra_pc[6] at LC_X32_Y20_N0
--operation mode is normal
L1_E_extra_pc[6] = AMPP_FUNCTION(DE1__clk0, L1_D_br_taken_waddr_partial[6], L1_D_iw[21], L1_D_pc_plus_one[6], L1L218, E1_data_out, L1_W_stall);
--HC1_result[8] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[8] at LC_X18_Y12_N8
--operation mode is arithmetic
HC1_result[8] = AMPP_FUNCTION(L1L677, L1L611, HC1L15, HC1L23, HC1L24, L1_E_ctrl_alu_subtract);
--HC1L26 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[8]~COUT at LC_X18_Y12_N8
--operation mode is arithmetic
HC1L26 = AMPP_FUNCTION(L1L677, L1L611, HC1L23, L1_E_ctrl_alu_subtract);
--HC1L27 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[8]~COUTCOUT1_161 at LC_X18_Y12_N8
--operation mode is arithmetic
HC1L27 = AMPP_FUNCTION(L1L677, L1L611, HC1L24, L1_E_ctrl_alu_subtract);
--L1L28 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12908 at LC_X32_Y20_N2
--operation mode is normal
L1L28 = AMPP_FUNCTION(L1_E_extra_pc[6], L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[8]);
--L1_E_src2_imm[8] is std_1s10:inst|cpu:the_cpu|E_src2_imm[8] at LC_X17_Y9_N4
--operation mode is normal
L1_E_src2_imm[8] = AMPP_FUNCTION(DE1__clk0, L1L235, L1_D_iw[2], L1_D_iw[14], L1_D_iw[5], E1_data_out, L1_W_stall);
--L1_E_src2_prelim[8] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[8] at LC_X14_Y16_N5
--operation mode is normal
L1_E_src2_prelim[8] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[8], NC1_q_b[8], L1L1401, L1L403, E1_data_out, L1L399, L1_W_stall);
--L1_M_mul_shift_rot_result[8] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[8] at LC_X12_Y16_N2
--operation mode is normal
L1_M_mul_shift_rot_result[8] = AMPP_FUNCTION(DE1__clk0, QC1_result[40], L1L1284, L1L1261, QC1_result[8], E1_data_out, L1_M_ctrl_rot);
--L1L1399 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[8]~3687 at LC_X14_Y16_N3
--operation mode is normal
L1L1399 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[8], L1_M_ctrl_mul_shift_rot);
--L1L137 is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[8]~COMBOUT at LC_X24_Y20_N9
--operation mode is normal
L1L137 = AMPP_FUNCTION(L1_M_ld_align_sh16, L1_d_readdata_d1[24], L1_d_readdata_d1[8]);
--L1_av_ld_data_aligned_or_div[8] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[8] at LC_X24_Y20_N9
--operation mode is normal
L1_av_ld_data_aligned_or_div[8] = AMPP_FUNCTION(DE1__clk0, L1_M_ld_align_sh16, L1_d_readdata_d1[24], L1_av_fill_bit, L1_d_readdata_d1[8], E1_data_out, L1L846);
--L1L1400 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[8]~3688 at LC_X14_Y16_N6
--operation mode is normal
L1L1400 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[8], L1_M_alu_result[8], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L809 is std_1s10:inst|cpu:the_cpu|E_sth_data[8]~479 at LC_X14_Y16_N4
--operation mode is normal
L1L809 = AMPP_FUNCTION(L1L1400, L1_E_src2_hazard_M, L1_E_src2_prelim[8], L1L1399);
--L1L677 is std_1s10:inst|cpu:the_cpu|E_src2[8]~1512 at LC_X17_Y9_N7
--operation mode is normal
L1L677 = AMPP_FUNCTION(L1_E_ctrl_src2_is_imm, L1L809, L1_E_src2_imm[8]);
--L1_E_src1_prelim[8] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[8] at LC_X17_Y16_N8
--operation mode is normal
L1_E_src1_prelim[8] = AMPP_FUNCTION(DE1__clk0, L1_D_src1_hazard_W, L1_W_wr_data[8], L1L1401, MC1_q_b[8], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1L611 is std_1s10:inst|cpu:the_cpu|E_src1[8]~1986 at LC_X14_Y16_N7
--operation mode is normal
L1L611 = AMPP_FUNCTION(L1L1399, L1L1400, L1_E_src1_hazard_M, L1_E_src1_prelim[8]);
--L1L540 is std_1s10:inst|cpu:the_cpu|E_logic_result[8]~16135 at LC_X14_Y16_N8
--operation mode is normal
L1L540 = AMPP_FUNCTION(L1L611, L1_E_logic_op[0], L1L677, L1_E_logic_op[1]);
--L1_E_control_rd_data_without_mmu_regs[5] is std_1s10:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[5] at LC_X30_Y21_N9
--operation mode is normal
L1_E_control_rd_data_without_mmu_regs[5] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[8], L1_M_ipending_reg[5], L1L205, L1_M_ienable_reg[5], E1_data_out, L1_W_stall);
--L1_E_src1_prelim[5] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[5] at LC_X19_Y15_N4
--operation mode is normal
L1_E_src1_prelim[5] = AMPP_FUNCTION(DE1__clk0, L1_D_src1_hazard_W, L1_W_wr_data[5], L1L1392, MC1_q_b[5], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[5] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[5] at LC_X12_Y15_N2
--operation mode is normal
L1_M_mul_shift_rot_result[5] = AMPP_FUNCTION(DE1__clk0, QC1_result[5], L1L1284, L1L1258, QC1_result[37], E1_data_out, L1_M_ctrl_rot);
--L1L1390 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[5]~3689 at LC_X19_Y15_N6
--operation mode is normal
L1L1390 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[5], L1_M_ctrl_mul_shift_rot);
--L1_av_ld_data_aligned_or_div[5] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[5] at LC_X24_Y21_N9
--operation mode is normal
L1_av_ld_data_aligned_or_div[5] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[21], L1_d_readdata_d1[5], L1L147, L1_M_ld_align_sh16, E1_data_out, L1_M_ld_align_sh8);
--L1L1391 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[5]~3690 at LC_X19_Y15_N1
--operation mode is normal
L1L1391 = AMPP_FUNCTION(L1_M_alu_result[5], L1_av_ld_data_aligned_or_div[5], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot);
--L1L608 is std_1s10:inst|cpu:the_cpu|E_src1[5]~1987 at LC_X19_Y15_N3
--operation mode is normal
L1L608 = AMPP_FUNCTION(L1_E_src1_hazard_M, L1L1390, L1L1391, L1_E_src1_prelim[5]);
--L1_E_src2_imm[5] is std_1s10:inst|cpu:the_cpu|E_src2_imm[5] at LC_X17_Y9_N6
--operation mode is normal
L1_E_src2_imm[5] = AMPP_FUNCTION(DE1__clk0, L1L235, L1_D_iw[2], L1_D_iw[11], L1_D_iw[5], E1_data_out, L1_W_stall);
--L1L1335 is std_1s10:inst|cpu:the_cpu|M_st_data[13]~COMBOUT at LC_X18_Y17_N8
--operation mode is normal
L1L1335 = AMPP_FUNCTION(L1_E_src2_prelim[5], L1_E_src2_hazard_M, L1L1392);
--L1_M_st_data[13] is std_1s10:inst|cpu:the_cpu|M_st_data[13] at LC_X18_Y17_N8
--operation mode is normal
L1_M_st_data[13] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[5], L1_E_src2_hazard_M, L1L814, L1L1392, E1_data_out, L1L845, L1_W_stall);
--L1L674 is std_1s10:inst|cpu:the_cpu|E_src2[5]~1513 at LC_X17_Y9_N2
--operation mode is normal
L1L674 = AMPP_FUNCTION(L1_E_src2_imm[5], L1L1335, L1_E_ctrl_src2_is_imm);
--L1L29 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12909 at LC_X14_Y13_N0
--operation mode is normal
L1L29 = AMPP_FUNCTION(L1L608, L1_E_logic_op[1], L1L674, L1_E_logic_op[0]);
--L1_E_extra_pc[3] is std_1s10:inst|cpu:the_cpu|E_extra_pc[3] at LC_X35_Y20_N4
--operation mode is normal
L1_E_extra_pc[3] = AMPP_FUNCTION(DE1__clk0, L1_D_br_taken_waddr_partial[3], L1_D_iw[21], L1_D_pc_plus_one[3], L1L218, E1_data_out, L1_W_stall);
--HC1_result[5] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[5] at LC_X18_Y12_N5
--operation mode is arithmetic
HC1_result[5] = AMPP_FUNCTION(L1L674, L1L608, HC1L15, L1_E_ctrl_alu_subtract);
--HC1L17 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[5]~COUT at LC_X18_Y12_N5
--operation mode is arithmetic
HC1L17 = AMPP_FUNCTION(L1L674, L1L608, L1_E_ctrl_alu_subtract);
--HC1L18 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[5]~COUTCOUT1_155 at LC_X18_Y12_N5
--operation mode is arithmetic
HC1L18 = AMPP_FUNCTION(L1L674, L1L608, L1_E_ctrl_alu_subtract);
--L1L30 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12910 at LC_X30_Y21_N4
--operation mode is normal
L1L30 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, L1_E_extra_pc[3], HC1_result[5]);
--L1L31 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12911 at LC_X30_Y21_N0
--operation mode is normal
L1L31 = AMPP_FUNCTION(L1L29, L1_E_ctrl_dst_data_sel_logic_result, L1L30);
--L1L432 is std_1s10:inst|cpu:the_cpu|E_alu_result[5]~2249 at LC_X30_Y21_N1
--operation mode is normal
L1L432 = AMPP_FUNCTION(L1_E_ctrl_rdctl_inst, L1_E_control_rd_data_without_mmu_regs[5], L1_E_ctrl_dst_data_sel_cmp, L1L31);
--L1_M_alu_result[5] is std_1s10:inst|cpu:the_cpu|M_alu_result[5] at LC_X30_Y21_N1
--operation mode is normal
L1_M_alu_result[5] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_rdctl_inst, L1_E_control_rd_data_without_mmu_regs[5], L1_E_ctrl_dst_data_sel_cmp, L1L31, E1_data_out, L1_W_stall);
--L1_E_ctrl_st is std_1s10:inst|cpu:the_cpu|E_ctrl_st at LC_X23_Y20_N3
--operation mode is normal
L1_E_ctrl_st = AMPP_FUNCTION(DE1__clk0, L1_D_iw[1], L1_D_iw[0], E1_data_out, L1_W_stall);
--L1_E_extra_pc[4] is std_1s10:inst|cpu:the_cpu|E_extra_pc[4] at LC_X35_Y20_N3
--operation mode is normal
L1_E_extra_pc[4] = AMPP_FUNCTION(DE1__clk0, L1L218, L1_D_br_taken_waddr_partial[4], L1_D_iw[21], L1_D_pc_plus_one[4], E1_data_out, L1_W_stall);
--HC1_result[6] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[6] at LC_X18_Y12_N6
--operation mode is arithmetic
HC1_result[6] = AMPP_FUNCTION(L1L675, L1L609, HC1L15, HC1L17, HC1L18, L1_E_ctrl_alu_subtract);
--HC1L20 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[6]~COUT at LC_X18_Y12_N6
--operation mode is arithmetic
HC1L20 = AMPP_FUNCTION(L1L675, L1L609, HC1L17, L1_E_ctrl_alu_subtract);
--HC1L21 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[6]~COUTCOUT1_157 at LC_X18_Y12_N6
--operation mode is arithmetic
HC1L21 = AMPP_FUNCTION(L1L675, L1L609, HC1L18, L1_E_ctrl_alu_subtract);
--L1L32 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12912 at LC_X31_Y20_N5
--operation mode is normal
L1L32 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, L1_E_extra_pc[4], HC1_result[6]);
--L1_E_src1_prelim[6] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[6] at LC_X17_Y21_N2
--operation mode is normal
L1_E_src1_prelim[6] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[6], MC1_q_b[6], L1L1395, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[6] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[6] at LC_X12_Y15_N8
--operation mode is normal
L1_M_mul_shift_rot_result[6] = AMPP_FUNCTION(DE1__clk0, QC1_result[38], L1L1284, L1L1259, QC1_result[6], E1_data_out, L1_M_ctrl_rot);
--L1L1393 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[6]~3691 at LC_X17_Y21_N6
--operation mode is normal
L1L1393 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[6]);
--L1_av_ld_data_aligned_or_div[6] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[6] at LC_X24_Y21_N6
--operation mode is normal
L1_av_ld_data_aligned_or_div[6] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[6], L1_d_readdata_d1[22], L1L149, L1_M_ld_align_sh16, E1_data_out, L1_M_ld_align_sh8);
--L1L1394 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[6]~3692 at LC_X17_Y21_N0
--operation mode is normal
L1L1394 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[6], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot, L1_M_alu_result[6]);
--L1L609 is std_1s10:inst|cpu:the_cpu|E_src1[6]~1988 at LC_X17_Y21_N7
--operation mode is normal
L1L609 = AMPP_FUNCTION(L1_E_src1_hazard_M, L1L1393, L1L1394, L1_E_src1_prelim[6]);
--L1_E_src2_imm[6] is std_1s10:inst|cpu:the_cpu|E_src2_imm[6] at LC_X19_Y8_N1
--operation mode is normal
L1_E_src2_imm[6] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[5], L1L235, L1_D_iw[12], L1_D_iw[2], E1_data_out, L1_W_stall);
--L1L1337 is std_1s10:inst|cpu:the_cpu|M_st_data[14]~COMBOUT at LC_X18_Y17_N1
--operation mode is normal
L1L1337 = AMPP_FUNCTION(L1_E_src2_prelim[6], L1_E_src2_hazard_M, L1L1395);
--L1_M_st_data[14] is std_1s10:inst|cpu:the_cpu|M_st_data[14] at LC_X18_Y17_N1
--operation mode is normal
L1_M_st_data[14] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[6], L1_E_src2_hazard_M, L1L815, L1L1395, E1_data_out, L1L845, L1_W_stall);
--L1L675 is std_1s10:inst|cpu:the_cpu|E_src2[6]~1514 at LC_X19_Y8_N8
--operation mode is normal
L1L675 = AMPP_FUNCTION(L1_E_src2_imm[6], L1_E_ctrl_src2_is_imm, L1L1337);
--L1L538 is std_1s10:inst|cpu:the_cpu|E_logic_result[6]~16136 at LC_X18_Y13_N6
--operation mode is normal
L1L538 = AMPP_FUNCTION(L1_E_logic_op[1], L1L609, L1_E_logic_op[0], L1L675);
--W1L1 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~99 at LC_X39_Y19_N2
--operation mode is arithmetic
W1L1 = W1_lcd_display_control_slave_wait_counter[1] $ !W1L5;
--W1L2 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~100 at LC_X39_Y19_N2
--operation mode is arithmetic
W1L2_cout_0 = !W1_lcd_display_control_slave_wait_counter[1] & !W1L5;
W1L2 = CARRY(W1L2_cout_0);
--W1L3 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~100COUT1_133 at LC_X39_Y19_N2
--operation mode is arithmetic
W1L3_cout_1 = !W1_lcd_display_control_slave_wait_counter[1] & !W1L6;
W1L3 = CARRY(W1L3_cout_1);
--W1L29 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_wait_counter[1]~60 at LC_X39_Y18_N5
--operation mode is normal
W1L29 = !W1_lcd_display_control_slave_wait_counter[2] & !W1_lcd_display_control_slave_wait_counter[1];
--W1L21 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Equal2~91 at LC_X39_Y18_N1
--operation mode is normal
W1L21 = !W1_lcd_display_control_slave_wait_counter[3] & W1L35 & W1L29 & !W1_lcd_display_control_slave_wait_counter[0];
--W1L25 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_in_a_write_cycle~37 at LC_X40_Y18_N4
--operation mode is normal
W1L25 = L1_M_alu_result[7] & !W1_d1_reasons_to_wait & G1L1 & L1_internal_d_write;
--W1L4 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~101 at LC_X39_Y19_N1
--operation mode is arithmetic
W1L4 = !W1_lcd_display_control_slave_wait_counter[0];
--W1L5 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~102 at LC_X39_Y19_N1
--operation mode is arithmetic
W1L5_cout_0 = W1_lcd_display_control_slave_wait_counter[0];
W1L5 = CARRY(W1L5_cout_0);
--W1L6 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~102COUT1_131 at LC_X39_Y19_N1
--operation mode is arithmetic
W1L6_cout_1 = W1_lcd_display_control_slave_wait_counter[0];
W1L6 = CARRY(W1L6_cout_1);
--W1L23 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|lcd_display_control_slave_counter_load_value~1 at LC_X40_Y18_N5
--operation mode is normal
W1L23 = W1_d1_reasons_to_wait # !G1L1 # !L1_internal_d_read # !L1_M_alu_result[7];
--W1L7 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~103 at LC_X39_Y19_N4
--operation mode is arithmetic
W1L7 = W1_lcd_display_control_slave_wait_counter[3] $ (!W1L12);
--W1L8 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~104 at LC_X39_Y19_N4
--operation mode is arithmetic
--W1L11 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~105 at LC_X39_Y19_N3
--operation mode is arithmetic
W1L11 = W1_lcd_display_control_slave_wait_counter[2] $ W1L2;
--W1L12 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~106 at LC_X39_Y19_N3
--operation mode is arithmetic
W1L12_cout_0 = W1_lcd_display_control_slave_wait_counter[2] # !W1L2;
W1L12 = CARRY(W1L12_cout_0);
--W1L13 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~106COUT1_135 at LC_X39_Y19_N3
--operation mode is arithmetic
W1L13_cout_1 = W1_lcd_display_control_slave_wait_counter[2] # !W1L3;
W1L13 = CARRY(W1L13_cout_1);
--W1L14 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~107 at LC_X39_Y19_N6
--operation mode is normal
W1L14_carry_eqn = (!W1L8 & W1L16) # (W1L8 & W1L17);
W1L14 = W1_lcd_display_control_slave_wait_counter[5] $ !W1L14_carry_eqn;
--W1L15 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~109 at LC_X39_Y19_N5
--operation mode is arithmetic
W1L15_carry_eqn = (!W1L8 & GND) # (W1L8 & VCC);
W1L15 = W1_lcd_display_control_slave_wait_counter[4] $ (W1L15_carry_eqn);
--W1L16 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~110 at LC_X39_Y19_N5
--operation mode is arithmetic
W1L16_cout_0 = W1_lcd_display_control_slave_wait_counter[4] # !W1L8;
W1L16 = CARRY(W1L16_cout_0);
--W1L17 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Add0~110COUT1_137 at LC_X39_Y19_N5
--operation mode is arithmetic
W1L17_cout_1 = W1_lcd_display_control_slave_wait_counter[4] # !W1L8;
W1L17 = CARRY(W1L17_cout_1);
--HC1_result[0] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[0] at LC_X18_Y12_N0
--operation mode is arithmetic
HC1_result[0] = AMPP_FUNCTION(L1L669, L1L603);
--HC1L3 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUT at LC_X18_Y12_N0
--operation mode is arithmetic
HC1L3 = AMPP_FUNCTION(L1L669, L1L603, L1_E_ctrl_alu_subtract);
--HC1L4 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUTCOUT1_147 at LC_X18_Y12_N0
--operation mode is arithmetic
HC1L4 = AMPP_FUNCTION(L1L669, L1L603, L1_E_ctrl_alu_subtract);
--HC1_result[1] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[1] at LC_X18_Y12_N1
--operation mode is arithmetic
HC1_result[1] = AMPP_FUNCTION(L1L670, L1L604, HC1L3, HC1L4, L1_E_ctrl_alu_subtract);
--HC1L6 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUT at LC_X18_Y12_N1
--operation mode is arithmetic
HC1L6 = AMPP_FUNCTION(L1L670, L1L604, HC1L3, L1_E_ctrl_alu_subtract);
--HC1L7 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUTCOUT1_149 at LC_X18_Y12_N1
--operation mode is arithmetic
HC1L7 = AMPP_FUNCTION(L1L670, L1L604, HC1L4, L1_E_ctrl_alu_subtract);
--HE1_control_reg[9] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[9] at LC_X50_Y9_N3
--operation mode is normal
HE1_control_reg[9]_lut_out = L1_M_st_data[9];
HE1_control_reg[9] = DFFEAS(HE1_control_reg[9]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L13, , , , );
--KE1_pre_txd is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd at LC_X50_Y9_N0
--operation mode is normal
KE1_pre_txd_lut_out = !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] & (KE1_pre_txd # !KE1L37);
KE1_pre_txd = DFFEAS(KE1_pre_txd_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L446 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_select_n_to_the_ext_flash~0 at LC_X41_Y16_N3
--operation mode is normal
Q1L446 = Q1L104 # Q1L76 & (Q1L18 # Q1L15);
--Q1L440 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[22]~3312 at LC_X40_Y17_N0
--operation mode is normal
Q1L440 = !Q1L106 & (!Q1L12 & !Q1L9 # !Q1L82);
--Q1L70 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_ext_flash_s1~55 at LC_X40_Y14_N7
--operation mode is normal
Q1L70 = Q1L76 & (Q1L18 # Q1L15);
--Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[3] at LC_X40_Y14_N7
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[3] = DFFEAS(Q1L70, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1L342, , , , );
--Q1L441 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[22]~3313 at LC_X35_Y14_N2
--operation mode is normal
Q1L441 = L1_ic_fill_tag[10] & !Q1L70 & (Q1L104 # !Q1L71);
--Q1L439 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[21]~3315 at LC_X35_Y11_N2
--operation mode is normal
Q1L439 = L1_ic_fill_tag[9] & !Q1L70 & (Q1L104 # !Q1L71);
--Q1L438 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[20]~3317 at LC_X35_Y12_N7
--operation mode is normal
Q1L438 = L1_ic_fill_tag[8] & !Q1L70 & (Q1L104 # !Q1L71);
--Q1L442 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[22]~3319 at LC_X35_Y14_N5
--operation mode is normal
Q1L442 = !Q1L70 & (Q1L104 # !Q1L71);
--Q1L437 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[15]~3324 at LC_X40_Y17_N1
--operation mode is normal
Q1L437 = Q1L106 # !Q1L70 & (Q1L104 # !Q1L71);
--L1_ic_fill_ap_offset[2] is std_1s10:inst|cpu:the_cpu|ic_fill_ap_offset[2] at LC_X36_Y10_N9
--operation mode is normal
L1_ic_fill_ap_offset[2] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[2], L1_ic_fill_ap_offset[2], L1L121, L1_D_ic_fill_starting, E1_data_out, N1L153);
--L1_ic_fill_ap_offset[1] is std_1s10:inst|cpu:the_cpu|ic_fill_ap_offset[1] at LC_X36_Y10_N8
--operation mode is normal
L1_ic_fill_ap_offset[1] = AMPP_FUNCTION(DE1__clk0, L1_D_ic_fill_starting, L1_D_pc[1], L1L122, L1_ic_fill_ap_offset[1], E1_data_out, N1L153);
--L1_ic_fill_ap_offset[0] is std_1s10:inst|cpu:the_cpu|ic_fill_ap_offset[0] at LC_X40_Y13_N1
--operation mode is normal
L1_ic_fill_ap_offset[0] = AMPP_FUNCTION(DE1__clk0, L1_D_ic_fill_starting, L1_D_pc[0], L1L1050, L1_ic_fill_ap_offset[0], E1_data_out, N1L153);
--Q1L435 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[1]~3339 at LC_X40_Y17_N8
--operation mode is normal
Q1L435 = !Q1L106 & (!Q1L24 & !Q1L21 # !N1L146);
--Q1L433 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[0]~3340 at LC_X40_Y17_N6
--operation mode is normal
Q1L433 = Q1L72 # Q1L71 & !Q1L70 & Q1L435;
--N1_internal_cpu_instruction_master_dbs_address[1] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1] at LC_X39_Y15_N3
--operation mode is normal
N1_internal_cpu_instruction_master_dbs_address[1]_lut_out = N1_internal_cpu_instruction_master_dbs_address[1] $ (N1L147 & N1_internal_cpu_instruction_master_dbs_address[0] & Q1L104);
N1_internal_cpu_instruction_master_dbs_address[1] = DFFEAS(N1_internal_cpu_instruction_master_dbs_address[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L436 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[1]~3341 at LC_X40_Y17_N7
--operation mode is normal
Q1L436 = Q1L70 & (M1_internal_cpu_data_master_dbs_address[1]) # !Q1L70 & N1_internal_cpu_instruction_master_dbs_address[1] & (Q1L104);
--N1_internal_cpu_instruction_master_dbs_address[0] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[0] at LC_X39_Y15_N7
--operation mode is normal
N1_internal_cpu_instruction_master_dbs_address[0]_lut_out = N1_internal_cpu_instruction_master_dbs_address[0] $ (Q1_d1_ext_ram_bus_avalon_slave_end_xfer & Q1L247 & Q1L104);
N1_internal_cpu_instruction_master_dbs_address[0] = DFFEAS(N1_internal_cpu_instruction_master_dbs_address[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L434 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[0]~3343 at LC_X40_Y17_N4
--operation mode is normal
Q1L434 = Q1L70 & (M1_internal_cpu_data_master_dbs_address[0]) # !Q1L70 & N1_internal_cpu_instruction_master_dbs_address[0] & (Q1L104);
--X1L11 is std_1s10:inst|led_pio:the_led_pio|process0~51 at LC_X48_Y10_N4
--operation mode is normal
X1L11 = !L1_M_alu_result[5] & (L1_M_alu_result[7]);
--HE1L14 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~98 at LC_X40_Y12_N8
--operation mode is normal
HE1L14 = !L1_M_alu_result[3] & !L1_M_alu_result[2];
--X1L12 is std_1s10:inst|led_pio:the_led_pio|process0~52 at LC_X40_Y12_N9
--operation mode is normal
X1L12 = !M1_internal_cpu_data_master_waitrequest & L1_internal_d_write & !L1_M_alu_result[6] & HE1L14;
--X1L10 is std_1s10:inst|led_pio:the_led_pio|process0~1 at LC_X40_Y12_N6
--operation mode is normal
X1L10 = X1L13 & X1L12 & !L1_M_alu_result[4] & L1_M_mem_byte_en[0];
--HB1L18 is std_1s10:inst|seven_seg_pio:the_seven_seg_pio|process0~1 at LC_X40_Y12_N2
--operation mode is normal
HB1L18 = L1_M_alu_result[4] & (X1L13 & X1L12);
--L1L1327 is std_1s10:inst|cpu:the_cpu|M_st_data[9]~COMBOUT at LC_X19_Y20_N2
--operation mode is normal
L1L1327 = AMPP_FUNCTION(L1_E_src2_prelim[1], L1_E_src2_hazard_M, L1L1380);
--L1_M_st_data[9] is std_1s10:inst|cpu:the_cpu|M_st_data[9] at LC_X19_Y20_N2
--operation mode is normal
L1_M_st_data[9] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[1], L1_E_src2_hazard_M, L1L810, L1L1380, E1_data_out, L1L845, L1_W_stall);
--L1L1325 is std_1s10:inst|cpu:the_cpu|M_st_data[8]~COMBOUT at LC_X19_Y20_N7
--operation mode is normal
L1L1325 = AMPP_FUNCTION(L1_E_src2_prelim[0], L1_E_src2_hazard_M, L1L1377);
--L1_M_st_data[8] is std_1s10:inst|cpu:the_cpu|M_st_data[8] at LC_X19_Y20_N7
--operation mode is normal
L1_M_st_data[8] = AMPP_FUNCTION(DE1__clk0, L1_E_src2_prelim[0], L1_E_src2_hazard_M, L1L809, L1L1377, E1_data_out, L1L845, L1_W_stall);
--FB1L595 is std_1s10:inst|sdram:the_sdram|Mux104~1566 at LC_X36_Y5_N7
--operation mode is normal
FB1L595 = !FB1_m_state[6] & !FB1_m_state[3] & !FB1_m_state[4] & FB1_m_state[0];
--FB1_i_addr[0] is std_1s10:inst|sdram:the_sdram|i_addr[0] at LC_X40_Y1_N2
--operation mode is normal
FB1_i_addr[0]_lut_out = FB1_i_state[1] & FB1_i_state[0] & FB1_i_state[2];
FB1_i_addr[0] = DFFEAS(FB1_i_addr[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L596 is std_1s10:inst|sdram:the_sdram|Mux104~1567 at LC_X39_Y4_N1
--operation mode is normal
FB1L596 = FB1L518 & (FB1_init_done & FB1L205Q # !FB1_init_done & (!FB1_i_addr[0])) # !FB1L518 & FB1L205Q;
--FB1L597 is std_1s10:inst|sdram:the_sdram|Mux104~1568 at LC_X39_Y4_N8
--operation mode is normal
FB1L597 = FB1L205Q & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L598 is std_1s10:inst|sdram:the_sdram|Mux104~1569 at LC_X39_Y4_N9
--operation mode is normal
FB1L598 = FB1_m_state[6] & !FB1_m_state[0] # !FB1_m_state[6] & (FB1_m_state[0] & (FB1L597) # !FB1_m_state[0] & FB1L596);
--FB1L599 is std_1s10:inst|sdram:the_sdram|Mux104~1570 at LC_X39_Y2_N9
--operation mode is normal
FB1L599 = FB1_m_state[6] & (FB1L205Q # !FB1L598 & FB1L518) # !FB1_m_state[6] & FB1L598;
--FB1L600 is std_1s10:inst|sdram:the_sdram|Mux104~1571 at LC_X39_Y2_N7
--operation mode is normal
FB1L600 = FB1_m_state[1] & FB1L595 & FB1_active_addr[20] # !FB1_m_state[1] & (FB1L599);
--FB1L601 is std_1s10:inst|sdram:the_sdram|Mux104~1572 at LC_X39_Y2_N1
--operation mode is normal
FB1L601 = FB1_m_state[1] & !FB1L595;
--FB1L602 is std_1s10:inst|sdram:the_sdram|Mux104~1573 at LC_X33_Y2_N5
--operation mode is normal
FB1L602 = FB1_m_state[8] # FB1_m_state[5] # FB1_m_state[7] # FB1_m_state[2];
--FB1L603 is std_1s10:inst|sdram:the_sdram|Mux105~1395 at LC_X36_Y2_N6
--operation mode is normal
FB1L603 = FB1_init_done & (FB1L201Q) # !FB1_init_done & (FB1L518 & !FB1_i_addr[0] # !FB1L518 & (FB1L201Q));
--FB1L604 is std_1s10:inst|sdram:the_sdram|Mux105~1396 at LC_X36_Y2_N9
--operation mode is normal
FB1L604 = FB1L201Q & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L605 is std_1s10:inst|sdram:the_sdram|Mux105~1397 at LC_X36_Y2_N7
--operation mode is normal
FB1L605 = FB1_m_state[0] & FB1L604 & !FB1_m_state[6] # !FB1_m_state[0] & (FB1_m_state[6] # FB1L603);
--FB1L606 is std_1s10:inst|sdram:the_sdram|Mux105~1398 at LC_X36_Y2_N8
--operation mode is normal
FB1L606 = FB1_m_state[6] & (FB1L201Q # !FB1L605 & FB1L518) # !FB1_m_state[6] & FB1L605;
--FB1L607 is std_1s10:inst|sdram:the_sdram|Mux105~1399 at LC_X39_Y2_N4
--operation mode is normal
FB1L607 = FB1_m_state[1] & (FB1_active_addr[19] & FB1L595) # !FB1_m_state[1] & FB1L606;
--FB1L608 is std_1s10:inst|sdram:the_sdram|Mux106~1395 at LC_X39_Y4_N7
--operation mode is normal
FB1L608 = FB1L518 & (FB1_init_done & FB1L197Q # !FB1_init_done & (!FB1_i_addr[0])) # !FB1L518 & FB1L197Q;
--FB1L609 is std_1s10:inst|sdram:the_sdram|Mux106~1396 at LC_X39_Y4_N4
--operation mode is normal
FB1L609 = FB1L197Q & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L610 is std_1s10:inst|sdram:the_sdram|Mux106~1397 at LC_X39_Y4_N5
--operation mode is normal
FB1L610 = FB1_m_state[6] & !FB1_m_state[0] # !FB1_m_state[6] & (FB1_m_state[0] & (FB1L609) # !FB1_m_state[0] & FB1L608);
--FB1L611 is std_1s10:inst|sdram:the_sdram|Mux106~1398 at LC_X39_Y4_N0
--operation mode is normal
FB1L611 = FB1_m_state[6] & (FB1L197Q # !FB1L610 & FB1L518) # !FB1_m_state[6] & (FB1L610);
--FB1L612 is std_1s10:inst|sdram:the_sdram|Mux106~1399 at LC_X39_Y4_N2
--operation mode is normal
FB1L612 = FB1_m_state[1] & FB1_active_addr[18] & FB1L595 # !FB1_m_state[1] & (FB1L611);
--FB1L613 is std_1s10:inst|sdram:the_sdram|Mux107~1395 at LC_X36_Y2_N1
--operation mode is normal
FB1L613 = FB1_init_done & (FB1L193Q) # !FB1_init_done & (FB1L518 & !FB1_i_addr[0] # !FB1L518 & (FB1L193Q));
--FB1L614 is std_1s10:inst|sdram:the_sdram|Mux107~1396 at LC_X36_Y2_N2
--operation mode is normal
FB1L614 = FB1L193Q & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L615 is std_1s10:inst|sdram:the_sdram|Mux107~1397 at LC_X36_Y2_N3
--operation mode is normal
FB1L615 = FB1_m_state[0] & (!FB1_m_state[6] & FB1L614) # !FB1_m_state[0] & (FB1L613 # FB1_m_state[6]);
--FB1L616 is std_1s10:inst|sdram:the_sdram|Mux107~1398 at LC_X39_Y2_N8
--operation mode is normal
FB1L616 = FB1_m_state[6] & (FB1L193Q # !FB1L615 & FB1L518) # !FB1_m_state[6] & FB1L615;
--FB1L617 is std_1s10:inst|sdram:the_sdram|Mux107~1399 at LC_X39_Y2_N3
--operation mode is normal
FB1L617 = FB1_m_state[1] & (FB1_active_addr[17] & FB1L595) # !FB1_m_state[1] & FB1L616;
--FB1L618 is std_1s10:inst|sdram:the_sdram|Mux108~1481 at LC_X33_Y3_N0
--operation mode is normal
FB1L618 = !FB1_m_state[1] & !FB1_m_state[3] & FB1_m_state[0] & !FB1_m_state[4];
--FB1L619 is std_1s10:inst|sdram:the_sdram|Mux108~1482 at LC_X33_Y6_N2
--operation mode is normal
FB1L619 = FB1_m_state[3] & (FB1L189Q) # !FB1_m_state[3] & (FB1_m_state[4] & (FB1L189Q) # !FB1_m_state[4] & FB1_active_addr[16]);
--FB1L620 is std_1s10:inst|sdram:the_sdram|Mux108~1483 at LC_X33_Y6_N8
--operation mode is normal
FB1L620 = FB1_init_done & FB1L189Q # !FB1_init_done & (FB1L518 & (!FB1_i_addr[0]) # !FB1L518 & FB1L189Q);
--EE1L172 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[43]~495 at LC_X34_Y9_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[43]_qfbk = EE1_entry_1[43];
EE1L172 = EE1_rd_address & EE1_entry_1[43]_qfbk # !EE1_rd_address & (EE1_entry_0[43]);
--EE1_entry_1[43] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[43] at LC_X34_Y9_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[43] = DFFEAS(EE1L172, GLOBAL(DE1__clk0), VCC, , EE1L123, GB1L43, , , VCC);
--FB1_active_addr[7] is std_1s10:inst|sdram:the_sdram|active_addr[7] at LC_X33_Y6_N6
--operation mode is normal
FB1_active_addr[7]_lut_out = FB1L14 & (FB1L12 & (EE1L172) # !FB1L12 & FB1_active_addr[7]) # !FB1L14 & FB1_active_addr[7];
FB1_active_addr[7] = DFFEAS(FB1_active_addr[7]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L621 is std_1s10:inst|sdram:the_sdram|Mux108~1484 at LC_X33_Y6_N4
--operation mode is normal
FB1L621 = FB1L434 & (FB1_f_select & EE1L172 # !FB1_f_select & (FB1_active_addr[7]));
--FB1L622 is std_1s10:inst|sdram:the_sdram|Mux108~1485 at LC_X33_Y6_N9
--operation mode is normal
FB1L622 = FB1_m_state[1] & (!FB1_m_state[0]) # !FB1_m_state[1] & (FB1_m_state[0] & FB1L625 # !FB1_m_state[0] & (FB1L620));
--FB1L623 is std_1s10:inst|sdram:the_sdram|Mux108~1486 at LC_X33_Y6_N5
--operation mode is normal
FB1L623 = FB1_m_state[1] & (FB1L622 & (FB1L189Q) # !FB1L622 & FB1L619) # !FB1_m_state[1] & (FB1L622);
--FB1L624 is std_1s10:inst|sdram:the_sdram|Mux108~1487 at LC_X33_Y6_N3
--operation mode is normal
FB1L624 = FB1_m_state[6] & (FB1L618) # !FB1_m_state[6] & FB1L623;
--FB1L626 is std_1s10:inst|sdram:the_sdram|Mux109~1348 at LC_X33_Y6_N1
--operation mode is normal
FB1L626 = FB1L602 & (FB1L185Q) # !FB1L602 & FB1_m_state[6] & (FB1L618 # FB1L185Q);
--FB1L627 is std_1s10:inst|sdram:the_sdram|Mux109~1349 at LC_X34_Y6_N1
--operation mode is normal
FB1L627 = FB1_m_state[4] & (FB1L185Q) # !FB1_m_state[4] & (FB1_m_state[3] & (FB1L185Q) # !FB1_m_state[3] & FB1_active_addr[15]);
--FB1L628 is std_1s10:inst|sdram:the_sdram|Mux109~1350 at LC_X34_Y6_N3
--operation mode is normal
FB1L628 = FB1L518 & (FB1_init_done & FB1L185Q # !FB1_init_done & (!FB1_i_addr[0])) # !FB1L518 & FB1L185Q;
--EE1L171 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[42]~496 at LC_X35_Y6_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[42]_qfbk = EE1_entry_1[42];
EE1L171 = EE1_rd_address & EE1_entry_1[42]_qfbk # !EE1_rd_address & (EE1_entry_0[42]);
--EE1_entry_1[42] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[42] at LC_X35_Y6_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[42] = DFFEAS(EE1L171, GLOBAL(DE1__clk0), VCC, , EE1L123, GB1L42, , , VCC);
--FB1_active_addr[6] is std_1s10:inst|sdram:the_sdram|active_addr[6] at LC_X35_Y6_N4
--operation mode is normal
FB1_active_addr[6]_lut_out = FB1L14 & (FB1L12 & EE1L171 # !FB1L12 & (FB1_active_addr[6])) # !FB1L14 & (FB1_active_addr[6]);
FB1_active_addr[6] = DFFEAS(FB1_active_addr[6]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L629 is std_1s10:inst|sdram:the_sdram|Mux109~1351 at LC_X35_Y6_N9
--operation mode is normal
FB1L629 = FB1L434 & (FB1_f_select & EE1L171 # !FB1_f_select & (FB1_active_addr[6]));
--FB1L630 is std_1s10:inst|sdram:the_sdram|Mux109~1352 at LC_X34_Y6_N6
--operation mode is normal
FB1L630 = FB1_m_state[1] & !FB1_m_state[0] # !FB1_m_state[1] & (FB1_m_state[0] & (FB1L632) # !FB1_m_state[0] & FB1L628);
--FB1L631 is std_1s10:inst|sdram:the_sdram|Mux109~1353 at LC_X34_Y6_N4
--operation mode is normal
FB1L631 = FB1_m_state[1] & (FB1L630 & (FB1L185Q) # !FB1L630 & FB1L627) # !FB1_m_state[1] & (FB1L630);
--FB1L633 is std_1s10:inst|sdram:the_sdram|Mux110~1388 at LC_X34_Y3_N8
--operation mode is normal
FB1L633 = FB1L602 & (FB1L181Q) # !FB1L602 & FB1_m_state[6] & (FB1L618 # FB1L181Q);
--FB1L634 is std_1s10:inst|sdram:the_sdram|Mux110~1389 at LC_X34_Y3_N3
--operation mode is normal
FB1L634 = FB1_m_state[3] & (FB1L181Q) # !FB1_m_state[3] & (FB1_m_state[4] & (FB1L181Q) # !FB1_m_state[4] & FB1_active_addr[14]);
--FB1L635 is std_1s10:inst|sdram:the_sdram|Mux110~1390 at LC_X34_Y3_N6
--operation mode is normal
FB1L635 = FB1L181Q # !FB1_m_state[3] & !FB1_init_done & !FB1_m_state[4];
--EE1L170 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[41]~497 at LC_X34_Y9_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[41]_qfbk = EE1_entry_1[41];
EE1L170 = EE1_rd_address & EE1_entry_1[41]_qfbk # !EE1_rd_address & (EE1_entry_0[41]);
--EE1_entry_1[41] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[41] at LC_X34_Y9_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[41] = DFFEAS(EE1L170, GLOBAL(DE1__clk0), VCC, , EE1L123, GB1L41, , , VCC);
--FB1_active_addr[5] is std_1s10:inst|sdram:the_sdram|active_addr[5] at LC_X34_Y3_N0
--operation mode is normal
FB1_active_addr[5]_lut_out = FB1L12 & (FB1L14 & EE1L170 # !FB1L14 & (FB1_active_addr[5])) # !FB1L12 & (FB1_active_addr[5]);
FB1_active_addr[5] = DFFEAS(FB1_active_addr[5]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L636 is std_1s10:inst|sdram:the_sdram|Mux110~1391 at LC_X34_Y3_N1
--operation mode is normal
FB1L636 = FB1L434 & (FB1_f_select & EE1L170 # !FB1_f_select & (FB1_active_addr[5]));
--FB1L637 is std_1s10:inst|sdram:the_sdram|Mux110~1392 at LC_X34_Y3_N2
--operation mode is normal
FB1L637 = FB1_m_state[0] & !FB1_m_state[1] & FB1L639 # !FB1_m_state[0] & (FB1_m_state[1] # FB1L635);
--FB1L638 is std_1s10:inst|sdram:the_sdram|Mux110~1393 at LC_X34_Y3_N4
--operation mode is normal
FB1L638 = FB1L637 & (FB1L181Q # !FB1_m_state[1]) # !FB1L637 & FB1_m_state[1] & FB1L634;
--FB1L640 is std_1s10:inst|sdram:the_sdram|Mux111~1315 at LC_X34_Y3_N7
--operation mode is normal
FB1L640 = FB1L602 & (FB1L177Q) # !FB1L602 & FB1_m_state[6] & (FB1L618 # FB1L177Q);
--FB1L641 is std_1s10:inst|sdram:the_sdram|Mux111~1316 at LC_X34_Y5_N2
--operation mode is normal
FB1L641 = FB1_m_state[3] & (FB1L177Q) # !FB1_m_state[3] & (FB1_m_state[4] & (FB1L177Q) # !FB1_m_state[4] & FB1_active_addr[13]);
--FB1L642 is std_1s10:inst|sdram:the_sdram|Mux111~1317 at LC_X34_Y5_N6
--operation mode is normal
FB1L642 = FB1L177Q # !FB1_m_state[3] & !FB1_init_done & !FB1_m_state[4];
--EE1L169 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[40]~498 at LC_X34_Y9_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[40]_qfbk = EE1_entry_1[40];
EE1L169 = EE1_rd_address & EE1_entry_1[40]_qfbk # !EE1_rd_address & (EE1_entry_0[40]);
--EE1_entry_1[40] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[40] at LC_X34_Y9_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[40] = DFFEAS(EE1L169, GLOBAL(DE1__clk0), VCC, , EE1L123, GB1L40, , , VCC);
--FB1_active_addr[4] is std_1s10:inst|sdram:the_sdram|active_addr[4] at LC_X34_Y5_N0
--operation mode is normal
FB1_active_addr[4]_lut_out = FB1L14 & (FB1L12 & EE1L169 # !FB1L12 & (FB1_active_addr[4])) # !FB1L14 & (FB1_active_addr[4]);
FB1_active_addr[4] = DFFEAS(FB1_active_addr[4]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L643 is std_1s10:inst|sdram:the_sdram|Mux111~1318 at LC_X34_Y5_N3
--operation mode is normal
FB1L643 = FB1L434 & (FB1_f_select & EE1L169 # !FB1_f_select & (FB1_active_addr[4]));
--FB1L644 is std_1s10:inst|sdram:the_sdram|Mux111~1319 at LC_X34_Y5_N4
--operation mode is normal
FB1L644 = FB1_m_state[0] & !FB1_m_state[1] & FB1L646 # !FB1_m_state[0] & (FB1_m_state[1] # FB1L642);
--FB1L645 is std_1s10:inst|sdram:the_sdram|Mux111~1320 at LC_X34_Y5_N8
--operation mode is normal
FB1L645 = FB1_m_state[1] & (FB1L644 & (FB1L177Q) # !FB1L644 & FB1L641) # !FB1_m_state[1] & (FB1L644);
--FB1L647 is std_1s10:inst|sdram:the_sdram|Mux112~1347 at LC_X33_Y5_N3
--operation mode is normal
FB1L647 = FB1L602 & (FB1L173Q) # !FB1L602 & FB1_m_state[6] & (FB1L618 # FB1L173Q);
--FB1L648 is std_1s10:inst|sdram:the_sdram|Mux112~1348 at LC_X34_Y8_N1
--operation mode is normal
FB1L648 = FB1_m_state[3] & (FB1L173Q) # !FB1_m_state[3] & (FB1_m_state[4] & FB1L173Q # !FB1_m_state[4] & (FB1_active_addr[12]));
--FB1L649 is std_1s10:inst|sdram:the_sdram|Mux112~1349 at LC_X34_Y8_N6
--operation mode is normal
FB1L649 = FB1L518 & (FB1_init_done & FB1L173Q # !FB1_init_done & (!FB1_i_addr[0])) # !FB1L518 & (FB1L173Q);
--EE1L168 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[39]~499 at LC_X35_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[39]_qfbk = EE1_entry_1[39];
EE1L168 = EE1_rd_address & EE1_entry_1[39]_qfbk # !EE1_rd_address & (EE1_entry_0[39]);
--EE1_entry_1[39] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[39] at LC_X35_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[39] = DFFEAS(EE1L168, GLOBAL(DE1__clk0), VCC, , EE1L123, GB1L39, , , VCC);
--FB1_active_addr[3] is std_1s10:inst|sdram:the_sdram|active_addr[3] at LC_X35_Y6_N0
--operation mode is normal
FB1_active_addr[3]_lut_out = FB1L12 & (FB1L14 & EE1L168 # !FB1L14 & (FB1_active_addr[3])) # !FB1L12 & (FB1_active_addr[3]);
FB1_active_addr[3] = DFFEAS(FB1_active_addr[3]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L650 is std_1s10:inst|sdram:the_sdram|Mux112~1350 at LC_X35_Y6_N3
--operation mode is normal
FB1L650 = FB1L434 & (FB1_f_select & EE1L168 # !FB1_f_select & (FB1_active_addr[3]));
--FB1L651 is std_1s10:inst|sdram:the_sdram|Mux112~1351 at LC_X34_Y8_N8
--operation mode is normal
FB1L651 = FB1_m_state[1] & (!FB1_m_state[0]) # !FB1_m_state[1] & (FB1_m_state[0] & (FB1L653) # !FB1_m_state[0] & FB1L649);
--FB1L652 is std_1s10:inst|sdram:the_sdram|Mux112~1352 at LC_X34_Y8_N2
--operation mode is normal
FB1L652 = FB1_m_state[1] & (FB1L651 & FB1L173Q # !FB1L651 & (FB1L648)) # !FB1_m_state[1] & (FB1L651);
--FB1L654 is std_1s10:inst|sdram:the_sdram|Mux113~1347 at LC_X33_Y5_N1
--operation mode is normal
FB1L654 = FB1L602 & (FB1L169Q) # !FB1L602 & FB1_m_state[6] & (FB1L618 # FB1L169Q);
--FB1L655 is std_1s10:inst|sdram:the_sdram|Mux113~1348 at LC_X33_Y5_N2
--operation mode is normal
FB1L655 = FB1_m_state[4] & FB1L169Q # !FB1_m_state[4] & (FB1_m_state[3] & FB1L169Q # !FB1_m_state[3] & (FB1_active_addr[11]));
--FB1L656 is std_1s10:inst|sdram:the_sdram|Mux113~1349 at LC_X33_Y5_N4
--operation mode is normal
FB1L656 = FB1_init_done & FB1L169Q # !FB1_init_done & (FB1L518 & (!FB1_i_addr[0]) # !FB1L518 & FB1L169Q);
--EE1L167 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[38]~500 at LC_X34_Y9_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[38]_qfbk = EE1_entry_1[38];
EE1L167 = EE1_rd_address & EE1_entry_1[38]_qfbk # !EE1_rd_address & (EE1_entry_0[38]);
--EE1_entry_1[38] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[38] at LC_X34_Y9_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[38] = DFFEAS(EE1L167, GLOBAL(DE1__clk0), VCC, , EE1L123, GB1L38, , , VCC);
--FB1_active_addr[2] is std_1s10:inst|sdram:the_sdram|active_addr[2] at LC_X39_Y5_N7
--operation mode is normal
FB1_active_addr[2]_lut_out = FB1L14 & (FB1L12 & (EE1L167) # !FB1L12 & FB1_active_addr[2]) # !FB1L14 & FB1_active_addr[2];
FB1_active_addr[2] = DFFEAS(FB1_active_addr[2]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L657 is std_1s10:inst|sdram:the_sdram|Mux113~1350 at LC_X33_Y5_N7
--operation mode is normal
FB1L657 = FB1L434 & (FB1_f_select & (EE1L167) # !FB1_f_select & FB1_active_addr[2]);
--FB1L658 is std_1s10:inst|sdram:the_sdram|Mux113~1351 at LC_X33_Y5_N5
--operation mode is normal
FB1L658 = FB1_m_state[0] & (!FB1_m_state[1] & FB1L660) # !FB1_m_state[0] & (FB1L656 # FB1_m_state[1]);
--FB1L659 is std_1s10:inst|sdram:the_sdram|Mux113~1352 at LC_X33_Y5_N6
--operation mode is normal
FB1L659 = FB1L658 & (FB1L169Q # !FB1_m_state[1]) # !FB1L658 & FB1L655 & FB1_m_state[1];
--FB1L661 is std_1s10:inst|sdram:the_sdram|Mux114~1347 at LC_X35_Y5_N3
--operation mode is normal
FB1L661 = FB1L602 & (FB1L165Q) # !FB1L602 & FB1_m_state[6] & (FB1L618 # FB1L165Q);
--FB1L662 is std_1s10:inst|sdram:the_sdram|Mux114~1348 at LC_X35_Y5_N2
--operation mode is normal
FB1L662 = FB1_m_state[3] & (FB1L165Q) # !FB1_m_state[3] & (FB1_m_state[4] & (FB1L165Q) # !FB1_m_state[4] & FB1_active_addr[10]);
--FB1L663 is std_1s10:inst|sdram:the_sdram|Mux114~1349 at LC_X35_Y5_N4
--operation mode is normal
FB1L663 = FB1L518 & (FB1_init_done & (FB1L165Q) # !FB1_init_done & !FB1_i_addr[0]) # !FB1L518 & (FB1L165Q);
--EE1L166 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[37]~501 at LC_X39_Y7_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[37]_qfbk = EE1_entry_1[37];
EE1L166 = EE1_rd_address & EE1_entry_1[37]_qfbk # !EE1_rd_address & (EE1_entry_0[37]);
--EE1_entry_1[37] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[37] at LC_X39_Y7_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[37] = DFFEAS(EE1L166, GLOBAL(DE1__clk0), VCC, , EE1L123, GB1L37, , , VCC);
--FB1_active_addr[1] is std_1s10:inst|sdram:the_sdram|active_addr[1] at LC_X35_Y5_N0
--operation mode is normal
FB1_active_addr[1]_lut_out = FB1L14 & (FB1L12 & EE1L166 # !FB1L12 & (FB1_active_addr[1])) # !FB1L14 & (FB1_active_addr[1]);
FB1_active_addr[1] = DFFEAS(FB1_active_addr[1]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L664 is std_1s10:inst|sdram:the_sdram|Mux114~1350 at LC_X35_Y5_N8
--operation mode is normal
FB1L664 = FB1L434 & (FB1_f_select & EE1L166 # !FB1_f_select & (FB1_active_addr[1]));
--FB1L665 is std_1s10:inst|sdram:the_sdram|Mux114~1351 at LC_X35_Y5_N5
--operation mode is normal
FB1L665 = FB1_m_state[1] & !FB1_m_state[0] # !FB1_m_state[1] & (FB1_m_state[0] & FB1L667 # !FB1_m_state[0] & (FB1L663));
--FB1L666 is std_1s10:inst|sdram:the_sdram|Mux114~1352 at LC_X35_Y5_N6
--operation mode is normal
FB1L666 = FB1L665 & (FB1L165Q # !FB1_m_state[1]) # !FB1L665 & FB1L662 & (FB1_m_state[1]);
--FB1L668 is std_1s10:inst|sdram:the_sdram|Mux115~1347 at LC_X35_Y5_N1
--operation mode is normal
FB1L668 = FB1L602 & (FB1L161Q) # !FB1L602 & FB1_m_state[6] & (FB1L618 # FB1L161Q);
--FB1L669 is std_1s10:inst|sdram:the_sdram|Mux115~1348 at LC_X36_Y5_N5
--operation mode is normal
FB1L669 = FB1_m_state[3] & (FB1L161Q) # !FB1_m_state[3] & (FB1_m_state[4] & (FB1L161Q) # !FB1_m_state[4] & FB1_active_addr[9]);
--FB1L670 is std_1s10:inst|sdram:the_sdram|Mux115~1349 at LC_X36_Y5_N4
--operation mode is normal
FB1L670 = FB1_init_done & (FB1L161Q) # !FB1_init_done & (FB1L518 & !FB1_i_addr[0] # !FB1L518 & (FB1L161Q));
--EE1L165 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[36]~502 at LC_X36_Y5_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[36]_qfbk = EE1_entry_1[36];
EE1L165 = EE1_rd_address & (EE1_entry_1[36]_qfbk) # !EE1_rd_address & EE1_entry_0[36];
--EE1_entry_1[36] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[36] at LC_X36_Y5_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[36] = DFFEAS(EE1L165, GLOBAL(DE1__clk0), VCC, , EE1L123, GB1L36, , , VCC);
--FB1_active_addr[0] is std_1s10:inst|sdram:the_sdram|active_addr[0] at LC_X36_Y5_N8
--operation mode is normal
FB1_active_addr[0]_lut_out = FB1L14 & (FB1L12 & (EE1L165) # !FB1L12 & FB1_active_addr[0]) # !FB1L14 & FB1_active_addr[0];
FB1_active_addr[0] = DFFEAS(FB1_active_addr[0]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1L671 is std_1s10:inst|sdram:the_sdram|Mux115~1350 at LC_X36_Y5_N9
--operation mode is normal
FB1L671 = FB1L434 & (FB1_f_select & EE1L165 # !FB1_f_select & (FB1_active_addr[0]));
--FB1L672 is std_1s10:inst|sdram:the_sdram|Mux115~1351 at LC_X36_Y5_N3
--operation mode is normal
FB1L672 = FB1_m_state[1] & (!FB1_m_state[0]) # !FB1_m_state[1] & (FB1_m_state[0] & (FB1L674) # !FB1_m_state[0] & FB1L670);
--FB1L673 is std_1s10:inst|sdram:the_sdram|Mux115~1352 at LC_X36_Y5_N0
--operation mode is normal
FB1L673 = FB1L672 & (FB1L161Q # !FB1_m_state[1]) # !FB1L672 & FB1L669 & FB1_m_state[1];
--EE1L174 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[57]~503 at LC_X35_Y9_N5
--operation mode is normal
EE1L174 = EE1_rd_address & (EE1_entry_1[57]) # !EE1_rd_address & EE1_entry_0[57];
--FB1L675 is std_1s10:inst|sdram:the_sdram|Mux116~1300 at LC_X39_Y3_N3
--operation mode is normal
FB1L675 = FB1_m_state[1] & FB1_active_addr[21] # !FB1_m_state[1] & (FB1_f_select & (EE1L174) # !FB1_f_select & FB1_active_addr[21]);
--FB1L676 is std_1s10:inst|sdram:the_sdram|Mux116~1301 at LC_X32_Y3_N2
--operation mode is normal
FB1L676 = FB1_m_state[1] & !FB1_m_state[3] & !FB1_m_state[4] # !FB1_m_state[1] & (FB1_m_state[3] $ FB1_m_state[4]);
--FB1L448 is std_1s10:inst|sdram:the_sdram|Mux24~1458 at LC_X35_Y3_N8
--operation mode is normal
FB1L448 = FB1_m_state[0] & (!FB1_m_state[2] & !FB1_m_state[7]);
--FB1L480 is std_1s10:inst|sdram:the_sdram|Mux29~1320 at LC_X35_Y1_N2
--operation mode is normal
FB1L480 = !FB1_m_state[5] & !FB1_m_state[6];
--EE1L173 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[44]~504 at LC_X35_Y7_N9
--operation mode is normal
EE1L173 = EE1_rd_address & (EE1_entry_1[44]) # !EE1_rd_address & EE1_entry_0[44];
--FB1L677 is std_1s10:inst|sdram:the_sdram|Mux117~1184 at LC_X35_Y6_N1
--operation mode is normal
FB1L677 = FB1_m_state[1] & (FB1_active_addr[8]) # !FB1_m_state[1] & (FB1_f_select & EE1L173 # !FB1_f_select & (FB1_active_addr[8]));
--FB1_active_dqm[3] is std_1s10:inst|sdram:the_sdram|active_dqm[3] at LC_X39_Y3_N6
--operation mode is normal
FB1_active_dqm[3]_lut_out = FB1L14 & (FB1L12 & EE1L164 # !FB1L12 & (FB1_active_dqm[3])) # !FB1L14 & (FB1_active_dqm[3]);
FB1_active_dqm[3] = DFFEAS(FB1_active_dqm[3]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1L164 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[35]~505 at LC_X35_Y10_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[35]_qfbk = EE1_entry_1[35];
EE1L164 = EE1_rd_address & EE1_entry_1[35]_qfbk # !EE1_rd_address & (EE1_entry_0[35]);
--EE1_entry_1[35] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[35] at LC_X35_Y10_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[35] = DFFEAS(EE1L164, GLOBAL(DE1__clk0), VCC, , EE1L123, FB1L406, , , VCC);
--FB1L713 is std_1s10:inst|sdram:the_sdram|Mux150~1184 at LC_X39_Y3_N1
--operation mode is normal
FB1L713 = FB1_m_state[1] & (FB1_active_dqm[3]) # !FB1_m_state[1] & (FB1_f_select & EE1L164 # !FB1_f_select & (FB1_active_dqm[3]));
--FB1_active_dqm[2] is std_1s10:inst|sdram:the_sdram|active_dqm[2] at LC_X39_Y3_N7
--operation mode is normal
FB1_active_dqm[2]_lut_out = FB1L14 & (FB1L12 & (EE1L163) # !FB1L12 & FB1_active_dqm[2]) # !FB1L14 & (FB1_active_dqm[2]);
FB1_active_dqm[2] = DFFEAS(FB1_active_dqm[2]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1L163 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[34]~506 at LC_X35_Y10_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[34]_qfbk = EE1_entry_1[34];
EE1L163 = EE1_rd_address & EE1_entry_1[34]_qfbk # !EE1_rd_address & (EE1_entry_0[34]);
--EE1_entry_1[34] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[34] at LC_X35_Y10_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[34] = DFFEAS(EE1L163, GLOBAL(DE1__clk0), VCC, , EE1L123, FB1L405, , , VCC);
--FB1L714 is std_1s10:inst|sdram:the_sdram|Mux151~1184 at LC_X39_Y3_N4
--operation mode is normal
FB1L714 = FB1_m_state[1] & (FB1_active_dqm[2]) # !FB1_m_state[1] & (FB1_f_select & EE1L163 # !FB1_f_select & (FB1_active_dqm[2]));
--FB1_active_dqm[1] is std_1s10:inst|sdram:the_sdram|active_dqm[1] at LC_X39_Y5_N5
--operation mode is normal
FB1_active_dqm[1]_lut_out = FB1L14 & (FB1L12 & EE1L162 # !FB1L12 & (FB1_active_dqm[1])) # !FB1L14 & (FB1_active_dqm[1]);
FB1_active_dqm[1] = DFFEAS(FB1_active_dqm[1]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1L162 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[33]~507 at LC_X39_Y7_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[33]_qfbk = EE1_entry_1[33];
EE1L162 = EE1_rd_address & EE1_entry_1[33]_qfbk # !EE1_rd_address & (EE1_entry_0[33]);
--EE1_entry_1[33] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[33] at LC_X39_Y7_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[33] = DFFEAS(EE1L162, GLOBAL(DE1__clk0), VCC, , EE1L123, FB1L404, , , VCC);
--FB1L715 is std_1s10:inst|sdram:the_sdram|Mux152~1184 at LC_X39_Y7_N1
--operation mode is normal
FB1L715 = FB1_m_state[1] & FB1_active_dqm[1] # !FB1_m_state[1] & (FB1_f_select & (EE1L162) # !FB1_f_select & FB1_active_dqm[1]);
--FB1_active_dqm[0] is std_1s10:inst|sdram:the_sdram|active_dqm[0] at LC_X39_Y5_N2
--operation mode is normal
FB1_active_dqm[0]_lut_out = FB1L14 & (FB1L12 & (EE1L161) # !FB1L12 & FB1_active_dqm[0]) # !FB1L14 & FB1_active_dqm[0];
FB1_active_dqm[0] = DFFEAS(FB1_active_dqm[0]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1L161 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[32]~508 at LC_X39_Y7_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[32]_qfbk = EE1_entry_1[32];
EE1L161 = EE1_rd_address & EE1_entry_1[32]_qfbk # !EE1_rd_address & (EE1_entry_0[32]);
--EE1_entry_1[32] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[32] at LC_X39_Y7_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[32] = DFFEAS(EE1L161, GLOBAL(DE1__clk0), VCC, , EE1L123, FB1L403, , , VCC);
--FB1L716 is std_1s10:inst|sdram:the_sdram|Mux153~1184 at LC_X39_Y7_N4
--operation mode is normal
FB1L716 = FB1_m_state[1] & (FB1_active_dqm[0]) # !FB1_m_state[1] & (FB1_f_select & EE1L161 # !FB1_f_select & (FB1_active_dqm[0]));
--C1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo at LC_X28_Y26_N9
--operation mode is normal
C1_hub_tdo = AMPP_FUNCTION(A1L6, C1L15, C1_hub_tdo, RE1_state[3], RE1_state[4], !RE1_state[8]);
--L1_ic_fill_ap_cnt[3] is std_1s10:inst|cpu:the_cpu|ic_fill_ap_cnt[3] at LC_X40_Y13_N0
--operation mode is normal
L1_ic_fill_ap_cnt[3] = AMPP_FUNCTION(DE1__clk0, L1_internal_i_read, L1L123, N1L114, L1_ic_fill_ap_cnt[3], E1_data_out, L1L1064);
--N1L157 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~1 at LC_X40_Y13_N5
--operation mode is normal
N1L157 = Q1L24 # Q1L21 # !N1L146;
--N1L158 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~3 at LC_X39_Y17_N6
--operation mode is normal
N1L158 = Q1L30 # Q1L27 # !Q1L444;
--Q1_ext_flash_s1_wait_counter[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_wait_counter[0] at LC_X41_Y17_N4
--operation mode is normal
Q1_ext_flash_s1_wait_counter[0]_lut_out = !Q1_ext_flash_s1_wait_counter[0] & !Q1L251 & (!Q1L248);
Q1_ext_flash_s1_wait_counter[0] = DFFEAS(Q1_ext_flash_s1_wait_counter[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L247 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal10~110 at LC_X41_Y17_N5
--operation mode is normal
Q1L247 = !Q1_ext_flash_s1_wait_counter[3] & !Q1_ext_flash_s1_wait_counter[2] & !Q1_ext_flash_s1_wait_counter[1] & !Q1_ext_flash_s1_wait_counter[0];
--N1L147 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|internal_cpu_instruction_master_dbs_address[1]~37 at LC_X39_Y15_N9
--operation mode is normal
N1L147 = Q1L247 & Q1_d1_ext_ram_bus_avalon_slave_end_xfer;
--N1L160 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~14 at LC_X39_Y15_N6
--operation mode is normal
N1L160 = N1_internal_cpu_instruction_master_dbs_address[1] & N1_internal_cpu_instruction_master_dbs_address[0] & N1L147 # !N1L146;
--N1L107 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~136 at LC_X40_Y13_N9
--operation mode is normal
N1L107 = N1L160 & (Q1L6 # Q1L4 # !Q1L403);
--N1L159 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_1~8 at LC_X36_Y11_N6
--operation mode is normal
N1L159 = Q1_d1_ext_ram_bus_avalon_slave_end_xfer & !Q1L415 # !Q1L403;
--GB1_sdram_s1_arb_addend[1] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[1] at LC_X39_Y11_N9
--operation mode is normal
GB1_sdram_s1_arb_addend[1]_lut_out = GB1_WideOr1 & (GB1L62) # !GB1_WideOr1 & GB1_sdram_s1_arb_addend[1];
GB1_sdram_s1_arb_addend[1] = DFFEAS(GB1_sdram_s1_arb_addend[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FE1_fifo_contains_ones_n is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|fifo_contains_ones_n at LC_X40_Y10_N1
--operation mode is normal
FE1_fifo_contains_ones_n_lut_out = FE1L6 # FE1L2 # FE1L3 # FE1L4;
FE1_fifo_contains_ones_n = DFFEAS(FE1_fifo_contains_ones_n_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GE1L27, , , , );
--GB1L22 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_qualified_request_sdram_s1~108 at LC_X39_Y12_N8
--operation mode is normal
GB1L22 = M1_internal_cpu_data_master_waitrequest & !L1_internal_d_write & (!L1_internal_d_read) # !M1_internal_cpu_data_master_waitrequest & (!L1_internal_d_read # !FE1_fifo_contains_ones_n);
--GB1_sdram_s1_slavearbiterlockenable is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable at LC_X41_Y11_N0
--operation mode is normal
GB1_sdram_s1_slavearbiterlockenable_lut_out = GB1L81 & GB1_sdram_s1_slavearbiterlockenable # !GB1L81 & (GB1L35 & (GB1L88) # !GB1L35 & GB1_sdram_s1_slavearbiterlockenable);
GB1_sdram_s1_slavearbiterlockenable = DFFEAS(GB1_sdram_s1_slavearbiterlockenable_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--GB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|last_cycle_cpu_instruction_master_granted_slave_sdram_s1 at LC_X41_Y12_N8
--operation mode is normal
GB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1_lut_out = GB1L28 & (GB1L78 # GB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 & !GB1L80);
GB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1 = DFFEAS(GB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--GB1L76 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[5]~540 at LC_X41_Y12_N4
--operation mode is normal
GB1L76 = L1_internal_i_read & L1_ic_fill_tag[12] & !L1_ic_fill_tag[13] & GB1_last_cycle_cpu_instruction_master_granted_slave_sdram_s1;
--GB1L23 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_qualified_request_sdram_s1~109 at LC_X41_Y11_N2
--operation mode is normal
GB1L23 = GB1L22 & GB1L24 & (!GB1_sdram_s1_slavearbiterlockenable # !GB1L76);
--GB1L28 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_requests_sdram_s1~37 at LC_X40_Y11_N0
--operation mode is normal
GB1L28 = L1_internal_i_read & L1_ic_fill_tag[12] & !L1_ic_fill_tag[13];
--GB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|last_cycle_cpu_data_master_granted_slave_sdram_s1 at LC_X41_Y12_N0
--operation mode is normal
GB1_last_cycle_cpu_data_master_granted_slave_sdram_s1_lut_out = GB1L24 & (GB1L1 # GB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 & !GB1L80);
GB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 = DFFEAS(GB1_last_cycle_cpu_data_master_granted_slave_sdram_s1_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--GB1L19 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_arbiterlock~19 at LC_X41_Y11_N3
--operation mode is normal
GB1L19 = !L1_M_alu_result[25] & L1_M_alu_result[24] & GB1_last_cycle_cpu_data_master_granted_slave_sdram_s1 & QB1L4;
--GB1L30 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_qualified_request_sdram_s1~53 at LC_X40_Y11_N1
--operation mode is normal
GB1L30 = L1_internal_i_read & (N1_internal_cpu_instruction_master_latency_counter[1] # N1_internal_cpu_instruction_master_latency_counter[0]);
--GB1L26 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_qualified_request_sdram_s1~52 at LC_X41_Y11_N9
--operation mode is normal
GB1L26 = GB1L28 & !GB1L30 & (!GB1L19 # !GB1_sdram_s1_slavearbiterlockenable);
--GB1_sdram_s1_arb_addend[0] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[0] at LC_X39_Y11_N7
--operation mode is normal
GB1_sdram_s1_arb_addend[0]_lut_out = GB1_WideOr1 & (!GB1L60) # !GB1_WideOr1 & GB1_sdram_s1_arb_addend[0];
GB1_sdram_s1_arb_addend[0] = DFFEAS(GB1_sdram_s1_arb_addend[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--N1L163 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_2~8 at LC_X39_Y11_N0
--operation mode is normal
N1L163 = !GB1L23 & GB1_sdram_s1_arb_addend[1] # !GB1L26 # !GB1_sdram_s1_arb_addend[0];
--P1_cpu_jtag_debug_module_arb_addend[1] is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1] at LC_X36_Y21_N5
--operation mode is normal
P1_cpu_jtag_debug_module_arb_addend[1]_lut_out = P1L28 # P1L3 & (P1L35 # P1L29);
P1_cpu_jtag_debug_module_arb_addend[1] = DFFEAS(P1_cpu_jtag_debug_module_arb_addend[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--P1L39 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|internal_cpu_instruction_master_qualified_request_cpu_jtag_debug_module~31 at LC_X40_Y11_N4
--operation mode is normal
P1L39 = L1_internal_i_read & (GE1_fifo_contains_ones_n # N1_internal_cpu_instruction_master_latency_counter[1] # N1_internal_cpu_instruction_master_latency_counter[0]);
--P1L11 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~60 at LC_X36_Y12_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[3]_qfbk = L1_ic_fill_tag[3];
P1L11 = L1_ic_fill_tag[4] & !L1_ic_fill_tag[2] & !L1_ic_fill_tag[3]_qfbk & L1_internal_i_read;
--L1_ic_fill_tag[3] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[3] at LC_X36_Y12_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[3] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[13], E1_data_out, GND, L1_D_ic_fill_starting);
--P1L12 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~61 at LC_X36_Y12_N9
--operation mode is normal
P1L12 = Q1L245 & Q1L244 & !L1_ic_fill_tag[13] & P1L11;
--P1L13 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~62 at LC_X36_Y12_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[1]_qfbk = L1_ic_fill_tag[1];
P1L13 = !L1_ic_fill_tag[0] & (!L1_ic_fill_tag[1]_qfbk & !L1_ic_fill_line[6]);
--L1_ic_fill_tag[1] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[1] at LC_X36_Y12_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[1] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[11], E1_data_out, GND, L1_D_ic_fill_starting);
--P1_cpu_jtag_debug_module_arb_addend[0] is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0] at LC_X36_Y21_N2
--operation mode is normal
P1_cpu_jtag_debug_module_arb_addend[0]_lut_out = !P1L26 & (P1L29 # P1L35 # !P1L3);
P1_cpu_jtag_debug_module_arb_addend[0] = DFFEAS(P1_cpu_jtag_debug_module_arb_addend[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--P1L1 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|Add2~331 at LC_X36_Y12_N3
--operation mode is normal
P1L1 = !P1_cpu_jtag_debug_module_arb_addend[0] & (P1L39 # !P1L13 # !P1L12);
--P1L2 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|Add2~332 at LC_X36_Y12_N7
--operation mode is normal
P1L2 = P1L1 & (P1_cpu_jtag_debug_module_arb_addend[1] # !P1L8 # !P1L7) # !P1L1 & P1_cpu_jtag_debug_module_arb_addend[1] & (!P1L8 # !P1L7);
--P1L10 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_qualified_request_cpu_jtag_debug_module~254 at LC_X36_Y12_N5
--operation mode is normal
P1L10 = !P1L39 & P1L12 & (P1L13);
--N1L108 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~137 at LC_X36_Y11_N1
--operation mode is normal
N1L108 = N1L163 & (P1L2 # !P1L10 # !P1_cpu_jtag_debug_module_arb_addend[0]);
--Q1L360 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_cpu_instruction_master_qualified_request_ext_ram_s1~91 at LC_X36_Y13_N4
--operation mode is normal
Q1L360 = Q1L359 # Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable & Q1L69;
--N1L109 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~138 at LC_X36_Y11_N3
--operation mode is normal
N1L109 = !Q1L445 & !Q1L118 # !Q1L360;
--AB1L14 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_requests_onchip_ram_64_kbytes_s1~49 at LC_X35_Y14_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[5]_qfbk = L1_ic_fill_tag[5];
AB1L14 = !L1_ic_fill_tag[7] & !L1_ic_fill_tag[4] & !L1_ic_fill_tag[5]_qfbk & !L1_ic_fill_tag[6];
--L1_ic_fill_tag[5] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[5] at LC_X35_Y14_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[5] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[15], E1_data_out, GND, L1_D_ic_fill_starting);
--AB1L15 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_requests_onchip_ram_64_kbytes_s1~50 at LC_X36_Y14_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[10]_qfbk = L1_ic_fill_tag[10];
AB1L15 = L1_ic_fill_tag[8] & !L1_ic_fill_tag[10]_qfbk & !L1_ic_fill_tag[9];
--L1_ic_fill_tag[10] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[10] at LC_X36_Y14_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[10] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[20], E1_data_out, GND, L1_D_ic_fill_starting);
--AB1L17 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|internal_cpu_instruction_master_qualified_request_onchip_ram_64_kbytes_s1~29 at LC_X40_Y11_N3
--operation mode is normal
AB1L17 = L1_internal_i_read & (N1_internal_cpu_instruction_master_latency_counter[1] # GE1_fifo_contains_ones_n);
--AB1L11 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_qualified_request_onchip_ram_64_kbytes_s1~25 at LC_X34_Y11_N1
--operation mode is normal
AB1L11 = AB1L15 & !AB1L17 & AB1L13 & AB1L14;
--AB1_onchip_ram_64_kbytes_s1_arb_addend[1] is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_arb_addend[1] at LC_X34_Y11_N3
--operation mode is normal
AB1_onchip_ram_64_kbytes_s1_arb_addend[1]_lut_out = AB1_onchip_ram_64_kbytes_s1_arb_addend[1] & (!AB1L2 # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !AB1_onchip_ram_64_kbytes_s1_arb_addend[1] & AB1L11;
AB1_onchip_ram_64_kbytes_s1_arb_addend[1] = DFFEAS(AB1_onchip_ram_64_kbytes_s1_arb_addend[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--AB1L8 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_requests_onchip_ram_64_kbytes_s1~299 at LC_X35_Y12_N6
--operation mode is normal
AB1L8 = L1_M_alu_result[25] & !L1_M_alu_result[23] & L1_M_alu_result[20];
--AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_requests_onchip_ram_64_kbytes_s1 at LC_X39_Y12_N6
--operation mode is normal
AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 = AB1L7 & AB1L9 & AB1L6 & AB1L8;
--AB1_cpu_data_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register at LC_X39_Y12_N2
--operation mode is normal
AB1_cpu_data_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register_lut_out = AB1L3 & L1_internal_d_read & (AB1_onchip_ram_64_kbytes_s1_arb_addend[1] # !AB1L11);
AB1_cpu_data_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register = DFFEAS(AB1_cpu_data_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--AB1L2 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_qualified_request_onchip_ram_64_kbytes_s1~67 at LC_X39_Y12_N0
--operation mode is normal
AB1L2 = L1_internal_d_write & !M1_internal_cpu_data_master_waitrequest & (!AB1_cpu_data_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register # !L1_internal_d_read) # !L1_internal_d_write & (!AB1_cpu_data_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register # !L1_internal_d_read);
--N1L162 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_2~1 at LC_X34_Y11_N2
--operation mode is normal
N1L162 = !AB1L2 # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 # !AB1L11 # !AB1_onchip_ram_64_kbytes_s1_arb_addend[1];
--N1L161 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|r_2~0 at LC_X34_Y11_N7
--operation mode is normal
N1L161 = !AB1L14 # !AB1L13 # !AB1L17 # !AB1L15;
--GB1L31 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|internal_cpu_instruction_master_qualified_request_sdram_s1~54 at LC_X41_Y11_N4
--operation mode is normal
GB1L31 = GB1L30 # GB1L19 & GB1_sdram_s1_slavearbiterlockenable;
--EE1L126 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|Equal0~87 at LC_X39_Y10_N3
--operation mode is normal
EE1L126 = !EE1_entries[0] & EE1_entries[1];
--N1L110 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~139 at LC_X36_Y11_N4
--operation mode is normal
N1L110 = N1L161 & (!GB1L31 & !EE1L126 # !GB1L28);
--N1L111 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~140 at LC_X36_Y11_N2
--operation mode is normal
N1L111 = N1L110 & (!P1L39 & P1_d1_reasons_to_wait # !P1L14);
--N1L112 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~141 at LC_X36_Y11_N8
--operation mode is normal
N1L112 = N1L162 & N1L111 & (!Q1L360 # !Q1L402);
--N1L113 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~142 at LC_X36_Y11_N9
--operation mode is normal
N1L113 = N1L109 & N1L159 & N1L108 & N1L112;
--N1L114 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~143 at LC_X40_Y13_N3
--operation mode is normal
N1L114 = N1L113 & N1L107 & N1L157 & N1L158;
--L1_D_inst_ram_hit is std_1s10:inst|cpu:the_cpu|D_inst_ram_hit at LC_X35_Y16_N9
--operation mode is normal
L1_D_inst_ram_hit = AMPP_FUNCTION(DE1__clk0, L1L877, L1L880, L1L876, L1L878, E1_data_out, L1_W_stall);
--L1_ic_fill_prevent_refill is std_1s10:inst|cpu:the_cpu|ic_fill_prevent_refill at LC_X35_Y21_N1
--operation mode is normal
L1_ic_fill_prevent_refill = AMPP_FUNCTION(DE1__clk0, L1L260, L1L1077, L1L259, L1_ic_fill_prevent_refill, E1_data_out);
--L1_D_ic_fill_same_tag_line is std_1s10:inst|cpu:the_cpu|D_ic_fill_same_tag_line at LC_X34_Y14_N4
--operation mode is normal
L1_D_ic_fill_same_tag_line = AMPP_FUNCTION(DE1__clk0, L1L871, L1L868, L1L863, L1L869, E1_data_out, L1_W_stall);
--L1L259 is std_1s10:inst|cpu:the_cpu|D_ic_fill_starting~63 at LC_X35_Y21_N5
--operation mode is normal
L1L259 = AMPP_FUNCTION(L1_D_inst_ram_hit, L1_ic_fill_prevent_refill, L1_D_kill, L1_D_ic_fill_same_tag_line);
--L1_ic_fill_active is std_1s10:inst|cpu:the_cpu|ic_fill_active at LC_X36_Y20_N9
--operation mode is normal
L1_ic_fill_active = AMPP_FUNCTION(DE1__clk0, L1L1042, L1_i_readdatavalid_d1, L1_ic_fill_active, L1_D_ic_fill_starting, E1_data_out);
--L1L260 is std_1s10:inst|cpu:the_cpu|D_ic_fill_starting~64 at LC_X33_Y21_N9
--operation mode is normal
L1L260 = AMPP_FUNCTION(L1_M_pipe_flush, L1_ic_fill_active);
--L1_D_pc[21] is std_1s10:inst|cpu:the_cpu|D_pc[21] at LC_X33_Y14_N2
--operation mode is normal
L1_D_pc[21] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[21], E1_data_out, L1_W_stall);
--L1_D_pc[18] is std_1s10:inst|cpu:the_cpu|D_pc[18] at LC_X34_Y15_N7
--operation mode is normal
L1_D_pc[18] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[18], E1_data_out, L1_W_stall);
--L1_D_pc[19] is std_1s10:inst|cpu:the_cpu|D_pc[19] at LC_X33_Y14_N0
--operation mode is normal
L1_D_pc[19] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[19], E1_data_out, L1_W_stall);
--L1_D_pc[20] is std_1s10:inst|cpu:the_cpu|D_pc[20] at LC_X33_Y14_N7
--operation mode is normal
L1_D_pc[20] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[20], E1_data_out, L1_W_stall);
--L1_D_pc[22] is std_1s10:inst|cpu:the_cpu|D_pc[22] at LC_X34_Y14_N0
--operation mode is normal
L1_D_pc[22] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[22], E1_data_out, L1_W_stall);
--L1_D_pc[15] is std_1s10:inst|cpu:the_cpu|D_pc[15] at LC_X19_Y19_N8
--operation mode is normal
L1_D_pc[15] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[15], E1_data_out, L1_W_stall);
--L1_D_pc[16] is std_1s10:inst|cpu:the_cpu|D_pc[16] at LC_X34_Y16_N3
--operation mode is normal
L1_D_pc[16] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[16], E1_data_out, L1_W_stall);
--L1_D_pc[17] is std_1s10:inst|cpu:the_cpu|D_pc[17] at LC_X34_Y15_N0
--operation mode is normal
L1_D_pc[17] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[17], E1_data_out, L1_W_stall);
--L1_D_pc[14] is std_1s10:inst|cpu:the_cpu|D_pc[14] at LC_X33_Y16_N0
--operation mode is normal
L1_D_pc[14] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[14], E1_data_out, L1_W_stall);
--L1_D_pc[23] is std_1s10:inst|cpu:the_cpu|D_pc[23] at LC_X33_Y14_N9
--operation mode is normal
L1_D_pc[23] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[23], E1_data_out, L1_W_stall);
--Q1_ext_ram_bus_avalon_slave_arb_share_counter[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[1] at LC_X39_Y16_N2
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_share_counter[1]_lut_out = Q1L341 # !Q1L349 & (Q1L70 # Q1L104);
Q1_ext_ram_bus_avalon_slave_arb_share_counter[1] = DFFEAS(Q1_ext_ram_bus_avalon_slave_arb_share_counter[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1L336, , , , );
--Q1L349 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_firsttransfer~137 at LC_X39_Y16_N1
--operation mode is normal
Q1L349 = Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable & (Q1L101 # Q1L69 # Q1L103);
--Q1L358 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_slavearbiterlockenable~192 at LC_X39_Y16_N9
--operation mode is normal
Q1L358 = Q1L349 & (Q1_ext_ram_bus_avalon_slave_arb_share_counter[1]) # !Q1L349 & Q1L446;
--Q1L448 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~60 at LC_X39_Y13_N5
--operation mode is normal
Q1L448 = !Q1L118 & (!Q1L97 & L1_M_alu_result[25] # !Q1L95);
--Q1L449 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~61 at LC_X39_Y13_N6
--operation mode is normal
Q1L449 = !Q1L402 & !Q1_cpu_data_master_requests_lan91c111_s1 & !Q1L445 & Q1L448;
--Q1L450 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|process4~62 at LC_X39_Y13_N4
--operation mode is normal
--Q1L117 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register_in~11 at LC_X40_Y16_N5
--operation mode is normal
Q1L117 = !Q1L415 & (Q1_d1_ext_ram_bus_avalon_slave_end_xfer # Q1L345);
--Q1L346 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_end_xfer~79 at LC_X39_Y17_N5
--operation mode is normal
Q1L346 = !Q1L117 & (Q1L106 # QB1L4 & Q1L72);
--Q1L110 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register_in~12 at LC_X40_Y16_N8
--operation mode is normal
Q1L110 = Q1L247 & (Q1L345 # Q1_d1_ext_ram_bus_avalon_slave_end_xfer);
--Q1L347 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_end_xfer~80 at LC_X39_Y16_N7
--operation mode is normal
Q1L347 = Q1L346 # !Q1L110 & (Q1L249 # Q1_ext_flash_s1_in_a_read_cycle);
--Q1_d1_ext_ram_bus_avalon_slave_end_xfer is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_ext_ram_bus_avalon_slave_end_xfer at LC_X39_Y16_N7
--operation mode is normal
Q1_d1_ext_ram_bus_avalon_slave_end_xfer = DFFEAS(Q1L347, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1_cpu_data_master_requests_ext_ram_s1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_ram_s1 at LC_X39_Y13_N9
--operation mode is normal
Q1_cpu_data_master_requests_ext_ram_s1 = Q1L95 & (Q1L97);
--N1L5 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~42 at LC_X40_Y17_N2
--operation mode is normal
N1L5 = !Q1L104 & !Q1L106 & !Q1L105;
--Q1_WideOr6 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|WideOr6 at LC_X35_Y12_N2
--operation mode is normal
Q1_WideOr6 = Q1L70 # Q1L71 # Q1L72 # !N1L5;
--Q1L1 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4222 at LC_X35_Y12_N1
--operation mode is normal
Q1L1 = Q1L349 & Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5] # !Q1L349 & (Q1_WideOr6 & (Q1L71) # !Q1_WideOr6 & Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[5]);
--Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arbitration_holdoff_internal at LC_X39_Y15_N0
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arbitration_holdoff_internal = !Q1L345 & (!Q1L349 & !Q1_d1_ext_ram_bus_avalon_slave_end_xfer);
--Q1L333 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4]~COMBOUT at LC_X39_Y14_N7
--operation mode is normal
Q1L333 = Q1L342 & (Q1L70) # !Q1L342 & Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[3];
--Q1_ext_ram_bus_avalon_slave_arb_addend[4] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[4] at LC_X39_Y14_N7
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_addend[4] = DFFEAS(Q1L333, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1_WideOr6, Q1L105, , , Q1L347);
--Q1L329 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2]~COMBOUT at LC_X39_Y14_N5
--operation mode is normal
Q1L329 = Q1L342 & (Q1L72) # !Q1L342 & Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[1];
--Q1_ext_ram_bus_avalon_slave_arb_addend[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[2] at LC_X39_Y14_N5
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_addend[2] = DFFEAS(Q1L329, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1_WideOr6, Q1L104, , , Q1L347);
--GB1L25 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_granted_sdram_s1~77 at LC_X39_Y11_N4
--operation mode is normal
GB1L25 = GB1L26 & (!GB1L23 & GB1_sdram_s1_arb_addend[1] # !GB1_sdram_s1_arb_addend[0]);
--GE1_stage_6 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_6 at LC_X39_Y11_N4
--operation mode is normal
GE1_stage_6 = DFFEAS(GB1L25, GLOBAL(DE1__clk0), VCC, , GE1L20, , , , );
--GE1_stage_0 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_0 at LC_X44_Y10_N1
--operation mode is normal
GE1_stage_0_lut_out = GE1_full_1 & (GE1_stage_1) # !GE1_full_1 & GB1L25;
GE1_stage_0 = DFFEAS(GE1_stage_0_lut_out, GLOBAL(DE1__clk0), VCC, , GE1L26, , , , );
--GE1L35 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|updated_one_count~64 at LC_X44_Y16_N8
--operation mode is normal
GE1L35 = FB1_za_valid & (GE1_stage_0);
--GE1L1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1199 at LC_X40_Y10_N3
--operation mode is normal
GE1L1 = GE1_how_many_ones[2] & GE1_how_many_ones[0] & !GE1L35 & GE1_how_many_ones[1] # !GE1_how_many_ones[2] & !GE1_how_many_ones[0] & GE1L35 & !GE1_how_many_ones[1];
--GE1L2 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1200 at LC_X40_Y10_N8
--operation mode is normal
GE1_how_many_ones[3]_qfbk = GE1_how_many_ones[3];
GE1L2 = GE1_how_many_ones[3]_qfbk $ (GE1L1 & (GE1L36 $ !GE1_how_many_ones[2]));
--GE1_how_many_ones[3] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[3] at LC_X40_Y10_N8
--operation mode is normal
GE1_how_many_ones[3] = DFFEAS(GE1L2, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GE1L27, , , , );
--GE1L3 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1201 at LC_X40_Y10_N2
--operation mode is normal
GE1_how_many_ones[2]_qfbk = GE1_how_many_ones[2];
GE1L3 = GE1_how_many_ones[2]_qfbk $ (GE1L5 & (GE1L36 $ !GE1_how_many_ones[1]));
--GE1_how_many_ones[2] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[2] at LC_X40_Y10_N2
--operation mode is normal
GE1_how_many_ones[2] = DFFEAS(GE1L3, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GE1L27, , , , );
--GE1L4 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1202 at LC_X40_Y10_N0
--operation mode is normal
GE1_how_many_ones[1]_qfbk = GE1_how_many_ones[1];
GE1L4 = GE1_how_many_ones[1]_qfbk $ (GE1_how_many_ones[0] & !GE1L35 & GE1L36 # !GE1_how_many_ones[0] & GE1L35 & !GE1L36);
--GE1_how_many_ones[1] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[1] at LC_X40_Y10_N0
--operation mode is normal
GE1_how_many_ones[1] = DFFEAS(GE1L4, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GE1L27, , , , );
--GB1L20 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_granted_sdram_s1~30 at LC_X39_Y11_N2
--operation mode is normal
GB1L20 = GB1L23 & (GB1_sdram_s1_arb_addend[1] # !GB1_sdram_s1_arb_addend[0] & !GB1L26);
--FE1_stage_6 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_6 at LC_X39_Y11_N2
--operation mode is normal
FE1_stage_6 = DFFEAS(GB1L20, GLOBAL(DE1__clk0), VCC, , GE1L20, , , , );
--GB1L34 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|module_input5~28 at LC_X39_Y10_N5
--operation mode is normal
GB1L34 = !EE1L126 & (GB1L25 # L1_internal_d_read & GB1L20);
--GE1L27 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process15~0 at LC_X40_Y10_N5
--operation mode is normal
GE1L27 = FB1_za_valid # GB1L34;
--AB1L16 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_requests_onchip_ram_64_kbytes_s1~51 at LC_X34_Y11_N5
--operation mode is normal
AB1L16 = AB1L15 & (AB1L13 & AB1L14);
--N1L115 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_run~144 at LC_X40_Y13_N6
--operation mode is normal
N1L115 = N1L157 & (Q1L30 # Q1L27 # !Q1L444);
--N1L153 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter~0 at LC_X40_Y13_N8
--operation mode is normal
N1L153 = L1_internal_i_read & N1L115 & N1L113 & N1L107;
--N1L151 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter[1]~145 at LC_X41_Y12_N9
--operation mode is normal
N1L151 = !L1_ic_fill_tag[11] & !L1_ic_fill_tag[12];
--N1L152 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter[1]~146 at LC_X41_Y12_N5
--operation mode is normal
N1L152 = Q1L246 # N1L151 & (Q1L443 # !L1_ic_fill_tag[13]);
--Q1_ext_ram_bus_avalon_slave_arb_addend[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[0] at LC_X39_Y14_N2
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_addend[0]_lut_out = Q1L347 & !Q1L106 # !Q1L347 & (Q1L335 # !Q1L3);
Q1_ext_ram_bus_avalon_slave_arb_addend[0] = DFFEAS(Q1_ext_ram_bus_avalon_slave_arb_addend[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1_WideOr6, , , , );
--Q1L335 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5]~COMBOUT at LC_X39_Y14_N0
--operation mode is normal
Q1L335 = Q1L342 & (Q1L105) # !Q1L342 & Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[4];
--Q1_ext_ram_bus_avalon_slave_arb_addend[5] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[5] at LC_X39_Y14_N0
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_addend[5] = DFFEAS(Q1L335, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1_WideOr6, Q1L71, , , Q1L347);
--Q1L327 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1]~COMBOUT at LC_X39_Y14_N6
--operation mode is normal
Q1L327 = Q1L342 & Q1L106 # !Q1L342 & (Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[0]);
--Q1_ext_ram_bus_avalon_slave_arb_addend[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[1] at LC_X39_Y14_N6
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_addend[1] = DFFEAS(Q1L327, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1_WideOr6, Q1L72, , , Q1L347);
--Q1L331 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3]~COMBOUT at LC_X39_Y14_N4
--operation mode is normal
Q1L331 = Q1L342 & (Q1L104) # !Q1L342 & Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[2];
--Q1_ext_ram_bus_avalon_slave_arb_addend[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_addend[3] at LC_X39_Y14_N4
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_addend[3] = DFFEAS(Q1L331, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1_WideOr6, Q1L70, , , Q1L347);
--M1L305 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|pre_dbs_count_enable~74 at LC_X34_Y22_N2
--operation mode is normal
M1L305 = !Q1L67 & !Q1L66 & Q1_cpu_data_master_requests_ext_flash_s1 & !M1_internal_cpu_data_master_no_byte_enables_and_last_term;
--M1L306 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|pre_dbs_count_enable~75 at LC_X41_Y16_N7
--operation mode is normal
M1L306 = N1L147 & Q1L76 & (Q1L15 # Q1L18);
--M1L307 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|pre_dbs_count_enable~76 at LC_X41_Y16_N8
--operation mode is normal
M1L307 = Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[1] # L1_internal_d_write & (M1L305 # M1L306);
--GB1L21 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_granted_sdram_s1~31 at LC_X36_Y15_N4
--operation mode is normal
GB1L21 = GB1_sdram_s1_arb_addend[1] & (GB1L26 # GB1L23 # !GB1_sdram_s1_arb_addend[0]) # !GB1_sdram_s1_arb_addend[1] & (GB1L23 $ (GB1L26 # GB1_sdram_s1_arb_addend[0]));
--Q1L248 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Equal10~111 at LC_X41_Y17_N3
--operation mode is normal
Q1L248 = !Q1_ext_flash_s1_wait_counter[3] & !Q1_ext_flash_s1_wait_counter[2] & !Q1_ext_flash_s1_wait_counter[1];
--M1L313 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_1~137 at LC_X36_Y15_N7
--operation mode is normal
M1L313 = M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0]);
--M1L314 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_1~138 at LC_X36_Y15_N8
--operation mode is normal
M1L314 = Q1_ext_flash_s1_wait_counter[0] & Q1L248 & M1L313 # !L1_internal_d_write;
--M1L2 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1043 at LC_X36_Y15_N9
--operation mode is normal
M1L2 = M1L18 # Q1L36 # Q1L76 & !M1L314;
--M1L3 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1044 at LC_X36_Y15_N6
--operation mode is normal
M1L3 = M1L2 # L1_internal_d_read & (GB1L23 # !M1L1);
--W1L20 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|Equal1~69 at LC_X39_Y18_N4
--operation mode is normal
W1L20 = !W1_lcd_display_control_slave_wait_counter[3] & W1L35 & W1L29 & W1_lcd_display_control_slave_wait_counter[0];
--Q1L83 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_lan91c111_s1~71 at LC_X36_Y12_N2
--operation mode is normal
Q1L83 = P1_cpu_data_master_requests_cpu_jtag_debug_module & !P1_cpu_jtag_debug_module_arb_addend[1] & (P1_cpu_jtag_debug_module_arb_addend[0] # P1L10);
--W1L18 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|cpu_data_master_granted_lcd_display_control_slave~105 at LC_X50_Y12_N0
--operation mode is normal
W1L18 = L1_M_alu_result[7] & G1L1;
--M1L4 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1045 at LC_X39_Y18_N3
--operation mode is normal
M1L4 = Q1L83 # !W1L20 & W1L18 & L1_internal_d_read;
--M1L5 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1046 at LC_X36_Y16_N0
--operation mode is normal
M1L5 = Q1_lan91c111_s1_wait_counter[1] # Q1_lan91c111_s1_wait_counter[2] # Q1_lan91c111_s1_wait_counter[3] # !Q1_lan91c111_s1_wait_counter[0];
--M1L6 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1047 at LC_X35_Y10_N7
--operation mode is normal
M1L6 = M1L5 & !L1_internal_d_write & (Q1L9 # Q1L12) # !M1L5 & (Q1L9 # Q1L12);
--M1L7 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1048 at LC_X39_Y15_N2
--operation mode is normal
M1L7 = Q1L82 & (!M1L6) # !Q1L82 & !Q1_cpu_data_master_read_data_valid_lan91c111_s1_shift_register[0] & Q1_cpu_data_master_requests_lan91c111_s1;
--M1L8 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1049 at LC_X39_Y18_N7
--operation mode is normal
M1L8 = M1L4 # M1L7 # !W1L20 & W1L24;
--M1L311 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_0~180 at LC_X36_Y15_N0
--operation mode is normal
M1L311 = Q1_cpu_data_master_read_data_valid_ext_flash_s1_shift_register[0] # !L1_M_mem_byte_en[3] & L1_internal_d_write;
--M1L312 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|r_0~181 at LC_X36_Y15_N1
--operation mode is normal
M1L312 = Q1_cpu_data_master_requests_ext_flash_s1 & !Q1L76 & (!M1L313 # !M1L311);
--Q1L35 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~376 at LC_X39_Y17_N3
--operation mode is normal
Q1L35 = Q1L76 & (!Q1L15 & !Q1L18);
--AB1L3 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_qualified_request_onchip_ram_64_kbytes_s1~68 at LC_X34_Y12_N5
--operation mode is normal
AB1L3 = AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & AB1L2;
--M1L9 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1050 at LC_X36_Y15_N2
--operation mode is normal
M1L9 = Q1L35 # M1L312 # AB1L3 & AB1L1;
--EB1L2 is std_1s10:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1~44 at LC_X40_Y12_N1
--operation mode is normal
EB1L2 = !L1_M_alu_result[4] & EB1L4 & P1L7 & NB1L2;
--U1L2 is std_1s10:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave|cpu_data_master_requests_jtag_uart_avalon_jtag_slave~443 at LC_X41_Y15_N2
--operation mode is normal
U1L2 = !L1_M_alu_result[7] & (!L1_M_alu_result[3]);
--T1L69 is std_1s10:inst|jtag_uart:the_jtag_uart|process2~42 at LC_X39_Y12_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
T1_internal_av_waitrequest_qfbk = T1_internal_av_waitrequest;
T1L69 = !T1_internal_av_waitrequest_qfbk & (!L1_internal_d_write & !L1_internal_d_read # !M1_internal_cpu_data_master_waitrequest);
--T1_internal_av_waitrequest is std_1s10:inst|jtag_uart:the_jtag_uart|internal_av_waitrequest at LC_X39_Y12_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
T1_internal_av_waitrequest = DFFEAS(T1L69, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , T1L71, , , VCC);
--M1L10 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1051 at LC_X41_Y11_N8
--operation mode is normal
M1L10 = GB1L24 & (GB1L76 & GB1_sdram_s1_slavearbiterlockenable # !GB1L22);
--FE1_stage_0 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_0 at LC_X44_Y10_N9
--operation mode is normal
FE1_stage_0_lut_out = GE1_full_1 & (FE1_stage_1) # !GE1_full_1 & GB1L20;
FE1_stage_0 = DFFEAS(FE1_stage_0_lut_out, GLOBAL(DE1__clk0), VCC, , GE1L26, , , , );
--M1L11 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1052 at LC_X40_Y8_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
FB1_za_valid_qfbk = FB1_za_valid;
M1L11 = !FE1_stage_0 # !FB1_za_valid_qfbk # !FE1_fifo_contains_ones_n;
--FB1_za_valid is std_1s10:inst|sdram:the_sdram|za_valid at LC_X40_Y8_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
FB1_za_valid = DFFEAS(M1L11, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , FB1_rd_valid[2], , , VCC);
--M1L12 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1053 at LC_X39_Y12_N7
--operation mode is normal
M1L12 = AB1L2 & (M1L10 & M1L11) # !AB1L2 & (AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 # M1L10 & M1L11);
--YB1_slave_state[0] is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[0] at LC_X48_Y19_N9
--operation mode is normal
YB1_slave_state[0]_lut_out = !YB1L8 & (YB1_slave_state[2] # YB1L10 & !YB1L9);
YB1_slave_state[0] = DFFEAS(YB1_slave_state[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YB1_slave_state[1] is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[1] at LC_X48_Y20_N2
--operation mode is normal
YB1_slave_state[1]_lut_out = !YB1L6 & (YB1_slave_state[0] & (YB1_slave_state[1]) # !YB1_slave_state[0] & J1L1 & !YB1_slave_state[1]);
YB1_slave_state[1] = DFFEAS(YB1_slave_state[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L13 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1054 at LC_X48_Y19_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
XB2_data_in_d1_qfbk = XB2_data_in_d1;
M1L13 = !YB1_slave_state[1] & YB1_slave_state[0] & (SB1_data_out $ !XB2_data_in_d1_qfbk);
--XB2_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_done_edge_to_pulse|data_in_d1 at LC_X48_Y19_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
XB2_data_in_d1 = DFFEAS(M1L13, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , SB1_data_out, , , VCC);
--YB1_slave_state[2] is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[2] at LC_X48_Y19_N6
--operation mode is normal
YB1_slave_state[2]_lut_out = !YB1_slave_state[1] & !YB1L5 & (YB1_slave_state[2] # YB1L4);
YB1_slave_state[2] = DFFEAS(YB1_slave_state[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YB1L10 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux3~66 at LC_X48_Y19_N2
--operation mode is normal
YB1L10 = YB1_slave_state[1] $ !YB1_slave_state[0];
--YB1L7 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux2~228 at LC_X48_Y20_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
XB1_data_in_d1_qfbk = XB1_data_in_d1;
YB1L7 = YB1_slave_state[1] & (RB1_data_out $ XB1_data_in_d1_qfbk);
--XB1_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse|data_in_d1 at LC_X48_Y20_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
XB1_data_in_d1 = DFFEAS(YB1L7, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , RB1_data_out, , , VCC);
--M1L14 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1055 at LC_X48_Y19_N3
--operation mode is normal
M1L14 = YB1_slave_state[2] & M1L13 # !YB1_slave_state[2] & (!YB1L7 & YB1L10);
--J1_cpu_data_master_requests_clock_0_in is std_1s10:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in at LC_X48_Y10_N7
--operation mode is normal
J1_cpu_data_master_requests_clock_0_in = NB1L2 & J1L3 & P1L7 & X1L11;
--M1L15 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1056 at LC_X48_Y19_N4
--operation mode is normal
M1L15 = M1_internal_cpu_data_master_waitrequest # M1L14 & J1_cpu_data_master_requests_clock_0_in # !QB1L4;
--M1L16 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1057 at LC_X39_Y12_N5
--operation mode is normal
M1L16 = T1L71 # M1L12 # M1L15;
--M1L17 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1058 at LC_X36_Y17_N0
--operation mode is normal
M1L17 = M1L16 # !Q1L32 & !Q1L34 & Q1L80;
--E1_data_in_d1 is std_1s10:inst|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch|data_in_d1 at LC_X7_Y12_N8
--operation mode is normal
E1_data_in_d1_lut_out = VCC;
E1_data_in_d1 = DFFEAS(E1_data_in_d1_lut_out, GLOBAL(DE1__clk0), !GLOBAL(B1L1), , , , , , );
--BB1_count_done is std_1s10:inst|pll:the_pll|count_done at LC_X17_Y29_N3
--operation mode is normal
BB1_count_done_lut_out = BB1_count_done # BB1_countup[4] & BB1_countup[5] & BB1L35;
BB1_count_done = DFFEAS(BB1_count_done_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(BB1_not_areset), , , , , , );
--B1L1 is std_1s10:inst|reset_n_sources~17 at LC_X36_Y21_N9
--operation mode is normal
B1L1 = VC1_resetrequest # !BB1_count_done # !PLD_CLEAR_N;
--Q1L251 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_counter_load_value[3]~150 at LC_X41_Y17_N9
--operation mode is normal
Q1L251 = Q1_ext_ram_bus_avalon_slave_begins_xfer & (Q1L87 # Q1L104 # Q1L249);
--Q1L39 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add4~124 at LC_X41_Y18_N5
--operation mode is normal
Q1L39 = Q1_ext_flash_s1_wait_counter[1] # Q1_ext_flash_s1_wait_counter[0];
--Q1L250 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_counter_load_value[1]~153 at LC_X41_Y17_N6
--operation mode is normal
Q1L250 = Q1_ext_flash_s1_wait_counter[1] & (Q1_ext_flash_s1_wait_counter[0]) # !Q1_ext_flash_s1_wait_counter[1] & !Q1_ext_flash_s1_wait_counter[0] & (Q1_ext_flash_s1_wait_counter[3] # Q1_ext_flash_s1_wait_counter[2]);
--Q1L2 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4229 at LC_X40_Y16_N6
--operation mode is normal
Q1L2 = Q1_ext_ram_bus_avalon_slave_begins_xfer & (Q1L106 # L1_internal_d_read & Q1L72);
--Q1L37 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add3~125 at LC_X36_Y16_N1
--operation mode is normal
Q1L37 = Q1_lan91c111_s1_wait_counter[3] & (Q1_lan91c111_s1_wait_counter[1] # Q1_lan91c111_s1_wait_counter[2] # Q1_lan91c111_s1_wait_counter[0]);
--Q1L348 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_end_xfer~81 at LC_X36_Y16_N5
--operation mode is normal
Q1L348 = QB1L4 & Q1L82 & (Q1L9 # Q1L12);
--Q1L400 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_counter_load_value[3]~101 at LC_X36_Y16_N2
--operation mode is normal
Q1L400 = Q1_ext_ram_bus_avalon_slave_begins_xfer & (Q1L106 # Q1L72 & QB1L4);
--Q1L38 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add3~126 at LC_X36_Y16_N7
--operation mode is normal
Q1L38 = !Q1_lan91c111_s1_wait_counter[1] & (!Q1_lan91c111_s1_wait_counter[0]);
--FB1L449 is std_1s10:inst|sdram:the_sdram|Mux24~1459 at LC_X35_Y3_N5
--operation mode is normal
FB1L449 = FB1_m_state[6] & (FB1_m_state[4] # !FB1L416 # !FB1L448);
--FB1L238 is std_1s10:inst|sdram:the_sdram|m_count~759 at LC_X40_Y2_N0
--operation mode is normal
FB1L238 = FB1_refresh_request & FB1_init_done;
--FB1L450 is std_1s10:inst|sdram:the_sdram|Mux24~1460 at LC_X36_Y2_N4
--operation mode is normal
FB1L450 = !FB1_m_state[0] & FB1L594 & FB1L518 & FB1L238;
--FB1L451 is std_1s10:inst|sdram:the_sdram|Mux24~1461 at LC_X33_Y3_N5
--operation mode is normal
FB1L451 = !FB1_m_state[8] & !FB1_m_state[3] & FB1_m_state[0] & !FB1_m_state[4];
--FB1L452 is std_1s10:inst|sdram:the_sdram|Mux24~1462 at LC_X32_Y3_N7
--operation mode is normal
FB1L452 = FB1_m_state[2] & !FB1_m_state[5] & (FB1_m_next[1]) # !FB1_m_state[2] & FB1_m_state[5];
--FB1_m_count[2] is std_1s10:inst|sdram:the_sdram|m_count[2] at LC_X33_Y1_N6
--operation mode is normal
FB1_m_count[2]_lut_out = FB1_m_state[8] & FB1_m_count[2] & (FB1L521 # FB1L533) # !FB1_m_state[8] & (FB1L533);
FB1_m_count[2] = DFFEAS(FB1_m_count[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , !FB1_m_state[6], , , , );
--FB1_m_count[1] is std_1s10:inst|sdram:the_sdram|m_count[1] at LC_X32_Y1_N0
--operation mode is normal
FB1_m_count[1]_lut_out = FB1_m_state[4] & FB1_m_count[1] & (FB1L536 # FB1L546) # !FB1_m_state[4] & (FB1L546);
FB1_m_count[1] = DFFEAS(FB1_m_count[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , !FB1_m_state[6], , , , );
--FB1L158 is std_1s10:inst|sdram:the_sdram|LessThan1~52 at LC_X31_Y1_N2
--operation mode is normal
FB1L158 = FB1_m_count[1] # FB1_m_count[2];
--FB1L678 is std_1s10:inst|sdram:the_sdram|Mux118~1211 at LC_X35_Y1_N3
--operation mode is normal
FB1L678 = !FB1_m_state[8] & FB1_m_state[0] & !FB1_m_state[2] & !FB1_m_state[7];
--FB1L481 is std_1s10:inst|sdram:the_sdram|Mux29~1321 at LC_X35_Y1_N0
--operation mode is normal
FB1L481 = FB1_m_state[1] & (!FB1L480 # !FB1L518 # !FB1L678);
--FB1L482 is std_1s10:inst|sdram:the_sdram|Mux29~1322 at LC_X35_Y1_N6
--operation mode is normal
FB1L482 = !FB1_m_state[6] & !FB1_m_state[5] & !FB1_m_state[7];
--FB1L442 is std_1s10:inst|sdram:the_sdram|Mux22~1316 at LC_X32_Y2_N9
--operation mode is normal
FB1L442 = FB1_m_state[2] & !FB1_m_count[1] & !FB1_m_count[2];
--FB1L455 is std_1s10:inst|sdram:the_sdram|Mux25~1250 at LC_X32_Y2_N0
--operation mode is normal
FB1L455 = FB1_m_next[1] & FB1L442 & (FB1L451);
--FB1L561 is std_1s10:inst|sdram:the_sdram|Mux44~1251 at LC_X39_Y10_N1
--operation mode is normal
FB1L561 = !FB1_m_state[4] & !FB1_m_state[3] & (EE1_entries[0] # EE1_entries[1]);
--FB1L483 is std_1s10:inst|sdram:the_sdram|Mux29~1323 at LC_X35_Y4_N0
--operation mode is normal
FB1L483 = !FB1_m_state[8] & !FB1_m_state[0] & !FB1_m_state[2];
--FB1L484 is std_1s10:inst|sdram:the_sdram|Mux29~1324 at LC_X35_Y4_N4
--operation mode is normal
FB1L484 = !FB1_refresh_request & FB1L483 & FB1L561 & FB1_init_done;
--FB1L717 is std_1s10:inst|sdram:the_sdram|Mux154~540 at LC_X35_Y1_N1
--operation mode is normal
FB1L717 = !FB1_m_state[1] & !FB1_m_state[6] & !FB1_m_state[5] & !FB1_m_state[7];
--FB1L744 is std_1s10:inst|sdram:the_sdram|refresh_request~91 at LC_X39_Y10_N4
--operation mode is normal
FB1L744 = !EE1_entries[1] & !FB1_refresh_request & (!EE1_entries[0]);
--FB1L443 is std_1s10:inst|sdram:the_sdram|Mux22~1317 at LC_X32_Y2_N7
--operation mode is normal
FB1L443 = !FB1_m_state[2] & FB1L434 & (FB1L724 # !EE1L127);
--FB1L444 is std_1s10:inst|sdram:the_sdram|Mux22~1318 at LC_X32_Y2_N1
--operation mode is normal
FB1L444 = FB1_m_state[8] & (FB1L518) # !FB1_m_state[8] & (FB1L443 # FB1L446 & FB1L518);
--FB1L456 is std_1s10:inst|sdram:the_sdram|Mux25~1251 at LC_X33_Y1_N7
--operation mode is normal
FB1L456 = FB1_m_state[8] # FB1_m_state[6] # FB1_m_count[1] # FB1_m_count[2];
--FB1L549 is std_1s10:inst|sdram:the_sdram|Mux42~1466 at LC_X33_Y3_N7
--operation mode is normal
FB1L549 = FB1_m_state[0] & !FB1_m_state[3] & !FB1_m_state[4];
--FB1L519 is std_1s10:inst|sdram:the_sdram|Mux40~1436 at LC_X34_Y2_N5
--operation mode is normal
FB1L519 = !FB1_m_state[2] & (!FB1_m_state[1] & !FB1_m_state[7]);
--FB1L457 is std_1s10:inst|sdram:the_sdram|Mux25~1252 at LC_X34_Y2_N2
--operation mode is normal
FB1L457 = FB1_m_state[5] & (FB1L456 # !FB1L519 # !FB1L549);
--FB1L593 is std_1s10:inst|sdram:the_sdram|Mux59~1274 at LC_X39_Y10_N7
--operation mode is normal
FB1L593 = FB1L561 & !FB1_refresh_request;
--FB1L458 is std_1s10:inst|sdram:the_sdram|Mux25~1253 at LC_X34_Y2_N1
--operation mode is normal
FB1L458 = FB1L724 & FB1_m_state[8] & FB1L426 & FB1L593;
--FB1L470 is std_1s10:inst|sdram:the_sdram|Mux28~1602 at LC_X34_Y4_N9
--operation mode is normal
FB1L470 = FB1_m_state[2] & (FB1L479 # FB1_m_state[8] # !FB1L717);
--FB1L471 is std_1s10:inst|sdram:the_sdram|Mux28~1603 at LC_X33_Y3_N1
--operation mode is normal
FB1L471 = !FB1_m_state[5] & FB1_m_state[0] & !FB1_m_state[2];
--FB1L472 is std_1s10:inst|sdram:the_sdram|Mux28~1604 at LC_X33_Y3_N8
--operation mode is normal
FB1L472 = FB1_refresh_request & !FB1_m_state[1] & !FB1_m_state[6];
--FB1L473 is std_1s10:inst|sdram:the_sdram|Mux28~1605 at LC_X33_Y3_N2
--operation mode is normal
FB1L473 = FB1_m_state[8] & !FB1_m_state[3] & !FB1_m_state[7] & !FB1_m_state[4];
--FB1L474 is std_1s10:inst|sdram:the_sdram|Mux28~1606 at LC_X34_Y4_N4
--operation mode is normal
FB1L474 = EE1L127 & FB1L434 & !FB1L724 & !FB1_m_state[8];
--FB1L475 is std_1s10:inst|sdram:the_sdram|Mux28~1607 at LC_X33_Y3_N9
--operation mode is normal
FB1L475 = FB1L472 & (FB1L473 # !FB1L431 & FB1L474);
--FB1L476 is std_1s10:inst|sdram:the_sdram|Mux28~1608 at LC_X31_Y2_N4
--operation mode is normal
FB1L476 = !FB1_m_state[3] & !FB1_m_state[4] & !FB1_m_state[1] & !FB1_m_state[7];
--FB1L477 is std_1s10:inst|sdram:the_sdram|Mux28~1609 at LC_X34_Y1_N9
--operation mode is normal
FB1L477 = !FB1_m_state[4] & !FB1_m_state[3] & (FB1_m_state[1] $ FB1_m_state[7]);
--FB1L478 is std_1s10:inst|sdram:the_sdram|Mux28~1610 at LC_X33_Y3_N6
--operation mode is normal
FB1L478 = !FB1_m_state[8] & (FB1_m_state[6] & FB1L476 # !FB1_m_state[6] & (FB1L477));
--FB1L447 is std_1s10:inst|sdram:the_sdram|Mux23~1125 at LC_X32_Y2_N4
--operation mode is normal
FB1L447 = FB1L451 & FB1_m_next[7] & FB1L717 & FB1L442;
--FB1L459 is std_1s10:inst|sdram:the_sdram|Mux26~1221 at LC_X36_Y1_N9
--operation mode is normal
FB1L459 = FB1_m_state[4] & (FB1L464 # FB1_m_state[3] # !FB1L468);
--FB1L460 is std_1s10:inst|sdram:the_sdram|Mux26~1222 at LC_X32_Y2_N8
--operation mode is normal
FB1L460 = FB1_m_state[2] & !FB1_m_count[1] & !FB1_m_count[2] & !FB1_m_state[8];
--FB1L461 is std_1s10:inst|sdram:the_sdram|Mux26~1223 at LC_X32_Y3_N1
--operation mode is normal
FB1L461 = !FB1_m_state[2] & (FB1_m_state[8]);
--FB1L462 is std_1s10:inst|sdram:the_sdram|Mux26~1224 at LC_X32_Y3_N5
--operation mode is normal
FB1L462 = FB1L461 & !FB1_refresh_request & !FB1L724 & EE1L127;
--EE1L175 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[58]~509 at LC_X33_Y4_N3
--operation mode is normal
EE1L175 = EE1_rd_address & EE1_entry_1[58] # !EE1_rd_address & (EE1_entry_0[58]);
--FB1L463 is std_1s10:inst|sdram:the_sdram|Mux26~1225 at LC_X33_Y4_N4
--operation mode is normal
FB1L463 = EE1L175 & FB1_m_next[4] & (FB1L460) # !EE1L175 & (FB1L462 # FB1_m_next[4] & FB1L460);
--FB1L535 is std_1s10:inst|sdram:the_sdram|Mux41~1448 at LC_X36_Y1_N4
--operation mode is normal
FB1L535 = !FB1_m_state[3] & (FB1_m_state[0]);
--FB1L465 is std_1s10:inst|sdram:the_sdram|Mux27~1226 at LC_X36_Y1_N1
--operation mode is normal
FB1L465 = FB1_m_state[3] & (FB1L464 # FB1_m_state[4] # !FB1L468);
--FB1L466 is std_1s10:inst|sdram:the_sdram|Mux27~1227 at LC_X33_Y4_N9
--operation mode is normal
FB1L466 = EE1L175 & (FB1L462 # FB1_m_next[3] & FB1L460) # !EE1L175 & FB1_m_next[3] & (FB1L460);
--FB1L467 is std_1s10:inst|sdram:the_sdram|Mux27~1228 at LC_X36_Y1_N2
--operation mode is normal
FB1L467 = FB1_m_state[0] & (!FB1_m_state[4]);
--FB1L485 is std_1s10:inst|sdram:the_sdram|Mux30~1227 at LC_X31_Y2_N1
--operation mode is normal
FB1L485 = !FB1_m_next[0] & FB1L717 & FB1L460 & FB1L518;
--FB1L29 is std_1s10:inst|sdram:the_sdram|active_cs_n~277 at LC_X35_Y4_N2
--operation mode is normal
FB1L29 = !FB1_m_state[3] & !FB1_m_state[8] & !FB1_m_state[4] & FB1_init_done;
--FB1L30 is std_1s10:inst|sdram:the_sdram|active_cs_n~278 at LC_X2_Y12_N3
--operation mode is normal
FB1L30 = !FB1_m_state[2] & (FB1L717 & FB1L29);
--FB1L562 is std_1s10:inst|sdram:the_sdram|Mux44~1252 at LC_X34_Y4_N7
--operation mode is normal
FB1L562 = FB1L717 & !FB1_m_state[2] & !FB1_refresh_request;
--FB1L563 is std_1s10:inst|sdram:the_sdram|Mux44~1253 at LC_X35_Y4_N1
--operation mode is normal
FB1L563 = FB1_m_state[8] & FB1_m_state[0] # !FB1_m_state[8] & !FB1_m_state[0] & FB1_init_done;
--FB1L564 is std_1s10:inst|sdram:the_sdram|Mux44~1254 at LC_X34_Y4_N6
--operation mode is normal
FB1L564 = FB1L561 & FB1L563 & (!FB1_m_state[0] # !FB1L724);
--GB1L45 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[9]~154 at LC_X35_Y13_N2
--operation mode is normal
GB1L45 = GB1L20 & L1_M_alu_result[11] # !GB1L20 & (L1_ic_fill_line[6]);
--EE1_entry_1[45] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[45] at LC_X35_Y13_N2
--operation mode is normal
EE1_entry_1[45] = DFFEAS(GB1L45, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--FB1L407 is std_1s10:inst|sdram:the_sdram|module_input~19 at LC_X41_Y12_N1
--operation mode is normal
FB1L407 = GB1L25 # GB1L20 & (L1_internal_d_read # L1_internal_d_write);
--EE1_wr_address is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|wr_address at LC_X36_Y4_N0
--operation mode is normal
EE1_wr_address_lut_out = EE1_wr_address $ (FB1L407 & (EE1_entries[0] # !EE1_entries[1]));
EE1_wr_address = DFFEAS(EE1_wr_address_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L589 is std_1s10:inst|sdram:the_sdram|Mux58~1328 at LC_X35_Y7_N2
--operation mode is normal
FB1L589 = EE1_rd_address & EE1_entry_1[45] # !EE1_rd_address & (EE1_entry_0[45]);
--FB1L566 is std_1s10:inst|sdram:the_sdram|Mux47~1287 at LC_X35_Y4_N5
--operation mode is normal
FB1L566 = !FB1_refresh_request & !FB1L724 & FB1L434 & EE1L127;
--FB1L590 is std_1s10:inst|sdram:the_sdram|Mux58~1329 at LC_X35_Y4_N8
--operation mode is normal
FB1L590 = FB1L593 & (FB1_m_state[0] & !FB1L724 # !FB1_m_state[0] & (FB1_init_done));
--FB1L591 is std_1s10:inst|sdram:the_sdram|Mux58~1330 at LC_X35_Y4_N6
--operation mode is normal
FB1L591 = FB1_m_state[8] & FB1L590 & FB1_m_state[0] # !FB1_m_state[8] & (FB1_m_state[0] & (FB1L566) # !FB1_m_state[0] & FB1L590);
--FB1L592 is std_1s10:inst|sdram:the_sdram|Mux58~1331 at LC_X35_Y7_N3
--operation mode is normal
FB1L592 = FB1L591 & (FB1L589) # !FB1L591 & FB1_active_addr[9];
--FB1L565 is std_1s10:inst|sdram:the_sdram|Mux44~1256 at LC_X34_Y4_N0
--operation mode is normal
FB1L565 = !FB1_m_state[2] & FB1L717;
--GB1L44 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[8]~155 at LC_X35_Y15_N1
--operation mode is normal
GB1L44 = GB1L20 & L1_M_alu_result[10] # !GB1L20 & (L1_ic_fill_line[5]);
--EE1_entry_1[44] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[44] at LC_X35_Y15_N1
--operation mode is normal
EE1_entry_1[44] = DFFEAS(GB1L44, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--FB1L12 is std_1s10:inst|sdram:the_sdram|active_addr[8]~4927 at LC_X39_Y4_N6
--operation mode is normal
FB1L12 = FB1L565 & E1_data_out & (FB1_m_state[0] # FB1_init_done);
--FB1L13 is std_1s10:inst|sdram:the_sdram|active_addr[8]~4928 at LC_X35_Y4_N9
--operation mode is normal
FB1L13 = FB1_m_state[0] & (!FB1_m_state[8] # !FB1L724);
--FB1L14 is std_1s10:inst|sdram:the_sdram|active_addr[8]~4929 at LC_X35_Y4_N7
--operation mode is normal
FB1L14 = FB1_m_state[8] & FB1L593 & (FB1L13) # !FB1_m_state[8] & (FB1L13 & (FB1L566) # !FB1L13 & FB1L593);
--GB1L50 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[14]~156 at LC_X36_Y6_N6
--operation mode is normal
GB1L50 = GB1L20 & (L1_M_alu_result[16]) # !GB1L20 & L1_ic_fill_tag[4];
--EE1_entry_1[50] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[50] at LC_X36_Y6_N6
--operation mode is normal
EE1_entry_1[50] = DFFEAS(GB1L50, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--FB1L579 is std_1s10:inst|sdram:the_sdram|Mux53~1277 at LC_X36_Y6_N1
--operation mode is normal
FB1L579 = EE1_rd_address & (EE1_entry_1[50]) # !EE1_rd_address & EE1_entry_0[50];
--FB1L580 is std_1s10:inst|sdram:the_sdram|Mux53~1278 at LC_X36_Y6_N9
--operation mode is normal
FB1L580 = FB1L591 & FB1L579 # !FB1L591 & (FB1_active_addr[14]);
--GB1L49 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[13]~157 at LC_X35_Y13_N1
--operation mode is normal
GB1L49 = GB1L20 & (L1_M_alu_result[15]) # !GB1L20 & L1_ic_fill_tag[3];
--EE1_entry_1[49] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[49] at LC_X35_Y13_N1
--operation mode is normal
EE1_entry_1[49] = DFFEAS(GB1L49, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--FB1L581 is std_1s10:inst|sdram:the_sdram|Mux54~1277 at LC_X34_Y7_N2
--operation mode is normal
FB1L581 = EE1_rd_address & (EE1_entry_1[49]) # !EE1_rd_address & EE1_entry_0[49];
--FB1L582 is std_1s10:inst|sdram:the_sdram|Mux54~1278 at LC_X34_Y5_N1
--operation mode is normal
FB1L582 = FB1L591 & FB1L581 # !FB1L591 & (FB1_active_addr[13]);
--GB1L47 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[11]~158 at LC_X35_Y9_N6
--operation mode is normal
GB1L47 = GB1L20 & L1_M_alu_result[13] # !GB1L20 & (L1_ic_fill_tag[1]);
--EE1_entry_1[47] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[47] at LC_X35_Y9_N6
--operation mode is normal
EE1_entry_1[47] = DFFEAS(GB1L47, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--FB1L585 is std_1s10:inst|sdram:the_sdram|Mux56~1277 at LC_X35_Y9_N4
--operation mode is normal
FB1L585 = EE1_rd_address & EE1_entry_1[47] # !EE1_rd_address & (EE1_entry_0[47]);
--FB1L586 is std_1s10:inst|sdram:the_sdram|Mux56~1278 at LC_X35_Y9_N2
--operation mode is normal
FB1L586 = FB1L591 & FB1L585 # !FB1L591 & (FB1_active_addr[11]);
--GB1L57 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[21]~159 at LC_X35_Y9_N7
--operation mode is normal
GB1L57 = GB1L20 & (L1_M_alu_result[23]) # !GB1L20 & L1_ic_fill_tag[11];
--EE1_entry_1[57] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[57] at LC_X35_Y9_N7
--operation mode is normal
EE1_entry_1[57] = DFFEAS(GB1L57, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--GB1L52 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[16]~160 at LC_X35_Y14_N9
--operation mode is normal
GB1L52 = GB1L20 & L1_M_alu_result[18] # !GB1L20 & (L1_ic_fill_tag[6]);
--EE1_entry_1[52] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[52] at LC_X35_Y14_N9
--operation mode is normal
EE1_entry_1[52] = DFFEAS(GB1L52, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--FB1L575 is std_1s10:inst|sdram:the_sdram|Mux51~1277 at LC_X33_Y9_N0
--operation mode is normal
FB1L575 = EE1_rd_address & EE1_entry_1[52] # !EE1_rd_address & (EE1_entry_0[52]);
--FB1L576 is std_1s10:inst|sdram:the_sdram|Mux51~1278 at LC_X33_Y9_N1
--operation mode is normal
FB1L576 = FB1L591 & (FB1L575) # !FB1L591 & FB1_active_addr[16];
--GB1L51 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[15]~161 at LC_X35_Y14_N1
--operation mode is normal
GB1L51 = GB1L20 & (L1_M_alu_result[17]) # !GB1L20 & L1_ic_fill_tag[5];
--EE1_entry_1[51] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[51] at LC_X35_Y14_N1
--operation mode is normal
EE1_entry_1[51] = DFFEAS(GB1L51, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--FB1L577 is std_1s10:inst|sdram:the_sdram|Mux52~1277 at LC_X34_Y6_N2
--operation mode is normal
FB1L577 = EE1_rd_address & EE1_entry_1[51] # !EE1_rd_address & (EE1_entry_0[51]);
--FB1L578 is std_1s10:inst|sdram:the_sdram|Mux52~1278 at LC_X34_Y6_N5
--operation mode is normal
FB1L578 = FB1L591 & (FB1L577) # !FB1L591 & FB1_active_addr[15];
--GB1L53 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[17]~162 at LC_X35_Y14_N6
--operation mode is normal
GB1L53 = GB1L20 & (L1_M_alu_result[19]) # !GB1L20 & L1_ic_fill_tag[7];
--EE1_entry_1[53] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[53] at LC_X35_Y14_N6
--operation mode is normal
EE1_entry_1[53] = DFFEAS(GB1L53, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--FB1L573 is std_1s10:inst|sdram:the_sdram|Mux50~1277 at LC_X33_Y11_N0
--operation mode is normal
FB1L573 = EE1_rd_address & (EE1_entry_1[53]) # !EE1_rd_address & EE1_entry_0[53];
--FB1L574 is std_1s10:inst|sdram:the_sdram|Mux50~1278 at LC_X33_Y9_N5
--operation mode is normal
FB1L574 = FB1L591 & (FB1L573) # !FB1L591 & FB1_active_addr[17];
--GB1L46 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[10]~163 at LC_X33_Y11_N5
--operation mode is normal
GB1L46 = GB1L20 & L1_M_alu_result[12] # !GB1L20 & (L1_ic_fill_tag[0]);
--EE1_entry_1[46] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[46] at LC_X33_Y11_N5
--operation mode is normal
EE1_entry_1[46] = DFFEAS(GB1L46, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--FB1L587 is std_1s10:inst|sdram:the_sdram|Mux57~1277 at LC_X33_Y11_N9
--operation mode is normal
FB1L587 = EE1_rd_address & EE1_entry_1[46] # !EE1_rd_address & (EE1_entry_0[46]);
--FB1L588 is std_1s10:inst|sdram:the_sdram|Mux57~1278 at LC_X33_Y11_N7
--operation mode is normal
FB1L588 = FB1L591 & (FB1L587) # !FB1L591 & FB1_active_addr[10];
--GB1_sdram_s1_in_a_write_cycle is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_in_a_write_cycle at LC_X35_Y15_N9
--operation mode is normal
GB1_sdram_s1_in_a_write_cycle = GB1L20 & L1_internal_d_write;
--GB1L56 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[20]~164 at LC_X33_Y11_N6
--operation mode is normal
GB1L56 = GB1L20 & (L1_M_alu_result[22]) # !GB1L20 & L1_ic_fill_tag[10];
--EE1_entry_1[56] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[56] at LC_X33_Y11_N6
--operation mode is normal
EE1_entry_1[56] = DFFEAS(GB1L56, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--FB1L567 is std_1s10:inst|sdram:the_sdram|Mux47~1288 at LC_X33_Y9_N2
--operation mode is normal
FB1L567 = EE1_rd_address & (EE1_entry_1[56]) # !EE1_rd_address & EE1_entry_0[56];
--FB1L568 is std_1s10:inst|sdram:the_sdram|Mux47~1289 at LC_X33_Y9_N3
--operation mode is normal
FB1L568 = FB1L591 & (FB1L567) # !FB1L591 & FB1_active_addr[20];
--GB1L54 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[18]~165 at LC_X35_Y12_N3
--operation mode is normal
GB1L54 = GB1L20 & L1_M_alu_result[20] # !GB1L20 & (L1_ic_fill_tag[8]);
--EE1_entry_1[54] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[54] at LC_X35_Y12_N3
--operation mode is normal
EE1_entry_1[54] = DFFEAS(GB1L54, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--FB1L571 is std_1s10:inst|sdram:the_sdram|Mux49~1277 at LC_X35_Y12_N5
--operation mode is normal
FB1L571 = EE1_rd_address & (EE1_entry_1[54]) # !EE1_rd_address & (EE1_entry_0[54]);
--FB1L572 is std_1s10:inst|sdram:the_sdram|Mux49~1278 at LC_X35_Y12_N9
--operation mode is normal
FB1L572 = FB1L591 & (FB1L571) # !FB1L591 & FB1_active_addr[18];
--GB1L48 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[12]~166 at LC_X34_Y8_N3
--operation mode is normal
GB1L48 = GB1L20 & (L1_M_alu_result[14]) # !GB1L20 & L1_ic_fill_tag[2];
--EE1_entry_1[48] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[48] at LC_X34_Y8_N3
--operation mode is normal
EE1_entry_1[48] = DFFEAS(GB1L48, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--FB1L583 is std_1s10:inst|sdram:the_sdram|Mux55~1277 at LC_X34_Y8_N0
--operation mode is normal
FB1L583 = EE1_rd_address & EE1_entry_1[48] # !EE1_rd_address & (EE1_entry_0[48]);
--FB1L584 is std_1s10:inst|sdram:the_sdram|Mux55~1278 at LC_X34_Y8_N4
--operation mode is normal
FB1L584 = FB1L591 & (FB1L583) # !FB1L591 & FB1_active_addr[12];
--FB1L31 is std_1s10:inst|sdram:the_sdram|active_cs_n~279 at LC_X2_Y12_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
E1_data_out_qfbk = E1_data_out;
FB1L31 = E1_data_out_qfbk & !FB1_m_state[0];
--E1_data_out is std_1s10:inst|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch|data_out at LC_X2_Y12_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
E1_data_out = DFFEAS(FB1L31, GLOBAL(DE1__clk0), !GLOBAL(B1L1), , , E1_data_in_d1, , , VCC);
--FB1L32 is std_1s10:inst|sdram:the_sdram|active_cs_n~280 at LC_X2_Y12_N1
--operation mode is normal
FB1L32 = !FB1_m_state[2] & FB1L31 & FB1L717 & FB1L29;
--GB1L55 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[19]~167 at LC_X35_Y11_N4
--operation mode is normal
GB1L55 = GB1L20 & (L1_M_alu_result[21]) # !GB1L20 & L1_ic_fill_tag[9];
--EE1_entry_1[55] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[55] at LC_X35_Y11_N4
--operation mode is normal
EE1_entry_1[55] = DFFEAS(GB1L55, GLOBAL(DE1__clk0), VCC, , EE1L123, , , , );
--FB1L569 is std_1s10:inst|sdram:the_sdram|Mux48~1277 at LC_X35_Y11_N5
--operation mode is normal
FB1L569 = EE1_rd_address & EE1_entry_1[55] # !EE1_rd_address & (EE1_entry_0[55]);
--FB1L570 is std_1s10:inst|sdram:the_sdram|Mux48~1278 at LC_X35_Y11_N6
--operation mode is normal
FB1L570 = FB1L591 & (FB1L569) # !FB1L591 & FB1_active_addr[19];
--FB1_i_state[0] is std_1s10:inst|sdram:the_sdram|i_state[0] at LC_X41_Y3_N8
--operation mode is normal
FB1_i_state[0]_lut_out = FB1L411 # FB1L147 & (FB1_i_state[1] # FB1L112);
FB1_i_state[0] = DFFEAS(FB1_i_state[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_i_state[2] is std_1s10:inst|sdram:the_sdram|i_state[2] at LC_X40_Y2_N8
--operation mode is normal
FB1_i_state[2]_lut_out = FB1_i_state[0] & (FB1_i_state[1] & FB1L408 & !FB1_i_state[2] # !FB1_i_state[1] & (FB1_i_state[2]));
FB1_i_state[2] = DFFEAS(FB1_i_state[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_i_state[1] is std_1s10:inst|sdram:the_sdram|i_state[1] at LC_X40_Y2_N4
--operation mode is normal
FB1_i_state[1]_lut_out = FB1_i_state[0] & (FB1_i_state[1] & (FB1L409 # FB1_i_state[2]) # !FB1_i_state[1] & (!FB1_i_state[2])) # !FB1_i_state[0] & FB1_i_state[1] & (!FB1_i_state[2]);
FB1_i_state[1] = DFFEAS(FB1_i_state[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L134 is std_1s10:inst|sdram:the_sdram|i_cmd[0]~636 at LC_X40_Y2_N3
--operation mode is normal
FB1L134 = FB1_i_state[1] & FB1_i_state[0] # !FB1_i_state[2];
--FB1_refresh_counter[3] is std_1s10:inst|sdram:the_sdram|refresh_counter[3] at LC_X52_Y12_N4
--operation mode is normal
FB1_refresh_counter[3]_lut_out = !FB1L74;
FB1_refresh_counter[3] = DFFEAS(FB1_refresh_counter[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_refresh_counter[0] is std_1s10:inst|sdram:the_sdram|refresh_counter[0] at LC_X52_Y8_N9
--operation mode is normal
FB1_refresh_counter[0]_lut_out = FB1L77;
FB1_refresh_counter[0] = DFFEAS(FB1_refresh_counter[0]_lut_out, GLOBAL(DE1__clk0), VCC, , , A1L275, !GLOBAL(E1_data_out), , );
--FB1_refresh_counter[1] is std_1s10:inst|sdram:the_sdram|refresh_counter[1] at LC_X52_Y12_N2
--operation mode is normal
FB1_refresh_counter[1]_lut_out = FB1L79 & !FB1L112;
FB1_refresh_counter[1] = DFFEAS(FB1_refresh_counter[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_refresh_counter[2] is std_1s10:inst|sdram:the_sdram|refresh_counter[2] at LC_X52_Y12_N6
--operation mode is normal
FB1_refresh_counter[2]_lut_out = FB1L82;
FB1_refresh_counter[2] = DFFEAS(FB1_refresh_counter[2]_lut_out, GLOBAL(DE1__clk0), VCC, , , A1L275, !GLOBAL(E1_data_out), , );
--FB1L109 is std_1s10:inst|sdram:the_sdram|Equal1~166 at LC_X52_Y12_N9
--operation mode is normal
FB1L109 = !FB1_refresh_counter[1] & !FB1_refresh_counter[2] & !FB1_refresh_counter[0] & FB1_refresh_counter[3];
--FB1_refresh_counter[7] is std_1s10:inst|sdram:the_sdram|refresh_counter[7] at LC_X41_Y3_N3
--operation mode is normal
FB1_refresh_counter[7]_lut_out = FB1L112 # !FB1L85;
FB1_refresh_counter[7] = DFFEAS(FB1_refresh_counter[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_refresh_counter[4] is std_1s10:inst|sdram:the_sdram|refresh_counter[4] at LC_X52_Y11_N0
--operation mode is normal
FB1_refresh_counter[4]_lut_out = !FB1L112 & FB1L88;
FB1_refresh_counter[4] = DFFEAS(FB1_refresh_counter[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_refresh_counter[5] is std_1s10:inst|sdram:the_sdram|refresh_counter[5] at LC_X52_Y12_N1
--operation mode is normal
FB1_refresh_counter[5]_lut_out = !FB1L112 & FB1L91;
FB1_refresh_counter[5] = DFFEAS(FB1_refresh_counter[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_refresh_counter[6] is std_1s10:inst|sdram:the_sdram|refresh_counter[6] at LC_X52_Y12_N8
--operation mode is normal
FB1_refresh_counter[6]_lut_out = !FB1L112 & FB1L93;
FB1_refresh_counter[6] = DFFEAS(FB1_refresh_counter[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L110 is std_1s10:inst|sdram:the_sdram|Equal1~167 at LC_X52_Y11_N3
--operation mode is normal
FB1L110 = FB1_refresh_counter[7] & !FB1_refresh_counter[6] & !FB1_refresh_counter[5] & !FB1_refresh_counter[4];
--FB1_refresh_counter[12] is std_1s10:inst|sdram:the_sdram|refresh_counter[12] at LC_X52_Y10_N8
--operation mode is normal
FB1_refresh_counter[12]_lut_out = FB1L112 # !FB1L96;
FB1_refresh_counter[12] = DFFEAS(FB1_refresh_counter[12]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_refresh_counter[8] is std_1s10:inst|sdram:the_sdram|refresh_counter[8] at LC_X52_Y9_N2
--operation mode is normal
FB1_refresh_counter[8]_lut_out = !FB1L97;
FB1_refresh_counter[8] = DFFEAS(FB1_refresh_counter[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_refresh_counter[9] is std_1s10:inst|sdram:the_sdram|refresh_counter[9] at LC_X52_Y13_N2
--operation mode is normal
FB1_refresh_counter[9]_lut_out = !FB1L100;
FB1_refresh_counter[9] = DFFEAS(FB1_refresh_counter[9]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_refresh_counter[10] is std_1s10:inst|sdram:the_sdram|refresh_counter[10] at LC_X52_Y10_N9
--operation mode is normal
FB1_refresh_counter[10]_lut_out = !FB1L112 & FB1L103;
FB1_refresh_counter[10] = DFFEAS(FB1_refresh_counter[10]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_refresh_counter[11] is std_1s10:inst|sdram:the_sdram|refresh_counter[11] at LC_X52_Y11_N2
--operation mode is normal
FB1_refresh_counter[11]_lut_out = !FB1L112 & FB1L105;
FB1_refresh_counter[11] = DFFEAS(FB1_refresh_counter[11]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L111 is std_1s10:inst|sdram:the_sdram|Equal1~168 at LC_X52_Y10_N7
--operation mode is normal
FB1L111 = !FB1_refresh_counter[11] & FB1_refresh_counter[8] & FB1_refresh_counter[9] & !FB1_refresh_counter[10];
--FB1L112 is std_1s10:inst|sdram:the_sdram|Equal1~169 at LC_X52_Y11_N1
--operation mode is normal
FB1L112 = FB1L111 & FB1L109 & FB1L110 & FB1_refresh_counter[12];
--FB1_ack_refresh_request is std_1s10:inst|sdram:the_sdram|ack_refresh_request at LC_X35_Y3_N9
--operation mode is normal
FB1_ack_refresh_request_lut_out = FB1L441 & (FB1_m_state[7] # FB1_ack_refresh_request & !FB1_init_done) # !FB1L441 & (FB1_ack_refresh_request);
FB1_ack_refresh_request = DFFEAS(FB1_ack_refresh_request_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L511 is std_1s10:inst|sdram:the_sdram|Mux39~1227 at LC_X32_Y3_N3
--operation mode is normal
FB1L511 = FB1L476 & (FB1_refresh_request # FB1L724 & EE1L127);
--FB1L486 is std_1s10:inst|sdram:the_sdram|Mux32~1273 at LC_X31_Y3_N2
--operation mode is normal
FB1L486 = FB1L476 & FB1_init_done & (FB1_m_next[7] # FB1_refresh_request) # !FB1L476 & FB1_m_next[7];
--FB1L487 is std_1s10:inst|sdram:the_sdram|Mux32~1274 at LC_X31_Y3_N3
--operation mode is normal
FB1L487 = FB1_m_next[7] & (FB1_m_state[4] # FB1_m_state[1] # !FB1L391);
--FB1L488 is std_1s10:inst|sdram:the_sdram|Mux32~1275 at LC_X31_Y4_N1
--operation mode is normal
FB1L488 = FB1_m_state[4] & (FB1_m_state[7] # !FB1_m_state[1] & FB1L391) # !FB1_m_state[4] & (FB1_m_state[1]);
--FB1L489 is std_1s10:inst|sdram:the_sdram|Mux32~1276 at LC_X31_Y3_N8
--operation mode is normal
FB1L489 = FB1_m_state[3] & FB1_m_state[7] # !FB1_m_state[3] & FB1_m_next[7] & (FB1_m_state[7] $ !FB1L488);
--FB1L490 is std_1s10:inst|sdram:the_sdram|Mux32~1277 at LC_X31_Y3_N9
--operation mode is normal
FB1L490 = FB1_m_state[3] & (FB1L489 & (FB1_m_next[7]) # !FB1L489 & FB1L487) # !FB1_m_state[3] & (FB1L489);
--FB1L491 is std_1s10:inst|sdram:the_sdram|Mux32~1278 at LC_X31_Y3_N5
--operation mode is normal
FB1L491 = FB1_m_state[0] & FB1L490 & !FB1_m_state[8] # !FB1_m_state[0] & (FB1_m_state[8] # FB1L486);
--FB1L512 is std_1s10:inst|sdram:the_sdram|Mux39~1228 at LC_X32_Y3_N8
--operation mode is normal
FB1L512 = !FB1_m_state[2] & !FB1_m_state[6] & (!FB1_m_state[5]);
--FB1L513 is std_1s10:inst|sdram:the_sdram|Mux39~1229 at LC_X31_Y2_N2
--operation mode is normal
FB1L513 = FB1L476 & (!FB1_m_next[0] & !FB1_refresh_request # !FB1_init_done) # !FB1L476 & !FB1_m_next[0];
--FB1L514 is std_1s10:inst|sdram:the_sdram|Mux39~1230 at LC_X31_Y2_N0
--operation mode is normal
FB1L514 = FB1_m_state[7] # FB1_m_state[1] & (FB1_m_state[3] # FB1_m_state[4]);
--FB1L515 is std_1s10:inst|sdram:the_sdram|Mux39~1231 at LC_X31_Y2_N5
--operation mode is normal
FB1L515 = FB1L514 & FB1L518 # !FB1L514 & (FB1L391 & FB1L434);
--FB1L516 is std_1s10:inst|sdram:the_sdram|Mux39~1232 at LC_X31_Y2_N3
--operation mode is normal
FB1L516 = FB1_m_next[0] & FB1L515 & !FB1_m_state[1] # !FB1_m_next[0] & (FB1L514 # !FB1_m_state[1]);
--FB1L517 is std_1s10:inst|sdram:the_sdram|Mux39~1233 at LC_X31_Y2_N8
--operation mode is normal
FB1L517 = FB1_m_state[0] & !FB1_m_state[8] & FB1L516 # !FB1_m_state[0] & (FB1_m_state[8] # FB1L513);
--FB1L506 is std_1s10:inst|sdram:the_sdram|Mux38~1199 at LC_X31_Y3_N4
--operation mode is normal
FB1L506 = FB1_m_next[1] & (FB1_init_done & !FB1_refresh_request # !FB1L476);
--FB1L507 is std_1s10:inst|sdram:the_sdram|Mux38~1200 at LC_X31_Y4_N4
--operation mode is normal
FB1L507 = FB1_m_next[1] & (FB1_m_state[1] # FB1_m_state[4] # !FB1L391);
--FB1L508 is std_1s10:inst|sdram:the_sdram|Mux38~1201 at LC_X31_Y4_N9
--operation mode is normal
FB1L508 = FB1_m_state[3] & FB1_m_state[7] # !FB1_m_state[3] & FB1_m_next[1] & (FB1_m_state[7] $ !FB1L488);
--FB1L509 is std_1s10:inst|sdram:the_sdram|Mux38~1202 at LC_X31_Y4_N0
--operation mode is normal
FB1L509 = FB1L508 & (FB1_m_next[1] # !FB1_m_state[3]) # !FB1L508 & FB1L507 & FB1_m_state[3];
--FB1L510 is std_1s10:inst|sdram:the_sdram|Mux38~1203 at LC_X31_Y3_N0
--operation mode is normal
FB1L510 = FB1_m_state[0] & FB1L509 & !FB1_m_state[8] # !FB1_m_state[0] & (FB1_m_state[8] # FB1L506);
--FB1L499 is std_1s10:inst|sdram:the_sdram|Mux36~1263 at LC_X32_Y4_N9
--operation mode is normal
FB1L499 = FB1_m_next[3] & (!FB1L618 # !FB1L392);
--FB1L500 is std_1s10:inst|sdram:the_sdram|Mux36~1264 at LC_X33_Y4_N1
--operation mode is normal
FB1L500 = FB1_m_state[4] & (FB1_m_next[3]) # !FB1_m_state[4] & (FB1_m_state[3] & (FB1_m_next[3]) # !FB1_m_state[3] & FB1_active_rnw);
--FB1L501 is std_1s10:inst|sdram:the_sdram|Mux36~1265 at LC_X31_Y4_N5
--operation mode is normal
FB1L501 = FB1_m_next[3] & (FB1_init_done & !FB1_refresh_request # !FB1L518);
--FB1L502 is std_1s10:inst|sdram:the_sdram|Mux36~1266 at LC_X31_Y4_N6
--operation mode is normal
FB1L502 = FB1_m_state[0] & !FB1_m_state[1] & FB1L505 # !FB1_m_state[0] & (FB1_m_state[1] # FB1L501);
--FB1L503 is std_1s10:inst|sdram:the_sdram|Mux36~1267 at LC_X33_Y4_N5
--operation mode is normal
FB1L503 = FB1L502 & (FB1_m_next[3] # !FB1_m_state[1]) # !FB1L502 & FB1_m_state[1] & FB1L500;
--FB1L504 is std_1s10:inst|sdram:the_sdram|Mux36~1268 at LC_X32_Y4_N5
--operation mode is normal
FB1L504 = FB1_m_state[8] & (FB1L499 # FB1_m_state[7]) # !FB1_m_state[8] & FB1L503 & (!FB1_m_state[7]);
--FB1L492 is std_1s10:inst|sdram:the_sdram|Mux35~1193 at LC_X32_Y4_N4
--operation mode is normal
FB1L492 = FB1_m_next[4] & (!FB1L618 # !FB1L392);
--FB1L493 is std_1s10:inst|sdram:the_sdram|Mux35~1194 at LC_X33_Y4_N2
--operation mode is normal
FB1L493 = FB1_m_state[4] & (FB1_m_next[4]) # !FB1_m_state[4] & (FB1_m_state[3] & (FB1_m_next[4]) # !FB1_m_state[3] & !FB1_active_rnw);
--FB1L494 is std_1s10:inst|sdram:the_sdram|Mux35~1195 at LC_X31_Y4_N2
--operation mode is normal
FB1L494 = FB1_m_next[4] & (!FB1_refresh_request & FB1_init_done # !FB1L518);
--FB1L495 is std_1s10:inst|sdram:the_sdram|Mux35~1196 at LC_X31_Y4_N3
--operation mode is normal
FB1L495 = FB1_m_state[0] & FB1L498 & !FB1_m_state[1] # !FB1_m_state[0] & (FB1_m_state[1] # FB1L494);
--FB1L496 is std_1s10:inst|sdram:the_sdram|Mux35~1197 at LC_X33_Y4_N8
--operation mode is normal
FB1L496 = FB1L495 & (FB1_m_next[4] # !FB1_m_state[1]) # !FB1L495 & FB1L493 & FB1_m_state[1];
--FB1L497 is std_1s10:inst|sdram:the_sdram|Mux35~1198 at LC_X32_Y4_N3
--operation mode is normal
FB1L497 = FB1_m_state[8] & (FB1L492 # FB1_m_state[7]) # !FB1_m_state[8] & (FB1L496 & !FB1_m_state[7]);
--L1_M_ipending_reg[2] is std_1s10:inst|cpu:the_cpu|M_ipending_reg[2] at LC_X47_Y20_N3
--operation mode is normal
L1_M_ipending_reg[2] = AMPP_FUNCTION(DE1__clk0, M1L304, L1_M_ienable_reg[2], SC1_internal_oci_ienable1[2], T1L64, E1_data_out);
--L1_M_ienable_reg[2] is std_1s10:inst|cpu:the_cpu|M_ienable_reg[2] at LC_X28_Y21_N7
--operation mode is normal
L1_M_ienable_reg[2] = AMPP_FUNCTION(DE1__clk0, L1L429, E1_data_out, L1L1187);
--L1_D_iw[8] is std_1s10:inst|cpu:the_cpu|D_iw[8] at LC_X25_Y20_N8
--operation mode is normal
L1_D_iw[8] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1L1132, KC1_q_b[8], L1_hbreak_enabled, E1_data_out, L1_W_stall);
--L1_D_iw[7] is std_1s10:inst|cpu:the_cpu|D_iw[7] at LC_X25_Y20_N5
--operation mode is normal
L1_D_iw[7] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[7], E1_data_out, L1_W_stall);
--L1_D_iw[6] is std_1s10:inst|cpu:the_cpu|D_iw[6] at LC_X25_Y20_N4
--operation mode is normal
L1_D_iw[6] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[6], E1_data_out, L1_W_stall);
--L1L205 is std_1s10:inst|cpu:the_cpu|D_control_rd_data_without_mmu_regs[2]~418 at LC_X29_Y21_N5
--operation mode is normal
L1L205 = AMPP_FUNCTION(L1_D_iw[7], L1_D_iw[6], L1_D_iw[8]);
--L1_D_iw[4] is std_1s10:inst|cpu:the_cpu|D_iw[4] at LC_X25_Y20_N7
--operation mode is normal
L1_D_iw[4] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[4], E1_data_out, L1_W_stall);
--L1_D_iw[15] is std_1s10:inst|cpu:the_cpu|D_iw[15] at LC_X25_Y20_N2
--operation mode is normal
L1_D_iw[15] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[15], E1_data_out, L1_W_stall);
--L1_D_iw[5] is std_1s10:inst|cpu:the_cpu|D_iw[5] at LC_X25_Y20_N3
--operation mode is normal
L1_D_iw[5] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, KC1_q_b[5], L1L1132, L1_hbreak_enabled, E1_data_out, L1_W_stall);
--L1_D_iw[0] is std_1s10:inst|cpu:the_cpu|D_iw[0] at LC_X25_Y20_N1
--operation mode is normal
L1_D_iw[0] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[0], E1_data_out, L1_W_stall);
--L1_D_iw[1] is std_1s10:inst|cpu:the_cpu|D_iw[1] at LC_X25_Y20_N6
--operation mode is normal
L1_D_iw[1] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[1], E1_data_out, L1_W_stall);
--L1_D_iw[2] is std_1s10:inst|cpu:the_cpu|D_iw[2] at LC_X25_Y20_N0
--operation mode is normal
L1_D_iw[2] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[2], E1_data_out, L1_W_stall);
--L1_D_iw[3] is std_1s10:inst|cpu:the_cpu|D_iw[3] at LC_X25_Y20_N9
--operation mode is normal
L1_D_iw[3] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[3], E1_data_out, L1_W_stall);
--L1L827 is std_1s10:inst|cpu:the_cpu|Equal53~781 at LC_X23_Y6_N4
--operation mode is normal
L1L827 = AMPP_FUNCTION(L1_D_iw[2], L1_D_iw[3], L1_D_iw[0], L1_D_iw[1]);
--MC1_q_b[2] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[2] at M4K_X15_Y17
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 32, Port B Depth: 32, Port B Width: 32
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
MC1_q_b[2] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[31] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[31] at M4K_X15_Y17
MC1_q_b[31] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[30] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[30] at M4K_X15_Y17
MC1_q_b[30] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[29] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[29] at M4K_X15_Y17
MC1_q_b[29] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[28] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[28] at M4K_X15_Y17
MC1_q_b[28] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[27] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[27] at M4K_X15_Y17
MC1_q_b[27] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[26] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[26] at M4K_X15_Y17
MC1_q_b[26] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[1] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[1] at M4K_X15_Y17
MC1_q_b[1] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[0] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[0] at M4K_X15_Y17
MC1_q_b[0] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[6] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[6] at M4K_X15_Y17
MC1_q_b[6] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[5] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[5] at M4K_X15_Y17
MC1_q_b[5] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[8] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[8] at M4K_X15_Y17
MC1_q_b[8] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[9] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[9] at M4K_X15_Y17
MC1_q_b[9] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[10] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[10] at M4K_X15_Y17
MC1_q_b[10] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[11] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[11] at M4K_X15_Y17
MC1_q_b[11] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[12] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[12] at M4K_X15_Y17
MC1_q_b[12] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[13] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[13] at M4K_X15_Y17
MC1_q_b[13] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[14] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[14] at M4K_X15_Y17
MC1_q_b[14] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[15] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[15] at M4K_X15_Y17
MC1_q_b[15] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[20] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[20] at M4K_X15_Y17
MC1_q_b[20] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[25] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[25] at M4K_X15_Y17
MC1_q_b[25] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[23] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[23] at M4K_X15_Y17
MC1_q_b[23] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[16] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[16] at M4K_X15_Y17
MC1_q_b[16] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[17] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[17] at M4K_X15_Y17
MC1_q_b[17] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[18] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[18] at M4K_X15_Y17
MC1_q_b[18] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[19] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[19] at M4K_X15_Y17
MC1_q_b[19] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[24] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[24] at M4K_X15_Y17
MC1_q_b[24] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[21] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[21] at M4K_X15_Y17
MC1_q_b[21] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[22] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[22] at M4K_X15_Y17
MC1_q_b[22] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[4] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[4] at M4K_X15_Y17
MC1_q_b[4] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[7] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[7] at M4K_X15_Y17
MC1_q_b[7] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--MC1_q_b[3] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|q_b[3] at M4K_X15_Y17
MC1_q_b[3] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1383, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[27], KC1_q_b[28], KC1_q_b[29], KC1_q_b[30], KC1_q_b[31], GND, GND, GND, GND, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1449, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1452, L1L1437, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1392, L1L1395, L1L1377, L1L1380, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--L1_D_iw[29] is std_1s10:inst|cpu:the_cpu|D_iw[29] at LC_X31_Y20_N6
--operation mode is normal
L1_D_iw[29] = AMPP_FUNCTION(DE1__clk0, L1L1132, L1_hbreak_enabled, KC1_q_b[29], L1_latched_oci_tb_hbreak_req, E1_data_out, L1_W_stall);
--L1_D_iw[28] is std_1s10:inst|cpu:the_cpu|D_iw[28] at LC_X17_Y20_N0
--operation mode is normal
L1_D_iw[28] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[28], E1_data_out, L1_W_stall);
--L1L390 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_W~37 at LC_X23_Y20_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L390 = AMPP_FUNCTION(L1_W_dst_regnum[2], L1_D_iw[28], L1_D_iw[29]);
--L1_W_dst_regnum[1] is std_1s10:inst|cpu:the_cpu|W_dst_regnum[1] at LC_X23_Y20_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_W_dst_regnum[1] = AMPP_FUNCTION(DE1__clk0, L1_M_dst_regnum[1], E1_data_out, GND, L1_W_stall);
--L1_D_iw[30] is std_1s10:inst|cpu:the_cpu|D_iw[30] at LC_X17_Y20_N1
--operation mode is normal
L1_D_iw[30] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[30], E1_data_out, L1_W_stall);
--L1_D_iw[27] is std_1s10:inst|cpu:the_cpu|D_iw[27] at LC_X17_Y20_N9
--operation mode is normal
L1_D_iw[27] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[27], E1_data_out, L1_W_stall);
--L1L391 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_W~38 at LC_X19_Y19_N4
--operation mode is normal
L1L391 = AMPP_FUNCTION(L1_D_iw[27], L1_W_dst_regnum[0], L1_D_iw[30], L1_W_dst_regnum[3]);
--L1_W_wr_dst_reg is std_1s10:inst|cpu:the_cpu|W_wr_dst_reg at LC_X17_Y18_N2
--operation mode is normal
L1_W_wr_dst_reg = AMPP_FUNCTION(DE1__clk0, L1_M_wr_dst_reg, E1_data_out, L1_W_stall);
--L1_D_iw[31] is std_1s10:inst|cpu:the_cpu|D_iw[31] at LC_X17_Y20_N4
--operation mode is normal
L1_D_iw[31] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[31], E1_data_out, L1_W_stall);
--L1L392 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_W~39 at LC_X18_Y19_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L392 = AMPP_FUNCTION(L1_D_iw[31], L1_W_wr_dst_reg);
--L1_W_dst_regnum[4] is std_1s10:inst|cpu:the_cpu|W_dst_regnum[4] at LC_X18_Y19_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_W_dst_regnum[4] = AMPP_FUNCTION(DE1__clk0, L1_M_dst_regnum[4], E1_data_out, GND, L1_W_stall);
--L1L206 is std_1s10:inst|cpu:the_cpu|D_ctrl_a_not_src~70 at LC_X22_Y6_N9
--operation mode is normal
L1L206 = AMPP_FUNCTION(L1_D_iw[5], L1_D_iw[4]);
--L1L207 is std_1s10:inst|cpu:the_cpu|D_ctrl_a_not_src~71 at LC_X23_Y6_N5
--operation mode is normal
L1L207 = AMPP_FUNCTION(L1_D_iw[3], L1_D_iw[2], L1L206, L1_D_iw[1]);
--L1_E_ctrl_jmp_direct is std_1s10:inst|cpu:the_cpu|E_ctrl_jmp_direct at LC_X23_Y6_N5
--operation mode is normal
L1_E_ctrl_jmp_direct = AMPP_FUNCTION(DE1__clk0, L1_D_iw[3], L1_D_iw[2], L1L206, L1_D_iw[1], E1_data_out, L1_W_stall);
--L1_D_src1_hazard_W is std_1s10:inst|cpu:the_cpu|D_src1_hazard_W at LC_X19_Y19_N2
--operation mode is normal
L1_D_src1_hazard_W = AMPP_FUNCTION(L1L391, L1L392, L1L390, L1L207);
--L1L386 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_M~37 at LC_X17_Y19_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L386 = AMPP_FUNCTION(L1_D_iw[28], L1_D_iw[29], L1_M_dst_regnum[2]);
--L1_M_dst_regnum[1] is std_1s10:inst|cpu:the_cpu|M_dst_regnum[1] at LC_X17_Y19_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_dst_regnum[1] = AMPP_FUNCTION(DE1__clk0, L1_E_dst_regnum[1], E1_data_out, GND, L1_W_stall);
--L1L387 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_M~38 at LC_X19_Y19_N5
--operation mode is normal
L1L387 = AMPP_FUNCTION(L1_D_iw[27], L1_M_dst_regnum[3], L1_D_iw[30], L1_M_dst_regnum[0]);
--L1_M_wr_dst_reg is std_1s10:inst|cpu:the_cpu|M_wr_dst_reg at LC_X19_Y17_N1
--operation mode is normal
L1_M_wr_dst_reg = AMPP_FUNCTION(DE1__clk0, L1L822, E1_data_out, L1_W_stall);
--L1L388 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_M~39 at LC_X17_Y19_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L388 = AMPP_FUNCTION(L1_M_wr_dst_reg, L1_D_iw[31]);
--L1_M_dst_regnum[4] is std_1s10:inst|cpu:the_cpu|M_dst_regnum[4] at LC_X17_Y19_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_dst_regnum[4] = AMPP_FUNCTION(DE1__clk0, L1_E_dst_regnum[4], E1_data_out, GND, L1_W_stall);
--L1_D_src1_hazard_M is std_1s10:inst|cpu:the_cpu|D_src1_hazard_M at LC_X19_Y19_N6
--operation mode is normal
L1_D_src1_hazard_M = AMPP_FUNCTION(L1L388, L1L207, L1L386, L1L387);
--L1_E_wr_dst_reg_from_D is std_1s10:inst|cpu:the_cpu|E_wr_dst_reg_from_D at LC_X18_Y18_N6
--operation mode is normal
L1_E_wr_dst_reg_from_D = AMPP_FUNCTION(DE1__clk0, L1L251, L1L848, L1L420, L1L255, E1_data_out, L1_W_stall);
--L1L821 is std_1s10:inst|cpu:the_cpu|E_wr_dst_reg~35 at LC_X18_Y18_N1
--operation mode is normal
L1L821 = AMPP_FUNCTION(L1_M_pipe_flush, L1_E_wr_dst_reg_from_D);
--L1L822 is std_1s10:inst|cpu:the_cpu|E_wr_dst_reg~36 at LC_X32_Y24_N8
--operation mode is normal
L1L822 = AMPP_FUNCTION(L1L503, L1L1005, L1L821, L1L502);
--L1L382 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_E~52 at LC_X17_Y19_N5
--operation mode is normal
L1L382 = AMPP_FUNCTION(L1_D_iw[31], L1_E_dst_regnum[4], L1_D_iw[28], L1_E_dst_regnum[1]);
--L1_E_dst_regnum[2] is std_1s10:inst|cpu:the_cpu|E_dst_regnum[2] at LC_X18_Y19_N5
--operation mode is normal
L1_E_dst_regnum[2] = AMPP_FUNCTION(DE1__clk0, L1_D_ctrl_b_not_src, L1_D_iw[19], L1L254, L1_D_iw[24], E1_data_out, L1_W_stall);
--L1L383 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_E~53 at LC_X17_Y19_N6
--operation mode is normal
L1L383 = AMPP_FUNCTION(L1L382, L1_D_iw[29], L1_E_dst_regnum[2]);
--L1_E_dst_regnum[3] is std_1s10:inst|cpu:the_cpu|E_dst_regnum[3] at LC_X18_Y20_N3
--operation mode is normal
L1_E_dst_regnum[3] = AMPP_FUNCTION(DE1__clk0, L1_D_ctrl_b_not_src, L1L254, L1_D_iw[20], L1_D_iw[25], E1_data_out, L1_W_stall);
--L1_E_dst_regnum[0] is std_1s10:inst|cpu:the_cpu|E_dst_regnum[0] at LC_X18_Y20_N8
--operation mode is normal
L1_E_dst_regnum[0] = AMPP_FUNCTION(DE1__clk0, L1_D_ctrl_b_not_src, L1_D_iw[22], L1L254, L1_D_iw[17], E1_data_out, L1_W_stall);
--L1L384 is std_1s10:inst|cpu:the_cpu|D_src1_hazard_E~54 at LC_X18_Y20_N7
--operation mode is normal
L1L384 = AMPP_FUNCTION(L1_D_iw[30], L1_D_iw[27], L1_E_dst_regnum[3], L1_E_dst_regnum[0]);
--QC1_result[0] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[0] at DSPOUT_X11_Y9_N0
--DSP Block Operation Mode: Simple Multiplier (36-bit)
QC1_result[0] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[1] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[1] at DSPOUT_X11_Y9_N0
QC1_result[1] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[2] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[2] at DSPOUT_X11_Y9_N0
QC1_result[2] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[3] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[3] at DSPOUT_X11_Y9_N0
QC1_result[3] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[4] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[4] at DSPOUT_X11_Y9_N0
QC1_result[4] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[5] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[5] at DSPOUT_X11_Y9_N0
QC1_result[5] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[6] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[6] at DSPOUT_X11_Y9_N0
QC1_result[6] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[7] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[7] at DSPOUT_X11_Y9_N0
QC1_result[7] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[8] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[8] at DSPOUT_X11_Y9_N0
QC1_result[8] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[9] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[9] at DSPOUT_X11_Y9_N0
QC1_result[9] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[10] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[10] at DSPOUT_X11_Y9_N0
QC1_result[10] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[11] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[11] at DSPOUT_X11_Y9_N0
QC1_result[11] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[12] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[12] at DSPOUT_X11_Y9_N0
QC1_result[12] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[13] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[13] at DSPOUT_X11_Y9_N0
QC1_result[13] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[14] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[14] at DSPOUT_X11_Y9_N0
QC1_result[14] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[15] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[15] at DSPOUT_X11_Y9_N0
QC1_result[15] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[16] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[16] at DSPOUT_X11_Y9_N0
QC1_result[16] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[17] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[17] at DSPOUT_X11_Y9_N0
QC1_result[17] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[18] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[18] at DSPOUT_X11_Y9_N0
QC1_result[18] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[19] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[19] at DSPOUT_X11_Y9_N0
QC1_result[19] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[20] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[20] at DSPOUT_X11_Y9_N0
QC1_result[20] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[21] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[21] at DSPOUT_X11_Y9_N0
QC1_result[21] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[22] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[22] at DSPOUT_X11_Y9_N0
QC1_result[22] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[23] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[23] at DSPOUT_X11_Y9_N0
QC1_result[23] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[24] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[24] at DSPOUT_X11_Y9_N0
QC1_result[24] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[25] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[25] at DSPOUT_X11_Y9_N0
QC1_result[25] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[26] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[26] at DSPOUT_X11_Y9_N0
QC1_result[26] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[27] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[27] at DSPOUT_X11_Y9_N0
QC1_result[27] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[28] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[28] at DSPOUT_X11_Y9_N0
QC1_result[28] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[29] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[29] at DSPOUT_X11_Y9_N0
QC1_result[29] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[30] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[30] at DSPOUT_X11_Y9_N0
QC1_result[30] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[31] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[31] at DSPOUT_X11_Y9_N0
QC1_result[31] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[32] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[32] at DSPOUT_X11_Y9_N0
QC1_result[32] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[33] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[33] at DSPOUT_X11_Y9_N0
QC1_result[33] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[34] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[34] at DSPOUT_X11_Y9_N0
QC1_result[34] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[35] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[35] at DSPOUT_X11_Y9_N0
QC1_result[35] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[36] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[36] at DSPOUT_X11_Y9_N0
QC1_result[36] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[37] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[37] at DSPOUT_X11_Y9_N0
QC1_result[37] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[38] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[38] at DSPOUT_X11_Y9_N0
QC1_result[38] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[39] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[39] at DSPOUT_X11_Y9_N0
QC1_result[39] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[40] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[40] at DSPOUT_X11_Y9_N0
QC1_result[40] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[41] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[41] at DSPOUT_X11_Y9_N0
QC1_result[41] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[42] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[42] at DSPOUT_X11_Y9_N0
QC1_result[42] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[43] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[43] at DSPOUT_X11_Y9_N0
QC1_result[43] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[44] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[44] at DSPOUT_X11_Y9_N0
QC1_result[44] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[45] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[45] at DSPOUT_X11_Y9_N0
QC1_result[45] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[46] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[46] at DSPOUT_X11_Y9_N0
QC1_result[46] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[47] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[47] at DSPOUT_X11_Y9_N0
QC1_result[47] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[48] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[48] at DSPOUT_X11_Y9_N0
QC1_result[48] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[49] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[49] at DSPOUT_X11_Y9_N0
QC1_result[49] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[50] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[50] at DSPOUT_X11_Y9_N0
QC1_result[50] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[51] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[51] at DSPOUT_X11_Y9_N0
QC1_result[51] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[52] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[52] at DSPOUT_X11_Y9_N0
QC1_result[52] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[53] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[53] at DSPOUT_X11_Y9_N0
QC1_result[53] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[54] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[54] at DSPOUT_X11_Y9_N0
QC1_result[54] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[55] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[55] at DSPOUT_X11_Y9_N0
QC1_result[55] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[56] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[56] at DSPOUT_X11_Y9_N0
QC1_result[56] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[57] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[57] at DSPOUT_X11_Y9_N0
QC1_result[57] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[58] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[58] at DSPOUT_X11_Y9_N0
QC1_result[58] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[59] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[59] at DSPOUT_X11_Y9_N0
QC1_result[59] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[60] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[60] at DSPOUT_X11_Y9_N0
QC1_result[60] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[61] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[61] at DSPOUT_X11_Y9_N0
QC1_result[61] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[62] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[62] at DSPOUT_X11_Y9_N0
QC1_result[62] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--QC1_result[63] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|result[63] at DSPOUT_X11_Y9_N0
QC1_result[63] = AMPP_FUNCTION(GND, GND, QC1_mac_mult1, QC1L2, QC1L3, QC1L4, QC1L5, QC1L6, QC1L7, QC1L8, QC1L9, QC1L10, QC1L11, QC1L12, QC1L13, QC1L14, QC1L15, QC1L16, QC1L17, QC1L18, QC1L19, QC1L20, QC1L21, QC1L22, QC1L23, QC1L24, QC1L25, QC1L26, QC1L27, QC1L28, QC1L29, QC1L30, QC1L31, QC1L32, QC1L33, QC1L34, QC1L35, QC1L36, QC1_mac_mult2, QC1L110, QC1L111, QC1L112, QC1L113, QC1L114, QC1L115, QC1L116, QC1L117, QC1L118, QC1L119, QC1L120, QC1L121, QC1L122, QC1L123, QC1L124, QC1L125, QC1L126, QC1L127, QC1L128, QC1L129, QC1L130, QC1L131, QC1L132, QC1L133, QC1L134, QC1L135, QC1L136, QC1L137, QC1L138, QC1L139, QC1L140, QC1L141, QC1L142, QC1L143, QC1L144, QC1_mac_mult3, QC1L218, QC1L219, QC1L220, QC1L221, QC1L222, QC1L223, QC1L224, QC1L225, QC1L226, QC1L227, QC1L228, QC1L229, QC1L230, QC1L231, QC1L232, QC1L233, QC1L234, QC1L235, QC1L236, QC1L237, QC1L238, QC1L239, QC1L240, QC1L241, QC1L242, QC1L243, QC1L244, QC1L245, QC1L246, QC1L247, QC1L248, QC1L249, QC1L250, QC1L251, QC1L252, QC1_mac_mult4, QC1L326, QC1L327, QC1L328, QC1L329, QC1L330, QC1L331, QC1L332, QC1L333, QC1L334, QC1L335, QC1L336, QC1L337, QC1L338, QC1L339, QC1L340, QC1L341, QC1L342, QC1L343, QC1L344, QC1L345, QC1L346, QC1L347, QC1L348, QC1L349, QC1L350, QC1L351, QC1L352, QC1L353, QC1L354, QC1L355, QC1L356, QC1L357, QC1L358, QC1L359, QC1L360, DE1__clk0, E1_data_out, GND);
--L1L1255 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[2]~1344 at LC_X13_Y16_N1
--operation mode is normal
L1L1255 = AMPP_FUNCTION(QC1_result[34], QC1_result[2]);
--L1_M_ctrl_shift_right is std_1s10:inst|cpu:the_cpu|M_ctrl_shift_right at LC_X33_Y12_N5
--operation mode is normal
L1_M_ctrl_shift_right = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_shift_right, E1_data_out, L1_W_stall);
--L1_M_shift_rot_by_zero is std_1s10:inst|cpu:the_cpu|M_shift_rot_by_zero at LC_X13_Y12_N9
--operation mode is normal
L1_M_shift_rot_by_zero = AMPP_FUNCTION(DE1__clk0, L1L672, L1L849, L1L673, E1_data_out, L1_W_stall);
--L1L1284 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[31]~1345 at LC_X17_Y19_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L1284 = AMPP_FUNCTION(L1_M_ctrl_shift_right, L1_M_shift_rot_by_zero);
--L1_M_ctrl_mulx is std_1s10:inst|cpu:the_cpu|M_ctrl_mulx at LC_X17_Y19_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_ctrl_mulx = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_mulx, E1_data_out, GND, L1_W_stall);
--L1_M_ctrl_rot is std_1s10:inst|cpu:the_cpu|M_ctrl_rot at LC_X17_Y11_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_ctrl_rot = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_rot, E1_data_out, GND, L1_W_stall);
--L1_E_ctrl_mul_shift_rot is std_1s10:inst|cpu:the_cpu|E_ctrl_mul_shift_rot at LC_X19_Y10_N4
--operation mode is normal
L1_E_ctrl_mul_shift_rot = AMPP_FUNCTION(DE1__clk0, L1L222, L1L240, L1L248, L1L241, E1_data_out, L1_W_stall);
--L1_d_readdata_d1[2] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[2] at LC_X40_Y20_N8
--operation mode is normal
L1_d_readdata_d1[2] = AMPP_FUNCTION(DE1__clk0, M1L44, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L5, FC1L6, E1_data_out);
--L1_d_readdata_d1[18] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[18] at LC_X45_Y16_N2
--operation mode is normal
L1_d_readdata_d1[18] = AMPP_FUNCTION(DE1__clk0, P1_cpu_data_master_requests_cpu_jtag_debug_module, M1L160, FC1L22, FC1L21, E1_data_out);
--L1_M_ld_align_sh16 is std_1s10:inst|cpu:the_cpu|M_ld_align_sh16 at LC_X24_Y20_N4
--operation mode is normal
L1_M_ld_align_sh16 = AMPP_FUNCTION(L1_M_alu_result[1], L1_M_iw[4]);
--L1_M_ld_align_sh8 is std_1s10:inst|cpu:the_cpu|M_ld_align_sh8 at LC_X23_Y20_N5
--operation mode is normal
L1_M_ld_align_sh8 = AMPP_FUNCTION(L1_M_iw[4], L1_M_alu_result[0], L1_M_iw[3]);
--L1_av_ld_aligning_data is std_1s10:inst|cpu:the_cpu|av_ld_aligning_data at LC_X27_Y21_N3
--operation mode is normal
L1_av_ld_aligning_data = AMPP_FUNCTION(DE1__clk0, L1_internal_d_read, M1_internal_cpu_data_master_waitrequest, E1_data_out);
--L1L235 is std_1s10:inst|cpu:the_cpu|D_ctrl_hi_imm~98 at LC_X21_Y6_N1
--operation mode is normal
L1L235 = AMPP_FUNCTION(L1_D_iw[3], L1_D_iw[4], L1_D_iw[0], L1_D_iw[1]);
--L1_E_src2_prelim[2] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[2] at LC_X17_Y17_N3
--operation mode is normal
L1_E_src2_prelim[2] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[2], L1L403, L1L1383, L1_W_wr_data[2], E1_data_out, L1L399, L1_W_stall);
--L1L845 is std_1s10:inst|cpu:the_cpu|Equal143~6 at LC_X23_Y20_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L845 = AMPP_FUNCTION(L1_E_iw[4]);
--L1_E_iw[3] is std_1s10:inst|cpu:the_cpu|E_iw[3] at LC_X23_Y20_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[3] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[3], E1_data_out, GND, L1_W_stall);
--L1L214 is std_1s10:inst|cpu:the_cpu|D_ctrl_b_is_dst~79 at LC_X21_Y6_N6
--operation mode is normal
L1L214 = AMPP_FUNCTION(L1_D_iw[5], L1_D_iw[4], L1_D_iw[0], L1_D_iw[1]);
--L1L216 is std_1s10:inst|cpu:the_cpu|D_ctrl_b_not_src~56 at LC_X21_Y6_N7
--operation mode is normal
L1L216 = AMPP_FUNCTION(L1_D_iw[1], L1_D_iw[2], L1_D_iw[0], L1L214);
--L1L828 is std_1s10:inst|cpu:the_cpu|Equal53~782 at LC_X23_Y6_N9
--operation mode is normal
L1L828 = AMPP_FUNCTION(L1_D_iw[2], L1_D_iw[3], L1_D_iw[0], L1_D_iw[1]);
--L1L829 is std_1s10:inst|cpu:the_cpu|Equal53~783 at LC_X19_Y18_N2
--operation mode is normal
L1L829 = AMPP_FUNCTION(L1_D_iw[4], L1_D_iw[5], L1L828);
--L1_D_iw[12] is std_1s10:inst|cpu:the_cpu|D_iw[12] at LC_X31_Y20_N7
--operation mode is normal
L1_D_iw[12] = AMPP_FUNCTION(DE1__clk0, L1L1132, L1_hbreak_enabled, KC1_q_b[12], L1_latched_oci_tb_hbreak_req, E1_data_out, L1_W_stall);
--L1L830 is std_1s10:inst|cpu:the_cpu|Equal53~784 at LC_X19_Y18_N9
--operation mode is normal
L1L830 = AMPP_FUNCTION(L1_D_iw[5], L1_D_iw[4]);
--L1_D_iw[11] is std_1s10:inst|cpu:the_cpu|D_iw[11] at LC_X17_Y20_N2
--operation mode is normal
L1_D_iw[11] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[11], E1_data_out, L1_W_stall);
--L1L247 is std_1s10:inst|cpu:the_cpu|D_ctrl_wrctl_inst~23 at LC_X19_Y7_N7
--operation mode is normal
L1L247 = AMPP_FUNCTION(L1L830, L1_D_iw[12], L1L827, L1_D_iw[11]);
--L1_D_iw[16] is std_1s10:inst|cpu:the_cpu|D_iw[16] at LC_X17_Y20_N5
--operation mode is normal
L1_D_iw[16] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[16], L1_hbreak_enabled, L1L1132, L1_latched_oci_tb_hbreak_req, E1_data_out, L1_W_stall);
--L1_D_iw[14] is std_1s10:inst|cpu:the_cpu|D_iw[14] at LC_X17_Y20_N3
--operation mode is normal
L1_D_iw[14] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[14], E1_data_out, L1_W_stall);
--L1_D_iw[13] is std_1s10:inst|cpu:the_cpu|D_iw[13] at LC_X17_Y20_N8
--operation mode is normal
L1_D_iw[13] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[13], E1_data_out, L1_W_stall);
--L1L838 is std_1s10:inst|cpu:the_cpu|Equal77~562 at LC_X22_Y21_N7
--operation mode is normal
L1L838 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[13], L1_D_iw[15], L1_D_iw[14]);
--L1L839 is std_1s10:inst|cpu:the_cpu|Equal77~563 at LC_X22_Y21_N0
--operation mode is normal
L1L839 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[13], L1_D_iw[15], L1_D_iw[14]);
--L1L840 is std_1s10:inst|cpu:the_cpu|Equal77~564 at LC_X19_Y7_N3
--operation mode is normal
L1L840 = AMPP_FUNCTION(L1_D_iw[15], L1_D_iw[13], L1_D_iw[16], L1_D_iw[14]);
--L1L222 is std_1s10:inst|cpu:the_cpu|D_ctrl_dst_data_sel_cmp~271 at LC_X19_Y10_N7
--operation mode is normal
L1L222 = AMPP_FUNCTION(L1L225, L1L212);
--L1L831 is std_1s10:inst|cpu:the_cpu|Equal53~785 at LC_X23_Y6_N1
--operation mode is normal
L1L831 = AMPP_FUNCTION(L1_D_iw[3], L1_D_iw[1], L1_D_iw[0], L1_D_iw[2]);
--L1_D_br_taken_waddr_partial[0] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[0] at LC_X35_Y20_N5
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[0] = AMPP_FUNCTION(DE1__clk0, L1L933, KC1_q_b[8], E1_data_out, L1_W_stall);
--L1L175 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[0]~55 at LC_X35_Y20_N5
--operation mode is arithmetic
L1L175 = AMPP_FUNCTION(L1L933, KC1_q_b[8]);
--L1L176 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[0]~55COUT1_108 at LC_X35_Y20_N5
--operation mode is arithmetic
L1L176 = AMPP_FUNCTION(L1L933, KC1_q_b[8]);
--L1L217 is std_1s10:inst|cpu:the_cpu|D_ctrl_br_cond~92 at LC_X19_Y18_N1
--operation mode is normal
L1L217 = AMPP_FUNCTION(L1_D_iw[4], L1_D_iw[5], L1_D_iw[3], L1_D_iw[2]);
--L1L218 is std_1s10:inst|cpu:the_cpu|D_ctrl_br_cond~93 at LC_X19_Y18_N4
--operation mode is normal
L1L218 = AMPP_FUNCTION(L1_D_iw[0], L1L217, L1_D_iw[1]);
--L1_D_iw[21] is std_1s10:inst|cpu:the_cpu|D_iw[21] at LC_X17_Y20_N7
--operation mode is normal
L1_D_iw[21] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1_hbreak_enabled, L1L1132, KC1_q_b[21], E1_data_out, L1_W_stall);
--L1_E_ctrl_alu_subtract is std_1s10:inst|cpu:the_cpu|E_ctrl_alu_subtract at LC_X18_Y9_N5
--operation mode is normal
L1_E_ctrl_alu_subtract = AMPP_FUNCTION(DE1__clk0, L1L238, L1L210, L1L211, E1_data_out, L1_W_stall);
--L1L841 is std_1s10:inst|cpu:the_cpu|Equal77~565 at LC_X18_Y7_N1
--operation mode is normal
L1L841 = AMPP_FUNCTION(L1_D_iw[15], L1_D_iw[16], L1_D_iw[13], L1_D_iw[14]);
--L1L842 is std_1s10:inst|cpu:the_cpu|Equal77~566 at LC_X22_Y21_N8
--operation mode is normal
L1L842 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[13], L1_D_iw[15], L1_D_iw[14]);
--L1L843 is std_1s10:inst|cpu:the_cpu|Equal77~567 at LC_X22_Y21_N2
--operation mode is normal
L1L843 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[13], L1_D_iw[15], L1_D_iw[14]);
--L1L844 is std_1s10:inst|cpu:the_cpu|Equal77~568 at LC_X18_Y7_N6
--operation mode is normal
L1L844 = AMPP_FUNCTION(L1_D_iw[15], L1_D_iw[16], L1_D_iw[13], L1_D_iw[14]);
--L1L832 is std_1s10:inst|cpu:the_cpu|Equal53~786 at LC_X23_Y6_N6
--operation mode is normal
L1L832 = AMPP_FUNCTION(L1_D_iw[3], L1_D_iw[1], L1_D_iw[0], L1_D_iw[2]);
--L1L833 is std_1s10:inst|cpu:the_cpu|Equal53~787 at LC_X23_Y6_N8
--operation mode is normal
L1L833 = AMPP_FUNCTION(L1_D_iw[3], L1_D_iw[1], L1_D_iw[0], L1_D_iw[2]);
--L1L226 is std_1s10:inst|cpu:the_cpu|D_ctrl_dst_data_sel_logic_result~47 at LC_X23_Y6_N0
--operation mode is normal
L1L226 = AMPP_FUNCTION(L1L832, L1_D_iw[4], L1L833);
--L1L834 is std_1s10:inst|cpu:the_cpu|Equal53~788 at LC_X21_Y6_N8
--operation mode is normal
L1L834 = AMPP_FUNCTION(L1_D_iw[3], L1_D_iw[2], L1_D_iw[0], L1_D_iw[1]);
--L1L223 is std_1s10:inst|cpu:the_cpu|D_ctrl_dst_data_sel_cmp~272 at LC_X22_Y6_N2
--operation mode is normal
L1L223 = AMPP_FUNCTION(L1_D_iw[5], L1L834, L1_D_iw[4], L1L837);
--L1L224 is std_1s10:inst|cpu:the_cpu|D_ctrl_dst_data_sel_cmp~273 at LC_X22_Y6_N0
--operation mode is normal
L1L224 = AMPP_FUNCTION(L1L827, L1_D_iw[12], L1_D_iw[11], L1L830);
--L1_M_valid_mul_shift_rot_entered_M is std_1s10:inst|cpu:the_cpu|M_valid_mul_shift_rot_entered_M at LC_X27_Y22_N6
--operation mode is normal
L1_M_valid_mul_shift_rot_entered_M = AMPP_FUNCTION(DE1__clk0, L1L819, L1_E_ctrl_mul_shift_rot, L1_W_stall, E1_data_out);
--L1_M_ipending_reg[3] is std_1s10:inst|cpu:the_cpu|M_ipending_reg[3] at LC_X50_Y9_N2
--operation mode is normal
L1_M_ipending_reg[3] = AMPP_FUNCTION(DE1__clk0, HE1_irq, SC1_internal_oci_ienable1[3], L1_M_ienable_reg[3], E1_data_out);
--L1_M_ienable_reg[3] is std_1s10:inst|cpu:the_cpu|M_ienable_reg[3] at LC_X29_Y21_N1
--operation mode is normal
L1_M_ienable_reg[3] = AMPP_FUNCTION(DE1__clk0, L1L430, E1_data_out, L1L1187);
--L1L1256 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[3]~1346 at LC_X13_Y16_N3
--operation mode is normal
L1L1256 = AMPP_FUNCTION(QC1_result[35], QC1_result[3]);
--L1_d_readdata_d1[3] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[3] at LC_X44_Y21_N8
--operation mode is normal
L1_d_readdata_d1[3] = AMPP_FUNCTION(DE1__clk0, FC1L8, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L7, M1L53, E1_data_out);
--L1_d_readdata_d1[19] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[19] at LC_X46_Y20_N6
--operation mode is normal
L1_d_readdata_d1[19] = AMPP_FUNCTION(DE1__clk0, M1L165, FC1L23, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L21, E1_data_out);
--L1_D_iw[9] is std_1s10:inst|cpu:the_cpu|D_iw[9] at LC_X31_Y20_N9
--operation mode is normal
L1_D_iw[9] = AMPP_FUNCTION(DE1__clk0, L1L1132, L1_hbreak_enabled, KC1_q_b[9], L1_latched_oci_tb_hbreak_req, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[3] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[3] at LC_X19_Y21_N2
--operation mode is normal
L1_E_src2_prelim[3] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[3], L1L403, L1L1386, L1_W_wr_data[3], E1_data_out, L1L399, L1_W_stall);
--L1_D_br_taken_waddr_partial[1] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[1] at LC_X35_Y20_N6
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[1] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[9], L1L936, E1_data_out, L1_W_stall, L1L175, L1L176);
--L1L178 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[1]~56 at LC_X35_Y20_N6
--operation mode is arithmetic
L1L178 = AMPP_FUNCTION(KC1_q_b[9], L1L936, L1L175);
--L1L179 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[1]~56COUT1_110 at LC_X35_Y20_N6
--operation mode is arithmetic
L1L179 = AMPP_FUNCTION(KC1_q_b[9], L1L936, L1L176);
--L1_D_br_taken_waddr_partial[5] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[5] at LC_X35_Y19_N0
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[5] = AMPP_FUNCTION(DE1__clk0, L1L947, KC1_q_b[13], E1_data_out, L1_W_stall, L1L187);
--L1L189 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[5]~57 at LC_X35_Y19_N0
--operation mode is arithmetic
L1L189 = AMPP_FUNCTION(L1L947, KC1_q_b[13]);
--L1L190 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[5]~57COUT1_116 at LC_X35_Y19_N0
--operation mode is arithmetic
L1L190 = AMPP_FUNCTION(L1L947, KC1_q_b[13]);
--L1L1260 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[7]~1347 at LC_X12_Y17_N3
--operation mode is normal
L1L1260 = AMPP_FUNCTION(QC1_result[7], QC1_result[39]);
--L1_d_readdata_d1[7] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[7] at LC_X46_Y14_N4
--operation mode is normal
L1_d_readdata_d1[7] = AMPP_FUNCTION(DE1__clk0, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L10, M1L87, FC1L21, E1_data_out);
--L1_d_readdata_d1[23] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[23] at LC_X45_Y19_N4
--operation mode is normal
L1_d_readdata_d1[23] = AMPP_FUNCTION(DE1__clk0, FC1L21, FC1L27, P1_cpu_data_master_requests_cpu_jtag_debug_module, M1L185, E1_data_out);
--L1_E_src2_prelim[7] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[7] at LC_X17_Y17_N6
--operation mode is normal
L1_E_src2_prelim[7] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[7], NC1_q_b[7], L1L1398, L1L403, E1_data_out, L1L399, L1_W_stall);
--L1_D_issue is std_1s10:inst|cpu:the_cpu|D_issue at LC_X35_Y16_N6
--operation mode is normal
L1_D_issue = AMPP_FUNCTION(DE1__clk0, L1L876, L1L880, L1_F_kill, L1L881, E1_data_out, L1_W_stall);
--L1_E_ctrl_flush_pipe_always is std_1s10:inst|cpu:the_cpu|E_ctrl_flush_pipe_always at LC_X22_Y6_N8
--operation mode is normal
L1_E_ctrl_flush_pipe_always = AMPP_FUNCTION(DE1__clk0, L1L229, L1L232, L1L836, E1_data_out, L1_W_stall);
--GC1L1 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~558 at LC_X14_Y10_N6
--operation mode is normal
GC1L1 = AMPP_FUNCTION(GC1L6, GC1L3, GC1L4);
--HC1_result[32] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[32] at LC_X18_Y9_N2
--operation mode is normal
HC1_result[32] = AMPP_FUNCTION(GND, HC1L85, HC1L90, HC1L91, L1_E_ctrl_alu_subtract);
--L1L435 is std_1s10:inst|cpu:the_cpu|E_br_actually_taken~243 at LC_X27_Y21_N7
--operation mode is normal
L1L435 = AMPP_FUNCTION(HC1_result[32], L1_E_logic_op[0], L1_E_logic_op[1], GC1L1);
--L1L1288 is std_1s10:inst|cpu:the_cpu|M_pipe_flush_nxt~105 at LC_X27_Y21_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L1288 = AMPP_FUNCTION(L1L435, L1_E_iw[21]);
--L1_E_ctrl_br_cond is std_1s10:inst|cpu:the_cpu|E_ctrl_br_cond at LC_X27_Y21_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_ctrl_br_cond = AMPP_FUNCTION(DE1__clk0, L1L218, E1_data_out, GND, L1_W_stall);
--VC1_probepresent is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|probepresent at LC_X32_Y24_N6
--operation mode is normal
VC1_probepresent = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[19], DD1_internal_jdo1[18], VC1_probepresent, !C1_CLR_SIGNAL, DD1L190);
--DD1_internal_jdo1[20] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[20] at LC_X32_Y24_N1
--operation mode is normal
DD1_internal_jdo1[20] = AMPP_FUNCTION(!A1L9, DD1_sr[20], VCC, DD1L144);
--VC1L1 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|A_WE_StdLogicVector~9 at LC_X32_Y24_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
VC1L1 = AMPP_FUNCTION(DD1_internal_jdo1[20], VC1_jtag_break);
--DD1_internal_jdo1[21] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[21] at LC_X32_Y24_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[21] = AMPP_FUNCTION(!A1L9, DD1_sr[21], VCC, GND, DD1L144);
--C1_CLR_SIGNAL is sld_hub:sld_hub_inst|CLR_SIGNAL at LC_X28_Y4_N2
--operation mode is normal
C1_CLR_SIGNAL = AMPP_FUNCTION(!A1L6, ME1_Q[0], RE1_state[1], VCC);
--DD1_jxdr is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|jxdr at LC_X33_Y28_N6
--operation mode is normal
DD1_jxdr = AMPP_FUNCTION(DE1__clk0, DD1_dr_update1, DD1_dr_update2, VCC);
--DD1L189 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_a~42 at LC_X34_Y25_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1L189 = AMPP_FUNCTION(DD1_jxdr, DD1_ir[1], DD1_ir[0]);
--DD1_internal_jdo1[35] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[35] at LC_X34_Y25_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[35] = AMPP_FUNCTION(!A1L9, DD1_sr[35], VCC, GND, DD1L144);
--DD1L190 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_a~43 at LC_X34_Y25_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1L190 = AMPP_FUNCTION(DD1L189);
--DD1_internal_jdo1[34] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[34] at LC_X34_Y25_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[34] = AMPP_FUNCTION(!A1L9, DD1_sr[34], VCC, GND, DD1L144);
--L1L999 is std_1s10:inst|cpu:the_cpu|hbreak_enabled~268 at LC_X23_Y20_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L999 = AMPP_FUNCTION(L1_M_ctrl_break, L1_M_iw[3], L1_M_iw[4]);
--L1_M_iw[5] is std_1s10:inst|cpu:the_cpu|M_iw[5] at LC_X23_Y20_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_iw[5] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[5], E1_data_out, GND, L1_W_stall);
--L1L1000 is std_1s10:inst|cpu:the_cpu|hbreak_enabled~269 at LC_X27_Y22_N0
--operation mode is normal
L1L1000 = AMPP_FUNCTION(KB1L7, L1L999, L1L1480, L1_M_valid_from_E);
--L1_M_iw[2] is std_1s10:inst|cpu:the_cpu|M_iw[2] at LC_X14_Y17_N2
--operation mode is normal
L1_M_iw[2] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[2], E1_data_out, L1_W_stall);
--L1_M_iw[0] is std_1s10:inst|cpu:the_cpu|M_iw[0] at LC_X17_Y16_N3
--operation mode is normal
L1_M_iw[0] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[0], E1_data_out, L1_W_stall);
--L1_M_iw[16] is std_1s10:inst|cpu:the_cpu|M_iw[16] at LC_X25_Y21_N0
--operation mode is normal
L1_M_iw[16] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[16], E1_data_out, L1_W_stall);
--L1L1001 is std_1s10:inst|cpu:the_cpu|hbreak_enabled~270 at LC_X25_Y22_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L1001 = AMPP_FUNCTION(L1_M_iw[0], L1_M_iw[2], L1_M_iw[16]);
--L1_M_iw[1] is std_1s10:inst|cpu:the_cpu|M_iw[1] at LC_X25_Y22_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_iw[1] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[1], E1_data_out, GND, L1_W_stall);
--L1_M_iw[15] is std_1s10:inst|cpu:the_cpu|M_iw[15] at LC_X25_Y22_N0
--operation mode is normal
L1_M_iw[15] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[15], E1_data_out, L1_W_stall);
--L1_M_iw[13] is std_1s10:inst|cpu:the_cpu|M_iw[13] at LC_X32_Y20_N8
--operation mode is normal
L1_M_iw[13] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[13], E1_data_out, L1_W_stall);
--L1_M_iw[12] is std_1s10:inst|cpu:the_cpu|M_iw[12] at LC_X25_Y22_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_iw[12] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[12], E1_data_out, GND, L1_W_stall);
--L1L1002 is std_1s10:inst|cpu:the_cpu|hbreak_enabled~271 at LC_X25_Y22_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L1002 = AMPP_FUNCTION(L1_M_iw[12], L1_M_iw[13], L1_M_iw[15]);
--L1_M_iw[14] is std_1s10:inst|cpu:the_cpu|M_iw[14] at LC_X25_Y22_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_iw[14] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[14], E1_data_out, GND, L1_W_stall);
--L1L1003 is std_1s10:inst|cpu:the_cpu|hbreak_enabled~272 at LC_X25_Y22_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L1003 = AMPP_FUNCTION(L1L1001, L1L1002);
--L1_M_iw[11] is std_1s10:inst|cpu:the_cpu|M_iw[11] at LC_X25_Y22_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_iw[11] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[11], E1_data_out, GND, L1_W_stall);
--L1L1004 is std_1s10:inst|cpu:the_cpu|hbreak_enabled~273 at LC_X27_Y22_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L1004 = AMPP_FUNCTION(KB1L7, L1L1480, L1_M_valid_from_E);
--L1_M_ctrl_break is std_1s10:inst|cpu:the_cpu|M_ctrl_break at LC_X27_Y22_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_ctrl_break = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_break, E1_data_out, GND, L1_W_stall);
--SC1_internal_oci_single_step_mode1 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_single_step_mode1 at LC_X44_Y21_N9
--operation mode is normal
SC1_internal_oci_single_step_mode1 = AMPP_FUNCTION(DE1__clk0, SC1L13, SC1_internal_oci_single_step_mode1, L1_M_st_data[3], E1_data_out);
--L1_E_ctrl_ld_signed is std_1s10:inst|cpu:the_cpu|E_ctrl_ld_signed at LC_X21_Y6_N5
--operation mode is normal
L1_E_ctrl_ld_signed = AMPP_FUNCTION(DE1__clk0, L1_D_iw[0], L1_D_iw[2], L1_D_iw[1], E1_data_out, L1_W_stall);
--L1_M_ipending_reg[4] is std_1s10:inst|cpu:the_cpu|M_ipending_reg[4] at LC_X31_Y21_N9
--operation mode is normal
L1_M_ipending_reg[4] = AMPP_FUNCTION(DE1__clk0, SC1_internal_oci_ienable1[4], R1_timeout_occurred, R1_control_register[0], L1_M_ienable_reg[4], E1_data_out);
--L1_M_ienable_reg[4] is std_1s10:inst|cpu:the_cpu|M_ienable_reg[4] at LC_X29_Y20_N2
--operation mode is normal
L1_M_ienable_reg[4] = AMPP_FUNCTION(DE1__clk0, L1L431, E1_data_out, L1L1187);
--L1L1257 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[4]~1348 at LC_X14_Y15_N3
--operation mode is normal
L1L1257 = AMPP_FUNCTION(QC1_result[4], QC1_result[36]);
--L1_d_readdata_d1[4] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[4] at LC_X47_Y15_N7
--operation mode is normal
L1_d_readdata_d1[4] = AMPP_FUNCTION(DE1__clk0, N1L105, P1_cpu_data_master_requests_cpu_jtag_debug_module, M1L61, E1_data_out);
--L1_d_readdata_d1[20] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[20] at LC_X45_Y18_N2
--operation mode is normal
L1_d_readdata_d1[20] = AMPP_FUNCTION(DE1__clk0, FC1L24, FC1L21, P1_cpu_data_master_requests_cpu_jtag_debug_module, M1L170, E1_data_out);
--L1_D_iw[10] is std_1s10:inst|cpu:the_cpu|D_iw[10] at LC_X31_Y20_N8
--operation mode is normal
L1_D_iw[10] = AMPP_FUNCTION(DE1__clk0, L1L1132, L1_hbreak_enabled, KC1_q_b[10], L1_latched_oci_tb_hbreak_req, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[4] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[4] at LC_X14_Y19_N7
--operation mode is normal
L1_E_src2_prelim[4] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[4], L1L403, L1L1389, L1_W_wr_data[4], E1_data_out, L1L399, L1_W_stall);
--L1_D_br_taken_waddr_partial[2] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[2] at LC_X35_Y20_N7
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[2] = AMPP_FUNCTION(DE1__clk0, L1L938, KC1_q_b[10], E1_data_out, L1_W_stall, L1L178, L1L179);
--L1L181 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[2]~58 at LC_X35_Y20_N7
--operation mode is arithmetic
L1L181 = AMPP_FUNCTION(L1L938, KC1_q_b[10], L1L178);
--L1L182 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[2]~58COUT1_112 at LC_X35_Y20_N7
--operation mode is arithmetic
L1L182 = AMPP_FUNCTION(L1L938, KC1_q_b[10], L1L179);
--L1L81 is std_1s10:inst|cpu:the_cpu|Add1~250 at LC_X33_Y19_N4
--operation mode is arithmetic
L1L81 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[20], L1L96, L1L84, L1L85);
--L1L82 is std_1s10:inst|cpu:the_cpu|Add1~251 at LC_X33_Y19_N4
--operation mode is arithmetic
L1L82 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[20], L1L96, L1L84, L1L85);
--L1L1275 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[22]~1349 at LC_X14_Y15_N1
--operation mode is normal
L1L1275 = AMPP_FUNCTION(QC1_result[54], QC1_result[22]);
--L1_d_readdata_d1[22] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[22] at LC_X47_Y17_N2
--operation mode is normal
L1_d_readdata_d1[22] = AMPP_FUNCTION(DE1__clk0, FC1L21, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L26, M1L179, E1_data_out);
--L1_d_readdata_d1[15] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[15] at LC_X45_Y13_N2
--operation mode is normal
L1_d_readdata_d1[15] = AMPP_FUNCTION(DE1__clk0, FC1L21, M1L144, FC1L18, P1_cpu_data_master_requests_cpu_jtag_debug_module, E1_data_out);
--L1L169 is std_1s10:inst|cpu:the_cpu|av_sign_bit~0 at LC_X23_Y20_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L169 = AMPP_FUNCTION(L1_M_alu_result[0], L1_M_iw[4]);
--L1_M_iw[3] is std_1s10:inst|cpu:the_cpu|M_iw[3] at LC_X23_Y20_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_iw[3] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[3], E1_data_out, GND, L1_W_stall);
--L1L170 is std_1s10:inst|cpu:the_cpu|av_sign_bit~9 at LC_X23_Y20_N7
--operation mode is normal
L1L170 = AMPP_FUNCTION(L1L169, L1_d_readdata_d1[7], L1_M_alu_result[1], L1_d_readdata_d1[23]);
--L1_d_readdata_d1[31] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[31] at LC_X44_Y19_N6
--operation mode is normal
L1_d_readdata_d1[31] = AMPP_FUNCTION(DE1__clk0, P1_cpu_data_master_requests_cpu_jtag_debug_module, M1L225, FC1L35, FC1L21, E1_data_out);
--L1L171 is std_1s10:inst|cpu:the_cpu|av_sign_bit~10 at LC_X24_Y20_N8
--operation mode is normal
L1L171 = AMPP_FUNCTION(L1L170, L1L169, L1_d_readdata_d1[15], L1_d_readdata_d1[31]);
--L1L236 is std_1s10:inst|cpu:the_cpu|D_ctrl_hi_imm~99 at LC_X19_Y8_N6
--operation mode is normal
L1L236 = AMPP_FUNCTION(L1_D_iw[2], L1L235, L1_D_iw[5]);
--L1L410 is std_1s10:inst|cpu:the_cpu|D_src2_imm[22]~2231 at LC_X19_Y8_N5
--operation mode is normal
L1L410 = AMPP_FUNCTION(L1L236, L1_D_iw[12], L1_D_iw[21]);
--L1_E_src2_prelim[22] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[22] at LC_X17_Y17_N5
--operation mode is normal
L1_E_src2_prelim[22] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[22], L1L403, L1L1443, L1_W_wr_data[22], E1_data_out, L1L399, L1_W_stall);
--L1L83 is std_1s10:inst|cpu:the_cpu|Add1~252 at LC_X33_Y19_N3
--operation mode is arithmetic
L1L83 = AMPP_FUNCTION(L1_D_pc_plus_one[19], L1_D_iw[21], L1L96, L1L105, L1L106);
--L1L84 is std_1s10:inst|cpu:the_cpu|Add1~253 at LC_X33_Y19_N3
--operation mode is arithmetic
L1L84 = AMPP_FUNCTION(L1_D_pc_plus_one[19], L1_D_iw[21], L1L105);
--L1L85 is std_1s10:inst|cpu:the_cpu|Add1~253COUT1_353 at LC_X33_Y19_N3
--operation mode is arithmetic
L1L85 = AMPP_FUNCTION(L1_D_pc_plus_one[19], L1_D_iw[21], L1L106);
--L1L1274 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[21]~1350 at LC_X13_Y15_N9
--operation mode is normal
L1L1274 = AMPP_FUNCTION(QC1_result[53], QC1_result[21]);
--L1_d_readdata_d1[21] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[21] at LC_X47_Y19_N1
--operation mode is normal
L1_d_readdata_d1[21] = AMPP_FUNCTION(DE1__clk0, M1L175, FC1L21, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L25, E1_data_out);
--L1L409 is std_1s10:inst|cpu:the_cpu|D_src2_imm[21]~2233 at LC_X19_Y10_N5
--operation mode is normal
L1L409 = AMPP_FUNCTION(L1_D_iw[21], L1_D_iw[11], L1L236);
--L1_E_src2_prelim[21] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[21] at LC_X17_Y15_N6
--operation mode is normal
L1_E_src2_prelim[21] = AMPP_FUNCTION(DE1__clk0, L1L403, NC1_q_b[21], L1L1440, L1_W_wr_data[21], E1_data_out, L1L399, L1_W_stall);
--L1L86 is std_1s10:inst|cpu:the_cpu|Add1~254 at LC_X33_Y19_N6
--operation mode is arithmetic
L1L86 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[22], L1L82, L1L101, L1L102);
--L1L87 is std_1s10:inst|cpu:the_cpu|Add1~255 at LC_X33_Y19_N6
--operation mode is arithmetic
L1L87 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[22], L1L101);
--L1L88 is std_1s10:inst|cpu:the_cpu|Add1~255COUT1_357 at LC_X33_Y19_N6
--operation mode is arithmetic
L1L88 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[22], L1L102);
--L1L412 is std_1s10:inst|cpu:the_cpu|D_src2_imm[24]~2235 at LC_X19_Y10_N1
--operation mode is normal
L1L412 = AMPP_FUNCTION(L1_D_iw[14], L1_D_iw[21], L1L236);
--NC1_q_b[24] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[24] at M4K_X15_Y18
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 32, Port A Width: 32, Port B Depth: 32, Port B Width: 32
--Port A Logical Depth: 32, Port A Logical Width: 32, Port B Logical Depth: 32, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
NC1_q_b[24] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[31] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[31] at M4K_X15_Y18
NC1_q_b[31] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[30] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[30] at M4K_X15_Y18
NC1_q_b[30] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[29] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[29] at M4K_X15_Y18
NC1_q_b[29] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[28] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[28] at M4K_X15_Y18
NC1_q_b[28] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[27] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[27] at M4K_X15_Y18
NC1_q_b[27] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[26] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[26] at M4K_X15_Y18
NC1_q_b[26] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[0] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[0] at M4K_X15_Y18
NC1_q_b[0] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[1] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[1] at M4K_X15_Y18
NC1_q_b[1] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[6] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[6] at M4K_X15_Y18
NC1_q_b[6] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[5] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[5] at M4K_X15_Y18
NC1_q_b[5] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[20] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[20] at M4K_X15_Y18
NC1_q_b[20] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[23] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[23] at M4K_X15_Y18
NC1_q_b[23] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[16] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[16] at M4K_X15_Y18
NC1_q_b[16] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[17] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[17] at M4K_X15_Y18
NC1_q_b[17] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[18] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[18] at M4K_X15_Y18
NC1_q_b[18] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[19] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[19] at M4K_X15_Y18
NC1_q_b[19] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[21] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[21] at M4K_X15_Y18
NC1_q_b[21] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[22] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[22] at M4K_X15_Y18
NC1_q_b[22] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[4] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[4] at M4K_X15_Y18
NC1_q_b[4] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[7] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[7] at M4K_X15_Y18
NC1_q_b[7] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[3] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[3] at M4K_X15_Y18
NC1_q_b[3] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[2] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[2] at M4K_X15_Y18
NC1_q_b[2] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[8] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[8] at M4K_X15_Y18
NC1_q_b[8] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[9] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[9] at M4K_X15_Y18
NC1_q_b[9] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[10] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[10] at M4K_X15_Y18
NC1_q_b[10] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[11] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[11] at M4K_X15_Y18
NC1_q_b[11] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[12] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[12] at M4K_X15_Y18
NC1_q_b[12] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[13] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[13] at M4K_X15_Y18
NC1_q_b[13] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[14] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[14] at M4K_X15_Y18
NC1_q_b[14] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[15] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[15] at M4K_X15_Y18
NC1_q_b[15] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--NC1_q_b[25] is std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|q_b[25] at M4K_X15_Y18
NC1_q_b[25] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, !L1_M_wr_dst_reg, L1_W_stall, L1L1449, L1_M_dst_regnum[0], L1_M_dst_regnum[1], L1_M_dst_regnum[2], L1_M_dst_regnum[3], L1_M_dst_regnum[4], KC1_q_b[22], KC1_q_b[23], KC1_q_b[24], KC1_q_b[25], KC1_q_b[26], GND, GND, GND, GND, L1L1452, L1L1422, L1L1419, L1L1416, L1L1413, L1L1410, L1L1407, L1L1404, L1L1401, L1L1383, L1L1386, L1L1398, L1L1389, L1L1443, L1L1440, L1L1434, L1L1431, L1L1428, L1L1425, L1L1446, L1L1437, L1L1392, L1L1395, L1L1380, L1L1377, L1L1455, L1L1458, L1L1461, L1L1464, L1L1467, L1L1470);
--L1_D_iw[25] is std_1s10:inst|cpu:the_cpu|D_iw[25] at LC_X17_Y20_N6
--operation mode is normal
L1_D_iw[25] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, KC1_q_b[25], L1L1132, L1_hbreak_enabled, E1_data_out, L1_W_stall);
--L1_D_iw[26] is std_1s10:inst|cpu:the_cpu|D_iw[26] at LC_X18_Y19_N0
--operation mode is normal
L1_D_iw[26] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[26], L1_hbreak_enabled, L1_latched_oci_tb_hbreak_req, L1L1132, E1_data_out, L1_W_stall);
--L1_D_iw[24] is std_1s10:inst|cpu:the_cpu|D_iw[24] at LC_X18_Y19_N3
--operation mode is normal
L1_D_iw[24] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[24], L1_hbreak_enabled, L1_latched_oci_tb_hbreak_req, L1L1132, E1_data_out, L1_W_stall);
--L1L400 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_W~56 at LC_X18_Y19_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L400 = AMPP_FUNCTION(L1_W_dst_regnum[4], L1_D_iw[24], L1_D_iw[26]);
--L1_W_dst_regnum[2] is std_1s10:inst|cpu:the_cpu|W_dst_regnum[2] at LC_X18_Y19_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_W_dst_regnum[2] = AMPP_FUNCTION(DE1__clk0, L1_M_dst_regnum[2], E1_data_out, GND, L1_W_stall);
--L1_D_iw[22] is std_1s10:inst|cpu:the_cpu|D_iw[22] at LC_X18_Y20_N5
--operation mode is normal
L1_D_iw[22] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, KC1_q_b[22], L1_hbreak_enabled, L1L1132, E1_data_out, L1_W_stall);
--L1_D_iw[23] is std_1s10:inst|cpu:the_cpu|D_iw[23] at LC_X18_Y19_N9
--operation mode is normal
L1_D_iw[23] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[23], L1_hbreak_enabled, L1_latched_oci_tb_hbreak_req, L1L1132, E1_data_out, L1_W_stall);
--L1L401 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_W~57 at LC_X23_Y20_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L401 = AMPP_FUNCTION(L1_D_iw[22], L1_D_iw[23], L1_W_dst_regnum[1]);
--L1_W_dst_regnum[0] is std_1s10:inst|cpu:the_cpu|W_dst_regnum[0] at LC_X23_Y20_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_W_dst_regnum[0] = AMPP_FUNCTION(DE1__clk0, L1_M_dst_regnum[0], E1_data_out, GND, L1_W_stall);
--L1L402 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_W~58 at LC_X23_Y20_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L402 = AMPP_FUNCTION(L1L400, L1L401, L1_D_iw[25]);
--L1_W_dst_regnum[3] is std_1s10:inst|cpu:the_cpu|W_dst_regnum[3] at LC_X23_Y20_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_W_dst_regnum[3] = AMPP_FUNCTION(DE1__clk0, L1_M_dst_regnum[3], E1_data_out, GND, L1_W_stall);
--L1L403 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_W~59 at LC_X18_Y18_N0
--operation mode is normal
L1L403 = AMPP_FUNCTION(L1L216, L1L829, L1L402, L1_W_wr_dst_reg);
--L1L396 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_M~40 at LC_X18_Y19_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L396 = AMPP_FUNCTION(L1_D_iw[26], L1_M_dst_regnum[4], L1_D_iw[24]);
--L1_M_dst_regnum[2] is std_1s10:inst|cpu:the_cpu|M_dst_regnum[2] at LC_X18_Y19_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_dst_regnum[2] = AMPP_FUNCTION(DE1__clk0, L1_E_dst_regnum[2], E1_data_out, GND, L1_W_stall);
--L1L397 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_M~41 at LC_X18_Y20_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L397 = AMPP_FUNCTION(L1_M_dst_regnum[1], L1_D_iw[22], L1_D_iw[23]);
--L1_M_dst_regnum[0] is std_1s10:inst|cpu:the_cpu|M_dst_regnum[0] at LC_X18_Y20_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_dst_regnum[0] = AMPP_FUNCTION(DE1__clk0, L1_E_dst_regnum[0], E1_data_out, GND, L1_W_stall);
--L1L398 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_M~42 at LC_X18_Y20_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L398 = AMPP_FUNCTION(L1L397, L1L396, L1_D_iw[25]);
--L1_M_dst_regnum[3] is std_1s10:inst|cpu:the_cpu|M_dst_regnum[3] at LC_X18_Y20_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_dst_regnum[3] = AMPP_FUNCTION(DE1__clk0, L1_E_dst_regnum[3], E1_data_out, GND, L1_W_stall);
--L1L399 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_M~43 at LC_X18_Y18_N7
--operation mode is normal
L1L399 = AMPP_FUNCTION(L1L216, L1L829, L1L398, L1_M_wr_dst_reg);
--L1L393 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_E~39 at LC_X18_Y19_N1
--operation mode is normal
L1L393 = AMPP_FUNCTION(L1_E_dst_regnum[1], L1_D_iw[23], L1_E_dst_regnum[4], L1_D_iw[26]);
--L1L394 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_E~40 at LC_X18_Y20_N1
--operation mode is normal
L1L394 = AMPP_FUNCTION(L1_E_dst_regnum[0], L1_D_iw[25], L1_E_dst_regnum[3], L1_D_iw[22]);
--L1L395 is std_1s10:inst|cpu:the_cpu|D_src2_hazard_E~41 at LC_X19_Y17_N6
--operation mode is normal
L1L395 = AMPP_FUNCTION(L1L393, L1L216, L1L829, L1L394);
--L1L1277 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[24]~1351 at LC_X13_Y14_N1
--operation mode is normal
L1L1277 = AMPP_FUNCTION(QC1_result[56], QC1_result[24]);
--L1_d_readdata_d1[24] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[24] at LC_X44_Y15_N9
--operation mode is normal
L1_d_readdata_d1[24] = AMPP_FUNCTION(DE1__clk0, FC1L21, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L28, M1L190, E1_data_out);
--L1L89 is std_1s10:inst|cpu:the_cpu|Add1~256 at LC_X33_Y19_N1
--operation mode is arithmetic
L1L89 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[17], L1L96, L1L93, L1L94);
--L1L90 is std_1s10:inst|cpu:the_cpu|Add1~257 at LC_X33_Y19_N1
--operation mode is arithmetic
L1L90 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[17], L1L93);
--L1L91 is std_1s10:inst|cpu:the_cpu|Add1~257COUT1_349 at LC_X33_Y19_N1
--operation mode is arithmetic
L1L91 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[17], L1L94);
--L1L1272 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[19]~1352 at LC_X13_Y14_N3
--operation mode is normal
L1L1272 = AMPP_FUNCTION(QC1_result[51], QC1_result[19]);
--L1L407 is std_1s10:inst|cpu:the_cpu|D_src2_imm[19]~2237 at LC_X17_Y7_N9
--operation mode is normal
L1L407 = AMPP_FUNCTION(L1_D_iw[21], L1L236, L1_D_iw[9]);
--L1_E_src2_prelim[19] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[19] at LC_X17_Y15_N3
--operation mode is normal
L1_E_src2_prelim[19] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[19], L1_W_wr_data[19], L1L1434, L1L403, E1_data_out, L1L399, L1_W_stall);
--L1L92 is std_1s10:inst|cpu:the_cpu|Add1~258 at LC_X33_Y19_N0
--operation mode is arithmetic
L1L92 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[16], L1L96);
--L1L93 is std_1s10:inst|cpu:the_cpu|Add1~259 at LC_X33_Y19_N0
--operation mode is arithmetic
L1L93 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[16]);
--L1L94 is std_1s10:inst|cpu:the_cpu|Add1~259COUT1_347 at LC_X33_Y19_N0
--operation mode is arithmetic
L1L94 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[16]);
--L1L1271 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[18]~1353 at LC_X13_Y13_N2
--operation mode is normal
L1L1271 = AMPP_FUNCTION(QC1_result[18], QC1_result[50]);
--L1L406 is std_1s10:inst|cpu:the_cpu|D_src2_imm[18]~2239 at LC_X17_Y7_N4
--operation mode is normal
L1L406 = AMPP_FUNCTION(L1_D_iw[21], L1L236, L1_D_iw[8]);
--L1_E_src2_prelim[18] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[18] at LC_X17_Y15_N8
--operation mode is normal
L1_E_src2_prelim[18] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[18], L1_W_wr_data[18], L1L1431, L1L403, E1_data_out, L1L399, L1_W_stall);
--L1L95 is std_1s10:inst|cpu:the_cpu|Add1~260 at LC_X33_Y20_N9
--operation mode is arithmetic
L1L95 = AMPP_FUNCTION(L1_D_pc_plus_one[15], L1_D_iw[21], L1L117, L1L98, L1L99);
--L1L96 is std_1s10:inst|cpu:the_cpu|Add1~261 at LC_X33_Y20_N9
--operation mode is arithmetic
L1L96 = AMPP_FUNCTION(L1_D_pc_plus_one[15], L1_D_iw[21], L1L117, L1L98, L1L99);
--L1L1270 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[17]~1354 at LC_X12_Y14_N3
--operation mode is normal
L1L1270 = AMPP_FUNCTION(QC1_result[49], QC1_result[17]);
--L1_d_readdata_d1[17] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[17] at LC_X46_Y16_N4
--operation mode is normal
L1_d_readdata_d1[17] = AMPP_FUNCTION(DE1__clk0, P1_cpu_data_master_requests_cpu_jtag_debug_module, M1L155, FC1L20, FC1L21, E1_data_out);
--L1L405 is std_1s10:inst|cpu:the_cpu|D_src2_imm[17]~2241 at LC_X17_Y7_N8
--operation mode is normal
L1L405 = AMPP_FUNCTION(L1_D_iw[21], L1L236, L1_D_iw[7]);
--L1_E_src2_prelim[17] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[17] at LC_X17_Y15_N4
--operation mode is normal
L1_E_src2_prelim[17] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[17], NC1_q_b[17], L1L1428, L1L403, E1_data_out, L1L399, L1_W_stall);
--L1L97 is std_1s10:inst|cpu:the_cpu|Add1~262 at LC_X33_Y20_N8
--operation mode is arithmetic
L1L97 = AMPP_FUNCTION(L1_D_pc_plus_one[14], L1_D_iw[21], L1L117, L1L108, L1L109);
--L1L98 is std_1s10:inst|cpu:the_cpu|Add1~263 at LC_X33_Y20_N8
--operation mode is arithmetic
L1L98 = AMPP_FUNCTION(L1_D_pc_plus_one[14], L1_D_iw[21], L1L108);
--L1L99 is std_1s10:inst|cpu:the_cpu|Add1~263COUT1_345 at LC_X33_Y20_N8
--operation mode is arithmetic
L1L99 = AMPP_FUNCTION(L1_D_pc_plus_one[14], L1_D_iw[21], L1L109);
--L1L1269 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[16]~1355 at LC_X12_Y14_N0
--operation mode is normal
L1L1269 = AMPP_FUNCTION(QC1_result[16], QC1_result[48]);
--L1_d_readdata_d1[16] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[16] at LC_X41_Y19_N2
--operation mode is normal
L1_d_readdata_d1[16] = AMPP_FUNCTION(DE1__clk0, FC1L19, P1_cpu_data_master_requests_cpu_jtag_debug_module, M1L150, FC1L21, E1_data_out);
--L1L404 is std_1s10:inst|cpu:the_cpu|D_src2_imm[16]~2243 at LC_X17_Y7_N2
--operation mode is normal
L1L404 = AMPP_FUNCTION(L1_D_iw[21], L1L236, L1_D_iw[6]);
--L1_E_src2_prelim[16] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[16] at LC_X17_Y15_N1
--operation mode is normal
L1_E_src2_prelim[16] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[16], L1_W_wr_data[16], L1L1425, L1L403, E1_data_out, L1L399, L1_W_stall);
--L1L100 is std_1s10:inst|cpu:the_cpu|Add1~264 at LC_X33_Y19_N5
--operation mode is arithmetic
L1L100 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[21], L1L82);
--L1L101 is std_1s10:inst|cpu:the_cpu|Add1~265 at LC_X33_Y19_N5
--operation mode is arithmetic
L1L101 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[21]);
--L1L102 is std_1s10:inst|cpu:the_cpu|Add1~265COUT1_355 at LC_X33_Y19_N5
--operation mode is arithmetic
L1L102 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[21]);
--L1L1276 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[23]~1356 at LC_X12_Y14_N5
--operation mode is normal
L1L1276 = AMPP_FUNCTION(QC1_result[55], QC1_result[23]);
--L1L411 is std_1s10:inst|cpu:the_cpu|D_src2_imm[23]~2245 at LC_X19_Y10_N8
--operation mode is normal
L1L411 = AMPP_FUNCTION(L1_D_iw[13], L1_D_iw[21], L1L236);
--L1_E_src2_prelim[23] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[23] at LC_X17_Y18_N1
--operation mode is normal
L1_E_src2_prelim[23] = AMPP_FUNCTION(DE1__clk0, L1L403, NC1_q_b[23], L1L1446, L1_W_wr_data[23], E1_data_out, L1L399, L1_W_stall);
--L1L103 is std_1s10:inst|cpu:the_cpu|Add1~266 at LC_X33_Y19_N7
--operation mode is normal
L1L103 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[23], L1L82, L1L87, L1L88);
--L1L413 is std_1s10:inst|cpu:the_cpu|D_src2_imm[25]~2247 at LC_X17_Y7_N6
--operation mode is normal
L1L413 = AMPP_FUNCTION(L1_D_iw[15], L1L236, L1_D_iw[21]);
--L1L1278 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[25]~1357 at LC_X12_Y14_N7
--operation mode is normal
L1L1278 = AMPP_FUNCTION(QC1_result[57], QC1_result[25]);
--L1_d_readdata_d1[25] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[25] at LC_X44_Y17_N0
--operation mode is normal
L1_d_readdata_d1[25] = AMPP_FUNCTION(DE1__clk0, P1_cpu_data_master_requests_cpu_jtag_debug_module, M1L195, FC1L29, FC1L21, E1_data_out);
--L1L104 is std_1s10:inst|cpu:the_cpu|Add1~268 at LC_X33_Y19_N2
--operation mode is arithmetic
L1L104 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[18], L1L96, L1L90, L1L91);
--L1L105 is std_1s10:inst|cpu:the_cpu|Add1~269 at LC_X33_Y19_N2
--operation mode is arithmetic
L1L105 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[18], L1L90);
--L1L106 is std_1s10:inst|cpu:the_cpu|Add1~269COUT1_351 at LC_X33_Y19_N2
--operation mode is arithmetic
L1L106 = AMPP_FUNCTION(L1_D_iw[21], L1_D_pc_plus_one[18], L1L91);
--L1L1273 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[20]~1358 at LC_X12_Y14_N1
--operation mode is normal
L1L1273 = AMPP_FUNCTION(QC1_result[52], QC1_result[20]);
--L1L408 is std_1s10:inst|cpu:the_cpu|D_src2_imm[20]~2249 at LC_X18_Y8_N9
--operation mode is normal
L1L408 = AMPP_FUNCTION(L1L236, L1_D_iw[21], L1_D_iw[10]);
--L1_E_src2_prelim[20] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[20] at LC_X17_Y18_N8
--operation mode is normal
L1_E_src2_prelim[20] = AMPP_FUNCTION(DE1__clk0, L1L403, NC1_q_b[20], L1L1437, L1_W_wr_data[20], E1_data_out, L1L399, L1_W_stall);
--L1L107 is std_1s10:inst|cpu:the_cpu|Add1~270 at LC_X33_Y20_N7
--operation mode is arithmetic
L1L107 = AMPP_FUNCTION(L1_D_pc_plus_one[13], L1_D_iw[21], L1L117, L1L111, L1L112);
--L1L108 is std_1s10:inst|cpu:the_cpu|Add1~271 at LC_X33_Y20_N7
--operation mode is arithmetic
L1L108 = AMPP_FUNCTION(L1_D_pc_plus_one[13], L1_D_iw[21], L1L111);
--L1L109 is std_1s10:inst|cpu:the_cpu|Add1~271COUT1_343 at LC_X33_Y20_N7
--operation mode is arithmetic
L1L109 = AMPP_FUNCTION(L1_D_pc_plus_one[13], L1_D_iw[21], L1L112);
--L1L1268 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[15]~1359 at LC_X12_Y16_N1
--operation mode is normal
L1L1268 = AMPP_FUNCTION(QC1_result[47], QC1_result[15]);
--L1_av_fill_bit is std_1s10:inst|cpu:the_cpu|av_fill_bit at LC_X22_Y21_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_av_fill_bit = AMPP_FUNCTION(L1L171);
--L1_M_ctrl_ld_signed is std_1s10:inst|cpu:the_cpu|M_ctrl_ld_signed at LC_X22_Y21_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_ctrl_ld_signed = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_ld_signed, E1_data_out, GND, L1_W_stall);
--L1L846 is std_1s10:inst|cpu:the_cpu|Equal145~6 at LC_X23_Y20_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L846 = AMPP_FUNCTION(L1_M_iw[3]);
--L1_M_iw[4] is std_1s10:inst|cpu:the_cpu|M_iw[4] at LC_X23_Y20_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_iw[4] = AMPP_FUNCTION(DE1__clk0, L1_E_iw[4], E1_data_out, GND, L1_W_stall);
--L1L110 is std_1s10:inst|cpu:the_cpu|Add1~272 at LC_X33_Y20_N6
--operation mode is arithmetic
L1L110 = AMPP_FUNCTION(L1_D_iw[20], L1_D_pc_plus_one[12], L1L117, L1L114, L1L115);
--L1L111 is std_1s10:inst|cpu:the_cpu|Add1~273 at LC_X33_Y20_N6
--operation mode is arithmetic
L1L111 = AMPP_FUNCTION(L1_D_iw[20], L1_D_pc_plus_one[12], L1L114);
--L1L112 is std_1s10:inst|cpu:the_cpu|Add1~273COUT1_341 at LC_X33_Y20_N6
--operation mode is arithmetic
L1L112 = AMPP_FUNCTION(L1_D_iw[20], L1_D_pc_plus_one[12], L1L115);
--L1_D_iw[20] is std_1s10:inst|cpu:the_cpu|D_iw[20] at LC_X18_Y20_N9
--operation mode is normal
L1_D_iw[20] = AMPP_FUNCTION(DE1__clk0, L1_latched_oci_tb_hbreak_req, L1L1132, KC1_q_b[20], L1_hbreak_enabled, E1_data_out, L1_W_stall);
--L1L1267 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[14]~1360 at LC_X14_Y15_N5
--operation mode is normal
L1L1267 = AMPP_FUNCTION(QC1_result[46], QC1_result[14]);
--L1_d_readdata_d1[14] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[14] at LC_X44_Y12_N1
--operation mode is normal
L1_d_readdata_d1[14] = AMPP_FUNCTION(DE1__clk0, FC1L21, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L17, M1L137, E1_data_out);
--L1_d_readdata_d1[30] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[30] at LC_X47_Y16_N5
--operation mode is normal
L1_d_readdata_d1[30] = AMPP_FUNCTION(DE1__clk0, M1L219, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L34, FC1L21, E1_data_out);
--L1L113 is std_1s10:inst|cpu:the_cpu|Add1~274 at LC_X33_Y20_N5
--operation mode is arithmetic
L1L113 = AMPP_FUNCTION(L1_D_pc_plus_one[11], L1_D_iw[19], L1L117);
--L1L114 is std_1s10:inst|cpu:the_cpu|Add1~275 at LC_X33_Y20_N5
--operation mode is arithmetic
L1L114 = AMPP_FUNCTION(L1_D_pc_plus_one[11], L1_D_iw[19]);
--L1L115 is std_1s10:inst|cpu:the_cpu|Add1~275COUT1_339 at LC_X33_Y20_N5
--operation mode is arithmetic
L1L115 = AMPP_FUNCTION(L1_D_pc_plus_one[11], L1_D_iw[19]);
--L1_D_iw[19] is std_1s10:inst|cpu:the_cpu|D_iw[19] at LC_X18_Y19_N6
--operation mode is normal
L1_D_iw[19] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[19], L1_hbreak_enabled, L1_latched_oci_tb_hbreak_req, L1L1132, E1_data_out, L1_W_stall);
--L1L1266 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[13]~1361 at LC_X12_Y16_N5
--operation mode is normal
L1L1266 = AMPP_FUNCTION(QC1_result[13], QC1_result[45]);
--L1_d_readdata_d1[13] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[13] at LC_X47_Y17_N3
--operation mode is normal
L1_d_readdata_d1[13] = AMPP_FUNCTION(DE1__clk0, FC1L21, P1_cpu_data_master_requests_cpu_jtag_debug_module, M1L131, FC1L16, E1_data_out);
--L1_d_readdata_d1[29] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[29] at LC_X44_Y14_N6
--operation mode is normal
L1_d_readdata_d1[29] = AMPP_FUNCTION(DE1__clk0, P1_cpu_data_master_requests_cpu_jtag_debug_module, M1L215, FC1L33, FC1L21, E1_data_out);
--L1L116 is std_1s10:inst|cpu:the_cpu|Add1~276 at LC_X33_Y20_N4
--operation mode is arithmetic
L1L116 = AMPP_FUNCTION(L1_D_pc_plus_one[10], L1_D_iw[18], L1L119, L1L120);
--L1L117 is std_1s10:inst|cpu:the_cpu|Add1~277 at LC_X33_Y20_N4
--operation mode is arithmetic
L1L117 = AMPP_FUNCTION(L1_D_pc_plus_one[10], L1_D_iw[18], L1L119, L1L120);
--L1_D_iw[18] is std_1s10:inst|cpu:the_cpu|D_iw[18] at LC_X18_Y20_N0
--operation mode is normal
L1_D_iw[18] = AMPP_FUNCTION(DE1__clk0, L1_hbreak_enabled, L1L1132, L1_latched_oci_tb_hbreak_req, KC1_q_b[18], E1_data_out, L1_W_stall);
--L1L1265 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[12]~1362 at LC_X13_Y16_N7
--operation mode is normal
L1L1265 = AMPP_FUNCTION(QC1_result[44], QC1_result[12]);
--L1_d_readdata_d1[12] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[12] at LC_X45_Y11_N8
--operation mode is normal
L1_d_readdata_d1[12] = AMPP_FUNCTION(DE1__clk0, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L15, M1L125, FC1L21, E1_data_out);
--L1_d_readdata_d1[28] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[28] at LC_X44_Y20_N8
--operation mode is normal
L1_d_readdata_d1[28] = AMPP_FUNCTION(DE1__clk0, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L21, M1L210, FC1L32, E1_data_out);
--L1_D_br_taken_waddr_partial[9] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[9] at LC_X35_Y19_N4
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[9] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[17], L1L958, E1_data_out, L1_W_stall, L1L187, L1L198, L1L199);
--L1L201 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[9]~59 at LC_X35_Y19_N4
--operation mode is arithmetic
L1L201 = AMPP_FUNCTION(KC1_q_b[17], L1L958, L1L187, L1L198, L1L199);
--L1_D_iw[17] is std_1s10:inst|cpu:the_cpu|D_iw[17] at LC_X18_Y20_N4
--operation mode is normal
L1_D_iw[17] = AMPP_FUNCTION(DE1__clk0, L1_hbreak_enabled, L1L1132, L1_latched_oci_tb_hbreak_req, KC1_q_b[17], E1_data_out, L1_W_stall);
--L1L1264 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[11]~1363 at LC_X12_Y16_N3
--operation mode is normal
L1L1264 = AMPP_FUNCTION(QC1_result[43], QC1_result[11]);
--L1_d_readdata_d1[11] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[11] at LC_X47_Y16_N4
--operation mode is normal
L1_d_readdata_d1[11] = AMPP_FUNCTION(DE1__clk0, FC1L21, P1_cpu_data_master_requests_cpu_jtag_debug_module, M1L118, FC1L14, E1_data_out);
--L1_d_readdata_d1[27] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[27] at LC_X41_Y14_N8
--operation mode is normal
L1_d_readdata_d1[27] = AMPP_FUNCTION(DE1__clk0, M1L205, FC1L31, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L21, E1_data_out);
--L1_D_br_taken_waddr_partial[8] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[8] at LC_X35_Y19_N3
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[8] = AMPP_FUNCTION(DE1__clk0, L1L955, KC1_q_b[16], E1_data_out, L1_W_stall, L1L187, L1L195, L1L196);
--L1L198 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[8]~60 at LC_X35_Y19_N3
--operation mode is arithmetic
L1L198 = AMPP_FUNCTION(L1L955, KC1_q_b[16], L1L195);
--L1L199 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[8]~60COUT1_122 at LC_X35_Y19_N3
--operation mode is arithmetic
L1L199 = AMPP_FUNCTION(L1L955, KC1_q_b[16], L1L196);
--L1L1263 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[10]~1364 at LC_X12_Y16_N7
--operation mode is normal
L1L1263 = AMPP_FUNCTION(QC1_result[42], QC1_result[10]);
--L1_d_readdata_d1[10] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[10] at LC_X44_Y11_N2
--operation mode is normal
L1_d_readdata_d1[10] = AMPP_FUNCTION(DE1__clk0, M1L111, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L21, FC1L13, E1_data_out);
--L1_d_readdata_d1[26] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[26] at LC_X41_Y20_N2
--operation mode is normal
L1_d_readdata_d1[26] = AMPP_FUNCTION(DE1__clk0, FC1L21, M1L200, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L30, E1_data_out);
--L1_D_br_taken_waddr_partial[7] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[7] at LC_X35_Y19_N2
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[7] = AMPP_FUNCTION(DE1__clk0, L1L952, KC1_q_b[15], E1_data_out, L1_W_stall, L1L187, L1L192, L1L193);
--L1L195 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[7]~61 at LC_X35_Y19_N2
--operation mode is arithmetic
L1L195 = AMPP_FUNCTION(L1L952, KC1_q_b[15], L1L192);
--L1L196 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[7]~61COUT1_120 at LC_X35_Y19_N2
--operation mode is arithmetic
L1L196 = AMPP_FUNCTION(L1L952, KC1_q_b[15], L1L193);
--L1L1262 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[9]~1365 at LC_X12_Y15_N5
--operation mode is normal
L1L1262 = AMPP_FUNCTION(QC1_result[41], QC1_result[9]);
--L1_d_readdata_d1[9] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[9] at LC_X45_Y14_N5
--operation mode is normal
L1_d_readdata_d1[9] = AMPP_FUNCTION(DE1__clk0, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L21, FC1L12, M1L103, E1_data_out);
--L1_D_br_taken_waddr_partial[6] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[6] at LC_X35_Y19_N1
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[6] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[14], L1L950, E1_data_out, L1_W_stall, L1L187, L1L189, L1L190);
--L1L192 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[6]~62 at LC_X35_Y19_N1
--operation mode is arithmetic
L1L192 = AMPP_FUNCTION(KC1_q_b[14], L1L950, L1L189);
--L1L193 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[6]~62COUT1_118 at LC_X35_Y19_N1
--operation mode is arithmetic
L1L193 = AMPP_FUNCTION(KC1_q_b[14], L1L950, L1L190);
--L1L1261 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[8]~1366 at LC_X12_Y16_N0
--operation mode is normal
L1L1261 = AMPP_FUNCTION(QC1_result[40], QC1_result[8]);
--L1_d_readdata_d1[8] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[8] at LC_X46_Y13_N5
--operation mode is normal
L1_d_readdata_d1[8] = AMPP_FUNCTION(DE1__clk0, FC1L21, FC1L11, P1_cpu_data_master_requests_cpu_jtag_debug_module, M1L94, E1_data_out);
--L1_M_ipending_reg[5] is std_1s10:inst|cpu:the_cpu|M_ipending_reg[5] at LC_X41_Y21_N2
--operation mode is normal
L1_M_ipending_reg[5] = AMPP_FUNCTION(DE1__clk0, SC1_internal_oci_ienable1[5], L1L1199, L1L1198, L1_M_ienable_reg[5], E1_data_out);
--L1_M_ienable_reg[5] is std_1s10:inst|cpu:the_cpu|M_ienable_reg[5] at LC_X30_Y21_N2
--operation mode is normal
L1_M_ienable_reg[5] = AMPP_FUNCTION(DE1__clk0, L1L432, E1_data_out, L1L1187);
--L1L1258 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[5]~1367 at LC_X12_Y15_N3
--operation mode is normal
L1L1258 = AMPP_FUNCTION(QC1_result[5], QC1_result[37]);
--L1_d_readdata_d1[5] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[5] at LC_X48_Y12_N9
--operation mode is normal
L1_d_readdata_d1[5] = AMPP_FUNCTION(DE1__clk0, P1_cpu_data_master_requests_cpu_jtag_debug_module, M1L70, N1L106, E1_data_out);
--L1_E_src2_prelim[5] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[5] at LC_X17_Y15_N0
--operation mode is normal
L1_E_src2_prelim[5] = AMPP_FUNCTION(DE1__clk0, L1L403, NC1_q_b[5], L1L1392, L1_W_wr_data[5], E1_data_out, L1L399, L1_W_stall);
--L1_D_br_taken_waddr_partial[3] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[3] at LC_X35_Y20_N8
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[3] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[11], L1L941, E1_data_out, L1_W_stall, L1L181, L1L182);
--L1L184 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[3]~63 at LC_X35_Y20_N8
--operation mode is arithmetic
L1L184 = AMPP_FUNCTION(KC1_q_b[11], L1L941, L1L181);
--L1L185 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[3]~63COUT1_114 at LC_X35_Y20_N8
--operation mode is arithmetic
L1L185 = AMPP_FUNCTION(KC1_q_b[11], L1L941, L1L182);
--L1_D_br_taken_waddr_partial[4] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[4] at LC_X35_Y20_N9
--operation mode is arithmetic
L1_D_br_taken_waddr_partial[4] = AMPP_FUNCTION(DE1__clk0, KC1_q_b[12], L1L944, E1_data_out, L1_W_stall, L1L184, L1L185);
--L1L187 is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[4]~64 at LC_X35_Y20_N9
--operation mode is arithmetic
L1L187 = AMPP_FUNCTION(KC1_q_b[12], L1L944, L1L184, L1L185);
--L1L1259 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[6]~1368 at LC_X12_Y15_N4
--operation mode is normal
L1L1259 = AMPP_FUNCTION(QC1_result[38], QC1_result[6]);
--L1_d_readdata_d1[6] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[6] at LC_X47_Y11_N4
--operation mode is normal
L1_d_readdata_d1[6] = AMPP_FUNCTION(DE1__clk0, FC1L21, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L9, M1L78, E1_data_out);
--L1_E_src2_prelim[6] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[6] at LC_X17_Y18_N6
--operation mode is normal
L1_E_src2_prelim[6] = AMPP_FUNCTION(DE1__clk0, L1L403, NC1_q_b[6], L1L1395, L1_W_wr_data[6], E1_data_out, L1L399, L1_W_stall);
--L1_E_src2_imm[0] is std_1s10:inst|cpu:the_cpu|E_src2_imm[0] at LC_X19_Y12_N2
--operation mode is normal
L1_E_src2_imm[0] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[2], L1_D_iw[5], L1_D_iw[6], L1L235, E1_data_out, L1_W_stall);
--L1L669 is std_1s10:inst|cpu:the_cpu|E_src2[0]~1515 at LC_X19_Y12_N4
--operation mode is normal
L1L669 = AMPP_FUNCTION(L1_E_src2_imm[0], L1L1325, L1_E_ctrl_src2_is_imm);
--L1_E_src1_prelim[0] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[0] at LC_X18_Y21_N8
--operation mode is normal
L1_E_src1_prelim[0] = AMPP_FUNCTION(DE1__clk0, L1_D_src1_hazard_W, MC1_q_b[0], L1L1377, L1_W_wr_data[0], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[0] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[0] at LC_X12_Y15_N9
--operation mode is normal
L1_M_mul_shift_rot_result[0] = AMPP_FUNCTION(DE1__clk0, L1L1284, QC1_result[0], L1L1253, QC1_result[32], E1_data_out, L1_M_ctrl_rot);
--L1L1375 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[0]~3693 at LC_X18_Y21_N6
--operation mode is normal
L1L1375 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[0]);
--L1_av_ld_data_aligned_or_div[0] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[0] at LC_X40_Y20_N2
--operation mode is normal
L1_av_ld_data_aligned_or_div[0] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[16], L1_d_readdata_d1[0], L1L137, L1_M_ld_align_sh16, E1_data_out, L1_M_ld_align_sh8);
--L1L1376 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[0]~3694 at LC_X27_Y21_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L1376 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_av_ld_data_aligned_or_div[0], L1_M_alu_result[0]);
--L1_av_ld_or_div_done is std_1s10:inst|cpu:the_cpu|av_ld_or_div_done at LC_X27_Y21_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_av_ld_or_div_done = AMPP_FUNCTION(DE1__clk0, L1_av_ld_aligning_data, E1_data_out, GND);
--L1L603 is std_1s10:inst|cpu:the_cpu|E_src1[0]~1989 at LC_X18_Y21_N9
--operation mode is normal
L1L603 = AMPP_FUNCTION(L1_E_src1_prelim[0], L1L1375, L1_E_src1_hazard_M, L1L1376);
--L1_E_src2_imm[1] is std_1s10:inst|cpu:the_cpu|E_src2_imm[1] at LC_X17_Y12_N2
--operation mode is normal
L1_E_src2_imm[1] = AMPP_FUNCTION(DE1__clk0, L1L235, L1_D_iw[5], L1_D_iw[2], L1_D_iw[7], E1_data_out, L1_W_stall);
--L1L670 is std_1s10:inst|cpu:the_cpu|E_src2[1]~1516 at LC_X17_Y12_N7
--operation mode is normal
L1L670 = AMPP_FUNCTION(L1_E_src2_imm[1], L1_E_ctrl_src2_is_imm, L1L1327);
--L1_E_src1_prelim[1] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[1] at LC_X13_Y17_N6
--operation mode is normal
L1_E_src1_prelim[1] = AMPP_FUNCTION(DE1__clk0, MC1_q_b[1], L1_D_src1_hazard_W, L1L1380, L1_W_wr_data[1], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[1] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[1] at LC_X12_Y13_N0
--operation mode is normal
L1_M_mul_shift_rot_result[1] = AMPP_FUNCTION(DE1__clk0, QC1_result[1], L1L1284, L1L1254, QC1_result[33], E1_data_out, L1_M_ctrl_rot);
--L1L1378 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[1]~3695 at LC_X13_Y17_N0
--operation mode is normal
L1L1378 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[1]);
--L1_av_ld_data_aligned_or_div[1] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[1] at LC_X39_Y21_N2
--operation mode is normal
L1_av_ld_data_aligned_or_div[1] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[1], L1_d_readdata_d1[17], L1L139, L1_M_ld_align_sh16, E1_data_out, L1_M_ld_align_sh8);
--L1L1379 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[1]~3696 at LC_X30_Y21_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L1379 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_av_ld_or_div_done, L1_av_ld_data_aligned_or_div[1]);
--L1_M_alu_result[1] is std_1s10:inst|cpu:the_cpu|M_alu_result[1] at LC_X30_Y21_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_alu_result[1] = AMPP_FUNCTION(DE1__clk0, L1L428, E1_data_out, GND, L1_W_stall);
--L1L604 is std_1s10:inst|cpu:the_cpu|E_src1[1]~1990 at LC_X13_Y17_N5
--operation mode is normal
L1L604 = AMPP_FUNCTION(L1_E_src1_hazard_M, L1_E_src1_prelim[1], L1L1379, L1L1378);
--HE1L15 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~99 at LC_X47_Y10_N2
--operation mode is normal
HE1L15 = !L1_M_alu_result[4] & (L1_M_alu_result[3] & L1_M_alu_result[2]);
--LB1L2 is std_1s10:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~149 at LC_X48_Y11_N4
--operation mode is normal
LB1L2 = NB1L2 & QB1L4 & P1L7 & !L1_M_alu_result[7];
--QB1L2 is std_1s10:inst|uart1_s1_arbitrator:the_uart1_s1|cpu_data_master_granted_uart1_s1~102 at LC_X48_Y9_N7
--operation mode is normal
QB1L2 = L1_M_alu_result[6] & !L1_M_alu_result[5];
--HE1L13 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_wr_strobe~20 at LC_X48_Y9_N4
--operation mode is normal
HE1L13 = QB1L2 & HE1L15 & L1_internal_d_write & LB1L2;
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] at LC_X52_Y7_N5
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0]_lut_out = KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] & (!KE1_do_load_shifter);
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KE1L48, , , , );
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] at LC_X51_Y7_N9
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]_lut_out = KE1_do_load_shifter & (HE1_internal_tx_data[2]) # !KE1_do_load_shifter & KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4];
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KE1L48, , , , );
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] at LC_X52_Y7_N9
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]_lut_out = KE1_do_load_shifter & HE1_internal_tx_data[1] # !KE1_do_load_shifter & (KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]);
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KE1L48, , , , );
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] at LC_X52_Y7_N8
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1]_lut_out = KE1_do_load_shifter & HE1_internal_tx_data[0] # !KE1_do_load_shifter & (KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2]);
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KE1L48, , , , );
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] at LC_X51_Y7_N2
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4]_lut_out = KE1_do_load_shifter & HE1_internal_tx_data[3] # !KE1_do_load_shifter & (KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5]);
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KE1L48, , , , );
--KE1L35 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd~61 at LC_X51_Y7_N0
--operation mode is normal
KE1L35 = !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] & !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] & !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] & !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3];
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] at LC_X51_Y7_N4
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5]_lut_out = KE1_do_load_shifter & (HE1_internal_tx_data[4]) # !KE1_do_load_shifter & KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6];
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KE1L48, , , , );
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] at LC_X51_Y7_N8
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6]_lut_out = KE1_do_load_shifter & HE1_internal_tx_data[5] # !KE1_do_load_shifter & (KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7]);
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KE1L48, , , , );
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] at LC_X51_Y7_N5
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7]_lut_out = KE1_do_load_shifter & (HE1_internal_tx_data[6]) # !KE1_do_load_shifter & KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8];
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KE1L48, , , , );
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] at LC_X51_Y7_N3
--operation mode is normal
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8]_lut_out = KE1_do_load_shifter & (HE1_internal_tx_data[7]) # !KE1_do_load_shifter & KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9];
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] = DFFEAS(KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KE1L48, , , , );
--KE1L36 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd~62 at LC_X51_Y7_N6
--operation mode is normal
KE1L36 = !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] & !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] & !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] & !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5];
--KE1L37 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|pre_txd~63 at LC_X51_Y7_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]_qfbk = KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9];
KE1L37 = KE1L35 & !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9]_qfbk & KE1L36;
--KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] at LC_X51_Y7_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] = DFFEAS(KE1L37, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KE1L48, KE1_do_load_shifter, , , VCC);
--L1_D_pc[13] is std_1s10:inst|cpu:the_cpu|D_pc[13] at LC_X34_Y17_N0
--operation mode is normal
L1_D_pc[13] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[13], E1_data_out, L1_W_stall);
--L1_D_pc[12] is std_1s10:inst|cpu:the_cpu|D_pc[12] at LC_X34_Y16_N1
--operation mode is normal
L1_D_pc[12] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[12], E1_data_out, L1_W_stall);
--L1_D_pc[11] is std_1s10:inst|cpu:the_cpu|D_pc[11] at LC_X34_Y14_N3
--operation mode is normal
L1_D_pc[11] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[11], E1_data_out, L1_W_stall);
--L1_D_pc[10] is std_1s10:inst|cpu:the_cpu|D_pc[10] at LC_X34_Y17_N5
--operation mode is normal
L1_D_pc[10] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[10], E1_data_out, L1_W_stall);
--L1L1126 is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[6]~COMBOUT at LC_X35_Y15_N7
--operation mode is normal
L1L1126 = AMPP_FUNCTION(L1_D_ic_fill_starting, L1_D_pc[9], L1_ic_fill_line[6]);
--L1_ic_tag_wraddress[6] is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[6] at LC_X35_Y15_N7
--operation mode is normal
L1_ic_tag_wraddress[6] = AMPP_FUNCTION(DE1__clk0, L1_D_ic_fill_starting, L1_D_pc[9], L1_M_alu_result[11], L1_ic_fill_line[6], E1_data_out, !L1_reset_d1, L1L1077);
--L1L1124 is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[5]~COMBOUT at LC_X35_Y15_N3
--operation mode is normal
L1L1124 = AMPP_FUNCTION(L1_D_ic_fill_starting, L1_ic_fill_line[5], L1_D_pc[8]);
--L1_ic_tag_wraddress[5] is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[5] at LC_X35_Y15_N3
--operation mode is normal
L1_ic_tag_wraddress[5] = AMPP_FUNCTION(DE1__clk0, L1_D_ic_fill_starting, L1_ic_fill_line[5], L1_M_alu_result[10], L1_D_pc[8], E1_data_out, !L1_reset_d1, L1L1077);
--L1L1122 is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[4]~COMBOUT at LC_X35_Y15_N2
--operation mode is normal
L1L1122 = AMPP_FUNCTION(L1_D_ic_fill_starting, L1_ic_fill_line[4], L1_D_pc[7]);
--L1_ic_tag_wraddress[4] is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[4] at LC_X35_Y15_N2
--operation mode is normal
L1_ic_tag_wraddress[4] = AMPP_FUNCTION(DE1__clk0, L1_D_ic_fill_starting, L1_ic_fill_line[4], L1_M_alu_result[9], L1_D_pc[7], E1_data_out, !L1_reset_d1, L1L1077);
--L1L1120 is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[3]~COMBOUT at LC_X35_Y15_N0
--operation mode is normal
L1L1120 = AMPP_FUNCTION(L1_D_ic_fill_starting, L1_D_pc[6], L1_ic_fill_line[3]);
--L1_ic_tag_wraddress[3] is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[3] at LC_X35_Y15_N0
--operation mode is normal
L1_ic_tag_wraddress[3] = AMPP_FUNCTION(DE1__clk0, L1_D_ic_fill_starting, L1_D_pc[6], L1_M_alu_result[8], L1_ic_fill_line[3], E1_data_out, !L1_reset_d1, L1L1077);
--L1L1118 is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[2]~COMBOUT at LC_X41_Y15_N8
--operation mode is normal
L1L1118 = AMPP_FUNCTION(L1_D_ic_fill_starting, L1_D_pc[5], L1_ic_fill_line[2]);
--L1_ic_tag_wraddress[2] is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[2] at LC_X41_Y15_N8
--operation mode is normal
L1_ic_tag_wraddress[2] = AMPP_FUNCTION(DE1__clk0, L1_D_ic_fill_starting, L1_D_pc[5], L1_M_alu_result[7], L1_ic_fill_line[2], E1_data_out, !L1_reset_d1, L1L1077);
--L1L1116 is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[1]~COMBOUT at LC_X41_Y15_N1
--operation mode is normal
L1L1116 = AMPP_FUNCTION(L1_ic_fill_line[1], L1_D_pc[4], L1_D_ic_fill_starting);
--L1_ic_tag_wraddress[1] is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[1] at LC_X41_Y15_N1
--operation mode is normal
L1_ic_tag_wraddress[1] = AMPP_FUNCTION(DE1__clk0, L1_ic_fill_line[1], L1_D_pc[4], L1_M_alu_result[6], L1_D_ic_fill_starting, E1_data_out, !L1_reset_d1, L1L1077);
--L1L1075 is std_1s10:inst|cpu:the_cpu|ic_fill_line~121 at LC_X35_Y21_N2
--operation mode is normal
L1L1075 = AMPP_FUNCTION(L1_ic_fill_line[0], L1_D_pc[3], L1L259, L1L260);
--L1L121 is std_1s10:inst|cpu:the_cpu|Add5~37 at LC_X36_Y10_N3
--operation mode is normal
L1L121 = AMPP_FUNCTION(L1_ic_fill_ap_offset[2], L1_ic_fill_ap_offset[0], L1_ic_fill_ap_offset[1]);
--L1L122 is std_1s10:inst|cpu:the_cpu|Add5~38 at LC_X36_Y10_N7
--operation mode is normal
L1L122 = AMPP_FUNCTION(L1_ic_fill_ap_offset[0], L1_ic_fill_ap_offset[1]);
--L1_E_control_rd_data_without_mmu_regs[1] is std_1s10:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[1] at LC_X30_Y21_N6
--operation mode is normal
L1_E_control_rd_data_without_mmu_regs[1] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[8], L1_M_ipending_reg[1], L1L205, L1_M_ienable_reg[1], E1_data_out, L1_W_stall);
--L1L426 is std_1s10:inst|cpu:the_cpu|E_alu_result[1]~2250 at LC_X18_Y13_N8
--operation mode is normal
L1L426 = AMPP_FUNCTION(L1_E_logic_op[1], L1L670, L1_E_logic_op[0], L1L604);
--L1L427 is std_1s10:inst|cpu:the_cpu|E_alu_result[1]~2251 at LC_X30_Y21_N8
--operation mode is normal
L1L427 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[1], L1_E_ctrl_dst_data_sel_logic_result, L1L426);
--L1L428 is std_1s10:inst|cpu:the_cpu|E_alu_result[1]~2252 at LC_X30_Y21_N7
--operation mode is normal
L1L428 = AMPP_FUNCTION(L1_E_ctrl_rdctl_inst, L1_E_control_rd_data_without_mmu_regs[1], L1_E_ctrl_dst_data_sel_cmp, L1L427);
--L1_M_ienable_reg[1] is std_1s10:inst|cpu:the_cpu|M_ienable_reg[1] at LC_X30_Y21_N7
--operation mode is normal
L1_M_ienable_reg[1] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_rdctl_inst, L1_E_control_rd_data_without_mmu_regs[1], L1_E_ctrl_dst_data_sel_cmp, L1L427, E1_data_out, L1L1187);
--L1_E_control_rd_data_without_mmu_regs[0] is std_1s10:inst|cpu:the_cpu|E_control_rd_data_without_mmu_regs[0] at LC_X29_Y21_N8
--operation mode is normal
L1_E_control_rd_data_without_mmu_regs[0] = AMPP_FUNCTION(DE1__clk0, L1_M_bstatus_reg, L1L203, L1L204, L1_D_iw[6], E1_data_out, L1_W_stall);
--L1L422 is std_1s10:inst|cpu:the_cpu|E_alu_result[0]~2253 at LC_X29_Y21_N6
--operation mode is normal
L1L422 = AMPP_FUNCTION(L1_E_logic_op[1], L1L603, L1_E_logic_op[0], L1L669);
--L1L423 is std_1s10:inst|cpu:the_cpu|E_alu_result[0]~2254 at LC_X29_Y21_N0
--operation mode is normal
L1L423 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, L1_E_ctrl_dst_data_sel_logic_result, HC1_result[0], L1L422);
--L1L424 is std_1s10:inst|cpu:the_cpu|E_alu_result[0]~2255 at LC_X29_Y21_N2
--operation mode is normal
L1L424 = AMPP_FUNCTION(L1_E_control_rd_data_without_mmu_regs[0], L1_E_ctrl_rdctl_inst, L1L423);
--L1L425 is std_1s10:inst|cpu:the_cpu|E_alu_result[0]~2256 at LC_X27_Y21_N0
--operation mode is normal
L1L425 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_cmp, L1L435, L1L424);
--L1_M_alu_result[0] is std_1s10:inst|cpu:the_cpu|M_alu_result[0] at LC_X27_Y21_N0
--operation mode is normal
L1_M_alu_result[0] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_cmp, L1L435, L1L424, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[1] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[1] at LC_X17_Y18_N9
--operation mode is normal
L1_E_src2_prelim[1] = AMPP_FUNCTION(DE1__clk0, L1L403, L1_W_wr_data[1], L1L1380, NC1_q_b[1], E1_data_out, L1L399, L1_W_stall);
--L1_E_src2_prelim[0] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[0] at LC_X17_Y18_N7
--operation mode is normal
L1_E_src2_prelim[0] = AMPP_FUNCTION(DE1__clk0, L1L403, NC1_q_b[0], L1L1377, L1_W_wr_data[0], E1_data_out, L1L399, L1_W_stall);
--GB1L43 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[7]~168 at LC_X34_Y9_N8
--operation mode is normal
GB1L43 = GB1L20 & L1_M_alu_result[9] # !GB1L20 & (L1_ic_fill_line[4]);
--EE1_entry_0[43] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[43] at LC_X34_Y9_N8
--operation mode is normal
EE1_entry_0[43] = DFFEAS(GB1L43, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--GB1L42 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[6]~169 at LC_X34_Y10_N7
--operation mode is normal
GB1L42 = GB1L20 & L1_M_alu_result[8] # !GB1L20 & (L1_ic_fill_line[3]);
--EE1_entry_0[42] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[42] at LC_X34_Y10_N7
--operation mode is normal
EE1_entry_0[42] = DFFEAS(GB1L42, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--GB1L41 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[5]~170 at LC_X34_Y9_N1
--operation mode is normal
GB1L41 = GB1L20 & (L1_M_alu_result[7]) # !GB1L20 & L1_ic_fill_line[2];
--EE1_entry_0[41] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[41] at LC_X34_Y9_N1
--operation mode is normal
EE1_entry_0[41] = DFFEAS(GB1L41, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--GB1L40 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[4]~171 at LC_X34_Y9_N6
--operation mode is normal
GB1L40 = GB1L20 & (L1_M_alu_result[6]) # !GB1L20 & (L1_ic_fill_line[1]);
--EE1_entry_0[40] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[40] at LC_X34_Y9_N6
--operation mode is normal
EE1_entry_0[40] = DFFEAS(GB1L40, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--GB1L39 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[3]~172 at LC_X36_Y7_N0
--operation mode is normal
GB1L39 = GB1L20 & L1_M_alu_result[5] # !GB1L20 & (L1_ic_fill_line[0]);
--EE1_entry_0[39] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[39] at LC_X36_Y7_N0
--operation mode is normal
EE1_entry_0[39] = DFFEAS(GB1L39, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--GB1L38 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[2]~173 at LC_X36_Y7_N5
--operation mode is normal
GB1L38 = GB1L20 & L1_M_alu_result[4] # !GB1L20 & (L1_ic_fill_ap_offset[2]);
--EE1_entry_0[38] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[38] at LC_X36_Y7_N5
--operation mode is normal
EE1_entry_0[38] = DFFEAS(GB1L38, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--GB1L37 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[1]~174 at LC_X39_Y7_N6
--operation mode is normal
GB1L37 = GB1L20 & (L1_M_alu_result[3]) # !GB1L20 & L1_ic_fill_ap_offset[1];
--EE1_entry_0[37] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[37] at LC_X39_Y7_N6
--operation mode is normal
EE1_entry_0[37] = DFFEAS(GB1L37, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--GB1L36 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_address[0]~175 at LC_X34_Y10_N8
--operation mode is normal
GB1L36 = GB1L20 & (L1_M_alu_result[2]) # !GB1L20 & L1_ic_fill_ap_offset[0];
--EE1_entry_0[36] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[36] at LC_X34_Y10_N8
--operation mode is normal
EE1_entry_0[36] = DFFEAS(GB1L36, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--FB1L406 is std_1s10:inst|sdram:the_sdram|module_input1[35]~36 at LC_X35_Y10_N0
--operation mode is normal
FB1L406 = !L1_M_mem_byte_en[3] & L1_internal_d_write & GB1L20;
--EE1_entry_0[35] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[35] at LC_X35_Y10_N0
--operation mode is normal
EE1_entry_0[35] = DFFEAS(FB1L406, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--FB1L405 is std_1s10:inst|sdram:the_sdram|module_input1[34]~37 at LC_X35_Y10_N9
--operation mode is normal
FB1L405 = !L1_M_mem_byte_en[2] & (L1_internal_d_write & GB1L20);
--EE1_entry_0[34] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[34] at LC_X35_Y10_N9
--operation mode is normal
EE1_entry_0[34] = DFFEAS(FB1L405, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--FB1L404 is std_1s10:inst|sdram:the_sdram|module_input1[33]~38 at LC_X35_Y10_N4
--operation mode is normal
FB1L404 = !L1_M_mem_byte_en[1] & (L1_internal_d_write & GB1L20);
--EE1_entry_0[33] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[33] at LC_X35_Y10_N4
--operation mode is normal
EE1_entry_0[33] = DFFEAS(FB1L404, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--FB1L403 is std_1s10:inst|sdram:the_sdram|module_input1[32]~39 at LC_X39_Y7_N9
--operation mode is normal
FB1L403 = !L1_M_mem_byte_en[0] & L1_internal_d_write & GB1L20;
--EE1_entry_0[32] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[32] at LC_X39_Y7_N9
--operation mode is normal
EE1_entry_0[32] = DFFEAS(FB1L403, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--ME3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] at LC_X29_Y28_N2
--operation mode is normal
ME3_Q[0] = AMPP_FUNCTION(!A1L6, ME3L3, DD1L118Q, ME3_Q[1], C1L17, !C1_CLR_SIGNAL, RE1_state[4], ME3L4);
--ME9_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] at LC_X29_Y26_N2
--operation mode is normal
ME9_Q[0] = AMPP_FUNCTION(!A1L6, ME3_Q[6], altera_internal_jtag, VCC, C1L18);
--NE1_WORD_SR[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] at LC_X28_Y28_N8
--operation mode is normal
NE1_WORD_SR[0] = AMPP_FUNCTION(!A1L6, NE1_WORD_SR[1], NE1L23, NE1_clear_signal, RE1_state[4], VCC, NE1L24);
--C1_HUB_BYPASS_REG is sld_hub:sld_hub_inst|HUB_BYPASS_REG at LC_X30_Y24_N4
--operation mode is normal
C1_HUB_BYPASS_REG = AMPP_FUNCTION(!A1L6, C1L11, VCC);
--SE1_dffe1a[0] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[0] at LC_X29_Y27_N9
--operation mode is normal
SE1_dffe1a[0] = AMPP_FUNCTION(!A1L6, ME3_Q[2], ME3_Q[3], C1L26, ME3_Q[1], !C1_CLR_SIGNAL, C1L5);
--C1L13 is sld_hub:sld_hub_inst|hub_tdo~543 at LC_X30_Y26_N3
--operation mode is normal
C1L13 = AMPP_FUNCTION(SE1_dffe1a[0], C1_HUB_BYPASS_REG, NE1_WORD_SR[0], ME9_Q[0]);
--QD1_td_shift[0] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[0] at LC_X31_Y26_N0
--operation mode is normal
QD1_td_shift[0] = AMPP_FUNCTION(!A1L6, QD1L67, QD1L65, ME4_Q[0], !C1_CLR_SIGNAL, !RE1_state[4], QD1L52);
--ME8_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] at LC_X29_Y26_N4
--operation mode is normal
ME8_Q[0] = AMPP_FUNCTION(!A1L6, ME3_Q[6], altera_internal_jtag, !C1_CLR_SIGNAL, C1L18);
--DD1_sr[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[0] at LC_X33_Y29_N5
--operation mode is normal
DD1_sr[0] = AMPP_FUNCTION(!A1L6, DD1L141, DD1L5, DD1L140, DD1L143, !C1_CLR_SIGNAL, DD1L6);
--ME8_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1] at LC_X29_Y26_N5
--operation mode is normal
ME8_Q[1] = AMPP_FUNCTION(!A1L6, ME3_Q[6], altera_internal_jtag, !C1_CLR_SIGNAL, C1L18);
--C1L14 is sld_hub:sld_hub_inst|hub_tdo~544 at LC_X30_Y26_N0
--operation mode is normal
C1L14 = AMPP_FUNCTION(DD1_sr[0], ME8_Q[0], QD1_td_shift[0], ME8_Q[1]);
--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 at LC_X28_Y23_N9
--operation mode is normal
C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(!A1L6, C1L6, C1L7, QE1_dffs[1], QE1_dffs[0], RE1_state[0], RE1_state[12]);
--C1L15 is sld_hub:sld_hub_inst|hub_tdo~545 at LC_X30_Y26_N1
--operation mode is normal
C1L15 = AMPP_FUNCTION(C1L13, C1L14, ME3_Q[0], C1_jtag_debug_mode_usr1);
--RE1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] at LC_X28_Y26_N0
--operation mode is normal
RE1_state[4] = AMPP_FUNCTION(!A1L6, RE1_state[7], RE1_state[3], RE1_state[4], VCC, !A1L8);
--RE1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] at LC_X28_Y5_N2
--operation mode is normal
RE1_state[3] = AMPP_FUNCTION(!A1L6, A1L8, RE1_state[2], VCC);
--RE1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8] at LC_X28_Y6_N4
--operation mode is normal
RE1_state[8] = AMPP_FUNCTION(!A1L6, RE1_state[7], RE1_state[5], VCC, A1L8);
--DB1_data_out is std_1s10:inst|reconfig_request_pio:the_reconfig_request_pio|data_out at LC_X41_Y15_N4
--operation mode is normal
DB1_data_out_lut_out = DB1L3 & (HE1L14 & (L1_M_st_data[0]) # !HE1L14 & DB1_data_out) # !DB1L3 & DB1_data_out;
DB1_data_out = DFFEAS(DB1_data_out_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--DB1_data_dir is std_1s10:inst|reconfig_request_pio:the_reconfig_request_pio|data_dir at LC_X41_Y15_N7
--operation mode is normal
DB1_data_dir_lut_out = HE1L16 & (DB1L3 & L1_M_st_data[0] # !DB1L3 & (DB1_data_dir)) # !HE1L16 & (DB1_data_dir);
DB1_data_dir = DFFEAS(DB1_data_dir_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1L243 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[31]~COMB_OUT at LC_X32_Y23_N1
--operation mode is normal
Q1L243 = L1_M_st_data[31] & (Q1L72 # !Q1L70);
--Q1L152 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~COMB_OUT at LC_X40_Y16_N2
--operation mode is normal
Q1L152 = !Q1L345 & L1_internal_d_write & (!Q1L462);
--Q1L240 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[30]~COMB_OUT at LC_X32_Y23_N5
--operation mode is normal
Q1L240 = L1_M_st_data[30] & (Q1L72 # !Q1L70);
--Q1L237 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[29]~COMB_OUT at LC_X32_Y23_N9
--operation mode is normal
Q1L237 = L1_M_st_data[29] & (Q1L72 # !Q1L70);
--Q1L234 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[28]~COMB_OUT at LC_X32_Y23_N4
--operation mode is normal
Q1L234 = L1_M_st_data[28] & (Q1L72 # !Q1L70);
--Q1L231 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[27]~COMB_OUT at LC_X32_Y23_N3
--operation mode is normal
Q1L231 = L1_M_st_data[27] & (Q1L72 # !Q1L70);
--Q1L228 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[26]~COMB_OUT at LC_X32_Y23_N0
--operation mode is normal
Q1L228 = L1_M_st_data[26] & (Q1L72 # !Q1L70);
--Q1L225 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[25]~COMB_OUT at LC_X32_Y23_N7
--operation mode is normal
Q1L225 = L1_M_st_data[25] & (Q1L72 # !Q1L70);
--Q1L222 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[24]~COMB_OUT at LC_X32_Y23_N6
--operation mode is normal
Q1L222 = L1_M_st_data[24] & (Q1L72 # !Q1L70);
--Q1L219 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[23]~COMB_OUT at LC_X32_Y23_N8
--operation mode is normal
Q1L219 = L1_M_st_data[23] & (Q1L72 # !Q1L70);
--Q1L216 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[22]~COMB_OUT at LC_X40_Y23_N6
--operation mode is normal
Q1L216 = L1_M_st_data[22] & (Q1L72 # !Q1L70);
--Q1L213 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[21]~COMB_OUT at LC_X40_Y23_N3
--operation mode is normal
Q1L213 = L1_M_st_data[21] & (Q1L72 # !Q1L70);
--Q1L210 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[20]~COMB_OUT at LC_X40_Y23_N9
--operation mode is normal
Q1L210 = L1_M_st_data[20] & (Q1L72 # !Q1L70);
--Q1L207 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[19]~COMB_OUT at LC_X40_Y23_N4
--operation mode is normal
Q1L207 = L1_M_st_data[19] & (Q1L72 # !Q1L70);
--Q1L204 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[18]~COMB_OUT at LC_X40_Y23_N1
--operation mode is normal
Q1L204 = L1_M_st_data[18] & (Q1L72 # !Q1L70);
--Q1L201 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[17]~COMB_OUT at LC_X40_Y23_N5
--operation mode is normal
Q1L201 = L1_M_st_data[17] & (Q1L72 # !Q1L70);
--Q1L198 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[16]~COMB_OUT at LC_X40_Y23_N0
--operation mode is normal
Q1L198 = L1_M_st_data[16] & (Q1L72 # !Q1L70);
--Q1L195 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[15]~COMB_OUT at LC_X40_Y23_N7
--operation mode is normal
Q1L195 = L1_M_st_data[15] & (Q1L72 # !Q1L70);
--Q1L192 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[14]~COMB_OUT at LC_X40_Y23_N2
--operation mode is normal
Q1L192 = L1_M_st_data[14] & (Q1L72 # !Q1L70);
--Q1L189 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[13]~COMB_OUT at LC_X40_Y23_N8
--operation mode is normal
Q1L189 = L1_M_st_data[13] & (Q1L72 # !Q1L70);
--Q1L186 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[12]~COMB_OUT at LC_X19_Y20_N9
--operation mode is normal
Q1L186 = L1_M_st_data[12] & (Q1L72 # !Q1L70);
--Q1L183 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[11]~COMB_OUT at LC_X19_Y20_N4
--operation mode is normal
Q1L183 = L1_M_st_data[11] & (Q1L72 # !Q1L70);
--Q1L180 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[10]~COMB_OUT at LC_X19_Y20_N8
--operation mode is normal
Q1L180 = L1_M_st_data[10] & (Q1L72 # !Q1L70);
--Q1L177 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[9]~COMB_OUT at LC_X19_Y20_N1
--operation mode is normal
Q1L177 = L1_M_st_data[9] & (Q1L72 # !Q1L70);
--Q1L174 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[8]~COMB_OUT at LC_X19_Y20_N3
--operation mode is normal
Q1L174 = L1_M_st_data[8] & (Q1L72 # !Q1L70);
--Q1L171 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7]~COMB_OUT at LC_X21_Y23_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[7]_qfbk = L1_M_st_data[7];
Q1L171 = M1L260 & (Q1L432 & Q1L431 # !Q1L432 & (L1_M_st_data[7]_qfbk)) # !M1L260 & (L1_M_st_data[7]_qfbk);
--L1_M_st_data[7] is std_1s10:inst|cpu:the_cpu|M_st_data[7] at LC_X21_Y23_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[7] = AMPP_FUNCTION(DE1__clk0, L1L1339, E1_data_out, GND, L1_W_stall);
--Q1L169 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6]~COMB_OUT at LC_X21_Y23_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[6]_qfbk = L1_M_st_data[6];
Q1L169 = M1L260 & (Q1L432 & Q1L429 # !Q1L432 & (L1_M_st_data[6]_qfbk)) # !M1L260 & (L1_M_st_data[6]_qfbk);
--L1_M_st_data[6] is std_1s10:inst|cpu:the_cpu|M_st_data[6] at LC_X21_Y23_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[6] = AMPP_FUNCTION(DE1__clk0, L1L1337, E1_data_out, GND, L1_W_stall);
--Q1L167 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5]~COMB_OUT at LC_X21_Y23_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[5]_qfbk = L1_M_st_data[5];
Q1L167 = M1L260 & (Q1L432 & Q1L427 # !Q1L432 & (L1_M_st_data[5]_qfbk)) # !M1L260 & (L1_M_st_data[5]_qfbk);
--L1_M_st_data[5] is std_1s10:inst|cpu:the_cpu|M_st_data[5] at LC_X21_Y23_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[5] = AMPP_FUNCTION(DE1__clk0, L1L1335, E1_data_out, GND, L1_W_stall);
--Q1L165 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[4]~COMB_OUT at LC_X21_Y23_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[4]_qfbk = L1_M_st_data[4];
Q1L165 = M1L260 & (Q1L432 & Q1L425 # !Q1L432 & (L1_M_st_data[4]_qfbk)) # !M1L260 & (L1_M_st_data[4]_qfbk);
--L1_M_st_data[4] is std_1s10:inst|cpu:the_cpu|M_st_data[4] at LC_X21_Y23_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[4] = AMPP_FUNCTION(DE1__clk0, L1L1333, E1_data_out, GND, L1_W_stall);
--Q1L163 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[3]~COMB_OUT at LC_X21_Y23_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[3]_qfbk = L1_M_st_data[3];
Q1L163 = M1L260 & (Q1L432 & Q1L423 # !Q1L432 & (L1_M_st_data[3]_qfbk)) # !M1L260 & (L1_M_st_data[3]_qfbk);
--L1_M_st_data[3] is std_1s10:inst|cpu:the_cpu|M_st_data[3] at LC_X21_Y23_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[3] = AMPP_FUNCTION(DE1__clk0, L1L1331, E1_data_out, GND, L1_W_stall);
--Q1L161 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[2]~COMB_OUT at LC_X21_Y23_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[2]_qfbk = L1_M_st_data[2];
Q1L161 = M1L260 & (Q1L432 & Q1L421 # !Q1L432 & (L1_M_st_data[2]_qfbk)) # !M1L260 & (L1_M_st_data[2]_qfbk);
--L1_M_st_data[2] is std_1s10:inst|cpu:the_cpu|M_st_data[2] at LC_X21_Y23_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[2] = AMPP_FUNCTION(DE1__clk0, L1L1329, E1_data_out, GND, L1_W_stall);
--Q1L159 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[1]~COMB_OUT at LC_X21_Y23_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[1]_qfbk = L1_M_st_data[1];
Q1L159 = M1L260 & (Q1L432 & Q1L419 # !Q1L432 & (L1_M_st_data[1]_qfbk)) # !M1L260 & (L1_M_st_data[1]_qfbk);
--L1_M_st_data[1] is std_1s10:inst|cpu:the_cpu|M_st_data[1] at LC_X21_Y23_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[1] = AMPP_FUNCTION(DE1__clk0, L1L1327, E1_data_out, GND, L1_W_stall);
--Q1L157 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[0]~COMB_OUT at LC_X21_Y23_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[0]_qfbk = L1_M_st_data[0];
Q1L157 = M1L260 & (Q1L432 & Q1L417 # !Q1L432 & (L1_M_st_data[0]_qfbk)) # !M1L260 & (L1_M_st_data[0]_qfbk);
--L1_M_st_data[0] is std_1s10:inst|cpu:the_cpu|M_st_data[0] at LC_X21_Y23_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_st_data[0] = AMPP_FUNCTION(DE1__clk0, L1L1325, E1_data_out, GND, L1_W_stall);
--FB1L366 is std_1s10:inst|sdram:the_sdram|m_data[31]~COMB_OUT at LC_X36_Y3_N0
--operation mode is normal
FB1L366 = FB1L680 & (FB1L681 & FB1L679 # !FB1L681 & (FB1L365Q)) # !FB1L680 & (FB1L365Q);
--FB1L365Q is std_1s10:inst|sdram:the_sdram|m_data[31]~_Duplicate_1 at LC_X36_Y3_N0
--operation mode is normal
FB1L365Q = DFFEAS(FB1L366, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_oe is std_1s10:inst|sdram:the_sdram|oe at LC_X36_Y1_N7
--operation mode is normal
FB1_oe_lut_out = FB1L718 & (!FB1L724 & EE1L127 # !FB1_f_pop);
FB1_oe = DFFEAS(FB1_oe_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L362 is std_1s10:inst|sdram:the_sdram|m_data[30]~COMB_OUT at LC_X36_Y3_N6
--operation mode is normal
FB1L362 = FB1L681 & (FB1L680 & (FB1L682) # !FB1L680 & FB1L361Q) # !FB1L681 & FB1L361Q;
--FB1L361Q is std_1s10:inst|sdram:the_sdram|m_data[30]~_Duplicate_1 at LC_X36_Y3_N6
--operation mode is normal
FB1L361Q = DFFEAS(FB1L362, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L358 is std_1s10:inst|sdram:the_sdram|m_data[29]~COMB_OUT at LC_X36_Y3_N8
--operation mode is normal
FB1L358 = FB1L680 & (FB1L681 & FB1L683 # !FB1L681 & (FB1L357Q)) # !FB1L680 & (FB1L357Q);
--FB1L357Q is std_1s10:inst|sdram:the_sdram|m_data[29]~_Duplicate_1 at LC_X36_Y3_N8
--operation mode is normal
FB1L357Q = DFFEAS(FB1L358, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L354 is std_1s10:inst|sdram:the_sdram|m_data[28]~COMB_OUT at LC_X36_Y3_N7
--operation mode is normal
FB1L354 = FB1L680 & (FB1L681 & (FB1L684) # !FB1L681 & FB1L353Q) # !FB1L680 & (FB1L353Q);
--FB1L353Q is std_1s10:inst|sdram:the_sdram|m_data[28]~_Duplicate_1 at LC_X36_Y3_N7
--operation mode is normal
FB1L353Q = DFFEAS(FB1L354, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L350 is std_1s10:inst|sdram:the_sdram|m_data[27]~COMB_OUT at LC_X39_Y6_N0
--operation mode is normal
FB1L350 = FB1L680 & (FB1L681 & FB1L685 # !FB1L681 & (FB1L349Q)) # !FB1L680 & (FB1L349Q);
--FB1L349Q is std_1s10:inst|sdram:the_sdram|m_data[27]~_Duplicate_1 at LC_X39_Y6_N0
--operation mode is normal
FB1L349Q = DFFEAS(FB1L350, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L346 is std_1s10:inst|sdram:the_sdram|m_data[26]~COMB_OUT at LC_X39_Y6_N3
--operation mode is normal
FB1L346 = FB1L681 & (FB1L680 & FB1L686 # !FB1L680 & (FB1L345Q)) # !FB1L681 & (FB1L345Q);
--FB1L345Q is std_1s10:inst|sdram:the_sdram|m_data[26]~_Duplicate_1 at LC_X39_Y6_N3
--operation mode is normal
FB1L345Q = DFFEAS(FB1L346, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L342 is std_1s10:inst|sdram:the_sdram|m_data[25]~COMB_OUT at LC_X39_Y6_N5
--operation mode is normal
FB1L342 = FB1L680 & (FB1L681 & (FB1L687) # !FB1L681 & FB1L341Q) # !FB1L680 & FB1L341Q;
--FB1L341Q is std_1s10:inst|sdram:the_sdram|m_data[25]~_Duplicate_1 at LC_X39_Y6_N5
--operation mode is normal
FB1L341Q = DFFEAS(FB1L342, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L338 is std_1s10:inst|sdram:the_sdram|m_data[24]~COMB_OUT at LC_X41_Y4_N9
--operation mode is normal
FB1L338 = FB1L680 & (FB1L681 & FB1L688 # !FB1L681 & (FB1L337Q)) # !FB1L680 & (FB1L337Q);
--FB1L337Q is std_1s10:inst|sdram:the_sdram|m_data[24]~_Duplicate_1 at LC_X41_Y4_N9
--operation mode is normal
FB1L337Q = DFFEAS(FB1L338, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L334 is std_1s10:inst|sdram:the_sdram|m_data[23]~COMB_OUT at LC_X41_Y4_N5
--operation mode is normal
FB1L334 = FB1L681 & (FB1L680 & (FB1L689) # !FB1L680 & FB1L333Q) # !FB1L681 & (FB1L333Q);
--FB1L333Q is std_1s10:inst|sdram:the_sdram|m_data[23]~_Duplicate_1 at LC_X41_Y4_N5
--operation mode is normal
FB1L333Q = DFFEAS(FB1L334, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L330 is std_1s10:inst|sdram:the_sdram|m_data[22]~COMB_OUT at LC_X41_Y4_N4
--operation mode is normal
FB1L330 = FB1L681 & (FB1L680 & FB1L690 # !FB1L680 & (FB1L329Q)) # !FB1L681 & (FB1L329Q);
--FB1L329Q is std_1s10:inst|sdram:the_sdram|m_data[22]~_Duplicate_1 at LC_X41_Y4_N4
--operation mode is normal
FB1L329Q = DFFEAS(FB1L330, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L326 is std_1s10:inst|sdram:the_sdram|m_data[21]~COMB_OUT at LC_X40_Y3_N9
--operation mode is normal
FB1L326 = FB1L680 & (FB1L681 & FB1L691 # !FB1L681 & (FB1L325Q)) # !FB1L680 & (FB1L325Q);
--FB1L325Q is std_1s10:inst|sdram:the_sdram|m_data[21]~_Duplicate_1 at LC_X40_Y3_N9
--operation mode is normal
FB1L325Q = DFFEAS(FB1L326, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L322 is std_1s10:inst|sdram:the_sdram|m_data[20]~COMB_OUT at LC_X40_Y3_N7
--operation mode is normal
FB1L322 = FB1L680 & (FB1L681 & (FB1L692) # !FB1L681 & FB1L321Q) # !FB1L680 & FB1L321Q;
--FB1L321Q is std_1s10:inst|sdram:the_sdram|m_data[20]~_Duplicate_1 at LC_X40_Y3_N7
--operation mode is normal
FB1L321Q = DFFEAS(FB1L322, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L318 is std_1s10:inst|sdram:the_sdram|m_data[19]~COMB_OUT at LC_X40_Y3_N8
--operation mode is normal
FB1L318 = FB1L681 & (FB1L680 & (FB1L693) # !FB1L680 & FB1L317Q) # !FB1L681 & FB1L317Q;
--FB1L317Q is std_1s10:inst|sdram:the_sdram|m_data[19]~_Duplicate_1 at LC_X40_Y3_N8
--operation mode is normal
FB1L317Q = DFFEAS(FB1L318, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L314 is std_1s10:inst|sdram:the_sdram|m_data[18]~COMB_OUT at LC_X41_Y6_N7
--operation mode is normal
FB1L314 = FB1L681 & (FB1L680 & FB1L694 # !FB1L680 & (FB1L313Q)) # !FB1L681 & (FB1L313Q);
--FB1L313Q is std_1s10:inst|sdram:the_sdram|m_data[18]~_Duplicate_1 at LC_X41_Y6_N7
--operation mode is normal
FB1L313Q = DFFEAS(FB1L314, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L310 is std_1s10:inst|sdram:the_sdram|m_data[17]~COMB_OUT at LC_X41_Y6_N9
--operation mode is normal
FB1L310 = FB1L680 & (FB1L681 & FB1L695 # !FB1L681 & (FB1L309Q)) # !FB1L680 & (FB1L309Q);
--FB1L309Q is std_1s10:inst|sdram:the_sdram|m_data[17]~_Duplicate_1 at LC_X41_Y6_N9
--operation mode is normal
FB1L309Q = DFFEAS(FB1L310, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L306 is std_1s10:inst|sdram:the_sdram|m_data[16]~COMB_OUT at LC_X41_Y6_N3
--operation mode is normal
FB1L306 = FB1L680 & (FB1L681 & (FB1L696) # !FB1L681 & FB1L305Q) # !FB1L680 & (FB1L305Q);
--FB1L305Q is std_1s10:inst|sdram:the_sdram|m_data[16]~_Duplicate_1 at LC_X41_Y6_N3
--operation mode is normal
FB1L305Q = DFFEAS(FB1L306, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L302 is std_1s10:inst|sdram:the_sdram|m_data[15]~COMB_OUT at LC_X44_Y4_N9
--operation mode is normal
FB1L302 = FB1L680 & (FB1L681 & FB1L697 # !FB1L681 & (FB1L301Q)) # !FB1L680 & (FB1L301Q);
--FB1L301Q is std_1s10:inst|sdram:the_sdram|m_data[15]~_Duplicate_1 at LC_X44_Y4_N9
--operation mode is normal
FB1L301Q = DFFEAS(FB1L302, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L298 is std_1s10:inst|sdram:the_sdram|m_data[14]~COMB_OUT at LC_X44_Y4_N4
--operation mode is normal
FB1L298 = FB1L680 & (FB1L681 & (FB1L698) # !FB1L681 & FB1L297Q) # !FB1L680 & FB1L297Q;
--FB1L297Q is std_1s10:inst|sdram:the_sdram|m_data[14]~_Duplicate_1 at LC_X44_Y4_N4
--operation mode is normal
FB1L297Q = DFFEAS(FB1L298, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L294 is std_1s10:inst|sdram:the_sdram|m_data[13]~COMB_OUT at LC_X44_Y4_N7
--operation mode is normal
FB1L294 = FB1L680 & (FB1L681 & (FB1L699) # !FB1L681 & FB1L293Q) # !FB1L680 & (FB1L293Q);
--FB1L293Q is std_1s10:inst|sdram:the_sdram|m_data[13]~_Duplicate_1 at LC_X44_Y4_N7
--operation mode is normal
FB1L293Q = DFFEAS(FB1L294, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L290 is std_1s10:inst|sdram:the_sdram|m_data[12]~COMB_OUT at LC_X44_Y6_N9
--operation mode is normal
FB1L290 = FB1L681 & (FB1L680 & FB1L700 # !FB1L680 & (FB1L289Q)) # !FB1L681 & (FB1L289Q);
--FB1L289Q is std_1s10:inst|sdram:the_sdram|m_data[12]~_Duplicate_1 at LC_X44_Y6_N9
--operation mode is normal
FB1L289Q = DFFEAS(FB1L290, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L286 is std_1s10:inst|sdram:the_sdram|m_data[11]~COMB_OUT at LC_X44_Y6_N4
--operation mode is normal
FB1L286 = FB1L681 & (FB1L680 & (FB1L701) # !FB1L680 & FB1L285Q) # !FB1L681 & FB1L285Q;
--FB1L285Q is std_1s10:inst|sdram:the_sdram|m_data[11]~_Duplicate_1 at LC_X44_Y6_N4
--operation mode is normal
FB1L285Q = DFFEAS(FB1L286, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L282 is std_1s10:inst|sdram:the_sdram|m_data[10]~COMB_OUT at LC_X44_Y6_N8
--operation mode is normal
FB1L282 = FB1L680 & (FB1L681 & (FB1L702) # !FB1L681 & FB1L281Q) # !FB1L680 & FB1L281Q;
--FB1L281Q is std_1s10:inst|sdram:the_sdram|m_data[10]~_Duplicate_1 at LC_X44_Y6_N8
--operation mode is normal
FB1L281Q = DFFEAS(FB1L282, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L278 is std_1s10:inst|sdram:the_sdram|m_data[9]~COMB_OUT at LC_X44_Y3_N9
--operation mode is normal
FB1L278 = FB1L681 & (FB1L680 & FB1L703 # !FB1L680 & (FB1L277Q)) # !FB1L681 & (FB1L277Q);
--FB1L277Q is std_1s10:inst|sdram:the_sdram|m_data[9]~_Duplicate_1 at LC_X44_Y3_N9
--operation mode is normal
FB1L277Q = DFFEAS(FB1L278, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L274 is std_1s10:inst|sdram:the_sdram|m_data[8]~COMB_OUT at LC_X44_Y3_N7
--operation mode is normal
FB1L274 = FB1L681 & (FB1L680 & (FB1L704) # !FB1L680 & FB1L273Q) # !FB1L681 & (FB1L273Q);
--FB1L273Q is std_1s10:inst|sdram:the_sdram|m_data[8]~_Duplicate_1 at LC_X44_Y3_N7
--operation mode is normal
FB1L273Q = DFFEAS(FB1L274, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L270 is std_1s10:inst|sdram:the_sdram|m_data[7]~COMB_OUT at LC_X44_Y3_N4
--operation mode is normal
FB1L270 = FB1L681 & (FB1L680 & FB1L705 # !FB1L680 & (FB1L269Q)) # !FB1L681 & (FB1L269Q);
--FB1L269Q is std_1s10:inst|sdram:the_sdram|m_data[7]~_Duplicate_1 at LC_X44_Y3_N4
--operation mode is normal
FB1L269Q = DFFEAS(FB1L270, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L266 is std_1s10:inst|sdram:the_sdram|m_data[6]~COMB_OUT at LC_X45_Y5_N6
--operation mode is normal
FB1L266 = FB1L681 & (FB1L680 & (FB1L706) # !FB1L680 & FB1L265Q) # !FB1L681 & FB1L265Q;
--FB1L265Q is std_1s10:inst|sdram:the_sdram|m_data[6]~_Duplicate_1 at LC_X45_Y5_N6
--operation mode is normal
FB1L265Q = DFFEAS(FB1L266, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L262 is std_1s10:inst|sdram:the_sdram|m_data[5]~COMB_OUT at LC_X45_Y5_N7
--operation mode is normal
FB1L262 = FB1L681 & (FB1L680 & (FB1L707) # !FB1L680 & FB1L261Q) # !FB1L681 & (FB1L261Q);
--FB1L261Q is std_1s10:inst|sdram:the_sdram|m_data[5]~_Duplicate_1 at LC_X45_Y5_N7
--operation mode is normal
FB1L261Q = DFFEAS(FB1L262, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L258 is std_1s10:inst|sdram:the_sdram|m_data[4]~COMB_OUT at LC_X45_Y5_N1
--operation mode is normal
FB1L258 = FB1L681 & (FB1L680 & (FB1L708) # !FB1L680 & FB1L257Q) # !FB1L681 & FB1L257Q;
--FB1L257Q is std_1s10:inst|sdram:the_sdram|m_data[4]~_Duplicate_1 at LC_X45_Y5_N1
--operation mode is normal
FB1L257Q = DFFEAS(FB1L258, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L254 is std_1s10:inst|sdram:the_sdram|m_data[3]~COMB_OUT at LC_X45_Y4_N6
--operation mode is normal
FB1L254 = FB1L681 & (FB1L680 & (FB1L709) # !FB1L680 & FB1L253Q) # !FB1L681 & FB1L253Q;
--FB1L253Q is std_1s10:inst|sdram:the_sdram|m_data[3]~_Duplicate_1 at LC_X45_Y4_N6
--operation mode is normal
FB1L253Q = DFFEAS(FB1L254, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L250 is std_1s10:inst|sdram:the_sdram|m_data[2]~COMB_OUT at LC_X45_Y4_N8
--operation mode is normal
FB1L250 = FB1L681 & (FB1L680 & FB1L710 # !FB1L680 & (FB1L249Q)) # !FB1L681 & (FB1L249Q);
--FB1L249Q is std_1s10:inst|sdram:the_sdram|m_data[2]~_Duplicate_1 at LC_X45_Y4_N8
--operation mode is normal
FB1L249Q = DFFEAS(FB1L250, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L246 is std_1s10:inst|sdram:the_sdram|m_data[1]~COMB_OUT at LC_X45_Y4_N2
--operation mode is normal
FB1L246 = FB1L680 & (FB1L681 & (FB1L711) # !FB1L681 & FB1L245Q) # !FB1L680 & FB1L245Q;
--FB1L245Q is std_1s10:inst|sdram:the_sdram|m_data[1]~_Duplicate_1 at LC_X45_Y4_N2
--operation mode is normal
FB1L245Q = DFFEAS(FB1L246, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L242 is std_1s10:inst|sdram:the_sdram|m_data[0]~COMB_OUT at LC_X40_Y5_N9
--operation mode is normal
FB1L242 = FB1L680 & (FB1L681 & (FB1L712) # !FB1L681 & FB1L241Q) # !FB1L680 & FB1L241Q;
--FB1L241Q is std_1s10:inst|sdram:the_sdram|m_data[0]~_Duplicate_1 at LC_X40_Y5_N9
--operation mode is normal
FB1L241Q = DFFEAS(FB1L242, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--L1_ic_fill_ap_cnt[2] is std_1s10:inst|cpu:the_cpu|ic_fill_ap_cnt[2] at LC_X40_Y13_N2
--operation mode is normal
L1_ic_fill_ap_cnt[2] = AMPP_FUNCTION(DE1__clk0, N1L114, L1_ic_fill_ap_cnt[2], L1L124, L1_internal_i_read, E1_data_out, L1L1064);
--L1_ic_fill_ap_cnt[1] is std_1s10:inst|cpu:the_cpu|ic_fill_ap_cnt[1] at LC_X41_Y13_N0
--operation mode is normal
L1_ic_fill_ap_cnt[1] = AMPP_FUNCTION(DE1__clk0, L1_internal_i_read, L1_ic_fill_ap_cnt[1], N1L114, L1_ic_fill_ap_cnt[0], E1_data_out, L1L1064);
--L1_ic_fill_ap_cnt[0] is std_1s10:inst|cpu:the_cpu|ic_fill_ap_cnt[0] at LC_X41_Y13_N4
--operation mode is normal
L1_ic_fill_ap_cnt[0] = AMPP_FUNCTION(DE1__clk0, L1_D_ic_fill_starting, N1L114, L1_internal_i_read, L1_ic_fill_ap_cnt[0], E1_data_out);
--L1L123 is std_1s10:inst|cpu:the_cpu|Add6~103 at LC_X41_Y13_N2
--operation mode is normal
L1L123 = AMPP_FUNCTION(L1_ic_fill_ap_cnt[0], L1_ic_fill_ap_cnt[2], L1_ic_fill_ap_cnt[1]);
--L1L1064 is std_1s10:inst|cpu:the_cpu|ic_fill_initial_offset[0]~801 at LC_X40_Y13_N4
--operation mode is normal
L1L1064 = AMPP_FUNCTION(L1_internal_i_read, L1_D_ic_fill_starting, N1L114);
--GB1L77 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[5]~541 at LC_X41_Y11_N7
--operation mode is normal
GB1L77 = GB1_sdram_s1_slavearbiterlockenable & (GB1L19 # GB1L76);
--GB1L78 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_winner[0]~30 at LC_X41_Y12_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
GB1_sdram_s1_saved_chosen_master_vector[0]_qfbk = GB1_sdram_s1_saved_chosen_master_vector[0];
GB1L78 = GB1L77 & (GB1_sdram_s1_saved_chosen_master_vector[0]_qfbk) # !GB1L77 & (GB1L25 # GB1_sdram_s1_saved_chosen_master_vector[0]_qfbk & !GB1L20);
--GB1_sdram_s1_saved_chosen_master_vector[0] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_saved_chosen_master_vector[0] at LC_X41_Y12_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
GB1_sdram_s1_saved_chosen_master_vector[0] = DFFEAS(GB1L78, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GB1L79, GB1L25, , , VCC);
--GB1L62 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[1]~733 at LC_X39_Y11_N8
--operation mode is normal
GB1L62 = EE1L126 & (FB1L407 & GB1L20 # !FB1L407 & (GB1L78)) # !EE1L126 & (GB1L78);
--GB1_WideOr1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|WideOr1 at LC_X39_Y11_N1
--operation mode is normal
GB1_WideOr1 = GB1_sdram_s1_arb_addend[0] & GB1_sdram_s1_arb_addend[1] & (GB1L26 # GB1L23) # !GB1_sdram_s1_arb_addend[0] & (GB1L26 # GB1L23);
--FE1L21 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|updated_one_count~62 at LC_X39_Y10_N6
--operation mode is normal
FE1L21 = !EE1L126 & GB1L20 & (L1_internal_d_read # GB1L25);
--FE1L22 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|updated_one_count~63 at LC_X44_Y10_N7
--operation mode is normal
FE1L22 = FE1_stage_0 & FB1_za_valid;
--FE1L1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1192 at LC_X44_Y10_N5
--operation mode is normal
FE1L1 = FE1_how_many_ones[1] & FE1_how_many_ones[0] & !FE1L22 & FE1_how_many_ones[2] # !FE1_how_many_ones[1] & !FE1_how_many_ones[0] & FE1L22 & !FE1_how_many_ones[2];
--FE1L2 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1193 at LC_X41_Y10_N2
--operation mode is normal
FE1_how_many_ones[3]_qfbk = FE1_how_many_ones[3];
FE1L2 = FE1_how_many_ones[3]_qfbk $ (FE1L1 & (FE1L21 $ !FE1_how_many_ones[2]));
--FE1_how_many_ones[3] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[3] at LC_X41_Y10_N2
--operation mode is normal
FE1_how_many_ones[3] = DFFEAS(FE1L2, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GE1L27, , , , );
--FE1L3 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1194 at LC_X41_Y10_N4
--operation mode is normal
FE1_how_many_ones[2]_qfbk = FE1_how_many_ones[2];
FE1L3 = FE1_how_many_ones[2]_qfbk $ (FE1L5 & (FE1L21 $ !FE1_how_many_ones[1]));
--FE1_how_many_ones[2] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[2] at LC_X41_Y10_N4
--operation mode is normal
FE1_how_many_ones[2] = DFFEAS(FE1L3, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GE1L27, , , , );
--FE1L4 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1195 at LC_X40_Y10_N6
--operation mode is normal
FE1_how_many_ones[1]_qfbk = FE1_how_many_ones[1];
FE1L4 = FE1_how_many_ones[1]_qfbk $ (FE1L22 & !FE1L21 & !FE1_how_many_ones[0] # !FE1L22 & FE1L21 & FE1_how_many_ones[0]);
--FE1_how_many_ones[1] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[1] at LC_X40_Y10_N6
--operation mode is normal
FE1_how_many_ones[1] = DFFEAS(FE1L4, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GE1L27, , , , );
--GB1L2 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~99 at LC_X40_Y9_N1
--operation mode is arithmetic
GB1L2 = !GB1_sdram_s1_arb_share_counter[0];
--GB1L3 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~100 at LC_X40_Y9_N1
--operation mode is arithmetic
GB1L3_cout_0 = GB1_sdram_s1_arb_share_counter[0];
GB1L3 = CARRY(GB1L3_cout_0);
--GB1L4 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~100COUT1_131 at LC_X40_Y9_N1
--operation mode is arithmetic
GB1L4_cout_1 = GB1_sdram_s1_arb_share_counter[0];
GB1L4 = CARRY(GB1L4_cout_1);
--GB1_sdram_s1_arb_share_counter[3] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[3] at LC_X40_Y9_N0
--operation mode is normal
GB1_sdram_s1_arb_share_counter[3]_lut_out = GB1L73 & GB1L14;
GB1_sdram_s1_arb_share_counter[3] = DFFEAS(GB1_sdram_s1_arb_share_counter[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GB1L64, , , , );
--GB1L90 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|WideOr0~28 at LC_X40_Y9_N9
--operation mode is normal
GB1L90 = GB1_sdram_s1_arb_share_counter[1] # GB1_sdram_s1_arb_share_counter[2] # GB1_sdram_s1_arb_share_counter[0] # GB1_sdram_s1_arb_share_counter[3];
--GB1_sdram_s1_arb_share_counter[4] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[4] at LC_X40_Y9_N8
--operation mode is normal
GB1_sdram_s1_arb_share_counter[4]_lut_out = GB1L11 & GB1L73;
GB1_sdram_s1_arb_share_counter[4] = DFFEAS(GB1_sdram_s1_arb_share_counter[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GB1L64, , , , );
--GB1_sdram_s1_arb_share_counter[5] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[5] at LC_X41_Y9_N9
--operation mode is normal
GB1_sdram_s1_arb_share_counter[5]_lut_out = GB1L73 & GB1L18;
GB1_sdram_s1_arb_share_counter[5] = DFFEAS(GB1_sdram_s1_arb_share_counter[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GB1L64, , , , );
--GB1_WideOr0 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|WideOr0 at LC_X41_Y9_N8
--operation mode is normal
GB1_WideOr0 = GB1_sdram_s1_arb_share_counter[4] # GB1L90 # GB1_sdram_s1_arb_share_counter[5];
--GB1L72 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[0]~542 at LC_X41_Y9_N3
--operation mode is normal
GB1L72 = GB1L77 & GB1_WideOr0 & (GB1L2) # !GB1L77 & (GB1L25);
--GB1_sdram_s1_arb_share_counter[0] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[0] at LC_X41_Y9_N3
--operation mode is normal
GB1_sdram_s1_arb_share_counter[0] = DFFEAS(GB1L72, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GB1L64, , , , );
--GB1L5 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~101 at LC_X40_Y9_N2
--operation mode is arithmetic
GB1L5 = GB1_sdram_s1_arb_share_counter[1] $ (!GB1L3);
--GB1L6 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~102 at LC_X40_Y9_N2
--operation mode is arithmetic
GB1L6_cout_0 = !GB1_sdram_s1_arb_share_counter[1] & (!GB1L3);
GB1L6 = CARRY(GB1L6_cout_0);
--GB1L7 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~102COUT1_133 at LC_X40_Y9_N2
--operation mode is arithmetic
GB1L7_cout_1 = !GB1_sdram_s1_arb_share_counter[1] & (!GB1L4);
GB1L7 = CARRY(GB1L7_cout_1);
--GB1L74 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[1]~543 at LC_X41_Y9_N4
--operation mode is normal
GB1L74 = GB1L77 & GB1_WideOr0 & (GB1L5) # !GB1L77 & (GB1L25);
--GB1_sdram_s1_arb_share_counter[1] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[1] at LC_X41_Y9_N4
--operation mode is normal
GB1_sdram_s1_arb_share_counter[1] = DFFEAS(GB1L74, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GB1L64, , , , );
--GB1L8 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~103 at LC_X40_Y9_N3
--operation mode is arithmetic
GB1L8 = GB1_sdram_s1_arb_share_counter[2] $ GB1L6;
--GB1L9 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~104 at LC_X40_Y9_N3
--operation mode is arithmetic
GB1L9_cout_0 = GB1_sdram_s1_arb_share_counter[2] # !GB1L6;
GB1L9 = CARRY(GB1L9_cout_0);
--GB1L10 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~104COUT1_135 at LC_X40_Y9_N3
--operation mode is arithmetic
GB1L10_cout_1 = GB1_sdram_s1_arb_share_counter[2] # !GB1L7;
GB1L10 = CARRY(GB1L10_cout_1);
--GB1L75 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[2]~544 at LC_X41_Y9_N6
--operation mode is normal
GB1L75 = GB1L77 & GB1_WideOr0 & GB1L8 # !GB1L77 & (GB1L25);
--GB1_sdram_s1_arb_share_counter[2] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter[2] at LC_X41_Y9_N6
--operation mode is normal
GB1_sdram_s1_arb_share_counter[2] = DFFEAS(GB1L75, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GB1L64, , , , );
--GB1L73 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_share_counter_next_value[0]~545 at LC_X41_Y11_N5
--operation mode is normal
GB1L73 = GB1_WideOr0 & GB1_sdram_s1_slavearbiterlockenable & (GB1L19 # GB1L76);
--GB1L11 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~105 at LC_X40_Y9_N5
--operation mode is arithmetic
GB1L11_carry_eqn = (!GB1L15 & GND) # (GB1L15 & VCC);
GB1L11 = GB1_sdram_s1_arb_share_counter[4] $ (GB1L11_carry_eqn);
--GB1L12 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~106 at LC_X40_Y9_N5
--operation mode is arithmetic
GB1L12_cout_0 = GB1_sdram_s1_arb_share_counter[4] # !GB1L15;
GB1L12 = CARRY(GB1L12_cout_0);
--GB1L13 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~106COUT1_137 at LC_X40_Y9_N5
--operation mode is arithmetic
GB1L13_cout_1 = GB1_sdram_s1_arb_share_counter[4] # !GB1L15;
GB1L13 = CARRY(GB1L13_cout_1);
--GB1L14 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~107 at LC_X40_Y9_N4
--operation mode is arithmetic
GB1L14 = GB1_sdram_s1_arb_share_counter[3] $ !GB1L9;
--GB1L15 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~108 at LC_X40_Y9_N4
--operation mode is arithmetic
--GB1L18 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|Add1~109 at LC_X40_Y9_N6
--operation mode is normal
GB1L18_carry_eqn = (!GB1L15 & GB1L12) # (GB1L15 & GB1L13);
GB1L18 = GB1L18_carry_eqn $ !GB1_sdram_s1_arb_share_counter[5];
--GB1L87 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable~154 at LC_X40_Y9_N7
--operation mode is normal
GB1L87 = GB1L73 & (GB1L18 # GB1L11 # GB1L14);
--GB1L88 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_slavearbiterlockenable~155 at LC_X41_Y9_N2
--operation mode is normal
GB1L88 = GB1L87 # GB1L75 # GB1L72 # GB1L74;
--GB1L35 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|process2~43 at LC_X41_Y11_N6
--operation mode is normal
GB1L35 = GB1L23 # GB1L28 & (!GB1L31) # !GB1L28 & !GB1L24;
--GB1L80 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arbitration_holdoff_internal~150 at LC_X39_Y11_N3
--operation mode is normal
GB1L80 = !GB1L77 & !GB1_d1_reasons_to_wait & (GB1L26 # GB1L23);
--GB1L1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|A_WE_StdLogicVector~128 at LC_X41_Y12_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
GB1_sdram_s1_saved_chosen_master_vector[1]_qfbk = GB1_sdram_s1_saved_chosen_master_vector[1];
GB1L1 = GB1L77 & (GB1_sdram_s1_saved_chosen_master_vector[1]_qfbk) # !GB1L77 & (GB1L20 # !GB1L25 & GB1_sdram_s1_saved_chosen_master_vector[1]_qfbk);
--GB1_sdram_s1_saved_chosen_master_vector[1] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_saved_chosen_master_vector[1] at LC_X41_Y12_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
GB1_sdram_s1_saved_chosen_master_vector[1] = DFFEAS(GB1L1, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GB1L79, GB1L20, , , VCC);
--GB1L60 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_addend[0]~735 at LC_X39_Y11_N5
--operation mode is normal
GB1L60 = EE1L126 & (FB1L407 & GB1L25 # !FB1L407 & (!GB1L78)) # !EE1L126 & (!GB1L78);
--P1L9 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_granted_cpu_jtag_debug_module~83 at LC_X36_Y11_N7
--operation mode is normal
P1L9 = P1L10 & (P1L2 # !P1_cpu_jtag_debug_module_arb_addend[0]);
--P1L3 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_granted_cpu_jtag_debug_module~54 at LC_X36_Y10_N1
--operation mode is normal
P1L3 = P1_cpu_data_master_requests_cpu_jtag_debug_module & (P1_cpu_jtag_debug_module_arb_addend[1] # !P1L10 & !P1_cpu_jtag_debug_module_arb_addend[0]);
--P1L30 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_begintransfer~56 at LC_X36_Y12_N1
--operation mode is normal
P1L30 = !P1_d1_reasons_to_wait & (P1L10 # P1L7 & P1L8);
--P1L35 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_end_xfer~38 at LC_X36_Y21_N8
--operation mode is normal
P1L35 = P1L30 & (P1L9 # P1L3 & QB1L4);
--P1_d1_reasons_to_wait is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_reasons_to_wait at LC_X36_Y21_N8
--operation mode is normal
P1_d1_reasons_to_wait = DFFEAS(P1L35, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--P1L28 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1]~737 at LC_X36_Y21_N6
--operation mode is normal
P1L28 = P1L9 & (!P1L35) # !P1L9 & !P1L3 & P1_cpu_jtag_debug_module_arb_addend[1];
--P1L29 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_winner[0]~20 at LC_X36_Y21_N1
--operation mode is normal
P1_cpu_jtag_debug_module_saved_chosen_master_vector[0]_qfbk = P1_cpu_jtag_debug_module_saved_chosen_master_vector[0];
P1L29 = P1L9 # P1_cpu_jtag_debug_module_saved_chosen_master_vector[0]_qfbk & !P1L3;
--P1_cpu_jtag_debug_module_saved_chosen_master_vector[0] is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_saved_chosen_master_vector[0] at LC_X36_Y21_N1
--operation mode is normal
P1_cpu_jtag_debug_module_saved_chosen_master_vector[0] = DFFEAS(P1L29, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--P1L26 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0]~739 at LC_X36_Y21_N7
--operation mode is normal
P1L26 = P1L9 & (P1L35) # !P1L9 & !P1L3 & !P1_cpu_jtag_debug_module_arb_addend[0];
--L1L835 is std_1s10:inst|cpu:the_cpu|Equal53~789 at LC_X23_Y6_N2
--operation mode is normal
L1L835 = AMPP_FUNCTION(L1_D_iw[2], L1_D_iw[3], L1_D_iw[0], L1_D_iw[1]);
--L1L172 is std_1s10:inst|cpu:the_cpu|D_br_pred_taken~34 at LC_X23_Y6_N3
--operation mode is normal
L1L172 = AMPP_FUNCTION(L1_D_iw[21], L1L206, L1L221, L1L835);
--L1_D_refetch is std_1s10:inst|cpu:the_cpu|D_refetch at LC_X30_Y20_N2
--operation mode is normal
L1_D_refetch = AMPP_FUNCTION(L1_D_inst_ram_hit, L1_D_kill);
--L1_F_kill is std_1s10:inst|cpu:the_cpu|F_kill at LC_X35_Y16_N4
--operation mode is normal
L1_F_kill = AMPP_FUNCTION(L1_D_refetch, L1L172, L1_M_pipe_flush, L1_D_issue);
--L1_D_kill is std_1s10:inst|cpu:the_cpu|D_kill at LC_X35_Y16_N4
--operation mode is normal
L1_D_kill = AMPP_FUNCTION(DE1__clk0, L1_D_refetch, L1L172, L1_M_pipe_flush, L1_D_issue, E1_data_out, L1_W_stall);
--L1_F_pc[12] is std_1s10:inst|cpu:the_cpu|F_pc[12] at LC_X34_Y16_N5
--operation mode is normal
L1_F_pc[12] = AMPP_FUNCTION(DE1__clk0, L1L33, L1_D_refetch, L1_M_pipe_flush_waddr[12], L1_D_pc[12], E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1_F_pc[16] is std_1s10:inst|cpu:the_cpu|F_pc[16] at LC_X34_Y16_N2
--operation mode is normal
L1_F_pc[16] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[16], L1L34, L1_M_pipe_flush_waddr[16], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--LC1_q_b[14] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[14] at M4K_X37_Y15
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 128, Port A Width: 22, Port B Depth: 128, Port B Width: 22
--Port A Logical Depth: 128, Port A Logical Width: 22, Port B Logical Depth: 128, Port B Logical Width: 22
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
LC1_q_b[14] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[6] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[6] at M4K_X37_Y15
LC1_q_b[6] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[0] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[0] at M4K_X37_Y15
LC1_q_b[0] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[4] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[4] at M4K_X37_Y15
LC1_q_b[4] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[2] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[2] at M4K_X37_Y15
LC1_q_b[2] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[7] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[7] at M4K_X37_Y15
LC1_q_b[7] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[1] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[1] at M4K_X37_Y15
LC1_q_b[1] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[3] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[3] at M4K_X37_Y15
LC1_q_b[3] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[5] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[5] at M4K_X37_Y15
LC1_q_b[5] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[11] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[11] at M4K_X37_Y15
LC1_q_b[11] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[8] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[8] at M4K_X37_Y15
LC1_q_b[8] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[21] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[21] at M4K_X37_Y15
LC1_q_b[21] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[13] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[13] at M4K_X37_Y15
LC1_q_b[13] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[9] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[9] at M4K_X37_Y15
LC1_q_b[9] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[20] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[20] at M4K_X37_Y15
LC1_q_b[20] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[19] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[19] at M4K_X37_Y15
LC1_q_b[19] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[12] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[12] at M4K_X37_Y15
LC1_q_b[12] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[16] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[16] at M4K_X37_Y15
LC1_q_b[16] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[15] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[15] at M4K_X37_Y15
LC1_q_b[15] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[18] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[18] at M4K_X37_Y15
LC1_q_b[18] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[17] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[17] at M4K_X37_Y15
LC1_q_b[17] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--LC1_q_b[10] is std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|q_b[10] at M4K_X37_Y15
LC1_q_b[10] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_ic_tag_wren, L1_W_stall, L1_ic_fill_tag[6], L1_ic_tag_wraddress[0], L1_ic_tag_wraddress[1], L1_ic_tag_wraddress[2], L1_ic_tag_wraddress[3], L1_ic_tag_wraddress[4], L1_ic_tag_wraddress[5], L1_ic_tag_wraddress[6], L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_ic_fill_tag[2], L1_ic_fill_tag[9], L1_ic_fill_tag[10], L1_ic_fill_tag[7], L1_ic_fill_tag[8], L1_ic_fill_tag[4], L1_ic_fill_tag[11], L1_ic_fill_tag[12], L1_ic_fill_tag[1], L1_ic_fill_tag[5], L1_ic_fill_tag[13], L1_ic_fill_tag[0], L1_ic_fill_tag[3], L1_ic_fill_valid_bits[5], L1_ic_fill_valid_bits[3], L1_ic_fill_valid_bits[1], L1_ic_fill_valid_bits[7], L1_ic_fill_valid_bits[2], L1_ic_fill_valid_bits[4], L1_ic_fill_valid_bits[0], L1_ic_fill_valid_bits[6]);
--L1L872 is std_1s10:inst|cpu:the_cpu|F_ic_hit~116 at LC_X34_Y16_N6
--operation mode is normal
L1L872 = AMPP_FUNCTION(LC1_q_b[10], LC1_q_b[14], L1_F_pc[12], L1_F_pc[16]);
--L1_F_pc[20] is std_1s10:inst|cpu:the_cpu|F_pc[20] at LC_X34_Y17_N2
--operation mode is normal
L1_F_pc[20] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[20], L1_D_refetch, L1_M_pipe_flush_waddr[20], L1L35, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1_F_pc[19] is std_1s10:inst|cpu:the_cpu|F_pc[19] at LC_X33_Y14_N8
--operation mode is normal
L1_F_pc[19] = AMPP_FUNCTION(DE1__clk0, L1L36, L1_D_refetch, L1_M_pipe_flush_waddr[19], L1_D_pc[19], E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1L873 is std_1s10:inst|cpu:the_cpu|F_ic_hit~117 at LC_X33_Y14_N1
--operation mode is normal
L1L873 = AMPP_FUNCTION(LC1_q_b[17], L1_F_pc[19], L1_F_pc[20], LC1_q_b[18]);
--L1_F_pc[18] is std_1s10:inst|cpu:the_cpu|F_pc[18] at LC_X34_Y15_N6
--operation mode is normal
L1_F_pc[18] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[18], L1L37, L1_M_pipe_flush_waddr[18], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1_F_pc[17] is std_1s10:inst|cpu:the_cpu|F_pc[17] at LC_X34_Y15_N8
--operation mode is normal
L1_F_pc[17] = AMPP_FUNCTION(DE1__clk0, L1_D_refetch, L1L38, L1_M_pipe_flush_waddr[17], L1_D_pc[17], E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1L874 is std_1s10:inst|cpu:the_cpu|F_ic_hit~118 at LC_X34_Y15_N5
--operation mode is normal
L1L874 = AMPP_FUNCTION(L1_F_pc[17], LC1_q_b[15], LC1_q_b[16], L1_F_pc[18]);
--L1_F_pc[21] is std_1s10:inst|cpu:the_cpu|F_pc[21] at LC_X33_Y14_N4
--operation mode is normal
L1_F_pc[21] = AMPP_FUNCTION(DE1__clk0, L1L39, L1_D_refetch, L1_M_pipe_flush_waddr[21], L1_D_pc[21], E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1_F_pc[14] is std_1s10:inst|cpu:the_cpu|F_pc[14] at LC_X34_Y15_N1
--operation mode is normal
L1_F_pc[14] = AMPP_FUNCTION(DE1__clk0, L1_D_refetch, L1L40, L1_M_pipe_flush_waddr[14], L1_D_pc[14], E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1L875 is std_1s10:inst|cpu:the_cpu|F_ic_hit~119 at LC_X33_Y16_N8
--operation mode is normal
L1L875 = AMPP_FUNCTION(L1_F_pc[14], LC1_q_b[12], LC1_q_b[19], L1_F_pc[21]);
--L1L876 is std_1s10:inst|cpu:the_cpu|F_ic_hit~120 at LC_X35_Y16_N7
--operation mode is normal
L1L876 = AMPP_FUNCTION(L1L874, L1L873, L1L875, L1L872);
--L1_F_pc[11] is std_1s10:inst|cpu:the_cpu|F_pc[11] at LC_X34_Y14_N1
--operation mode is normal
L1_F_pc[11] = AMPP_FUNCTION(DE1__clk0, L1L41, L1_D_refetch, L1_M_pipe_flush_waddr[11], L1_D_pc[11], E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1_F_pc[22] is std_1s10:inst|cpu:the_cpu|F_pc[22] at LC_X34_Y14_N5
--operation mode is normal
L1_F_pc[22] = AMPP_FUNCTION(DE1__clk0, L1L42, L1_D_refetch, L1_M_pipe_flush_waddr[22], L1_D_pc[22], E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1L877 is std_1s10:inst|cpu:the_cpu|F_ic_hit~121 at LC_X34_Y14_N8
--operation mode is normal
L1L877 = AMPP_FUNCTION(L1_F_pc[11], LC1_q_b[20], L1_F_pc[22], LC1_q_b[9]);
--L1_F_pc[23] is std_1s10:inst|cpu:the_cpu|F_pc[23] at LC_X33_Y14_N5
--operation mode is normal
L1_F_pc[23] = AMPP_FUNCTION(DE1__clk0, L1L43, L1_D_refetch, L1_M_pipe_flush_waddr[23], L1_D_pc[23], E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1_F_pc[15] is std_1s10:inst|cpu:the_cpu|F_pc[15] at LC_X19_Y10_N2
--operation mode is normal
L1_F_pc[15] = AMPP_FUNCTION(DE1__clk0, L1_D_refetch, L1L44, L1_M_pipe_flush_waddr[15], L1_D_pc[15], E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1L878 is std_1s10:inst|cpu:the_cpu|F_ic_hit~122 at LC_X35_Y16_N8
--operation mode is normal
L1L878 = AMPP_FUNCTION(L1_F_pc[23], L1_F_pc[15], LC1_q_b[21], LC1_q_b[13]);
--L1_F_pc[13] is std_1s10:inst|cpu:the_cpu|F_pc[13] at LC_X34_Y17_N7
--operation mode is normal
L1_F_pc[13] = AMPP_FUNCTION(DE1__clk0, L1L45, L1_D_refetch, L1_M_pipe_flush_waddr[13], L1_D_pc[13], E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1_F_pc[10] is std_1s10:inst|cpu:the_cpu|F_pc[10] at LC_X34_Y17_N4
--operation mode is normal
L1_F_pc[10] = AMPP_FUNCTION(DE1__clk0, L1L46, L1_D_pc[10], L1_M_pipe_flush_waddr[10], L1_D_refetch, E1_data_out, !L1_M_pipe_flush, L1_W_stall);
--L1L879 is std_1s10:inst|cpu:the_cpu|F_ic_hit~123 at LC_X34_Y17_N6
--operation mode is normal
L1L879 = AMPP_FUNCTION(LC1_q_b[11], LC1_q_b[8], L1_F_pc[13], L1_F_pc[10]);
--L1L903 is std_1s10:inst|cpu:the_cpu|F_ic_valid~23 at LC_X35_Y17_N1
--operation mode is normal
L1L903 = AMPP_FUNCTION(L1_F_pc[1], L1_F_pc[2], LC1_q_b[1], LC1_q_b[3]);
--L1L904 is std_1s10:inst|cpu:the_cpu|F_ic_valid~24 at LC_X35_Y17_N3
--operation mode is normal
L1L904 = AMPP_FUNCTION(LC1_q_b[5], L1L903, L1_F_pc[2], LC1_q_b[7]);
--L1L905 is std_1s10:inst|cpu:the_cpu|F_ic_valid~25 at LC_X35_Y17_N4
--operation mode is normal
L1L905 = AMPP_FUNCTION(LC1_q_b[0], L1_F_pc[2], L1_F_pc[1], LC1_q_b[4]);
--L1L906 is std_1s10:inst|cpu:the_cpu|F_ic_valid~26 at LC_X35_Y17_N0
--operation mode is normal
L1L906 = AMPP_FUNCTION(LC1_q_b[2], L1_F_pc[1], LC1_q_b[6], L1L905);
--L1L880 is std_1s10:inst|cpu:the_cpu|F_ic_hit~124 at LC_X35_Y16_N0
--operation mode is normal
L1L880 = AMPP_FUNCTION(L1L879, L1L906, L1_F_pc[0], L1L904);
--L1_M_ctrl_invalidate_i is std_1s10:inst|cpu:the_cpu|M_ctrl_invalidate_i at LC_X25_Y21_N1
--operation mode is normal
L1_M_ctrl_invalidate_i = AMPP_FUNCTION(DE1__clk0, L1L452, L1_E_iw[14], L1L564, L1L565, E1_data_out, L1_W_stall);
--L1L1077 is std_1s10:inst|cpu:the_cpu|ic_fill_prevent_refill_nxt~0 at LC_X35_Y21_N0
--operation mode is normal
L1L1077 = AMPP_FUNCTION(L1_M_valid_from_E, L1_M_ctrl_invalidate_i);
--L1L859 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~195 at LC_X35_Y13_N3
--operation mode is normal
L1L859 = AMPP_FUNCTION(L1_ic_fill_tag[7], L1_F_pc[19], L1_ic_fill_tag[9], L1_F_pc[17]);
--L1L860 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~196 at LC_X35_Y13_N8
--operation mode is normal
L1L860 = AMPP_FUNCTION(L1_F_pc[13], L1_F_pc[9], L1_ic_fill_tag[3], L1_ic_fill_line[6]);
--L1L861 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~197 at LC_X32_Y20_N4
--operation mode is normal
L1L861 = AMPP_FUNCTION(L1_ic_fill_line[4], L1_F_pc[7], L1_ic_fill_tag[11], L1_F_pc[21]);
--L1L862 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~198 at LC_X35_Y13_N9
--operation mode is normal
L1L862 = AMPP_FUNCTION(L1_F_pc[5], L1_ic_fill_tag[1], L1_F_pc[11], L1_ic_fill_line[2]);
--L1L863 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~199 at LC_X35_Y13_N4
--operation mode is normal
L1L863 = AMPP_FUNCTION(L1L860, L1L862, L1L861, L1L859);
--L1L864 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~200 at LC_X34_Y15_N2
--operation mode is normal
L1L864 = AMPP_FUNCTION(L1_F_pc[14], L1_ic_fill_tag[4], L1_F_pc[3], L1_ic_fill_line[0]);
--L1L865 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~201 at LC_X34_Y15_N9
--operation mode is normal
L1L865 = AMPP_FUNCTION(L1_ic_fill_line[5], L1_F_pc[18], L1_ic_fill_tag[8], L1_F_pc[8]);
--L1L866 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~202 at LC_X34_Y17_N9
--operation mode is normal
L1L866 = AMPP_FUNCTION(L1_F_pc[10], L1_ic_fill_tag[10], L1_ic_fill_tag[0], L1_F_pc[20]);
--L1L867 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~203 at LC_X19_Y10_N0
--operation mode is normal
L1L867 = AMPP_FUNCTION(L1_F_pc[4], L1_ic_fill_tag[5], L1_ic_fill_line[1], L1_F_pc[15]);
--L1L868 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~204 at LC_X34_Y15_N3
--operation mode is normal
L1L868 = AMPP_FUNCTION(L1L867, L1L865, L1L866, L1L864);
--L1L869 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~205 at LC_X34_Y14_N6
--operation mode is normal
L1L869 = AMPP_FUNCTION(L1_F_pc[16], L1_ic_fill_tag[13], L1_ic_fill_tag[6], L1_F_pc[23]);
--L1L870 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~206 at LC_X34_Y16_N7
--operation mode is normal
L1L870 = AMPP_FUNCTION(L1_F_pc[6], L1_F_pc[12], L1_ic_fill_tag[2], L1_ic_fill_line[3]);
--L1L871 is std_1s10:inst|cpu:the_cpu|F_ic_fill_same_tag_line~207 at LC_X34_Y14_N7
--operation mode is normal
L1L871 = AMPP_FUNCTION(L1_ic_fill_tag[12], L1_F_pc[22], L1L870);
--L1_i_readdatavalid_d1 is std_1s10:inst|cpu:the_cpu|i_readdatavalid_d1 at LC_X41_Y13_N6
--operation mode is normal
L1_i_readdatavalid_d1 = AMPP_FUNCTION(DE1__clk0, N1L104, P1L9, P1L30, N1_cpu_instruction_master_read_but_no_slave_selected, E1_data_out);
--L1_ic_fill_dp_offset[2] is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset[2] at LC_X36_Y19_N0
--operation mode is normal
L1_ic_fill_dp_offset[2] = AMPP_FUNCTION(DE1__clk0, L1_D_ic_fill_starting_d1, L1L1060, L1_ic_fill_initial_offset[2], E1_data_out, L1L1057);
--L1L1060 is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[2]~152 at LC_X36_Y20_N5
--operation mode is normal
L1L1060 = AMPP_FUNCTION(L1_ic_fill_dp_offset[0], L1_D_ic_fill_starting_d1, L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2]);
--L1_ic_fill_initial_offset[0] is std_1s10:inst|cpu:the_cpu|ic_fill_initial_offset[0] at LC_X36_Y20_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_initial_offset[0] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[0], E1_data_out, GND, L1_D_ic_fill_starting);
--L1L1041 is std_1s10:inst|cpu:the_cpu|ic_fill_active_nxt~270 at LC_X36_Y19_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L1041 = AMPP_FUNCTION(L1_ic_fill_dp_offset[1], L1_ic_fill_initial_offset[0], L1_ic_fill_dp_offset[0]);
--L1_ic_fill_initial_offset[1] is std_1s10:inst|cpu:the_cpu|ic_fill_initial_offset[1] at LC_X36_Y19_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_initial_offset[1] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[1], E1_data_out, GND, L1_D_ic_fill_starting);
--L1L1042 is std_1s10:inst|cpu:the_cpu|ic_fill_active_nxt~271 at LC_X36_Y19_N7
--operation mode is normal
L1L1042 = AMPP_FUNCTION(L1L1041, L1_D_ic_fill_starting_d1, L1L1060, L1_ic_fill_initial_offset[2]);
--Q1_ext_ram_bus_avalon_slave_arb_share_counter[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter[0] at LC_X39_Y16_N0
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_arb_share_counter[0]_lut_out = Q1L340 # !Q1L349 & (Q1L70 # Q1L104);
Q1_ext_ram_bus_avalon_slave_arb_share_counter[0] = DFFEAS(Q1_ext_ram_bus_avalon_slave_arb_share_counter[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1L336, , , , );
--Q1L341 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter_next_value[1]~81 at LC_X39_Y15_N5
--operation mode is normal
Q1L341 = Q1_ext_ram_bus_avalon_slave_arb_share_counter[0] & (Q1L349 & Q1_ext_ram_bus_avalon_slave_arb_share_counter[1]);
--Q1L462 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|WideOr6~14 at LC_X40_Y14_N6
--operation mode is normal
Q1L462 = !Q1L70 & (!Q1L72 & !Q1L71);
--Q1L336 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_counter_enable~18 at LC_X39_Y16_N8
--operation mode is normal
Q1L336 = !Q1L347 & (Q1L449 # !N1L5 # !Q1L462);
--Q1L342 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_winner~0 at LC_X39_Y17_N0
--operation mode is normal
Q1L342 = !Q1L349 & (!Q1L462 # !N1L5);
--FB1_rd_valid[2] is std_1s10:inst|sdram:the_sdram|rd_valid[2] at LC_X40_Y8_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
FB1_rd_valid[2]_lut_out = GND;
FB1_rd_valid[2] = DFFEAS(FB1_rd_valid[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , FB1_rd_valid[1], , , VCC);
--GE1_stage_1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_1 at LC_X44_Y10_N0
--operation mode is normal
GE1_stage_1_lut_out = GE1_full_2 & (GE1_stage_2) # !GE1_full_2 & GB1L25;
GE1_stage_1 = DFFEAS(GE1_stage_1_lut_out, GLOBAL(DE1__clk0), VCC, , GE1L25, , , , );
--GE1_full_1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_1 at LC_X45_Y9_N9
--operation mode is normal
GE1_full_1_lut_out = FB1_za_valid & (GB1L34 & (GE1_full_0) # !GB1L34 & GE1_full_2) # !FB1_za_valid & (GE1_full_0);
GE1_full_1 = DFFEAS(GE1_full_1_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FE1L13, , , , );
--GE1_full_0 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_0 at LC_X45_Y9_N4
--operation mode is normal
GE1_full_0_lut_out = GB1L34 # GE1_full_1 # !FB1_za_valid;
GE1_full_0 = DFFEAS(GE1_full_0_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FE1L13, , , , );
--GE1L26 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process12~3 at LC_X45_Y9_N2
--operation mode is normal
GE1L26 = FB1_za_valid # GB1L34 & !GE1_full_0;
--Q1L3 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|A_WE_StdLogicVector~4230 at LC_X39_Y14_N9
--operation mode is normal
Q1L3 = !Q1L333 & !Q1L327 & !Q1L329 & !Q1L331;
--FE1_stage_1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_1 at LC_X44_Y10_N6
--operation mode is normal
FE1_stage_1_lut_out = GE1_full_2 & (FE1_stage_2) # !GE1_full_2 & (GB1L20);
FE1_stage_1 = DFFEAS(FE1_stage_1_lut_out, GLOBAL(DE1__clk0), VCC, , GE1L25, , , , );
--YB1L8 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux2~229 at LC_X48_Y19_N7
--operation mode is normal
YB1L8 = YB1L7 # YB1_slave_state[2] & !M1L13;
--YB1L9 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux2~230 at LC_X48_Y19_N8
--operation mode is normal
YB1L9 = !YB1_slave_state[1] & (M1_internal_cpu_data_master_waitrequest # !QB1L4 # !J1_cpu_data_master_requests_clock_0_in);
--SB1_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync|data_in_d1 at LC_X47_Y21_N4
--operation mode is normal
SB1_data_in_d1_lut_out = WB1_internal_master_write_done;
SB1_data_in_d1 = DFFEAS(SB1_data_in_d1_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--J1L1 is std_1s10:inst|clock_0_in_arbitrator:the_clock_0_in|clock_0_in_read~25 at LC_X48_Y20_N6
--operation mode is normal
J1L1 = L1_internal_d_read & !M1_internal_cpu_data_master_waitrequest & (J1_cpu_data_master_requests_clock_0_in);
--YB1L6 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux1~130 at LC_X48_Y20_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
RB1_data_out_qfbk = RB1_data_out;
YB1L6 = YB1_slave_state[2] # YB1_slave_state[0] & (RB1_data_out_qfbk $ XB1_data_in_d1);
--RB1_data_out is std_1s10:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_out at LC_X48_Y20_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
RB1_data_out = DFFEAS(YB1L6, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , RB1_data_in_d1, , , VCC);
--YB1L5 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Mux0~139 at LC_X48_Y19_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
SB1_data_out_qfbk = SB1_data_out;
YB1L5 = YB1_slave_state[2] & (SB1_data_out_qfbk $ XB2_data_in_d1 # !YB1_slave_state[0]) # !YB1_slave_state[2] & YB1_slave_state[0];
--SB1_data_out is std_1s10:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync|data_out at LC_X48_Y19_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
SB1_data_out = DFFEAS(YB1L5, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , SB1_data_in_d1, , , VCC);
--YB1L4 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_write_request~32 at LC_X48_Y20_N4
--operation mode is normal
YB1L4 = L1_internal_d_write & !M1_internal_cpu_data_master_waitrequest & !L1_internal_d_read & J1_cpu_data_master_requests_clock_0_in;
--RB1_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_in_d1 at LC_X48_Y22_N2
--operation mode is normal
RB1_data_in_d1_lut_out = WB1_internal_master_read_done;
RB1_data_in_d1 = DFFEAS(RB1_data_in_d1_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--DD1_internal_jdo1[22] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[22] at LC_X32_Y24_N4
--operation mode is normal
DD1_internal_jdo1[22] = AMPP_FUNCTION(!A1L9, DD1_sr[22], VCC, DD1L144);
--BB1_countup[4] is std_1s10:inst|pll:the_pll|countup[4] at LC_X17_Y29_N8
--operation mode is arithmetic
BB1_countup[4]_lut_out = BB1_countup[4] $ (BB1L29);
BB1_countup[4] = DFFEAS(BB1_countup[4]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(BB1_not_areset), , !BB1_count_done, , , , );
--BB1L32 is std_1s10:inst|pll:the_pll|countup[4]~594 at LC_X17_Y29_N8
--operation mode is arithmetic
BB1L32_cout_0 = !BB1L29 # !BB1_countup[4];
BB1L32 = CARRY(BB1L32_cout_0);
--BB1L33 is std_1s10:inst|pll:the_pll|countup[4]~594COUT1_626 at LC_X17_Y29_N8
--operation mode is arithmetic
BB1L33_cout_1 = !BB1L30 # !BB1_countup[4];
BB1L33 = CARRY(BB1L33_cout_1);
--BB1_countup[5] is std_1s10:inst|pll:the_pll|countup[5] at LC_X17_Y29_N9
--operation mode is normal
BB1_countup[5]_lut_out = BB1L32 $ !BB1_countup[5];
BB1_countup[5] = DFFEAS(BB1_countup[5]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(BB1_not_areset), , !BB1_count_done, , , , );
--BB1_countup[1] is std_1s10:inst|pll:the_pll|countup[1] at LC_X17_Y29_N5
--operation mode is arithmetic
BB1_countup[1]_lut_out = BB1_countup[0] $ BB1_countup[1];
BB1_countup[1] = DFFEAS(BB1_countup[1]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(BB1_not_areset), , !BB1_count_done, , , , );
--BB1L23 is std_1s10:inst|pll:the_pll|countup[1]~596 at LC_X17_Y29_N5
--operation mode is arithmetic
BB1L23_cout_0 = BB1_countup[0] & BB1_countup[1];
BB1L23 = CARRY(BB1L23_cout_0);
--BB1L24 is std_1s10:inst|pll:the_pll|countup[1]~596COUT1_620 at LC_X17_Y29_N5
--operation mode is arithmetic
BB1L24_cout_1 = BB1_countup[0] & BB1_countup[1];
BB1L24 = CARRY(BB1L24_cout_1);
--BB1_countup[2] is std_1s10:inst|pll:the_pll|countup[2] at LC_X17_Y29_N6
--operation mode is arithmetic
BB1_countup[2]_lut_out = BB1_countup[2] $ BB1L23;
BB1_countup[2] = DFFEAS(BB1_countup[2]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(BB1_not_areset), , !BB1_count_done, , , , );
--BB1L26 is std_1s10:inst|pll:the_pll|countup[2]~597 at LC_X17_Y29_N6
--operation mode is arithmetic
BB1L26_cout_0 = !BB1L23 # !BB1_countup[2];
BB1L26 = CARRY(BB1L26_cout_0);
--BB1L27 is std_1s10:inst|pll:the_pll|countup[2]~597COUT1_622 at LC_X17_Y29_N6
--operation mode is arithmetic
BB1L27_cout_1 = !BB1L24 # !BB1_countup[2];
BB1L27 = CARRY(BB1L27_cout_1);
--BB1_countup[3] is std_1s10:inst|pll:the_pll|countup[3] at LC_X17_Y29_N7
--operation mode is arithmetic
BB1_countup[3]_lut_out = BB1_countup[3] $ (!BB1L26);
BB1_countup[3] = DFFEAS(BB1_countup[3]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(BB1_not_areset), , !BB1_count_done, , , , );
--BB1L29 is std_1s10:inst|pll:the_pll|countup[3]~598 at LC_X17_Y29_N7
--operation mode is arithmetic
BB1L29_cout_0 = BB1_countup[3] & (!BB1L26);
BB1L29 = CARRY(BB1L29_cout_0);
--BB1L30 is std_1s10:inst|pll:the_pll|countup[3]~598COUT1_624 at LC_X17_Y29_N7
--operation mode is arithmetic
BB1L30_cout_1 = BB1_countup[3] & (!BB1L27);
BB1L30 = CARRY(BB1L30_cout_1);
--BB1_countup[0] is std_1s10:inst|pll:the_pll|countup[0] at LC_X17_Y29_N4
--operation mode is normal
BB1_countup[0]_lut_out = BB1_countup[0] $ (!BB1_count_done);
BB1_countup[0] = DFFEAS(BB1_countup[0]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(BB1_not_areset), , , , , , );
--BB1L35 is std_1s10:inst|pll:the_pll|Equal0~41 at LC_X17_Y29_N2
--operation mode is normal
BB1L35 = BB1_countup[3] & BB1_countup[2] & BB1_countup[1] & BB1_countup[0];
--BB1_not_areset is std_1s10:inst|pll:the_pll|not_areset at LC_X28_Y1_N2
--operation mode is normal
BB1_not_areset_lut_out = VCC;
BB1_not_areset = DFFEAS(BB1_not_areset_lut_out, GLOBAL(PLD_CLOCKINPUT), VCC, , , , , , );
--FB1L520 is std_1s10:inst|sdram:the_sdram|Mux40~1437 at LC_X33_Y2_N9
--operation mode is normal
FB1L520 = !FB1_m_state[1] & !FB1_m_state[5] & !FB1_m_state[7] & !FB1_m_state[2];
--FB1L521 is std_1s10:inst|sdram:the_sdram|Mux40~1438 at LC_X32_Y3_N6
--operation mode is normal
FB1L521 = !FB1_refresh_request & (!EE1L127 # !FB1L724) # !FB1L534;
--FB1L522 is std_1s10:inst|sdram:the_sdram|Mux40~1439 at LC_X33_Y1_N2
--operation mode is normal
FB1L522 = FB1_m_count[2] & (!FB1L520 # !FB1L518 # !FB1L238);
--FB1L523 is std_1s10:inst|sdram:the_sdram|Mux40~1440 at LC_X33_Y2_N8
--operation mode is normal
FB1L523 = !FB1_m_state[1] & !FB1_m_state[3] & !FB1_m_state[7] & !FB1_m_state[2];
--FB1L524 is std_1s10:inst|sdram:the_sdram|Mux40~1441 at LC_X33_Y1_N8
--operation mode is normal
FB1L524 = FB1L724 # !FB1L523 # !FB1_refresh_request # !EE1L127;
--FB1_m_count[0] is std_1s10:inst|sdram:the_sdram|m_count[0] at LC_X34_Y2_N8
--operation mode is normal
FB1_m_count[0]_lut_out = FB1_m_state[5] & (FB1L558 & FB1_m_count[0] # !FB1L558 & (FB1L550)) # !FB1_m_state[5] & (FB1L558);
FB1_m_count[0] = DFFEAS(FB1_m_count[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , !FB1_m_state[6], , , , );
--FB1L525 is std_1s10:inst|sdram:the_sdram|Mux40~1442 at LC_X33_Y1_N5
--operation mode is normal
FB1L525 = FB1_m_count[2] & (FB1_m_count[1] # FB1_m_count[0] # !FB1L523);
--FB1L526 is std_1s10:inst|sdram:the_sdram|Mux40~1443 at LC_X33_Y1_N4
--operation mode is normal
FB1L526 = FB1L724 # !EE1L127 # !FB1L469 # !FB1_refresh_request;
--FB1L527 is std_1s10:inst|sdram:the_sdram|Mux40~1444 at LC_X34_Y1_N4
--operation mode is normal
FB1L527 = FB1_m_count[2] & (FB1_m_count[0] # FB1_m_count[1] # !FB1L469);
--FB1L528 is std_1s10:inst|sdram:the_sdram|Mux40~1445 at LC_X32_Y2_N2
--operation mode is normal
FB1L528 = FB1_m_count[2] & (FB1_m_state[1] $ !FB1_m_state[7]);
--FB1L529 is std_1s10:inst|sdram:the_sdram|Mux40~1446 at LC_X32_Y2_N6
--operation mode is normal
FB1L529 = FB1_m_state[2] & (FB1_m_state[3] # FB1L527) # !FB1_m_state[2] & !FB1_m_state[3] & (FB1L528);
--FB1L530 is std_1s10:inst|sdram:the_sdram|Mux40~1447 at LC_X33_Y1_N9
--operation mode is normal
FB1L530 = FB1_m_state[3] & FB1_m_count[2] & (FB1L526 # FB1L529) # !FB1_m_state[3] & (FB1L529);
--FB1L531 is std_1s10:inst|sdram:the_sdram|Mux40~1448 at LC_X33_Y1_N0
--operation mode is normal
FB1L531 = FB1_m_state[5] & (FB1_m_state[4] # FB1L525) # !FB1_m_state[5] & !FB1_m_state[4] & (FB1L530);
--FB1L532 is std_1s10:inst|sdram:the_sdram|Mux40~1449 at LC_X33_Y1_N3
--operation mode is normal
FB1L532 = FB1_m_state[4] & FB1_m_count[2] & (FB1L524 # FB1L531) # !FB1_m_state[4] & (FB1L531);
--FB1L533 is std_1s10:inst|sdram:the_sdram|Mux40~1450 at LC_X33_Y1_N1
--operation mode is normal
FB1L533 = FB1_m_state[8] & !FB1_m_state[0] # !FB1_m_state[8] & (FB1_m_state[0] & FB1L532 # !FB1_m_state[0] & (FB1L522));
--FB1L536 is std_1s10:inst|sdram:the_sdram|Mux41~1449 at LC_X32_Y1_N3
--operation mode is normal
FB1L536 = FB1L724 # !FB1L547 # !EE1L127 # !FB1_refresh_request;
--FB1L537 is std_1s10:inst|sdram:the_sdram|Mux41~1450 at LC_X32_Y1_N8
--operation mode is normal
FB1L537 = FB1_m_count[1] & (!FB1L535 # !FB1L392 # !FB1L520);
--FB1L538 is std_1s10:inst|sdram:the_sdram|Mux41~1451 at LC_X32_Y1_N5
--operation mode is normal
FB1L538 = !FB1L724 & FB1_refresh_request & EE1L127 & FB1L520;
--FB1L539 is std_1s10:inst|sdram:the_sdram|Mux41~1452 at LC_X32_Y3_N9
--operation mode is normal
FB1L539 = !FB1_m_state[2] & (!FB1_m_state[5]);
--FB1L540 is std_1s10:inst|sdram:the_sdram|Mux41~1453 at LC_X33_Y2_N7
--operation mode is normal
FB1L540 = FB1_m_state[1] & (FB1_m_state[5] # FB1_m_state[2]) # !FB1_m_state[1] & !FB1_m_count[0] & (FB1_m_state[5] $ FB1_m_state[2]);
--FB1L541 is std_1s10:inst|sdram:the_sdram|Mux41~1454 at LC_X33_Y2_N2
--operation mode is normal
FB1L541 = FB1L540 & (FB1_m_count[2] # FB1_m_count[1]);
--FB1L542 is std_1s10:inst|sdram:the_sdram|Mux41~1455 at LC_X33_Y2_N3
--operation mode is normal
FB1L542 = FB1_m_state[7] & (FB1_m_state[1]) # !FB1_m_state[7] & (FB1_m_count[1] & (FB1_m_state[1] $ !FB1L541) # !FB1_m_count[1] & !FB1_m_state[1] & FB1L541);
--FB1L543 is std_1s10:inst|sdram:the_sdram|Mux41~1456 at LC_X33_Y2_N4
--operation mode is normal
FB1L543 = FB1_m_state[7] & (FB1_m_count[1] # !FB1L542 & FB1L539) # !FB1_m_state[7] & FB1L542;
--FB1L544 is std_1s10:inst|sdram:the_sdram|Mux41~1457 at LC_X32_Y1_N4
--operation mode is normal
FB1L544 = FB1_m_state[0] & FB1L543 & !FB1_m_state[3] # !FB1_m_state[0] & (FB1_m_state[3] # FB1L548);
--FB1L545 is std_1s10:inst|sdram:the_sdram|Mux41~1458 at LC_X32_Y1_N1
--operation mode is normal
FB1L545 = FB1_m_state[3] & (FB1_m_count[1] # !FB1L544 & FB1L538) # !FB1_m_state[3] & FB1L544;
--FB1L546 is std_1s10:inst|sdram:the_sdram|Mux41~1459 at LC_X32_Y1_N7
--operation mode is normal
FB1L546 = FB1_m_state[8] & (FB1_m_state[4] # FB1L537) # !FB1_m_state[8] & !FB1_m_state[4] & FB1L545;
--FB1_i_next[0] is std_1s10:inst|sdram:the_sdram|i_next[0] at LC_X40_Y4_N2
--operation mode is normal
FB1_i_next[0]_lut_out = FB1_i_state[2] # CD1L35 & !FB1_i_refs[1] & !FB1_i_refs[2];
FB1_i_next[0] = DFFEAS(FB1_i_next[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , CD1L36, , , , );
--FB1_i_count[2] is std_1s10:inst|sdram:the_sdram|i_count[2] at LC_X41_Y3_N7
--operation mode is normal
FB1_i_count[2]_lut_out = FB1_i_state[1] & FB1_i_state[0] & (FB1L412 # FB1_i_state[2]);
FB1_i_count[2] = DFFEAS(FB1_i_count[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FB1L413, , , , );
--FB1_i_count[1] is std_1s10:inst|sdram:the_sdram|i_count[1] at LC_X41_Y3_N2
--operation mode is normal
FB1_i_count[1]_lut_out = FB1_i_state[1] & !FB1_i_state[2] & (FB1L414 # !FB1_i_state[0]);
FB1_i_count[1] = DFFEAS(FB1_i_count[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FB1L413, , , , );
--FB1L157 is std_1s10:inst|sdram:the_sdram|LessThan0~41 at LC_X41_Y2_N5
--operation mode is normal
FB1L157 = FB1_i_count[2] # FB1_i_count[1];
--FB1L410 is std_1s10:inst|sdram:the_sdram|Mux9~221 at LC_X41_Y3_N0
--operation mode is normal
FB1L410 = FB1_i_state[1] & (!FB1_i_state[2]);
--FB1L411 is std_1s10:inst|sdram:the_sdram|Mux9~222 at LC_X41_Y3_N6
--operation mode is normal
FB1L411 = FB1_i_state[0] & (FB1L157 # FB1_i_next[0] # !FB1L410);
--FB1L147 is std_1s10:inst|sdram:the_sdram|i_refs[0]~278 at LC_X41_Y3_N4
--operation mode is normal
FB1L147 = !FB1_i_state[0] & (!FB1_i_state[2]);
--FB1L408 is std_1s10:inst|sdram:the_sdram|Mux7~95 at LC_X41_Y2_N2
--operation mode is normal
FB1L408 = !FB1_i_count[2] & (!FB1_i_count[1] & FB1_i_next[0]);
--FB1_i_next[1] is std_1s10:inst|sdram:the_sdram|i_next[1] at LC_X40_Y4_N3
--operation mode is normal
FB1_i_next[1]_lut_out = !FB1_i_state[2];
FB1_i_next[1] = DFFEAS(FB1_i_next[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , CD1L36, , , , );
--FB1L409 is std_1s10:inst|sdram:the_sdram|Mux8~208 at LC_X41_Y2_N4
--operation mode is normal
FB1L409 = FB1_i_count[2] # FB1_i_count[1] # FB1_i_next[1];
--FB1L74 is std_1s10:inst|sdram:the_sdram|Add0~218 at LC_X52_Y11_N7
--operation mode is arithmetic
FB1L74_carry_eqn = (!FB1L78 & FB1L83) # (FB1L78 & FB1L84);
FB1L74 = FB1_refresh_counter[3] $ FB1L74_carry_eqn;
--FB1L75 is std_1s10:inst|sdram:the_sdram|Add0~219 at LC_X52_Y11_N7
--operation mode is arithmetic
FB1L75_cout_0 = FB1_refresh_counter[3] & !FB1L83;
FB1L75 = CARRY(FB1L75_cout_0);
--FB1L76 is std_1s10:inst|sdram:the_sdram|Add0~219COUT1_295 at LC_X52_Y11_N7
--operation mode is arithmetic
FB1L76_cout_1 = FB1_refresh_counter[3] & !FB1L84;
FB1L76 = CARRY(FB1L76_cout_1);
--FB1L77 is std_1s10:inst|sdram:the_sdram|Add0~220 at LC_X52_Y11_N4
--operation mode is arithmetic
FB1L77 = !FB1_refresh_counter[0];
--FB1L78 is std_1s10:inst|sdram:the_sdram|Add0~221 at LC_X52_Y11_N4
--operation mode is arithmetic
FB1L78 = CARRY(FB1_refresh_counter[0]);
--FB1L79 is std_1s10:inst|sdram:the_sdram|Add0~222 at LC_X52_Y11_N5
--operation mode is arithmetic
FB1L79 = FB1_refresh_counter[1] $ (!FB1L79_carry_eqn);
--FB1L80 is std_1s10:inst|sdram:the_sdram|Add0~223 at LC_X52_Y11_N5
--operation mode is arithmetic
FB1L80_cout_0 = !FB1_refresh_counter[1] & (!FB1L78);
FB1L80 = CARRY(FB1L80_cout_0);
--FB1L81 is std_1s10:inst|sdram:the_sdram|Add0~223COUT1_291 at LC_X52_Y11_N5
--operation mode is arithmetic
FB1L81_cout_1 = !FB1_refresh_counter[1] & (!FB1L78);
FB1L81 = CARRY(FB1L81_cout_1);
--FB1L82 is std_1s10:inst|sdram:the_sdram|Add0~224 at LC_X52_Y11_N6
--operation mode is arithmetic
FB1L82_carry_eqn = (!FB1L78 & FB1L80) # (FB1L78 & FB1L81);
FB1L82 = FB1_refresh_counter[2] $ (FB1L82_carry_eqn);
--FB1L83 is std_1s10:inst|sdram:the_sdram|Add0~225 at LC_X52_Y11_N6
--operation mode is arithmetic
FB1L83_cout_0 = FB1_refresh_counter[2] # !FB1L80;
FB1L83 = CARRY(FB1L83_cout_0);
--FB1L84 is std_1s10:inst|sdram:the_sdram|Add0~225COUT1_293 at LC_X52_Y11_N6
--operation mode is arithmetic
FB1L84_cout_1 = FB1_refresh_counter[2] # !FB1L81;
FB1L84 = CARRY(FB1L84_cout_1);
--FB1L85 is std_1s10:inst|sdram:the_sdram|Add0~226 at LC_X52_Y10_N1
--operation mode is arithmetic
FB1L85_carry_eqn = (!FB1L92 & FB1L94) # (FB1L92 & FB1L95);
FB1L85 = FB1_refresh_counter[7] $ (FB1L85_carry_eqn);
--FB1L86 is std_1s10:inst|sdram:the_sdram|Add0~227 at LC_X52_Y10_N1
--operation mode is arithmetic
FB1L86_cout_0 = FB1_refresh_counter[7] & (!FB1L94);
FB1L86 = CARRY(FB1L86_cout_0);
--FB1L87 is std_1s10:inst|sdram:the_sdram|Add0~227COUT1_301 at LC_X52_Y10_N1
--operation mode is arithmetic
FB1L87_cout_1 = FB1_refresh_counter[7] & (!FB1L95);
FB1L87 = CARRY(FB1L87_cout_1);
--FB1L88 is std_1s10:inst|sdram:the_sdram|Add0~228 at LC_X52_Y11_N8
--operation mode is arithmetic
FB1L88_carry_eqn = (!FB1L78 & FB1L75) # (FB1L78 & FB1L76);
FB1L88 = FB1_refresh_counter[4] $ FB1L88_carry_eqn;
--FB1L89 is std_1s10:inst|sdram:the_sdram|Add0~229 at LC_X52_Y11_N8
--operation mode is arithmetic
FB1L89_cout_0 = FB1_refresh_counter[4] # !FB1L75;
FB1L89 = CARRY(FB1L89_cout_0);
--FB1L90 is std_1s10:inst|sdram:the_sdram|Add0~229COUT1_297 at LC_X52_Y11_N8
--operation mode is arithmetic
FB1L90_cout_1 = FB1_refresh_counter[4] # !FB1L76;
FB1L90 = CARRY(FB1L90_cout_1);
--FB1L91 is std_1s10:inst|sdram:the_sdram|Add0~230 at LC_X52_Y11_N9
--operation mode is arithmetic
FB1L91_carry_eqn = (!FB1L78 & FB1L89) # (FB1L78 & FB1L90);
FB1L91 = FB1_refresh_counter[5] $ !FB1L91_carry_eqn;
--FB1L92 is std_1s10:inst|sdram:the_sdram|Add0~231 at LC_X52_Y11_N9
--operation mode is arithmetic
FB1L92 = CARRY(!FB1_refresh_counter[5] & !FB1L90);
--FB1L93 is std_1s10:inst|sdram:the_sdram|Add0~232 at LC_X52_Y10_N0
--operation mode is arithmetic
FB1L93 = FB1_refresh_counter[6] $ (FB1L93_carry_eqn);
--FB1L94 is std_1s10:inst|sdram:the_sdram|Add0~233 at LC_X52_Y10_N0
--operation mode is arithmetic
FB1L94_cout_0 = FB1_refresh_counter[6] # !FB1L92;
FB1L94 = CARRY(FB1L94_cout_0);
--FB1L95 is std_1s10:inst|sdram:the_sdram|Add0~233COUT1_299 at LC_X52_Y10_N0
--operation mode is arithmetic
FB1L95_cout_1 = FB1_refresh_counter[6] # !FB1L92;
FB1L95 = CARRY(FB1L95_cout_1);
--FB1L96 is std_1s10:inst|sdram:the_sdram|Add0~234 at LC_X52_Y10_N6
--operation mode is normal
FB1L96_carry_eqn = (!FB1L104 & FB1L106) # (FB1L104 & FB1L107);
FB1L96 = FB1L96_carry_eqn $ !FB1_refresh_counter[12];
--FB1L97 is std_1s10:inst|sdram:the_sdram|Add0~236 at LC_X52_Y10_N2
--operation mode is arithmetic
FB1L97_carry_eqn = (!FB1L92 & FB1L86) # (FB1L92 & FB1L87);
FB1L97 = FB1_refresh_counter[8] $ !FB1L97_carry_eqn;
--FB1L98 is std_1s10:inst|sdram:the_sdram|Add0~237 at LC_X52_Y10_N2
--operation mode is arithmetic
FB1L98_cout_0 = !FB1L86 # !FB1_refresh_counter[8];
FB1L98 = CARRY(FB1L98_cout_0);
--FB1L99 is std_1s10:inst|sdram:the_sdram|Add0~237COUT1_303 at LC_X52_Y10_N2
--operation mode is arithmetic
FB1L99_cout_1 = !FB1L87 # !FB1_refresh_counter[8];
FB1L99 = CARRY(FB1L99_cout_1);
--FB1L100 is std_1s10:inst|sdram:the_sdram|Add0~238 at LC_X52_Y10_N3
--operation mode is arithmetic
FB1L100_carry_eqn = (!FB1L92 & FB1L98) # (FB1L92 & FB1L99);
FB1L100 = FB1_refresh_counter[9] $ FB1L100_carry_eqn;
--FB1L101 is std_1s10:inst|sdram:the_sdram|Add0~239 at LC_X52_Y10_N3
--operation mode is arithmetic
FB1L101_cout_0 = FB1_refresh_counter[9] & !FB1L98;
FB1L101 = CARRY(FB1L101_cout_0);
--FB1L102 is std_1s10:inst|sdram:the_sdram|Add0~239COUT1_305 at LC_X52_Y10_N3
--operation mode is arithmetic
FB1L102_cout_1 = FB1_refresh_counter[9] & !FB1L99;
FB1L102 = CARRY(FB1L102_cout_1);
--FB1L103 is std_1s10:inst|sdram:the_sdram|Add0~240 at LC_X52_Y10_N4
--operation mode is arithmetic
FB1L103_carry_eqn = (!FB1L92 & FB1L101) # (FB1L92 & FB1L102);
FB1L103 = FB1_refresh_counter[10] $ FB1L103_carry_eqn;
--FB1L104 is std_1s10:inst|sdram:the_sdram|Add0~241 at LC_X52_Y10_N4
--operation mode is arithmetic
FB1L104 = CARRY(FB1_refresh_counter[10] # !FB1L102);
--FB1L105 is std_1s10:inst|sdram:the_sdram|Add0~242 at LC_X52_Y10_N5
--operation mode is arithmetic
FB1L105 = FB1_refresh_counter[11] $ (!FB1L105_carry_eqn);
--FB1L106 is std_1s10:inst|sdram:the_sdram|Add0~243 at LC_X52_Y10_N5
--operation mode is arithmetic
FB1L106_cout_0 = !FB1_refresh_counter[11] & (!FB1L104);
FB1L106 = CARRY(FB1L106_cout_0);
--FB1L107 is std_1s10:inst|sdram:the_sdram|Add0~243COUT1_307 at LC_X52_Y10_N5
--operation mode is arithmetic
FB1L107_cout_1 = !FB1_refresh_counter[11] & (!FB1L104);
FB1L107 = CARRY(FB1L107_cout_1);
--FB1L440 is std_1s10:inst|sdram:the_sdram|Mux21~1080 at LC_X35_Y3_N2
--operation mode is normal
FB1L440 = !FB1_m_state[2] & (FB1_m_state[0] $ !FB1_m_state[7]);
--FB1L441 is std_1s10:inst|sdram:the_sdram|Mux21~1081 at LC_X35_Y3_N1
--operation mode is normal
FB1L441 = FB1L440 & !FB1_m_state[4] & FB1L416 & !FB1_m_state[6];
--T1_fifo_AE is std_1s10:inst|jtag_uart:the_jtag_uart|fifo_AE at LC_X50_Y17_N5
--operation mode is normal
T1_fifo_AE_lut_out = !ZD1_safe_q[5] & !ZD1_safe_q[4] & !WD1_b_full & !T1L65;
T1_fifo_AE = DFFEAS(T1_fifo_AE_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--T1L64 is std_1s10:inst|jtag_uart:the_jtag_uart|ipen_AE~11 at LC_X50_Y17_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
T1_ien_AE_qfbk = T1_ien_AE;
T1L64 = T1_fifo_AE & T1_ien_AE_qfbk;
--T1_ien_AE is std_1s10:inst|jtag_uart:the_jtag_uart|ien_AE at LC_X50_Y17_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
T1_ien_AE = DFFEAS(T1L64, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , T1L61, L1_M_st_data[1], , , VCC);
--T1_fifo_AF is std_1s10:inst|jtag_uart:the_jtag_uart|fifo_AF at LC_X50_Y16_N9
--operation mode is normal
T1_fifo_AF_lut_out = T1L22 & !T1L67 & !T1L3 & !T1L66;
T1_fifo_AF = DFFEAS(T1_fifo_AF_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--T1_pause_irq is std_1s10:inst|jtag_uart:the_jtag_uart|pause_irq at LC_X50_Y16_N1
--operation mode is normal
T1_pause_irq_lut_out = T1_read_0 & QD1L39Q & (WD2_b_non_empty) # !T1_read_0 & (T1_pause_irq # QD1L39Q & WD2_b_non_empty);
T1_pause_irq = DFFEAS(T1_pause_irq_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L304 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~2077 at LC_X50_Y16_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
T1_ien_AF_qfbk = T1_ien_AF;
M1L304 = T1_ien_AF_qfbk & (T1_pause_irq # T1_fifo_AF);
--T1_ien_AF is std_1s10:inst|jtag_uart:the_jtag_uart|ien_AF at LC_X50_Y16_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
T1_ien_AF = DFFEAS(M1L304, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , T1L61, L1_M_st_data[0], , , VCC);
--SC1_internal_oci_ienable1[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[2] at LC_X47_Y20_N1
--operation mode is normal
SC1_internal_oci_ienable1[2] = AMPP_FUNCTION(DE1__clk0, L1_M_st_data[2], E1_data_out, SC1L12);
--L1_E_ctrl_wrctl_inst is std_1s10:inst|cpu:the_cpu|E_ctrl_wrctl_inst at LC_X28_Y21_N0
--operation mode is normal
L1_E_ctrl_wrctl_inst = AMPP_FUNCTION(DE1__clk0, L1L843, L1L247, E1_data_out, L1_W_stall);
--L1L824 is std_1s10:inst|cpu:the_cpu|E_wrctl_bstatus~9 at LC_X28_Y21_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L824 = AMPP_FUNCTION(L1_E_iw[8], L1_E_ctrl_wrctl_inst);
--L1_E_iw[7] is std_1s10:inst|cpu:the_cpu|E_iw[7] at LC_X28_Y21_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[7] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[7], E1_data_out, GND, L1_W_stall);
--L1L1187 is std_1s10:inst|cpu:the_cpu|M_ienable_reg[2]~3 at LC_X29_Y20_N7
--operation mode is normal
L1L1187 = AMPP_FUNCTION(L1_E_iw[6], L1L824, L1L819, L1_W_stall);
--KC1_q_b[8] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[8] at M4K_X37_Y16
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[8] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[8], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[6], L1_i_readdata_d1[29], L1_i_readdata_d1[9]);
--KC1_q_b[9] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[9] at M4K_X37_Y16
KC1_q_b[9] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[8], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[6], L1_i_readdata_d1[29], L1_i_readdata_d1[9]);
--KC1_q_b[29] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[29] at M4K_X37_Y16
KC1_q_b[29] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[8], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[6], L1_i_readdata_d1[29], L1_i_readdata_d1[9]);
--KC1_q_b[6] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[6] at M4K_X37_Y16
KC1_q_b[6] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[8], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[6], L1_i_readdata_d1[29], L1_i_readdata_d1[9]);
--L1_M_status_reg_pie is std_1s10:inst|cpu:the_cpu|M_status_reg_pie at LC_X27_Y21_N9
--operation mode is normal
L1_M_status_reg_pie = AMPP_FUNCTION(DE1__clk0, L1L1369, L1L1366, L1L1371, L1L1368, E1_data_out);
--L1L1131 is std_1s10:inst|cpu:the_cpu|intr_req~66 at LC_X31_Y21_N7
--operation mode is normal
L1L1131 = AMPP_FUNCTION(L1_M_ipending_reg[3], L1_M_ipending_reg[5], L1_M_ipending_reg[2], L1_M_ipending_reg[4]);
--L1_M_ipending_reg[1] is std_1s10:inst|cpu:the_cpu|M_ipending_reg[1] at LC_X31_Y21_N1
--operation mode is normal
L1_M_ipending_reg[1] = AMPP_FUNCTION(DE1__clk0, SC1_internal_oci_ienable1[1], L1_M_ienable_reg[1], KB1_control_register[0], KB1_timeout_occurred, E1_data_out);
--L1_M_ipending_reg[0] is std_1s10:inst|cpu:the_cpu|M_ipending_reg[0] at LC_X31_Y21_N4
--operation mode is normal
L1_M_ipending_reg[0] = AMPP_FUNCTION(DE1__clk0, SC1_internal_oci_ienable1[0], Q1_d1_irq_from_the_lan91c111, L1_M_ienable_reg[0], E1_data_out);
--L1L1132 is std_1s10:inst|cpu:the_cpu|intr_req~67 at LC_X31_Y21_N8
--operation mode is normal
L1L1132 = AMPP_FUNCTION(L1_M_status_reg_pie, L1_M_ipending_reg[1], L1L1131, L1_M_ipending_reg[0]);
--KC1_q_b[7] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[7] at M4K_X37_Y20
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[7] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[7], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[0], L1_i_readdata_d1[2], L1_i_readdata_d1[3]);
--KC1_q_b[3] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[3] at M4K_X37_Y20
KC1_q_b[3] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[7], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[0], L1_i_readdata_d1[2], L1_i_readdata_d1[3]);
--KC1_q_b[2] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[2] at M4K_X37_Y20
KC1_q_b[2] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[7], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[0], L1_i_readdata_d1[2], L1_i_readdata_d1[3]);
--KC1_q_b[0] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[0] at M4K_X37_Y20
KC1_q_b[0] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[7], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[0], L1_i_readdata_d1[2], L1_i_readdata_d1[3]);
--KC1_q_b[4] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[4] at M4K_X37_Y18
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[4] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[4], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[15], L1_i_readdata_d1[5], L1_i_readdata_d1[1]);
--KC1_q_b[1] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[1] at M4K_X37_Y18
KC1_q_b[1] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[4], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[15], L1_i_readdata_d1[5], L1_i_readdata_d1[1]);
--KC1_q_b[5] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[5] at M4K_X37_Y18
KC1_q_b[5] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[4], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[15], L1_i_readdata_d1[5], L1_i_readdata_d1[1]);
--KC1_q_b[15] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[15] at M4K_X37_Y18
KC1_q_b[15] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[4], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[15], L1_i_readdata_d1[5], L1_i_readdata_d1[1]);
--KC1_q_b[27] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[27] at M4K_X15_Y20
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[27] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[27], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[28], L1_i_readdata_d1[31], L1_i_readdata_d1[25]);
--KC1_q_b[25] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[25] at M4K_X15_Y20
KC1_q_b[25] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[27], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[28], L1_i_readdata_d1[31], L1_i_readdata_d1[25]);
--KC1_q_b[31] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[31] at M4K_X15_Y20
KC1_q_b[31] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[27], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[28], L1_i_readdata_d1[31], L1_i_readdata_d1[25]);
--KC1_q_b[28] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[28] at M4K_X15_Y20
KC1_q_b[28] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[27], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[28], L1_i_readdata_d1[31], L1_i_readdata_d1[25]);
--KC1_q_b[30] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[30] at M4K_X37_Y17
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[30] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[30], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[12], L1_i_readdata_d1[11], L1_i_readdata_d1[10]);
--KC1_q_b[10] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[10] at M4K_X37_Y17
KC1_q_b[10] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[30], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[12], L1_i_readdata_d1[11], L1_i_readdata_d1[10]);
--KC1_q_b[11] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[11] at M4K_X37_Y17
KC1_q_b[11] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[30], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[12], L1_i_readdata_d1[11], L1_i_readdata_d1[10]);
--KC1_q_b[12] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[12] at M4K_X37_Y17
KC1_q_b[12] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[30], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[12], L1_i_readdata_d1[11], L1_i_readdata_d1[10]);
--L1L250 is std_1s10:inst|cpu:the_cpu|D_dst_regnum[1]~573 at LC_X18_Y18_N3
--operation mode is normal
L1L250 = AMPP_FUNCTION(L1_D_iw[18], L1L829, L1_D_iw[23], L1L216);
--L1L219 is std_1s10:inst|cpu:the_cpu|D_ctrl_break~35 at LC_X19_Y7_N0
--operation mode is normal
L1L219 = AMPP_FUNCTION(L1_D_iw[13], L1_D_iw[16], L1_D_iw[14]);
--L1L220 is std_1s10:inst|cpu:the_cpu|D_ctrl_break~36 at LC_X19_Y7_N6
--operation mode is normal
L1L220 = AMPP_FUNCTION(L1L830, L1L219, L1L827, L1_D_iw[12]);
--L1L251 is std_1s10:inst|cpu:the_cpu|D_dst_regnum[1]~574 at LC_X18_Y18_N5
--operation mode is normal
L1L251 = AMPP_FUNCTION(L1L250, L1L220, L1L207, L1_D_iw[15]);
--L1_E_dst_regnum[1] is std_1s10:inst|cpu:the_cpu|E_dst_regnum[1] at LC_X18_Y18_N5
--operation mode is normal
L1_E_dst_regnum[1] = AMPP_FUNCTION(DE1__clk0, L1L250, L1L220, L1L207, L1_D_iw[15], E1_data_out, L1_W_stall);
--L1L254 is std_1s10:inst|cpu:the_cpu|D_dst_regnum[4]~575 at LC_X18_Y18_N9
--operation mode is normal
L1L254 = AMPP_FUNCTION(L1L220, L1L207, L1_D_iw[15]);
--L1L255 is std_1s10:inst|cpu:the_cpu|D_dst_regnum[4]~576 at LC_X18_Y19_N7
--operation mode is normal
L1L255 = AMPP_FUNCTION(L1_D_iw[26], L1_D_iw[21], L1L254, L1_D_ctrl_b_not_src);
--L1_E_dst_regnum[4] is std_1s10:inst|cpu:the_cpu|E_dst_regnum[4] at LC_X18_Y19_N7
--operation mode is normal
L1_E_dst_regnum[4] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[26], L1_D_iw[21], L1L254, L1_D_ctrl_b_not_src, E1_data_out, L1_W_stall);
--L1L252 is std_1s10:inst|cpu:the_cpu|D_dst_regnum[2]~577 at LC_X19_Y18_N5
--operation mode is normal
L1L252 = AMPP_FUNCTION(L1L829, L1_D_iw[19], L1_D_iw[24], L1L216);
--L1L249 is std_1s10:inst|cpu:the_cpu|D_dst_regnum[0]~578 at LC_X19_Y18_N3
--operation mode is normal
L1L249 = AMPP_FUNCTION(L1L829, L1_D_iw[22], L1_D_iw[17], L1L216);
--L1L253 is std_1s10:inst|cpu:the_cpu|D_dst_regnum[3]~579 at LC_X19_Y18_N0
--operation mode is normal
L1L253 = AMPP_FUNCTION(L1L829, L1_D_iw[20], L1_D_iw[25], L1L216);
--L1L848 is std_1s10:inst|cpu:the_cpu|Equal171~117 at LC_X19_Y18_N6
--operation mode is normal
L1L848 = AMPP_FUNCTION(L1L249, L1L253, L1L254, L1L252);
--QC1_mac_mult1 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1 at DSPMULT_X10_Y15_N0
--DSP Block Multiplier Base Width: 18-bits
QC1_mac_mult1 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L2 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT1 at DSPMULT_X10_Y15_N0
QC1L2 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L3 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT2 at DSPMULT_X10_Y15_N0
QC1L3 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L4 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT3 at DSPMULT_X10_Y15_N0
QC1L4 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L5 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT4 at DSPMULT_X10_Y15_N0
QC1L5 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L6 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT5 at DSPMULT_X10_Y15_N0
QC1L6 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L7 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT6 at DSPMULT_X10_Y15_N0
QC1L7 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L8 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT7 at DSPMULT_X10_Y15_N0
QC1L8 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L9 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT8 at DSPMULT_X10_Y15_N0
QC1L9 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L10 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT9 at DSPMULT_X10_Y15_N0
QC1L10 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L11 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT10 at DSPMULT_X10_Y15_N0
QC1L11 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L12 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT11 at DSPMULT_X10_Y15_N0
QC1L12 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L13 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT12 at DSPMULT_X10_Y15_N0
QC1L13 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L14 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT13 at DSPMULT_X10_Y15_N0
QC1L14 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L15 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT14 at DSPMULT_X10_Y15_N0
QC1L15 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L16 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT15 at DSPMULT_X10_Y15_N0
QC1L16 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L17 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT16 at DSPMULT_X10_Y15_N0
QC1L17 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L18 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT17 at DSPMULT_X10_Y15_N0
QC1L18 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L19 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT18 at DSPMULT_X10_Y15_N0
QC1L19 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L20 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT19 at DSPMULT_X10_Y15_N0
QC1L20 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L21 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT20 at DSPMULT_X10_Y15_N0
QC1L21 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L22 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT21 at DSPMULT_X10_Y15_N0
QC1L22 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L23 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT22 at DSPMULT_X10_Y15_N0
QC1L23 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L24 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT23 at DSPMULT_X10_Y15_N0
QC1L24 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L25 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT24 at DSPMULT_X10_Y15_N0
QC1L25 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L26 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT25 at DSPMULT_X10_Y15_N0
QC1L26 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L27 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT26 at DSPMULT_X10_Y15_N0
QC1L27 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L28 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT27 at DSPMULT_X10_Y15_N0
QC1L28 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L29 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT28 at DSPMULT_X10_Y15_N0
QC1L29 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L30 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT29 at DSPMULT_X10_Y15_N0
QC1L30 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L31 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT30 at DSPMULT_X10_Y15_N0
QC1L31 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L32 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT31 at DSPMULT_X10_Y15_N0
QC1L32 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L33 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT32 at DSPMULT_X10_Y15_N0
QC1L33 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L34 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT33 at DSPMULT_X10_Y15_N0
QC1L34 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L35 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT34 at DSPMULT_X10_Y15_N0
QC1L35 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L36 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1~DATAOUT35 at DSPMULT_X10_Y15_N0
QC1L36 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1_mac_mult2 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2 at DSPMULT_X10_Y13_N0
--DSP Block Multiplier Base Width: 18-bits
QC1_mac_mult2 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L110 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT1 at DSPMULT_X10_Y13_N0
QC1L110 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L111 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT2 at DSPMULT_X10_Y13_N0
QC1L111 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L112 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT3 at DSPMULT_X10_Y13_N0
QC1L112 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L113 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT4 at DSPMULT_X10_Y13_N0
QC1L113 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L114 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT5 at DSPMULT_X10_Y13_N0
QC1L114 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L115 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT6 at DSPMULT_X10_Y13_N0
QC1L115 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L116 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT7 at DSPMULT_X10_Y13_N0
QC1L116 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L117 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT8 at DSPMULT_X10_Y13_N0
QC1L117 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L118 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT9 at DSPMULT_X10_Y13_N0
QC1L118 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L119 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT10 at DSPMULT_X10_Y13_N0
QC1L119 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L120 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT11 at DSPMULT_X10_Y13_N0
QC1L120 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L121 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT12 at DSPMULT_X10_Y13_N0
QC1L121 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L122 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT13 at DSPMULT_X10_Y13_N0
QC1L122 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L123 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT14 at DSPMULT_X10_Y13_N0
QC1L123 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L124 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT15 at DSPMULT_X10_Y13_N0
QC1L124 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L125 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT16 at DSPMULT_X10_Y13_N0
QC1L125 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L126 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT17 at DSPMULT_X10_Y13_N0
QC1L126 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L127 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT18 at DSPMULT_X10_Y13_N0
QC1L127 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L128 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT19 at DSPMULT_X10_Y13_N0
QC1L128 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L129 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT20 at DSPMULT_X10_Y13_N0
QC1L129 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L130 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT21 at DSPMULT_X10_Y13_N0
QC1L130 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L131 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT22 at DSPMULT_X10_Y13_N0
QC1L131 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L132 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT23 at DSPMULT_X10_Y13_N0
QC1L132 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L133 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT24 at DSPMULT_X10_Y13_N0
QC1L133 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L134 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT25 at DSPMULT_X10_Y13_N0
QC1L134 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L135 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT26 at DSPMULT_X10_Y13_N0
QC1L135 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L136 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT27 at DSPMULT_X10_Y13_N0
QC1L136 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L137 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT28 at DSPMULT_X10_Y13_N0
QC1L137 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L138 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT29 at DSPMULT_X10_Y13_N0
QC1L138 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L139 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT30 at DSPMULT_X10_Y13_N0
QC1L139 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L140 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT31 at DSPMULT_X10_Y13_N0
QC1L140 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L141 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT32 at DSPMULT_X10_Y13_N0
QC1L141 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L142 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT33 at DSPMULT_X10_Y13_N0
QC1L142 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L143 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT34 at DSPMULT_X10_Y13_N0
QC1L143 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L144 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2~DATAOUT35 at DSPMULT_X10_Y13_N0
QC1L144 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1_mac_mult3 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3 at DSPMULT_X10_Y11_N0
--DSP Block Multiplier Base Width: 18-bits
QC1_mac_mult3 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L218 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT1 at DSPMULT_X10_Y11_N0
QC1L218 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L219 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT2 at DSPMULT_X10_Y11_N0
QC1L219 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L220 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT3 at DSPMULT_X10_Y11_N0
QC1L220 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L221 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT4 at DSPMULT_X10_Y11_N0
QC1L221 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L222 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT5 at DSPMULT_X10_Y11_N0
QC1L222 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L223 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT6 at DSPMULT_X10_Y11_N0
QC1L223 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L224 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT7 at DSPMULT_X10_Y11_N0
QC1L224 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L225 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT8 at DSPMULT_X10_Y11_N0
QC1L225 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L226 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT9 at DSPMULT_X10_Y11_N0
QC1L226 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L227 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT10 at DSPMULT_X10_Y11_N0
QC1L227 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L228 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT11 at DSPMULT_X10_Y11_N0
QC1L228 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L229 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT12 at DSPMULT_X10_Y11_N0
QC1L229 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L230 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT13 at DSPMULT_X10_Y11_N0
QC1L230 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L231 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT14 at DSPMULT_X10_Y11_N0
QC1L231 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L232 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT15 at DSPMULT_X10_Y11_N0
QC1L232 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L233 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT16 at DSPMULT_X10_Y11_N0
QC1L233 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L234 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT17 at DSPMULT_X10_Y11_N0
QC1L234 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L235 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT18 at DSPMULT_X10_Y11_N0
QC1L235 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L236 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT19 at DSPMULT_X10_Y11_N0
QC1L236 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L237 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT20 at DSPMULT_X10_Y11_N0
QC1L237 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L238 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT21 at DSPMULT_X10_Y11_N0
QC1L238 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L239 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT22 at DSPMULT_X10_Y11_N0
QC1L239 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L240 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT23 at DSPMULT_X10_Y11_N0
QC1L240 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L241 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT24 at DSPMULT_X10_Y11_N0
QC1L241 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L242 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT25 at DSPMULT_X10_Y11_N0
QC1L242 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L243 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT26 at DSPMULT_X10_Y11_N0
QC1L243 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L244 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT27 at DSPMULT_X10_Y11_N0
QC1L244 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L245 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT28 at DSPMULT_X10_Y11_N0
QC1L245 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L246 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT29 at DSPMULT_X10_Y11_N0
QC1L246 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L247 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT30 at DSPMULT_X10_Y11_N0
QC1L247 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L248 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT31 at DSPMULT_X10_Y11_N0
QC1L248 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L249 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT32 at DSPMULT_X10_Y11_N0
QC1L249 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L250 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT33 at DSPMULT_X10_Y11_N0
QC1L250 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L251 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT34 at DSPMULT_X10_Y11_N0
QC1L251 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1L252 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3~DATAOUT35 at DSPMULT_X10_Y11_N0
QC1L252 = AMPP_FUNCTION(GND, GND, L1L618, L1L619, L1L620, L1L621, L1L622, L1L623, L1L624, L1L625, L1L626, L1L627, L1L628, L1L629, L1L630, L1L631, L1L632, L1L633, L1L634, QC1_w7w[32], VCC, VCC, VCC, L1L735, L1L736, L1L737, L1L738, L1L739, L1L740, L1L741, L1L742, L1L743, L1L744, L1L745, L1L746, L1L747, L1L748, L1L749, DE1__clk0, E1_data_out, GND);
--QC1_mac_mult4 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4 at DSPMULT_X10_Y9_N0
--DSP Block Multiplier Base Width: 18-bits
QC1_mac_mult4 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L326 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT1 at DSPMULT_X10_Y9_N0
QC1L326 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L327 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT2 at DSPMULT_X10_Y9_N0
QC1L327 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L328 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT3 at DSPMULT_X10_Y9_N0
QC1L328 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L329 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT4 at DSPMULT_X10_Y9_N0
QC1L329 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L330 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT5 at DSPMULT_X10_Y9_N0
QC1L330 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L331 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT6 at DSPMULT_X10_Y9_N0
QC1L331 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L332 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT7 at DSPMULT_X10_Y9_N0
QC1L332 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L333 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT8 at DSPMULT_X10_Y9_N0
QC1L333 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L334 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT9 at DSPMULT_X10_Y9_N0
QC1L334 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L335 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT10 at DSPMULT_X10_Y9_N0
QC1L335 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L336 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT11 at DSPMULT_X10_Y9_N0
QC1L336 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L337 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT12 at DSPMULT_X10_Y9_N0
QC1L337 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L338 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT13 at DSPMULT_X10_Y9_N0
QC1L338 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L339 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT14 at DSPMULT_X10_Y9_N0
QC1L339 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L340 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT15 at DSPMULT_X10_Y9_N0
QC1L340 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L341 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT16 at DSPMULT_X10_Y9_N0
QC1L341 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L342 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT17 at DSPMULT_X10_Y9_N0
QC1L342 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L343 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT18 at DSPMULT_X10_Y9_N0
QC1L343 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L344 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT19 at DSPMULT_X10_Y9_N0
QC1L344 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L345 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT20 at DSPMULT_X10_Y9_N0
QC1L345 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L346 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT21 at DSPMULT_X10_Y9_N0
QC1L346 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L347 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT22 at DSPMULT_X10_Y9_N0
QC1L347 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L348 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT23 at DSPMULT_X10_Y9_N0
QC1L348 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L349 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT24 at DSPMULT_X10_Y9_N0
QC1L349 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L350 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT25 at DSPMULT_X10_Y9_N0
QC1L350 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L351 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT26 at DSPMULT_X10_Y9_N0
QC1L351 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L352 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT27 at DSPMULT_X10_Y9_N0
QC1L352 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L353 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT28 at DSPMULT_X10_Y9_N0
QC1L353 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L354 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT29 at DSPMULT_X10_Y9_N0
QC1L354 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L355 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT30 at DSPMULT_X10_Y9_N0
QC1L355 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L356 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT31 at DSPMULT_X10_Y9_N0
QC1L356 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L357 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT32 at DSPMULT_X10_Y9_N0
QC1L357 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L358 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT33 at DSPMULT_X10_Y9_N0
QC1L358 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L359 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT34 at DSPMULT_X10_Y9_N0
QC1L359 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--QC1L360 is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4~DATAOUT35 at DSPMULT_X10_Y9_N0
QC1L360 = AMPP_FUNCTION(GND, GND, VCC, VCC, VCC, L1L603, L1L604, L1L605, L1L606, L1L607, L1L608, L1L609, L1L610, L1L611, L1L612, L1L613, L1L614, L1L615, L1L616, L1L617, L1L750, L1L751, L1L752, L1L753, L1L754, L1L755, L1L756, L1L757, L1L758, L1L759, L1L760, L1L761, L1L762, L1L764, L1L765, L1L766, L1L767, QC1_w23w[32], DE1__clk0, E1_data_out, GND);
--L1_E_ctrl_mulx is std_1s10:inst|cpu:the_cpu|E_ctrl_mulx at LC_X17_Y11_N6
--operation mode is normal
L1_E_ctrl_mulx = AMPP_FUNCTION(DE1__clk0, L1L830, L1L827, L1_D_iw[12], L1L242, E1_data_out, L1_W_stall);
--L1_E_ctrl_shift_right is std_1s10:inst|cpu:the_cpu|E_ctrl_shift_right at LC_X19_Y7_N8
--operation mode is normal
L1_E_ctrl_shift_right = AMPP_FUNCTION(DE1__clk0, L1L830, L1L244, L1L827, L1_D_iw[12], E1_data_out, L1_W_stall);
--L1L849 is std_1s10:inst|cpu:the_cpu|Equal230~89 at LC_X14_Y13_N1
--operation mode is normal
L1L849 = AMPP_FUNCTION(L1L671, L1L669, L1L670);
--L1_E_ctrl_rot is std_1s10:inst|cpu:the_cpu|E_ctrl_rot at LC_X17_Y11_N3
--operation mode is normal
L1_E_ctrl_rot = AMPP_FUNCTION(DE1__clk0, L1_D_iw[15], L1L243, E1_data_out, L1_W_stall);
--L1L240 is std_1s10:inst|cpu:the_cpu|D_ctrl_mul_shift_rot~227 at LC_X19_Y10_N6
--operation mode is normal
L1L240 = AMPP_FUNCTION(L1_D_iw[5], L1_D_iw[4], L1L832);
--F1_readdata[2] is std_1s10:inst|button_pio:the_button_pio|readdata[2] at LC_X48_Y13_N4
--operation mode is normal
F1_readdata[2]_lut_out = L1_M_alu_result[3] & (F1L26) # !L1_M_alu_result[3] & !L1_M_alu_result[2] & (in_port_to_the_button_pio[2]);
F1_readdata[2] = DFFEAS(F1_readdata[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L37 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4830 at LC_X48_Y13_N5
--operation mode is normal
M1L37 = L1_M_alu_result[7] & (A1L141) # !L1_M_alu_result[7] & F1_readdata[2] # !G1L1;
--M1_registered_cpu_data_master_readdata[2] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[2] at LC_X48_Y15_N7
--operation mode is normal
M1_registered_cpu_data_master_readdata[2]_lut_out = M1L298 & M1L270 & (FB1_za_data[2] # !GB1L24);
M1_registered_cpu_data_master_readdata[2] = DFFEAS(M1_registered_cpu_data_master_readdata[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L38 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4831 at LC_X48_Y13_N6
--operation mode is normal
M1L38 = M1L37 & (M1_registered_cpu_data_master_readdata[2] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--KB1_readdata[2] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[2] at LC_X50_Y5_N6
--operation mode is normal
KB1_readdata[2]_lut_out = KB1L188 # KB1L189 # !KB1_period_l_register[2] & HE1L20;
KB1_readdata[2] = DFFEAS(KB1_readdata[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--LB1L3 is std_1s10:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1~150 at LC_X46_Y12_N1
--operation mode is normal
LB1L3 = !L1_M_alu_result[6] & (!L1_M_alu_result[5]);
--NB1L3 is std_1s10:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~59 at LC_X48_Y11_N6
--operation mode is normal
NB1L3 = !L1_M_alu_result[4] & L1_M_alu_result[3];
--NB1L4 is std_1s10:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~60 at LC_X48_Y11_N3
--operation mode is normal
NB1L4 = L1_M_alu_result[5] & !L1_M_alu_result[6] & L1_internal_d_read & NB1L3;
--NB1_cpu_data_master_granted_sysid_control_slave is std_1s10:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave at LC_X48_Y11_N0
--operation mode is normal
NB1_cpu_data_master_granted_sysid_control_slave = NB1L2 & P1L7 & NB1L4 & !L1_M_alu_result[7];
--M1L39 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4832 at LC_X46_Y12_N6
--operation mode is normal
M1L39 = !NB1_cpu_data_master_granted_sysid_control_slave & (KB1_readdata[2] # !LB1L2 # !LB1L3);
--BE1_q_a[0] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[0] at MRAM_X20_Y7
--RAM Block Operation Mode: Single Port
--Port A Depth: 16384, Port A Width: 32
--Port A Logical Depth: 16384, Port A Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[0] = BE1_q_a[0]_PORT_A_data_out[0];
--BE1_q_a[1] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[1] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[1] = BE1_q_a[0]_PORT_A_data_out[1];
--BE1_q_a[2] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[2] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[2] = BE1_q_a[0]_PORT_A_data_out[2];
--BE1_q_a[3] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[3] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[3] = BE1_q_a[0]_PORT_A_data_out[3];
--BE1_q_a[4] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[4] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[4] = BE1_q_a[0]_PORT_A_data_out[4];
--BE1_q_a[5] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[5] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[5] = BE1_q_a[0]_PORT_A_data_out[5];
--BE1_q_a[6] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[6] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[6] = BE1_q_a[0]_PORT_A_data_out[6];
--BE1_q_a[7] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[7] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[7] = BE1_q_a[0]_PORT_A_data_out[7];
--BE1_q_a[31] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[31] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[31] = BE1_q_a[0]_PORT_A_data_out[31];
--BE1_q_a[30] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[30] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[30] = BE1_q_a[0]_PORT_A_data_out[30];
--BE1_q_a[29] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[29] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[29] = BE1_q_a[0]_PORT_A_data_out[29];
--BE1_q_a[28] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[28] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[28] = BE1_q_a[0]_PORT_A_data_out[28];
--BE1_q_a[27] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[27] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[27] = BE1_q_a[0]_PORT_A_data_out[27];
--BE1_q_a[26] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[26] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[26] = BE1_q_a[0]_PORT_A_data_out[26];
--BE1_q_a[25] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[25] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[25] = BE1_q_a[0]_PORT_A_data_out[25];
--BE1_q_a[24] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[24] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[24] = BE1_q_a[0]_PORT_A_data_out[24];
--BE1_q_a[15] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[15] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[15] = BE1_q_a[0]_PORT_A_data_out[23];
--BE1_q_a[14] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[14] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[14] = BE1_q_a[0]_PORT_A_data_out[22];
--BE1_q_a[13] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[13] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[13] = BE1_q_a[0]_PORT_A_data_out[21];
--BE1_q_a[12] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[12] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[12] = BE1_q_a[0]_PORT_A_data_out[20];
--BE1_q_a[11] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[11] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[11] = BE1_q_a[0]_PORT_A_data_out[19];
--BE1_q_a[10] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[10] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[10] = BE1_q_a[0]_PORT_A_data_out[18];
--BE1_q_a[9] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[9] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[9] = BE1_q_a[0]_PORT_A_data_out[17];
--BE1_q_a[8] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[8] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[8] = BE1_q_a[0]_PORT_A_data_out[16];
--BE1_q_a[23] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[23] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[23] = BE1_q_a[0]_PORT_A_data_out[15];
--BE1_q_a[22] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[22] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[22] = BE1_q_a[0]_PORT_A_data_out[14];
--BE1_q_a[21] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[21] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[21] = BE1_q_a[0]_PORT_A_data_out[13];
--BE1_q_a[20] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[20] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[20] = BE1_q_a[0]_PORT_A_data_out[12];
--BE1_q_a[19] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[19] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[19] = BE1_q_a[0]_PORT_A_data_out[11];
--BE1_q_a[18] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[18] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[18] = BE1_q_a[0]_PORT_A_data_out[10];
--BE1_q_a[17] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[17] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[17] = BE1_q_a[0]_PORT_A_data_out[9];
--BE1_q_a[16] is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|q_a[16] at MRAM_X20_Y7
BE1_q_a[0]_PORT_A_data_in = BUS(L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31]);
BE1_q_a[0]_PORT_A_data_in_reg = DFFE(BE1_q_a[0]_PORT_A_data_in, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_address = BUS(AB1L18, AB1L19, AB1L20, AB1L21, AB1L22, AB1L23, AB1L24, AB1L25, AB1L26, AB1L27, AB1L28, AB1L29, AB1L30, AB1L31);
BE1_q_a[0]_PORT_A_address_reg = DFFE(BE1_q_a[0]_PORT_A_address, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_write_enable = Z1L1;
BE1_q_a[0]_PORT_A_write_enable_reg = DFFE(BE1_q_a[0]_PORT_A_write_enable, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_PORT_A_byte_mask = BUS(AB1L34, AB1L36, AB1L35, AB1L37);
BE1_q_a[0]_PORT_A_byte_mask_reg = DFFE(BE1_q_a[0]_PORT_A_byte_mask, BE1_q_a[0]_clock_0, , , );
BE1_q_a[0]_clock_0 = GLOBAL(DE1__clk0);
BE1_q_a[0]_PORT_A_data_out = MEMORY(BE1_q_a[0]_PORT_A_data_in_reg, , BE1_q_a[0]_PORT_A_address_reg, , BE1_q_a[0]_PORT_A_write_enable_reg, , BE1_q_a[0]_PORT_A_byte_mask_reg, , BE1_q_a[0]_clock_0, , , , , );
BE1_q_a[16] = BE1_q_a[0]_PORT_A_data_out[8];
--M1L40 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4833 at LC_X46_Y12_N7
--operation mode is normal
M1L40 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[2] & (BE1_q_a[2] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[2] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--R1_readdata[2] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[2] at LC_X47_Y8_N2
--operation mode is normal
R1_readdata[2]_lut_out = R1L188 # R1L187 # !R1_period_l_register[2] & HE1L20;
R1_readdata[2] = DFFEAS(R1_readdata[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--S1L2 is std_1s10:inst|high_res_timer_s1_arbitrator:the_high_res_timer_s1|cpu_data_master_requests_high_res_timer_s1~144 at LC_X48_Y12_N8
--operation mode is normal
S1L2 = L1_M_alu_result[5] & L1_M_alu_result[6];
--M1L41 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4834 at LC_X46_Y12_N8
--operation mode is normal
M1L41 = M1L40 & M1L39 & (R1_readdata[2] # !S1_cpu_data_master_requests_high_res_timer_s1);
--M1L42 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4835 at LC_X47_Y12_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[2]_qfbk = M1_dbs_8_reg_segment_0[2];
M1L42 = Q1_cpu_data_master_requests_ext_flash_s1 & M1_dbs_8_reg_segment_0[2]_qfbk & (M1_registered_cpu_data_master_readdata[2] # !GB1L24) # !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[2] # !GB1L24);
--M1_dbs_8_reg_segment_0[2] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[2] at LC_X47_Y12_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[2] = DFFEAS(M1L42, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L308, Q1_internal_incoming_ext_ram_bus_data[2], , , VCC);
--HE1_readdata[2] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[2] at LC_X50_Y8_N1
--operation mode is normal
HE1_readdata[2]_lut_out = !L1_M_alu_result[4] & (L1_M_alu_result[2] & (HE1L51) # !L1_M_alu_result[2] & HE1L52);
HE1_readdata[2] = DFFEAS(HE1_readdata[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--EB1_cpu_data_master_requests_reconfig_request_pio_s1 is std_1s10:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1 at LC_X46_Y15_N9
--operation mode is normal
EB1_cpu_data_master_requests_reconfig_request_pio_s1 = L1_M_alu_result[7] & EB1L2;
--M1L43 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4836 at LC_X46_Y12_N2
--operation mode is normal
M1L43 = M1L45 & !EB1_cpu_data_master_requests_reconfig_request_pio_s1 & (HE1_readdata[2] # !QB1_cpu_data_master_granted_uart1_s1);
--M1L44 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4837 at LC_X46_Y12_N5
--operation mode is normal
M1L44 = M1L41 & (M1L38 & M1L43);
--P1L15 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[0]~90 at LC_X34_Y10_N6
--operation mode is normal
P1L15 = P1L3 & (L1_M_alu_result[2]) # !P1L3 & L1_ic_fill_ap_offset[0];
--P1L23 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[8]~91 at LC_X45_Y16_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_line[5]_qfbk = L1_ic_fill_line[5];
P1L23 = P1L3 & (L1_M_alu_result[10]) # !P1L3 & (L1_ic_fill_line[5]_qfbk);
--L1_ic_fill_line[5] is std_1s10:inst|cpu:the_cpu|ic_fill_line[5] at LC_X45_Y16_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_line[5] = AMPP_FUNCTION(DE1__clk0, L1L1124, E1_data_out, GND);
--P1L16 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[1]~92 at LC_X36_Y10_N2
--operation mode is normal
P1L16 = P1L3 & (L1_M_alu_result[3]) # !P1L3 & L1_ic_fill_ap_offset[1];
--P1L22 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[7]~93 at LC_X39_Y20_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_line[4]_qfbk = L1_ic_fill_line[4];
P1L22 = P1L3 & L1_M_alu_result[9] # !P1L3 & (L1_ic_fill_line[4]_qfbk);
--L1_ic_fill_line[4] is std_1s10:inst|cpu:the_cpu|ic_fill_line[4] at LC_X39_Y20_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_line[4] = AMPP_FUNCTION(DE1__clk0, L1L1122, E1_data_out, GND);
--P1L20 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[5]~94 at LC_X40_Y21_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_line[2]_qfbk = L1_ic_fill_line[2];
P1L20 = P1L3 & L1_M_alu_result[7] # !P1L3 & (L1_ic_fill_line[2]_qfbk);
--L1_ic_fill_line[2] is std_1s10:inst|cpu:the_cpu|ic_fill_line[2] at LC_X40_Y21_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_line[2] = AMPP_FUNCTION(DE1__clk0, L1L1118, E1_data_out, GND);
--SC1L1 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~67 at LC_X40_Y21_N9
--operation mode is normal
SC1L1 = AMPP_FUNCTION(P1L23, P1L22, P1L16, P1L20);
--P1L18 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[3]~95 at LC_X35_Y21_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_line[0]_qfbk = L1_ic_fill_line[0];
P1L18 = P1L3 & L1_M_alu_result[5] # !P1L3 & (L1_ic_fill_line[0]_qfbk);
--L1_ic_fill_line[0] is std_1s10:inst|cpu:the_cpu|ic_fill_line[0] at LC_X35_Y21_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_line[0] = AMPP_FUNCTION(DE1__clk0, L1L1075, E1_data_out, GND);
--P1L19 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[4]~96 at LC_X40_Y12_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_line[1]_qfbk = L1_ic_fill_line[1];
P1L19 = P1L3 & L1_M_alu_result[6] # !P1L3 & (L1_ic_fill_line[1]_qfbk);
--L1_ic_fill_line[1] is std_1s10:inst|cpu:the_cpu|ic_fill_line[1] at LC_X40_Y12_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_line[1] = AMPP_FUNCTION(DE1__clk0, L1L1116, E1_data_out, GND);
--P1L21 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[6]~97 at LC_X34_Y10_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_line[3]_qfbk = L1_ic_fill_line[3];
P1L21 = P1L3 & L1_M_alu_result[8] # !P1L3 & (L1_ic_fill_line[3]_qfbk);
--L1_ic_fill_line[3] is std_1s10:inst|cpu:the_cpu|ic_fill_line[3] at LC_X34_Y10_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_line[3] = AMPP_FUNCTION(DE1__clk0, L1L1120, E1_data_out, GND);
--P1L17 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[2]~98 at LC_X36_Y10_N4
--operation mode is normal
P1L17 = P1L3 & L1_M_alu_result[4] # !P1L3 & (L1_ic_fill_ap_offset[2]);
--SC1L2 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~68 at LC_X40_Y21_N3
--operation mode is normal
SC1L2 = AMPP_FUNCTION(P1L18, P1L21, P1L19, P1L17);
--FC1L21 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[18]~1195 at LC_X40_Y21_N4
--operation mode is normal
FC1L21 = AMPP_FUNCTION(P1L15, SC1L1, SC1L2, P1L23);
--SC1L3 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~69 at LC_X40_Y21_N6
--operation mode is normal
SC1L3 = AMPP_FUNCTION(SC1L2, P1L15, SC1L1);
--FC1L5 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[2]~1196 at LC_X40_Y20_N3
--operation mode is normal
FC1L5 = AMPP_FUNCTION(FC1L21, SC1_internal_oci_ienable1[2], SC1L3);
--VC1_internal_monitor_go is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_go at LC_X34_Y25_N5
--operation mode is normal
VC1_internal_monitor_go = AMPP_FUNCTION(DE1__clk0, VC1_internal_monitor_go, SC1L13, DD1_internal_jdo1[23], VC1L5, VCC);
--PD1_q_a[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[0] at M4K_X37_Y24
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 16, Port B Depth: 256, Port B Width: 16
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
PD1_q_a[0] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[1] at M4K_X37_Y24
PD1_q_a[1] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[2] at M4K_X37_Y24
PD1_q_a[2] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[3] at M4K_X37_Y24
PD1_q_a[3] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[4] at M4K_X37_Y24
PD1_q_a[4] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[5] at M4K_X37_Y24
PD1_q_a[5] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[6] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[6] at M4K_X37_Y24
PD1_q_a[6] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[7] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[7] at M4K_X37_Y24
PD1_q_a[7] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[0] at M4K_X37_Y24
PD1_q_b[0] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[1] at M4K_X37_Y24
PD1_q_b[1] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[2] at M4K_X37_Y24
PD1_q_b[2] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[3] at M4K_X37_Y24
PD1_q_b[3] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[4] at M4K_X37_Y24
PD1_q_b[4] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[5] at M4K_X37_Y24
PD1_q_b[5] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[6] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[6] at M4K_X37_Y24
PD1_q_b[6] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[7] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[7] at M4K_X37_Y24
PD1_q_b[7] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[23] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[23] at M4K_X37_Y24
PD1_q_a[23] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[22] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[22] at M4K_X37_Y24
PD1_q_a[22] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[21] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[21] at M4K_X37_Y24
PD1_q_a[21] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[20] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[20] at M4K_X37_Y24
PD1_q_a[20] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[19] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[19] at M4K_X37_Y24
PD1_q_a[19] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[18] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[18] at M4K_X37_Y24
PD1_q_a[18] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[17] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[17] at M4K_X37_Y24
PD1_q_a[17] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_a[16] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[16] at M4K_X37_Y24
PD1_q_a[16] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[23] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[23] at M4K_X37_Y24
PD1_q_b[23] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[22] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[22] at M4K_X37_Y24
PD1_q_b[22] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[21] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[21] at M4K_X37_Y24
PD1_q_b[21] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[20] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[20] at M4K_X37_Y24
PD1_q_b[20] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[19] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[19] at M4K_X37_Y24
PD1_q_b[19] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[18] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[18] at M4K_X37_Y24
PD1_q_b[18] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[17] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[17] at M4K_X37_Y24
PD1_q_b[17] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--PD1_q_b[16] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[16] at M4K_X37_Y24
PD1_q_b[16] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[2], L1_M_st_data[3], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[7], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L31, CD1_internal_MonDReg[0], CD1_internal_MonDReg[1], CD1_internal_MonDReg[2], CD1_internal_MonDReg[3], CD1_internal_MonDReg[4], CD1_internal_MonDReg[5], CD1_internal_MonDReg[6], CD1_internal_MonDReg[7], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[16], L1_M_st_data[17], L1_M_st_data[18], L1_M_st_data[19], L1_M_st_data[20], L1_M_st_data[21], L1_M_st_data[22], L1_M_st_data[23], CD1_internal_MonDReg[16], CD1_internal_MonDReg[17], CD1_internal_MonDReg[18], CD1_internal_MonDReg[19], CD1_internal_MonDReg[20], CD1_internal_MonDReg[21], CD1_internal_MonDReg[22], CD1_internal_MonDReg[23], P1L33);
--FC1L6 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[2]~1197 at LC_X40_Y20_N6
--operation mode is normal
FC1L6 = AMPP_FUNCTION(PD1_q_a[2], P1L23, VC1_internal_monitor_go, SC1L3);
--EB1L3 is std_1s10:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1~45 at LC_X40_Y12_N4
--operation mode is normal
--M1L97 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~4838 at LC_X48_Y14_N9
--operation mode is normal
M1L97 = !L1_M_alu_result[4] & !L1_M_alu_result[7] # !EB1L3;
--M1L145 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~4839 at LC_X47_Y13_N3
--operation mode is normal
M1L145 = M1L97 & (L1_M_alu_result[5] & !L1_M_alu_result[6] # !LB1L2);
--M1L156 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~4840 at LC_X45_Y16_N7
--operation mode is normal
M1L156 = Q1_internal_incoming_ext_ram_bus_data[18] & (BE1_q_a[18] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_internal_incoming_ext_ram_bus_data[18] & !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[18] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1_registered_cpu_data_master_readdata[18] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[18] at LC_X51_Y16_N8
--operation mode is normal
M1_registered_cpu_data_master_readdata[18]_lut_out = !J1_cpu_data_master_requests_clock_0_in & M1L284 & (T1L26 # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
M1_registered_cpu_data_master_readdata[18] = DFFEAS(M1_registered_cpu_data_master_readdata[18]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L157 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~4841 at LC_X41_Y16_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[2]_qfbk = M1_dbs_8_reg_segment_2[2];
M1L157 = Q1_cpu_data_master_requests_ext_flash_s1 & M1_dbs_8_reg_segment_2[2]_qfbk & (M1_registered_cpu_data_master_readdata[18] # !GB1L24) # !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[18] # !GB1L24);
--M1_dbs_8_reg_segment_2[2] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[2] at LC_X41_Y16_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[2] = DFFEAS(M1L157, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L310, Q1_internal_incoming_ext_ram_bus_data[2], , , VCC);
--M1L158 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~4842 at LC_X45_Y16_N6
--operation mode is normal
M1L158 = M1L157 & M1L156 & (Q1_internal_incoming_ext_ram_bus_data[18] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L159 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~4843 at LC_X45_Y16_N8
--operation mode is normal
M1L159 = M1L158 & (M1_registered_cpu_data_master_readdata[18] # !J1_cpu_data_master_requests_clock_0_in & !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
--M1L160 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[18]~4844 at LC_X45_Y16_N9
--operation mode is normal
M1L160 = M1L145 & (!NB1_cpu_data_master_granted_sysid_control_slave & M1L159);
--FC1L22 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[18]~1198 at LC_X45_Y16_N1
--operation mode is normal
FC1L22 = AMPP_FUNCTION(L1_M_alu_result[10], PD1_q_a[18], P1L3, L1_ic_fill_line[5]);
--KC1_q_b[16] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[16] at M4K_X37_Y19
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[16] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[16], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[14], L1_i_readdata_d1[13], L1_i_readdata_d1[21]);
--KC1_q_b[21] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[21] at M4K_X37_Y19
KC1_q_b[21] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[16], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[14], L1_i_readdata_d1[13], L1_i_readdata_d1[21]);
--KC1_q_b[13] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[13] at M4K_X37_Y19
KC1_q_b[13] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[16], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[14], L1_i_readdata_d1[13], L1_i_readdata_d1[21]);
--KC1_q_b[14] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[14] at M4K_X37_Y19
KC1_q_b[14] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[16], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[14], L1_i_readdata_d1[13], L1_i_readdata_d1[21]);
--L1L933 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[0]~48 at LC_X34_Y20_N3
--operation mode is arithmetic
L1L933 = AMPP_FUNCTION(L1_F_pc[0]);
--L1_D_pc_plus_one[0] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[0] at LC_X34_Y20_N3
--operation mode is arithmetic
L1_D_pc_plus_one[0] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[0], E1_data_out, L1_W_stall);
--L1L934 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[0]~49 at LC_X34_Y20_N3
--operation mode is arithmetic
L1L934 = AMPP_FUNCTION(L1_F_pc[0]);
--L1L935 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[0]~49COUT1_188 at LC_X34_Y20_N3
--operation mode is arithmetic
L1L935 = AMPP_FUNCTION(L1_F_pc[0]);
--L1L208 is std_1s10:inst|cpu:the_cpu|D_ctrl_alu_signed_cmp~318 at LC_X19_Y6_N4
--operation mode is normal
L1L208 = AMPP_FUNCTION(L1L835, L1L834);
--L1L210 is std_1s10:inst|cpu:the_cpu|D_ctrl_alu_subtract~408 at LC_X19_Y6_N7
--operation mode is normal
L1L210 = AMPP_FUNCTION(L1L208, L1L213, L1L827, L1_D_iw[4]);
--L1L244 is std_1s10:inst|cpu:the_cpu|D_ctrl_shift_right~48 at LC_X19_Y7_N9
--operation mode is normal
L1L244 = AMPP_FUNCTION(L1_D_iw[15], L1_D_iw[14], L1_D_iw[13]);
--L1L211 is std_1s10:inst|cpu:the_cpu|D_ctrl_alu_subtract~409 at LC_X18_Y9_N4
--operation mode is normal
L1L211 = AMPP_FUNCTION(L1L244, L1_D_iw[11], L1L212);
--HE1_irq is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|irq at LC_X50_Y9_N5
--operation mode is normal
HE1_irq_lut_out = HE1L36 # HE1L35 # JE1_internal_rx_char_ready & HE1_control_reg[7];
HE1_irq = DFFEAS(HE1_irq_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--SC1_internal_oci_ienable1[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[3] at LC_X44_Y21_N1
--operation mode is normal
SC1_internal_oci_ienable1[3] = AMPP_FUNCTION(DE1__clk0, L1_M_st_data[3], E1_data_out, SC1L12);
--F1_readdata[3] is std_1s10:inst|button_pio:the_button_pio|readdata[3] at LC_X50_Y12_N9
--operation mode is normal
F1_readdata[3]_lut_out = L1_M_alu_result[3] & F1L27 # !L1_M_alu_result[3] & (!L1_M_alu_result[2] & in_port_to_the_button_pio[3]);
F1_readdata[3] = DFFEAS(F1_readdata[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L46 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4845 at LC_X50_Y12_N1
--operation mode is normal
M1L46 = L1_M_alu_result[7] & A1L140 # !L1_M_alu_result[7] & (F1_readdata[3]) # !G1L1;
--M1_registered_cpu_data_master_readdata[3] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[3] at LC_X41_Y12_N2
--operation mode is normal
M1_registered_cpu_data_master_readdata[3]_lut_out = M1L271 & M1L299 & (FB1_za_data[3] # !GB1L24);
M1_registered_cpu_data_master_readdata[3] = DFFEAS(M1_registered_cpu_data_master_readdata[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L47 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4846 at LC_X50_Y12_N2
--operation mode is normal
M1L47 = !EB1_cpu_data_master_requests_reconfig_request_pio_s1 & M1L46 & (M1_registered_cpu_data_master_readdata[3] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
--M1L48 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4847 at LC_X48_Y20_N5
--operation mode is normal
M1L48 = L1_M_alu_result[2] & !NB1_cpu_data_master_granted_sysid_control_slave & (M1_registered_cpu_data_master_readdata[3] # !J1_cpu_data_master_requests_clock_0_in) # !L1_M_alu_result[2] & (M1_registered_cpu_data_master_readdata[3] # !J1_cpu_data_master_requests_clock_0_in);
--M1L49 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4848 at LC_X44_Y21_N0
--operation mode is normal
M1L49 = AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & BE1_q_a[3] & (Q1_internal_incoming_ext_ram_bus_data[3] # !Q1_cpu_data_master_requests_lan91c111_s1) # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[3] # !Q1_cpu_data_master_requests_lan91c111_s1);
--KB1_readdata[3] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[3] at LC_X50_Y2_N6
--operation mode is normal
KB1_readdata[3]_lut_out = KB1L190 # KB1L191 # !KB1_period_l_register[3] & HE1L20;
KB1_readdata[3] = DFFEAS(KB1_readdata[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L50 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4849 at LC_X44_Y21_N4
--operation mode is normal
M1L50 = M1L48 & M1L49 & (KB1_readdata[3] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--R1_readdata[3] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[3] at LC_X46_Y8_N3
--operation mode is normal
R1_readdata[3]_lut_out = R1L189 # R1L190 # HE1L20 & !R1_period_l_register[3];
R1_readdata[3] = DFFEAS(R1_readdata[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L51 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4850 at LC_X47_Y12_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[3]_qfbk = M1_dbs_8_reg_segment_0[3];
M1L51 = Q1_cpu_data_master_requests_ext_flash_s1 & M1_dbs_8_reg_segment_0[3]_qfbk & (M1_registered_cpu_data_master_readdata[3] # !GB1L24) # !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[3] # !GB1L24);
--M1_dbs_8_reg_segment_0[3] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[3] at LC_X47_Y12_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[3] = DFFEAS(M1L51, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L308, Q1_internal_incoming_ext_ram_bus_data[3], , , VCC);
--HE1_readdata[3] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[3] at LC_X46_Y8_N0
--operation mode is normal
HE1_readdata[3]_lut_out = !L1_M_alu_result[4] & (L1_M_alu_result[2] & (HE1L53) # !L1_M_alu_result[2] & HE1L54);
HE1_readdata[3] = DFFEAS(HE1_readdata[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L52 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4851 at LC_X46_Y8_N2
--operation mode is normal
M1L52 = M1L226 & M1L54 & (HE1_readdata[3] # !QB1_cpu_data_master_granted_uart1_s1);
--M1L53 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4852 at LC_X44_Y21_N7
--operation mode is normal
M1L53 = M1L47 & M1L52 & M1L50;
--FC1L7 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[3]~1199 at LC_X44_Y21_N5
--operation mode is normal
FC1L7 = AMPP_FUNCTION(SC1_internal_oci_ienable1[3], FC1L21, SC1L3);
--FC1L8 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[3]~1200 at LC_X44_Y21_N2
--operation mode is normal
FC1L8 = AMPP_FUNCTION(P1L23, SC1_internal_oci_single_step_mode1, PD1_q_a[3], SC1L3);
--M1L161 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~4853 at LC_X46_Y20_N7
--operation mode is normal
M1L161 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[19] & (BE1_q_a[19] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[19] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1_registered_cpu_data_master_readdata[19] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[19] at LC_X46_Y20_N1
--operation mode is normal
M1_registered_cpu_data_master_readdata[19]_lut_out = M1L285 & !J1_cpu_data_master_requests_clock_0_in & (T1L30 # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
M1_registered_cpu_data_master_readdata[19] = DFFEAS(M1_registered_cpu_data_master_readdata[19]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L162 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~4854 at LC_X41_Y16_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[3]_qfbk = M1_dbs_8_reg_segment_2[3];
M1L162 = Q1_cpu_data_master_requests_ext_flash_s1 & M1_dbs_8_reg_segment_2[3]_qfbk & (M1_registered_cpu_data_master_readdata[19] # !GB1L24) # !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[19] # !GB1L24);
--M1_dbs_8_reg_segment_2[3] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[3] at LC_X41_Y16_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[3] = DFFEAS(M1L162, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L310, Q1_internal_incoming_ext_ram_bus_data[3], , , VCC);
--M1L163 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~4855 at LC_X46_Y20_N3
--operation mode is normal
M1L163 = M1L161 & M1L162 & (Q1_internal_incoming_ext_ram_bus_data[19] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L164 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~4856 at LC_X46_Y20_N4
--operation mode is normal
M1L164 = M1L163 & (M1_registered_cpu_data_master_readdata[19] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L165 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[19]~4857 at LC_X46_Y20_N2
--operation mode is normal
M1L165 = M1L145 & M1L164 & (L1_M_alu_result[2] # !NB1_cpu_data_master_granted_sysid_control_slave);
--FC1L23 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[19]~1201 at LC_X46_Y20_N9
--operation mode is normal
FC1L23 = AMPP_FUNCTION(PD1_q_a[19], L1_M_alu_result[10], L1_ic_fill_line[5], P1L3);
--L1L936 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[1]~50 at LC_X34_Y20_N4
--operation mode is arithmetic
L1L936 = AMPP_FUNCTION(L1_F_pc[1], L1L934, L1L935);
--L1_D_pc_plus_one[1] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[1] at LC_X34_Y20_N4
--operation mode is arithmetic
L1_D_pc_plus_one[1] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[1], E1_data_out, L1_W_stall, L1L934, L1L935);
--L1L937 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[1]~51 at LC_X34_Y20_N4
--operation mode is arithmetic
L1L937 = AMPP_FUNCTION(L1_F_pc[1], L1L934, L1L935);
--L1L947 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[5]~52 at LC_X34_Y20_N8
--operation mode is arithmetic
L1L947 = AMPP_FUNCTION(L1_F_pc[5], L1L937, L1L945, L1L946);
--L1_D_pc_plus_one[5] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[5] at LC_X34_Y20_N8
--operation mode is arithmetic
L1_D_pc_plus_one[5] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[5], E1_data_out, L1_W_stall, L1L937, L1L945, L1L946);
--L1L948 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[5]~53 at LC_X34_Y20_N8
--operation mode is arithmetic
L1L948 = AMPP_FUNCTION(L1_F_pc[5], L1L945);
--L1L949 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[5]~53COUT1_196 at LC_X34_Y20_N8
--operation mode is arithmetic
L1L949 = AMPP_FUNCTION(L1_F_pc[5], L1L946);
--M1L63 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4858 at LC_X48_Y14_N8
--operation mode is normal
M1L63 = L1_M_alu_result[4] $ !L1_M_alu_result[7] # !EB1L3;
--M1L80 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4859 at LC_X48_Y14_N5
--operation mode is normal
M1L80 = M1L63 & (L1_M_alu_result[2] # !NB1_cpu_data_master_granted_sysid_control_slave);
--M1_registered_cpu_data_master_readdata[7] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[7] at LC_X48_Y18_N4
--operation mode is normal
M1_registered_cpu_data_master_readdata[7]_lut_out = M1L275 & M1L303 & (FB1_za_data[7] # !GB1L24);
M1_registered_cpu_data_master_readdata[7] = DFFEAS(M1_registered_cpu_data_master_readdata[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L81 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4860 at LC_X46_Y14_N6
--operation mode is normal
M1L81 = M1_registered_cpu_data_master_readdata[7] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--M1L82 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4861 at LC_X45_Y12_N9
--operation mode is normal
M1L82 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[7] & (BE1_q_a[7] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[7] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--HE1_readdata[7] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[7] at LC_X51_Y6_N8
--operation mode is normal
HE1_readdata[7]_lut_out = !L1_M_alu_result[4] & (L1_M_alu_result[2] & (HE1L61) # !L1_M_alu_result[2] & HE1L62);
HE1_readdata[7] = DFFEAS(HE1_readdata[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L83 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4862 at LC_X46_Y14_N7
--operation mode is normal
M1L83 = M1L82 & M1L81 & (HE1_readdata[7] # !QB1_cpu_data_master_granted_uart1_s1);
--M1L84 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4863 at LC_X47_Y12_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[7]_qfbk = M1_dbs_8_reg_segment_0[7];
M1L84 = Q1_cpu_data_master_requests_ext_flash_s1 & M1_dbs_8_reg_segment_0[7]_qfbk & (M1_registered_cpu_data_master_readdata[7] # !GB1L24) # !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[7] # !GB1L24);
--M1_dbs_8_reg_segment_0[7] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[7] at LC_X47_Y12_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[7] = DFFEAS(M1L84, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L308, Q1_internal_incoming_ext_ram_bus_data[7], , , VCC);
--R1_readdata[7] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[7] at LC_X47_Y9_N3
--operation mode is normal
R1_readdata[7]_lut_out = L1_M_alu_result[3] & R1L198 & !L1_M_alu_result[4] # !L1_M_alu_result[3] & (L1_M_alu_result[4] & R1L197);
R1_readdata[7] = DFFEAS(R1_readdata[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L85 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4864 at LC_X47_Y9_N2
--operation mode is normal
M1L85 = M1L88 & (R1_readdata[7] # !LB1L2 # !S1L2);
--KB1_readdata[7] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[7] at LC_X50_Y6_N7
--operation mode is normal
KB1_readdata[7]_lut_out = L1_M_alu_result[4] & !L1_M_alu_result[3] & KB1L198 # !L1_M_alu_result[4] & L1_M_alu_result[3] & (KB1L199);
KB1_readdata[7] = DFFEAS(KB1_readdata[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L86 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4865 at LC_X50_Y6_N5
--operation mode is normal
M1L86 = A1L136 & (KB1_readdata[7] # !LB1_cpu_data_master_requests_sys_clk_timer_s1) # !A1L136 & !W1L18 & (KB1_readdata[7] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--M1L87 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4866 at LC_X46_Y14_N5
--operation mode is normal
M1L87 = M1L85 & M1L80 & M1L83 & M1L86;
--FC1L10 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[7]~1202 at LC_X41_Y14_N5
--operation mode is normal
FC1L10 = AMPP_FUNCTION(L1_M_alu_result[10], P1L3, PD1_q_a[7], L1_ic_fill_line[5]);
--M1L181 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~4867 at LC_X45_Y19_N2
--operation mode is normal
M1L181 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[23] & (BE1_q_a[23] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[23] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1_registered_cpu_data_master_readdata[23] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[23] at LC_X46_Y18_N0
--operation mode is normal
M1_registered_cpu_data_master_readdata[23]_lut_out = M1L289 & !J1_cpu_data_master_requests_clock_0_in & (FB1_za_data[23] # !GB1L24);
M1_registered_cpu_data_master_readdata[23] = DFFEAS(M1_registered_cpu_data_master_readdata[23]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L182 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~4868 at LC_X46_Y18_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[7]_qfbk = M1_dbs_8_reg_segment_2[7];
M1L182 = Q1_cpu_data_master_requests_ext_flash_s1 & M1_dbs_8_reg_segment_2[7]_qfbk & (M1_registered_cpu_data_master_readdata[23] # !GB1L24) # !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[23] # !GB1L24);
--M1_dbs_8_reg_segment_2[7] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[7] at LC_X46_Y18_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[7] = DFFEAS(M1L182, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L310, Q1_internal_incoming_ext_ram_bus_data[7], , , VCC);
--M1L183 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~4869 at LC_X46_Y18_N7
--operation mode is normal
M1L183 = M1L181 & M1L182 & (Q1_internal_incoming_ext_ram_bus_data[23] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L184 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~4870 at LC_X46_Y18_N4
--operation mode is normal
M1L184 = M1L183 & (M1_registered_cpu_data_master_readdata[23] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L185 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[23]~4871 at LC_X45_Y19_N3
--operation mode is normal
M1L185 = M1L184 & !NB1_cpu_data_master_granted_sysid_control_slave & M1L145;
--FC1L27 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[23]~1203 at LC_X45_Y19_N9
--operation mode is normal
FC1L27 = AMPP_FUNCTION(L1_M_alu_result[10], PD1_q_a[23], P1L3, L1_ic_fill_line[5]);
--L1L881 is std_1s10:inst|cpu:the_cpu|F_ic_hit~125 at LC_X35_Y16_N5
--operation mode is normal
L1L881 = AMPP_FUNCTION(L1L877, L1L878);
--L1L229 is std_1s10:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~729 at LC_X22_Y6_N1
--operation mode is normal
L1L229 = AMPP_FUNCTION(L1L247, L1L843, L1L233);
--L1L230 is std_1s10:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~730 at LC_X18_Y7_N0
--operation mode is normal
L1L230 = AMPP_FUNCTION(L1_D_iw[13], L1_D_iw[14], L1_D_iw[16], L1_D_iw[11]);
--L1L231 is std_1s10:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~731 at LC_X18_Y7_N9
--operation mode is normal
L1L231 = AMPP_FUNCTION(L1L234, L1_D_iw[15], L1L227, L1L230);
--L1L232 is std_1s10:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~732 at LC_X18_Y7_N2
--operation mode is normal
L1L232 = AMPP_FUNCTION(L1_D_iw[11], L1_D_iw[12], L1L231, L1L844);
--GC1L3 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~561 at LC_X14_Y10_N5
--operation mode is arithmetic
GC1L3 = AMPP_FUNCTION(L1L700, L1L634);
--GC1L4 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~561COUT1_799 at LC_X14_Y10_N5
--operation mode is arithmetic
GC1L4 = AMPP_FUNCTION(L1L700, L1L634);
--HC1_result[31] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[31] at LC_X18_Y9_N1
--operation mode is arithmetic
HC1_result[31] = AMPP_FUNCTION(L1L434, L1L433, HC1L85, HC1L87, HC1L88, L1_E_ctrl_alu_subtract);
--HC1L90 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[31]~COUT at LC_X18_Y9_N1
--operation mode is arithmetic
HC1L90 = AMPP_FUNCTION(L1L434, L1L433, HC1L87, L1_E_ctrl_alu_subtract);
--HC1L91 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[31]~COUTCOUT1_197 at LC_X18_Y9_N1
--operation mode is arithmetic
HC1L91 = AMPP_FUNCTION(L1L434, L1L433, HC1L88, L1_E_ctrl_alu_subtract);
--DD1_internal_jdo1[19] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[19] at LC_X32_Y24_N3
--operation mode is normal
DD1_internal_jdo1[19] = AMPP_FUNCTION(!A1L9, DD1_sr[19], VCC, DD1L144);
--DD1_internal_jdo1[18] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[18] at LC_X32_Y24_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[18] = AMPP_FUNCTION(!A1L9, DD1_sr[18], VCC, GND, DD1L144);
--DD1_sr[21] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[21] at LC_X32_Y27_N2
--operation mode is normal
DD1_sr[21] = AMPP_FUNCTION(!A1L6, DD1L10, DD1L9, DD1L8, DD1_sr[22], !C1_CLR_SIGNAL, DD1L12);
--C1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode at LC_X28_Y5_N6
--operation mode is normal
C1_jtag_debug_mode = AMPP_FUNCTION(!A1L6, C1L26, C1_jtag_debug_mode, C1L27, RE1_state[15], RE1_state[0]);
--ME2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] at LC_X31_Y26_N3
--operation mode is normal
ME2_Q[0] = AMPP_FUNCTION(!A1L6, ME2_Q[0], C1L1, SE1_dffe1a[1], ME9_Q[0], !C1_CLR_SIGNAL);
--DD1L144 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process3~12 at LC_X32_Y24_N5
--operation mode is normal
DD1L144 = AMPP_FUNCTION(ME8_Q[0], C1_jtag_debug_mode_usr1, ME2_Q[0], C1_jtag_debug_mode);
--DD1_sr[20] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[20] at LC_X32_Y27_N8
--operation mode is normal
DD1_sr[20] = AMPP_FUNCTION(!A1L6, DD1L15, DD1L9, DD1L14, DD1_sr[21], !C1_CLR_SIGNAL, DD1L12);
--RE1_state[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1] at LC_X28_Y4_N4
--operation mode is normal
RE1_state[1] = AMPP_FUNCTION(!A1L6, RE1_state[1], RE1_state[8], RE1_state[15], RE1_state[0], VCC, !A1L8);
--ME1_Q[0] is sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] at LC_X29_Y27_N6
--operation mode is normal
ME1_Q[0] = AMPP_FUNCTION(!A1L6, C1L2, ME1_Q[0], ME2_Q[0], SE1_dffe1a[7], C1_jtag_debug_mode_usr1);
--DD1_sr[34] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[34] at LC_X33_Y24_N5
--operation mode is normal
DD1_sr[34] = AMPP_FUNCTION(!A1L6, DD1L17, DD1_sr[35], DD1L141, DD1L16, !C1_CLR_SIGNAL, DD1L12);
--DD1_dr_update2 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|dr_update2 at LC_X33_Y28_N0
--operation mode is normal
DD1_dr_update2 = AMPP_FUNCTION(DE1__clk0, DD1_dr_update1, VCC);
--DD1_dr_update1 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|dr_update1 at LC_X33_Y28_N8
--operation mode is normal
DD1_dr_update1 = AMPP_FUNCTION(DE1__clk0, DD1_st_updatedr, VCC);
--DD1_sr[35] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[35] at LC_X33_Y28_N5
--operation mode is normal
DD1_sr[35] = AMPP_FUNCTION(!A1L6, DD1_ir[1], DD1L18, DD1L19, DD1L133, !C1_CLR_SIGNAL, !DD1_ir[0], DD1L12);
--ME5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] at LC_X30_Y28_N5
--operation mode is normal
ME5_Q[0] = AMPP_FUNCTION(!A1L6, ME7_Q[0], ME2_Q[0], ME3_Q[0], !C1_CLR_SIGNAL, C1L20);
--DD1_st_updateir is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updateir at LC_X32_Y29_N4
--operation mode is normal
DD1_st_updateir = AMPP_FUNCTION(!A1L6, DD1L145, VCC, !A1L9);
--DD1L116 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0]~0 at LC_X32_Y25_N5
--operation mode is normal
DD1L116 = AMPP_FUNCTION(C1_CLR_SIGNAL, DD1_st_updateir);
--ME5_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] at LC_X30_Y28_N2
--operation mode is normal
ME5_Q[1] = AMPP_FUNCTION(!A1L6, ME7_Q[1], ME2_Q[0], ME3_Q[1], !C1_CLR_SIGNAL, C1L20);
--L1_E_ctrl_break is std_1s10:inst|cpu:the_cpu|E_ctrl_break at LC_X18_Y18_N2
--operation mode is normal
L1_E_ctrl_break = AMPP_FUNCTION(DE1__clk0, L1_D_iw[15], L1L220, E1_data_out, L1_W_stall);
--CD1L70 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|module_input6~22 at LC_X40_Y21_N7
--operation mode is normal
CD1L70 = AMPP_FUNCTION(L1_hbreak_enabled, L1_internal_d_write, P1L3);
--SC1L13 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|take_action_ocireg~11 at LC_X40_Y21_N5
--operation mode is normal
SC1L13 = AMPP_FUNCTION(CD1L70, SC1L2, P1L15, SC1L1);
--R1_timeout_occurred is std_1s10:inst|high_res_timer:the_high_res_timer|timeout_occurred at LC_X50_Y7_N4
--operation mode is normal
R1_timeout_occurred_lut_out = R1L234 & (!HE1L21 # !S1_cpu_data_master_requests_high_res_timer_s1 # !KB1L7);
R1_timeout_occurred = DFFEAS(R1_timeout_occurred_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--SC1_internal_oci_ienable1[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[4] at LC_X47_Y20_N4
--operation mode is normal
SC1_internal_oci_ienable1[4] = AMPP_FUNCTION(DE1__clk0, L1_M_st_data[4], E1_data_out, SC1L12);
--M1_registered_cpu_data_master_readdata[4] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[4] at LC_X47_Y18_N0
--operation mode is normal
M1_registered_cpu_data_master_readdata[4]_lut_out = M1L300 & M1L272 & (FB1_za_data[4] # !GB1L24);
M1_registered_cpu_data_master_readdata[4] = DFFEAS(M1_registered_cpu_data_master_readdata[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L55 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4872 at LC_X47_Y15_N9
--operation mode is normal
M1L55 = M1_registered_cpu_data_master_readdata[4] # !J1_cpu_data_master_requests_clock_0_in & (!EB1L2 # !U1L2);
--M1L56 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4873 at LC_X45_Y12_N8
--operation mode is normal
M1L56 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[4] & (BE1_q_a[4] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[4] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--HE1_readdata[4] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[4] at LC_X51_Y6_N7
--operation mode is normal
HE1_readdata[4]_lut_out = !L1_M_alu_result[4] & (L1_M_alu_result[2] & (HE1L55) # !L1_M_alu_result[2] & HE1L56);
HE1_readdata[4] = DFFEAS(HE1_readdata[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L57 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4874 at LC_X47_Y15_N8
--operation mode is normal
M1L57 = M1L56 & M1L55 & (HE1_readdata[4] # !QB1_cpu_data_master_granted_uart1_s1);
--M1L58 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4875 at LC_X47_Y12_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[4]_qfbk = M1_dbs_8_reg_segment_0[4];
M1L58 = Q1_cpu_data_master_requests_ext_flash_s1 & M1_dbs_8_reg_segment_0[4]_qfbk & (M1_registered_cpu_data_master_readdata[4] # !GB1L24) # !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[4] # !GB1L24);
--M1_dbs_8_reg_segment_0[4] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[4] at LC_X47_Y12_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[4] = DFFEAS(M1L58, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L308, Q1_internal_incoming_ext_ram_bus_data[4], , , VCC);
--R1_readdata[4] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[4] at LC_X47_Y9_N7
--operation mode is normal
R1_readdata[4]_lut_out = L1_M_alu_result[3] & (!L1_M_alu_result[4] & R1L192) # !L1_M_alu_result[3] & R1L191 & L1_M_alu_result[4];
R1_readdata[4] = DFFEAS(R1_readdata[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L59 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4876 at LC_X47_Y9_N5
--operation mode is normal
M1L59 = M1L62 & (R1_readdata[4] # !S1L2 # !LB1L2);
--KB1_readdata[4] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[4] at LC_X50_Y6_N1
--operation mode is normal
KB1_readdata[4]_lut_out = L1_M_alu_result[3] & KB1L193 & !L1_M_alu_result[4] # !L1_M_alu_result[3] & (L1_M_alu_result[4] & KB1L192);
KB1_readdata[4] = DFFEAS(KB1_readdata[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L60 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4877 at LC_X50_Y6_N0
--operation mode is normal
M1L60 = A1L139 & (KB1_readdata[4] # !LB1_cpu_data_master_requests_sys_clk_timer_s1) # !A1L139 & !W1L18 & (KB1_readdata[4] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--M1L61 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4878 at LC_X47_Y15_N6
--operation mode is normal
M1L61 = M1L60 & M1L80 & M1L57 & M1L59;
--N1L105 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~1862 at LC_X47_Y18_N9
--operation mode is normal
N1L105 = SC1_internal_oci_ienable1[4] & (P1L23 # !PD1_q_a[4]) # !SC1_internal_oci_ienable1[4] & !FC1L21 & (P1L23 # !PD1_q_a[4]);
--M1L166 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~4879 at LC_X45_Y18_N3
--operation mode is normal
M1L166 = Q1_internal_incoming_ext_ram_bus_data[20] & (BE1_q_a[20] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_internal_incoming_ext_ram_bus_data[20] & !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[20] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1_registered_cpu_data_master_readdata[20] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[20] at LC_X46_Y19_N8
--operation mode is normal
M1_registered_cpu_data_master_readdata[20]_lut_out = M1L286 & !J1_cpu_data_master_requests_clock_0_in & (T1L36 # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
M1_registered_cpu_data_master_readdata[20] = DFFEAS(M1_registered_cpu_data_master_readdata[20]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L167 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~4880 at LC_X46_Y18_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[4]_qfbk = M1_dbs_8_reg_segment_2[4];
M1L167 = Q1_cpu_data_master_requests_ext_flash_s1 & M1_dbs_8_reg_segment_2[4]_qfbk & (M1_registered_cpu_data_master_readdata[20] # !GB1L24) # !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[20] # !GB1L24);
--M1_dbs_8_reg_segment_2[4] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[4] at LC_X46_Y18_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[4] = DFFEAS(M1L167, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L310, Q1_internal_incoming_ext_ram_bus_data[4], , , VCC);
--M1L168 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~4881 at LC_X45_Y18_N9
--operation mode is normal
M1L168 = M1L167 & M1L166 & (Q1_internal_incoming_ext_ram_bus_data[20] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L169 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~4882 at LC_X45_Y18_N6
--operation mode is normal
M1L169 = M1L168 & (M1_registered_cpu_data_master_readdata[20] # !J1_cpu_data_master_requests_clock_0_in & !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
--M1L170 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[20]~4883 at LC_X45_Y18_N4
--operation mode is normal
M1L170 = !NB1_cpu_data_master_granted_sysid_control_slave & M1L145 & M1L169;
--FC1L24 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[20]~1204 at LC_X45_Y18_N7
--operation mode is normal
FC1L24 = AMPP_FUNCTION(PD1_q_a[20], L1_M_alu_result[10], P1L3, L1_ic_fill_line[5]);
--L1L938 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[2]~54 at LC_X34_Y20_N5
--operation mode is arithmetic
L1L938 = AMPP_FUNCTION(L1_F_pc[2], L1L937);
--L1_D_pc_plus_one[2] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[2] at LC_X34_Y20_N5
--operation mode is arithmetic
L1_D_pc_plus_one[2] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[2], E1_data_out, L1_W_stall, L1L937);
--L1L939 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[2]~55 at LC_X34_Y20_N5
--operation mode is arithmetic
L1L939 = AMPP_FUNCTION(L1_F_pc[2]);
--L1L940 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[2]~55COUT1_190 at LC_X34_Y20_N5
--operation mode is arithmetic
L1L940 = AMPP_FUNCTION(L1_F_pc[2]);
--L1L989 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[20]~56 at LC_X34_Y18_N3
--operation mode is arithmetic
L1L989 = AMPP_FUNCTION(L1_F_pc[20], L1L979, L1L987, L1L988);
--L1_D_pc_plus_one[20] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[20] at LC_X34_Y18_N3
--operation mode is arithmetic
L1_D_pc_plus_one[20] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[20], E1_data_out, L1_W_stall, L1L979, L1L987, L1L988);
--L1L990 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[20]~57 at LC_X34_Y18_N3
--operation mode is arithmetic
L1L990 = AMPP_FUNCTION(L1_F_pc[20], L1L987);
--L1L991 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[20]~57COUT1_220 at LC_X34_Y18_N3
--operation mode is arithmetic
L1L991 = AMPP_FUNCTION(L1_F_pc[20], L1L988);
--M1_registered_cpu_data_master_readdata[22] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[22] at LC_X44_Y18_N6
--operation mode is normal
M1_registered_cpu_data_master_readdata[22]_lut_out = !J1_cpu_data_master_requests_clock_0_in & M1L288 & (T1L40 # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
M1_registered_cpu_data_master_readdata[22] = DFFEAS(M1_registered_cpu_data_master_readdata[22]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L176 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~4884 at LC_X47_Y15_N4
--operation mode is normal
M1L176 = M1_registered_cpu_data_master_readdata[22] # !J1_cpu_data_master_requests_clock_0_in & (!EB1L2 # !U1L2);
--M1L177 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~4885 at LC_X46_Y17_N6
--operation mode is normal
M1L177 = AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & BE1_q_a[22] & (Q1_internal_incoming_ext_ram_bus_data[22] # !Q1_cpu_data_master_requests_lan91c111_s1) # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[22] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1L178 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~4886 at LC_X46_Y18_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[6]_qfbk = M1_dbs_8_reg_segment_2[6];
M1L178 = M1_registered_cpu_data_master_readdata[22] & (M1_dbs_8_reg_segment_2[6]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[22] & !GB1L24 & (M1_dbs_8_reg_segment_2[6]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1_dbs_8_reg_segment_2[6] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[6] at LC_X46_Y18_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[6] = DFFEAS(M1L178, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L310, Q1_internal_incoming_ext_ram_bus_data[6], , , VCC);
--M1L179 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~4887 at LC_X46_Y17_N7
--operation mode is normal
M1L179 = M1L180 & M1L177 & M1L176 & M1L145;
--FC1L26 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[22]~1205 at LC_X41_Y20_N0
--operation mode is normal
FC1L26 = AMPP_FUNCTION(L1_M_alu_result[10], PD1_q_a[22], L1_ic_fill_line[5], P1L3);
--M1_registered_cpu_data_master_readdata[15] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[15] at LC_X50_Y14_N8
--operation mode is normal
M1_registered_cpu_data_master_readdata[15]_lut_out = !M1L283 & (T1_rvalid # !U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[15] = DFFEAS(M1_registered_cpu_data_master_readdata[15]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L139 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~4888 at LC_X50_Y14_N0
--operation mode is normal
M1L139 = M1_registered_cpu_data_master_readdata[15] # !J1_cpu_data_master_requests_clock_0_in & (!EB1L2 # !U1L2);
--M1L140 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~4889 at LC_X45_Y13_N4
--operation mode is normal
M1L140 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[15] & (BE1_q_a[15] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[15] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--KB1_readdata[15] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[15] at LC_X46_Y5_N1
--operation mode is normal
KB1_readdata[15]_lut_out = L1_M_alu_result[4] & !L1_M_alu_result[3] & (KB1L214) # !L1_M_alu_result[4] & L1_M_alu_result[3] & KB1L215;
KB1_readdata[15] = DFFEAS(KB1_readdata[15]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L141 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~4890 at LC_X45_Y13_N5
--operation mode is normal
M1L141 = M1L139 & M1L140 & (KB1_readdata[15] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--R1_readdata[15] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[15] at LC_X46_Y8_N9
--operation mode is normal
R1_readdata[15]_lut_out = L1_M_alu_result[3] & R1L214 & !L1_M_alu_result[4] # !L1_M_alu_result[3] & (L1_M_alu_result[4] & R1L213);
R1_readdata[15] = DFFEAS(R1_readdata[15]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L142 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~4891 at LC_X39_Y13_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[7]_qfbk = M1_dbs_8_reg_segment_1[7];
M1L142 = Q1_cpu_data_master_requests_ext_flash_s1 & (!M1_registered_cpu_data_master_readdata[15] & GB1L24 # !M1_dbs_8_reg_segment_1[7]_qfbk) # !Q1_cpu_data_master_requests_ext_flash_s1 & !M1_registered_cpu_data_master_readdata[15] & (GB1L24);
--M1_dbs_8_reg_segment_1[7] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[7] at LC_X39_Y13_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[7] = DFFEAS(M1L142, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L309, Q1_internal_incoming_ext_ram_bus_data[7], , , VCC);
--M1L143 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~4892 at LC_X39_Y13_N3
--operation mode is normal
M1L143 = !M1L142 & (Q1_internal_incoming_ext_ram_bus_data[15] # !Q1L97 # !Q1L95);
--M1L144 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[15]~4893 at LC_X45_Y13_N6
--operation mode is normal
M1L144 = M1L143 & M1L230 & M1L112 & M1L141;
--PD1_q_a[8] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[8] at M4K_X37_Y23
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 16, Port B Depth: 256, Port B Width: 16
--Port A Logical Depth: 256, Port A Logical Width: 32, Port B Logical Depth: 256, Port B Logical Width: 32
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
PD1_q_a[8] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[9] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[9] at M4K_X37_Y23
PD1_q_a[9] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[10] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[10] at M4K_X37_Y23
PD1_q_a[10] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[11] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[11] at M4K_X37_Y23
PD1_q_a[11] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[12] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[12] at M4K_X37_Y23
PD1_q_a[12] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[13] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[13] at M4K_X37_Y23
PD1_q_a[13] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[14] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[14] at M4K_X37_Y23
PD1_q_a[14] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[15] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[15] at M4K_X37_Y23
PD1_q_a[15] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[8] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[8] at M4K_X37_Y23
PD1_q_b[8] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[9] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[9] at M4K_X37_Y23
PD1_q_b[9] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[10] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[10] at M4K_X37_Y23
PD1_q_b[10] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[11] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[11] at M4K_X37_Y23
PD1_q_b[11] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[12] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[12] at M4K_X37_Y23
PD1_q_b[12] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[13] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[13] at M4K_X37_Y23
PD1_q_b[13] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[14] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[14] at M4K_X37_Y23
PD1_q_b[14] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[15] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[15] at M4K_X37_Y23
PD1_q_b[15] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[31] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[31] at M4K_X37_Y23
PD1_q_a[31] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[30] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[30] at M4K_X37_Y23
PD1_q_a[30] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[29] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[29] at M4K_X37_Y23
PD1_q_a[29] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[28] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[28] at M4K_X37_Y23
PD1_q_a[28] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[27] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[27] at M4K_X37_Y23
PD1_q_a[27] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[26] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[26] at M4K_X37_Y23
PD1_q_a[26] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[25] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[25] at M4K_X37_Y23
PD1_q_a[25] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_a[24] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_a[24] at M4K_X37_Y23
PD1_q_a[24] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[31] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[31] at M4K_X37_Y23
PD1_q_b[31] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[30] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[30] at M4K_X37_Y23
PD1_q_b[30] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[29] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[29] at M4K_X37_Y23
PD1_q_b[29] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[28] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[28] at M4K_X37_Y23
PD1_q_b[28] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[27] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[27] at M4K_X37_Y23
PD1_q_b[27] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[26] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[26] at M4K_X37_Y23
PD1_q_b[26] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[25] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[25] at M4K_X37_Y23
PD1_q_b[25] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--PD1_q_b[24] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|q_b[24] at M4K_X37_Y23
PD1_q_b[24] = AMPP_FUNCTION(CD1L71, CD1_MonWr, DE1__clk0, DE1__clk0, L1_M_st_data[8], L1_M_st_data[9], L1_M_st_data[10], L1_M_st_data[11], L1_M_st_data[12], L1_M_st_data[13], L1_M_st_data[14], L1_M_st_data[15], P1L15, P1L16, P1L17, P1L18, P1L19, P1L20, P1L21, P1L22, P1L32, CD1_internal_MonDReg[8], CD1_internal_MonDReg[9], CD1_internal_MonDReg[10], CD1_internal_MonDReg[11], CD1_internal_MonDReg[12], CD1_internal_MonDReg[13], CD1_internal_MonDReg[14], CD1_internal_MonDReg[15], CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[5], CD1_MonAReg[6], CD1_MonAReg[7], CD1_MonAReg[8], CD1_MonAReg[9], L1_M_st_data[24], L1_M_st_data[25], L1_M_st_data[26], L1_M_st_data[27], L1_M_st_data[28], L1_M_st_data[29], L1_M_st_data[30], L1_M_st_data[31], CD1_internal_MonDReg[24], CD1_internal_MonDReg[25], CD1_internal_MonDReg[26], CD1_internal_MonDReg[27], CD1_internal_MonDReg[28], CD1_internal_MonDReg[29], CD1_internal_MonDReg[30], CD1_internal_MonDReg[31], P1L34);
--FC1L18 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[15]~1206 at LC_X45_Y13_N1
--operation mode is normal
FC1L18 = AMPP_FUNCTION(PD1_q_a[15], P1L3, L1_ic_fill_line[5], L1_M_alu_result[10]);
--M1L221 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~4894 at LC_X44_Y19_N7
--operation mode is normal
M1L221 = BE1_q_a[31] & (Q1_internal_incoming_ext_ram_bus_data[31] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[31] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[31] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[31] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[31] at LC_X44_Y18_N1
--operation mode is normal
M1_registered_cpu_data_master_readdata[31]_lut_out = !J1_cpu_data_master_requests_clock_0_in & M1L297 & (!U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[31] = DFFEAS(M1_registered_cpu_data_master_readdata[31]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L222 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~4895 at LC_X46_Y18_N5
--operation mode is normal
M1L222 = M1_registered_cpu_data_master_readdata[31] & (Q1_internal_incoming_ext_ram_bus_data[7] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[31] & !GB1L24 & (Q1_internal_incoming_ext_ram_bus_data[7] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L223 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~4896 at LC_X44_Y19_N0
--operation mode is normal
M1L223 = M1L222 & M1L221 & (Q1_internal_incoming_ext_ram_bus_data[31] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L224 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~4897 at LC_X44_Y19_N8
--operation mode is normal
M1L224 = M1L223 & (M1_registered_cpu_data_master_readdata[31] # !J1_cpu_data_master_requests_clock_0_in & !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
--M1L225 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[31]~4898 at LC_X44_Y19_N9
--operation mode is normal
M1L225 = !NB1_cpu_data_master_granted_sysid_control_slave & M1L145 & M1L224;
--FC1L35 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[31]~1207 at LC_X44_Y19_N5
--operation mode is normal
FC1L35 = AMPP_FUNCTION(L1_M_alu_result[10], PD1_q_a[31], L1_ic_fill_line[5], P1L3);
--L1L986 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[19]~58 at LC_X34_Y18_N2
--operation mode is arithmetic
L1L986 = AMPP_FUNCTION(L1_F_pc[19], L1L979, L1L984, L1L985);
--L1_D_pc_plus_one[19] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[19] at LC_X34_Y18_N2
--operation mode is arithmetic
L1_D_pc_plus_one[19] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[19], E1_data_out, L1_W_stall, L1L979, L1L984, L1L985);
--L1L987 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[19]~59 at LC_X34_Y18_N2
--operation mode is arithmetic
L1L987 = AMPP_FUNCTION(L1_F_pc[19], L1L984);
--L1L988 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[19]~59COUT1_218 at LC_X34_Y18_N2
--operation mode is arithmetic
L1L988 = AMPP_FUNCTION(L1_F_pc[19], L1L985);
--M1L232 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~714 at LC_X46_Y20_N8
--operation mode is normal
M1L232 = !NB1_cpu_data_master_granted_sysid_control_slave # !L1_M_alu_result[2];
--M1L171 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~4899 at LC_X47_Y19_N6
--operation mode is normal
M1L171 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[21] & (BE1_q_a[21] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[21] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1_registered_cpu_data_master_readdata[21] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[21] at LC_X47_Y19_N0
--operation mode is normal
M1_registered_cpu_data_master_readdata[21]_lut_out = !J1_cpu_data_master_requests_clock_0_in & M1L287 & (T1L44 # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
M1_registered_cpu_data_master_readdata[21] = DFFEAS(M1_registered_cpu_data_master_readdata[21]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L172 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~4900 at LC_X46_Y18_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[5]_qfbk = M1_dbs_8_reg_segment_2[5];
M1L172 = M1_registered_cpu_data_master_readdata[21] & (M1_dbs_8_reg_segment_2[5]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[21] & !GB1L24 & (M1_dbs_8_reg_segment_2[5]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1_dbs_8_reg_segment_2[5] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[5] at LC_X46_Y18_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[5] = DFFEAS(M1L172, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L310, Q1_internal_incoming_ext_ram_bus_data[5], , , VCC);
--M1L173 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~4901 at LC_X47_Y19_N7
--operation mode is normal
M1L173 = M1L172 & M1L171 & (Q1_internal_incoming_ext_ram_bus_data[21] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L174 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~4902 at LC_X47_Y19_N2
--operation mode is normal
M1L174 = M1L173 & (M1_registered_cpu_data_master_readdata[21] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--FC1L25 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[21]~1208 at LC_X47_Y19_N9
--operation mode is normal
FC1L25 = AMPP_FUNCTION(PD1_q_a[21], P1L3, L1_M_alu_result[10], L1_ic_fill_line[5]);
--L1L994 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[22]~60 at LC_X34_Y18_N5
--operation mode is arithmetic
L1L994 = AMPP_FUNCTION(L1_F_pc[22], L1L993);
--L1_D_pc_plus_one[22] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[22] at LC_X34_Y18_N5
--operation mode is arithmetic
L1_D_pc_plus_one[22] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[22], E1_data_out, L1_W_stall, L1L993);
--L1L995 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[22]~61 at LC_X34_Y18_N5
--operation mode is arithmetic
L1L995 = AMPP_FUNCTION(L1_F_pc[22]);
--L1L996 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[22]~61COUT1_222 at LC_X34_Y18_N5
--operation mode is arithmetic
L1L996 = AMPP_FUNCTION(L1_F_pc[22]);
--KC1_q_b[22] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[22] at M4K_X15_Y16
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[22] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[22], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[20], L1_i_readdata_d1[18], L1_i_readdata_d1[17]);
--KC1_q_b[17] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[17] at M4K_X15_Y16
KC1_q_b[17] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[22], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[20], L1_i_readdata_d1[18], L1_i_readdata_d1[17]);
--KC1_q_b[18] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[18] at M4K_X15_Y16
KC1_q_b[18] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[22], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[20], L1_i_readdata_d1[18], L1_i_readdata_d1[17]);
--KC1_q_b[20] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[20] at M4K_X15_Y16
KC1_q_b[20] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[22], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[20], L1_i_readdata_d1[18], L1_i_readdata_d1[17]);
--KC1_q_b[23] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[23] at M4K_X15_Y19
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 32, Port B Logical Depth: 1024, Port B Logical Width: 32
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
KC1_q_b[23] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[23], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[24], L1_i_readdata_d1[26], L1_i_readdata_d1[19]);
--KC1_q_b[19] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[19] at M4K_X15_Y19
KC1_q_b[19] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[23], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[24], L1_i_readdata_d1[26], L1_i_readdata_d1[19]);
--KC1_q_b[26] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[26] at M4K_X15_Y19
KC1_q_b[26] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[23], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[24], L1_i_readdata_d1[26], L1_i_readdata_d1[19]);
--KC1_q_b[24] is std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|q_b[24] at M4K_X15_Y19
KC1_q_b[24] = AMPP_FUNCTION(GND, GND, DE1__clk0, DE1__clk0, L1_i_readdatavalid_d1, L1_W_stall, L1_i_readdata_d1[23], L1_ic_fill_dp_offset[0], L1_ic_fill_dp_offset[1], L1_ic_fill_dp_offset[2], L1_ic_fill_line[0], L1_ic_fill_line[1], L1_ic_fill_line[2], L1_ic_fill_line[3], L1_ic_fill_line[4], L1_ic_fill_line[5], L1_ic_fill_line[6], L1L851, L1L854, L1L857, L1L883, L1L886, L1L889, L1L892, L1L895, L1L898, L1L901, L1_i_readdata_d1[24], L1_i_readdata_d1[26], L1_i_readdata_d1[19]);
--M1L186 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~4903 at LC_X44_Y15_N5
--operation mode is normal
M1L186 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[24] & (BE1_q_a[24] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[24] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1_registered_cpu_data_master_readdata[24] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[24] at LC_X44_Y18_N3
--operation mode is normal
M1_registered_cpu_data_master_readdata[24]_lut_out = !J1_cpu_data_master_requests_clock_0_in & M1L290 & (!U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[24] = DFFEAS(M1_registered_cpu_data_master_readdata[24]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L187 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~4904 at LC_X46_Y15_N5
--operation mode is normal
M1L187 = Q1_internal_incoming_ext_ram_bus_data[0] & (M1_registered_cpu_data_master_readdata[24] # !GB1L24) # !Q1_internal_incoming_ext_ram_bus_data[0] & !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[24] # !GB1L24);
--M1L188 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~4905 at LC_X44_Y15_N4
--operation mode is normal
M1L188 = M1L187 & M1L186 & (Q1_internal_incoming_ext_ram_bus_data[24] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L189 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~4906 at LC_X44_Y15_N6
--operation mode is normal
M1L189 = M1L188 & (M1_registered_cpu_data_master_readdata[24] # !J1_cpu_data_master_requests_clock_0_in & !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
--M1L190 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[24]~4907 at LC_X44_Y15_N8
--operation mode is normal
M1L190 = !NB1_cpu_data_master_granted_sysid_control_slave & M1L145 & M1L189;
--FC1L28 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[24]~1209 at LC_X44_Y15_N7
--operation mode is normal
FC1L28 = AMPP_FUNCTION(L1_M_alu_result[10], P1L3, PD1_q_a[24], L1_ic_fill_line[5]);
--L1L980 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[17]~62 at LC_X34_Y18_N0
--operation mode is arithmetic
L1L980 = AMPP_FUNCTION(L1_F_pc[17], L1L979);
--L1_D_pc_plus_one[17] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[17] at LC_X34_Y18_N0
--operation mode is arithmetic
L1_D_pc_plus_one[17] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[17], E1_data_out, L1_W_stall, L1L979);
--L1L981 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[17]~63 at LC_X34_Y18_N0
--operation mode is arithmetic
L1L981 = AMPP_FUNCTION(L1_F_pc[17]);
--L1L982 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[17]~63COUT1_214 at LC_X34_Y18_N0
--operation mode is arithmetic
L1L982 = AMPP_FUNCTION(L1_F_pc[17]);
--L1L978 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[16]~64 at LC_X34_Y19_N9
--operation mode is arithmetic
L1L978 = AMPP_FUNCTION(L1_F_pc[16], L1L965, L1L976, L1L977);
--L1_D_pc_plus_one[16] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[16] at LC_X34_Y19_N9
--operation mode is arithmetic
L1_D_pc_plus_one[16] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[16], E1_data_out, L1_W_stall, L1L965, L1L976, L1L977);
--L1L979 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[16]~65 at LC_X34_Y19_N9
--operation mode is arithmetic
L1L979 = AMPP_FUNCTION(L1_F_pc[16], L1L965, L1L976, L1L977);
--L1L975 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[15]~66 at LC_X34_Y19_N8
--operation mode is arithmetic
L1L975 = AMPP_FUNCTION(L1_F_pc[15], L1L965, L1L973, L1L974);
--L1_D_pc_plus_one[15] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[15] at LC_X34_Y19_N8
--operation mode is arithmetic
L1_D_pc_plus_one[15] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[15], E1_data_out, L1_W_stall, L1L965, L1L973, L1L974);
--L1L976 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[15]~67 at LC_X34_Y19_N8
--operation mode is arithmetic
L1L976 = AMPP_FUNCTION(L1_F_pc[15], L1L973);
--L1L977 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[15]~67COUT1_212 at LC_X34_Y19_N8
--operation mode is arithmetic
L1L977 = AMPP_FUNCTION(L1_F_pc[15], L1L974);
--M1L151 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~4908 at LC_X46_Y16_N5
--operation mode is normal
M1L151 = AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & BE1_q_a[17] & (Q1_internal_incoming_ext_ram_bus_data[17] # !Q1_cpu_data_master_requests_lan91c111_s1) # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[17] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1_registered_cpu_data_master_readdata[17] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[17] at LC_X50_Y15_N9
--operation mode is normal
M1_registered_cpu_data_master_readdata[17]_lut_out = !J1_cpu_data_master_requests_clock_0_in & T1L53 & (FB1_za_data[17] # !GB1L24);
M1_registered_cpu_data_master_readdata[17] = DFFEAS(M1_registered_cpu_data_master_readdata[17]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L152 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~4909 at LC_X46_Y18_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[1]_qfbk = M1_dbs_8_reg_segment_2[1];
M1L152 = M1_registered_cpu_data_master_readdata[17] & (M1_dbs_8_reg_segment_2[1]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[17] & !GB1L24 & (M1_dbs_8_reg_segment_2[1]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1_dbs_8_reg_segment_2[1] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[1] at LC_X46_Y18_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[1] = DFFEAS(M1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L310, Q1_internal_incoming_ext_ram_bus_data[1], , , VCC);
--M1L153 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~4910 at LC_X46_Y16_N8
--operation mode is normal
M1L153 = M1L151 & M1L152 & (Q1_internal_incoming_ext_ram_bus_data[17] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L154 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~4911 at LC_X46_Y16_N6
--operation mode is normal
M1L154 = M1L153 & (M1_registered_cpu_data_master_readdata[17] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L155 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[17]~4912 at LC_X46_Y16_N9
--operation mode is normal
M1L155 = M1L145 & !NB1_cpu_data_master_granted_sysid_control_slave & M1L154;
--FC1L20 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[17]~1210 at LC_X46_Y16_N7
--operation mode is normal
FC1L20 = AMPP_FUNCTION(L1_M_alu_result[10], P1L3, PD1_q_a[17], L1_ic_fill_line[5]);
--L1L972 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[14]~68 at LC_X34_Y19_N7
--operation mode is arithmetic
L1L972 = AMPP_FUNCTION(L1_F_pc[14], L1L965, L1L970, L1L971);
--L1_D_pc_plus_one[14] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[14] at LC_X34_Y19_N7
--operation mode is arithmetic
L1_D_pc_plus_one[14] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[14], E1_data_out, L1_W_stall, L1L965, L1L970, L1L971);
--L1L973 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[14]~69 at LC_X34_Y19_N7
--operation mode is arithmetic
L1L973 = AMPP_FUNCTION(L1_F_pc[14], L1L970);
--L1L974 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[14]~69COUT1_210 at LC_X34_Y19_N7
--operation mode is arithmetic
L1L974 = AMPP_FUNCTION(L1_F_pc[14], L1L971);
--M1L146 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~4913 at LC_X41_Y19_N9
--operation mode is normal
M1L146 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[16] & (BE1_q_a[16] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[16] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1_registered_cpu_data_master_readdata[16] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[16] at LC_X48_Y13_N2
--operation mode is normal
M1_registered_cpu_data_master_readdata[16]_lut_out = T1L54 & !J1_cpu_data_master_requests_clock_0_in & (FB1_za_data[16] # !GB1L24);
M1_registered_cpu_data_master_readdata[16] = DFFEAS(M1_registered_cpu_data_master_readdata[16]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L147 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~4914 at LC_X46_Y18_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[0]_qfbk = M1_dbs_8_reg_segment_2[0];
M1L147 = M1_registered_cpu_data_master_readdata[16] & (M1_dbs_8_reg_segment_2[0]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[16] & !GB1L24 & (M1_dbs_8_reg_segment_2[0]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1_dbs_8_reg_segment_2[0] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_2[0] at LC_X46_Y18_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_2[0] = DFFEAS(M1L147, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L310, Q1_internal_incoming_ext_ram_bus_data[0], , , VCC);
--M1L148 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~4915 at LC_X41_Y19_N6
--operation mode is normal
M1L148 = M1L147 & M1L146 & (Q1_internal_incoming_ext_ram_bus_data[16] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L149 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~4916 at LC_X48_Y13_N0
--operation mode is normal
M1L149 = M1L148 & (M1_registered_cpu_data_master_readdata[16] # !J1_cpu_data_master_requests_clock_0_in & !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
--FC1L19 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[16]~1211 at LC_X41_Y19_N4
--operation mode is normal
FC1L19 = AMPP_FUNCTION(P1L3, L1_M_alu_result[10], PD1_q_a[16], L1_ic_fill_line[5]);
--L1L992 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[21]~70 at LC_X34_Y18_N4
--operation mode is arithmetic
L1L992 = AMPP_FUNCTION(L1_F_pc[21], L1L979, L1L990, L1L991);
--L1_D_pc_plus_one[21] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[21] at LC_X34_Y18_N4
--operation mode is arithmetic
L1_D_pc_plus_one[21] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[21], E1_data_out, L1_W_stall, L1L979, L1L990, L1L991);
--L1L993 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[21]~71 at LC_X34_Y18_N4
--operation mode is arithmetic
L1L993 = AMPP_FUNCTION(L1_F_pc[21], L1L979, L1L990, L1L991);
--L1L997 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[23]~72 at LC_X34_Y18_N6
--operation mode is normal
L1L997 = AMPP_FUNCTION(L1_F_pc[23], L1L993, L1L995, L1L996);
--L1_D_pc_plus_one[23] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[23] at LC_X34_Y18_N6
--operation mode is normal
L1_D_pc_plus_one[23] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[23], E1_data_out, L1_W_stall, L1L993, L1L995, L1L996);
--M1L191 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~4917 at LC_X44_Y17_N7
--operation mode is normal
M1L191 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[25] & (BE1_q_a[25] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[25] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1_registered_cpu_data_master_readdata[25] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[25] at LC_X44_Y17_N2
--operation mode is normal
M1_registered_cpu_data_master_readdata[25]_lut_out = !J1_cpu_data_master_requests_clock_0_in & M1L291 & (!EB1L2 # !U1L2);
M1_registered_cpu_data_master_readdata[25] = DFFEAS(M1_registered_cpu_data_master_readdata[25]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L192 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~4918 at LC_X44_Y17_N1
--operation mode is normal
M1L192 = GB1L24 & M1_registered_cpu_data_master_readdata[25] & (Q1_internal_incoming_ext_ram_bus_data[1] # !Q1_cpu_data_master_requests_ext_flash_s1) # !GB1L24 & (Q1_internal_incoming_ext_ram_bus_data[1] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L193 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~4919 at LC_X44_Y17_N3
--operation mode is normal
M1L193 = M1L192 & M1L191 & (Q1_internal_incoming_ext_ram_bus_data[25] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L194 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~4920 at LC_X44_Y17_N4
--operation mode is normal
M1L194 = M1L193 & (M1_registered_cpu_data_master_readdata[25] # !J1_cpu_data_master_requests_clock_0_in & !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
--M1L195 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[25]~4921 at LC_X44_Y17_N6
--operation mode is normal
M1L195 = M1L145 & (!NB1_cpu_data_master_granted_sysid_control_slave & M1L194);
--FC1L29 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[25]~1212 at LC_X44_Y12_N8
--operation mode is normal
FC1L29 = AMPP_FUNCTION(P1L3, L1_M_alu_result[10], PD1_q_a[25], L1_ic_fill_line[5]);
--L1L983 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[18]~74 at LC_X34_Y18_N1
--operation mode is arithmetic
L1L983 = AMPP_FUNCTION(L1_F_pc[18], L1L979, L1L981, L1L982);
--L1_D_pc_plus_one[18] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[18] at LC_X34_Y18_N1
--operation mode is arithmetic
L1_D_pc_plus_one[18] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[18], E1_data_out, L1_W_stall, L1L979, L1L981, L1L982);
--L1L984 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[18]~75 at LC_X34_Y18_N1
--operation mode is arithmetic
L1L984 = AMPP_FUNCTION(L1_F_pc[18], L1L981);
--L1L985 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[18]~75COUT1_216 at LC_X34_Y18_N1
--operation mode is arithmetic
L1L985 = AMPP_FUNCTION(L1_F_pc[18], L1L982);
--L1L969 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[13]~76 at LC_X34_Y19_N6
--operation mode is arithmetic
L1L969 = AMPP_FUNCTION(L1_F_pc[13], L1L965, L1L967, L1L968);
--L1_D_pc_plus_one[13] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[13] at LC_X34_Y19_N6
--operation mode is arithmetic
L1_D_pc_plus_one[13] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[13], E1_data_out, L1_W_stall, L1L965, L1L967, L1L968);
--L1L970 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[13]~77 at LC_X34_Y19_N6
--operation mode is arithmetic
L1L970 = AMPP_FUNCTION(L1_F_pc[13], L1L967);
--L1L971 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[13]~77COUT1_208 at LC_X34_Y19_N6
--operation mode is arithmetic
L1L971 = AMPP_FUNCTION(L1_F_pc[13], L1L968);
--L1L966 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[12]~78 at LC_X34_Y19_N5
--operation mode is arithmetic
L1L966 = AMPP_FUNCTION(L1_F_pc[12], L1L965);
--L1_D_pc_plus_one[12] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[12] at LC_X34_Y19_N5
--operation mode is arithmetic
L1_D_pc_plus_one[12] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[12], E1_data_out, L1_W_stall, L1L965);
--L1L967 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[12]~79 at LC_X34_Y19_N5
--operation mode is arithmetic
L1L967 = AMPP_FUNCTION(L1_F_pc[12]);
--L1L968 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[12]~79COUT1_206 at LC_X34_Y19_N5
--operation mode is arithmetic
L1L968 = AMPP_FUNCTION(L1_F_pc[12]);
--M1_registered_cpu_data_master_readdata[14] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[14] at LC_X50_Y14_N1
--operation mode is normal
M1_registered_cpu_data_master_readdata[14]_lut_out = !M1L282 & (T1_woverflow # !U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[14] = DFFEAS(M1_registered_cpu_data_master_readdata[14]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L132 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~4922 at LC_X50_Y14_N7
--operation mode is normal
M1L132 = M1_registered_cpu_data_master_readdata[14] # !J1_cpu_data_master_requests_clock_0_in & (!EB1L2 # !U1L2);
--M1L133 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~4923 at LC_X44_Y12_N5
--operation mode is normal
M1L133 = AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & BE1_q_a[14] & (Q1_internal_incoming_ext_ram_bus_data[14] # !Q1_cpu_data_master_requests_lan91c111_s1) # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[14] # !Q1_cpu_data_master_requests_lan91c111_s1);
--KB1_readdata[14] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[14] at LC_X46_Y5_N6
--operation mode is normal
KB1_readdata[14]_lut_out = L1_M_alu_result[4] & !L1_M_alu_result[3] & (KB1L212) # !L1_M_alu_result[4] & L1_M_alu_result[3] & KB1L213;
KB1_readdata[14] = DFFEAS(KB1_readdata[14]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L134 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~4924 at LC_X44_Y12_N6
--operation mode is normal
M1L134 = M1L132 & M1L133 & (KB1_readdata[14] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--M1L135 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~4925 at LC_X47_Y14_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[6]_qfbk = M1_dbs_8_reg_segment_1[6];
M1L135 = M1_registered_cpu_data_master_readdata[14] & (M1_dbs_8_reg_segment_1[6]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[14] & !GB1L24 & (M1_dbs_8_reg_segment_1[6]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1_dbs_8_reg_segment_1[6] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[6] at LC_X47_Y14_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[6] = DFFEAS(M1L135, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L309, Q1_internal_incoming_ext_ram_bus_data[6], , , VCC);
--R1_readdata[14] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[14] at LC_X47_Y10_N9
--operation mode is normal
R1_readdata[14]_lut_out = L1_M_alu_result[4] & R1L211 & !L1_M_alu_result[3] # !L1_M_alu_result[4] & (L1_M_alu_result[3] & R1L212);
R1_readdata[14] = DFFEAS(R1_readdata[14]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L136 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~4926 at LC_X47_Y10_N5
--operation mode is normal
M1L136 = M1L138 & M1L232 & (R1_readdata[14] # !S1_cpu_data_master_requests_high_res_timer_s1);
--M1L137 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~4927 at LC_X44_Y12_N0
--operation mode is normal
M1L137 = M1L134 & M1L112 & M1L136;
--FC1L17 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[14]~1213 at LC_X44_Y12_N3
--operation mode is normal
FC1L17 = AMPP_FUNCTION(P1L3, L1_M_alu_result[10], PD1_q_a[14], L1_ic_fill_line[5]);
--M1_registered_cpu_data_master_readdata[30] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[30] at LC_X47_Y13_N0
--operation mode is normal
M1_registered_cpu_data_master_readdata[30]_lut_out = !J1_cpu_data_master_requests_clock_0_in & M1L296 & (!EB1L2 # !U1L2);
M1_registered_cpu_data_master_readdata[30] = DFFEAS(M1_registered_cpu_data_master_readdata[30]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L216 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~4928 at LC_X47_Y13_N4
--operation mode is normal
M1L216 = M1_registered_cpu_data_master_readdata[30] # !J1_cpu_data_master_requests_clock_0_in & (!EB1L2 # !U1L2);
--M1L217 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~4929 at LC_X47_Y13_N6
--operation mode is normal
M1L217 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[30] & (BE1_q_a[30] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[30] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1L218 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~4930 at LC_X47_Y14_N2
--operation mode is normal
M1L218 = Q1_internal_incoming_ext_ram_bus_data[6] & (M1_registered_cpu_data_master_readdata[30] # !GB1L24) # !Q1_internal_incoming_ext_ram_bus_data[6] & !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[30] # !GB1L24);
--M1L219 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~4931 at LC_X47_Y13_N5
--operation mode is normal
M1L219 = M1L220 & M1L217 & M1L145 & M1L216;
--FC1L34 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[30]~1214 at LC_X47_Y16_N1
--operation mode is normal
FC1L34 = AMPP_FUNCTION(PD1_q_a[30], L1_ic_fill_line[5], L1_M_alu_result[10], P1L3);
--L1L964 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[11]~80 at LC_X34_Y19_N4
--operation mode is arithmetic
L1L964 = AMPP_FUNCTION(L1_F_pc[11], L1L951, L1L962, L1L963);
--L1_D_pc_plus_one[11] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[11] at LC_X34_Y19_N4
--operation mode is arithmetic
L1_D_pc_plus_one[11] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[11], E1_data_out, L1_W_stall, L1L951, L1L962, L1L963);
--L1L965 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[11]~81 at LC_X34_Y19_N4
--operation mode is arithmetic
L1L965 = AMPP_FUNCTION(L1_F_pc[11], L1L951, L1L962, L1L963);
--M1_registered_cpu_data_master_readdata[13] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[13] at LC_X48_Y17_N4
--operation mode is normal
M1_registered_cpu_data_master_readdata[13]_lut_out = !M1L281 & (!U1L2 # !WD1_b_full # !EB1L2);
M1_registered_cpu_data_master_readdata[13] = DFFEAS(M1_registered_cpu_data_master_readdata[13]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L126 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~4932 at LC_X48_Y17_N6
--operation mode is normal
M1L126 = M1_registered_cpu_data_master_readdata[13] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--M1L127 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~4933 at LC_X47_Y17_N5
--operation mode is normal
M1L127 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[13] & (BE1_q_a[13] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[13] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--KB1_readdata[13] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[13] at LC_X46_Y5_N7
--operation mode is normal
KB1_readdata[13]_lut_out = L1_M_alu_result[3] & KB1L211 & (!L1_M_alu_result[4]) # !L1_M_alu_result[3] & (KB1L210 & L1_M_alu_result[4]);
KB1_readdata[13] = DFFEAS(KB1_readdata[13]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L128 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~4934 at LC_X47_Y17_N6
--operation mode is normal
M1L128 = M1L126 & M1L127 & (KB1_readdata[13] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--R1_readdata[13] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[13] at LC_X46_Y5_N5
--operation mode is normal
R1_readdata[13]_lut_out = L1_M_alu_result[4] & R1L209 & !L1_M_alu_result[3] # !L1_M_alu_result[4] & (L1_M_alu_result[3] & R1L210);
R1_readdata[13] = DFFEAS(R1_readdata[13]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L129 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~4935 at LC_X47_Y14_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[5]_qfbk = M1_dbs_8_reg_segment_1[5];
M1L129 = M1_registered_cpu_data_master_readdata[13] & (!M1_dbs_8_reg_segment_1[5]_qfbk & Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[13] & (GB1L24 # !M1_dbs_8_reg_segment_1[5]_qfbk & Q1_cpu_data_master_requests_ext_flash_s1);
--M1_dbs_8_reg_segment_1[5] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[5] at LC_X47_Y14_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[5] = DFFEAS(M1L129, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L309, Q1_internal_incoming_ext_ram_bus_data[5], , , VCC);
--M1L130 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~4936 at LC_X47_Y17_N8
--operation mode is normal
M1L130 = !M1L129 & (Q1_internal_incoming_ext_ram_bus_data[13] # !Q1L97 # !Q1L95);
--M1L131 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[13]~4937 at LC_X47_Y17_N7
--operation mode is normal
M1L131 = M1L130 & M1L128 & M1L112 & M1L229;
--FC1L16 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[13]~1215 at LC_X47_Y17_N9
--operation mode is normal
FC1L16 = AMPP_FUNCTION(L1_M_alu_result[10], PD1_q_a[13], L1_ic_fill_line[5], P1L3);
--M1L211 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~4938 at LC_X44_Y14_N0
--operation mode is normal
M1L211 = Q1_internal_incoming_ext_ram_bus_data[29] & (BE1_q_a[29] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_internal_incoming_ext_ram_bus_data[29] & !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[29] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1_registered_cpu_data_master_readdata[29] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[29] at LC_X44_Y14_N2
--operation mode is normal
M1_registered_cpu_data_master_readdata[29]_lut_out = !J1_cpu_data_master_requests_clock_0_in & M1L295 & (!U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[29] = DFFEAS(M1_registered_cpu_data_master_readdata[29]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L212 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~4939 at LC_X44_Y14_N7
--operation mode is normal
M1L212 = M1_registered_cpu_data_master_readdata[29] & (Q1_internal_incoming_ext_ram_bus_data[5] # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[29] & !GB1L24 & (Q1_internal_incoming_ext_ram_bus_data[5] # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1L213 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~4940 at LC_X44_Y14_N9
--operation mode is normal
M1L213 = M1L211 & M1L212 & (Q1_internal_incoming_ext_ram_bus_data[29] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L214 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~4941 at LC_X44_Y14_N4
--operation mode is normal
M1L214 = M1L213 & (M1_registered_cpu_data_master_readdata[29] # !J1_cpu_data_master_requests_clock_0_in & !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
--FC1L33 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[29]~1216 at LC_X45_Y14_N4
--operation mode is normal
FC1L33 = AMPP_FUNCTION(L1_M_alu_result[10], PD1_q_a[29], L1_ic_fill_line[5], P1L3);
--L1L961 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[10]~82 at LC_X34_Y19_N3
--operation mode is arithmetic
L1L961 = AMPP_FUNCTION(L1_F_pc[10], L1L951, L1L959, L1L960);
--L1_D_pc_plus_one[10] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[10] at LC_X34_Y19_N3
--operation mode is arithmetic
L1_D_pc_plus_one[10] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[10], E1_data_out, L1_W_stall, L1L951, L1L959, L1L960);
--L1L962 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[10]~83 at LC_X34_Y19_N3
--operation mode is arithmetic
L1L962 = AMPP_FUNCTION(L1_F_pc[10], L1L959);
--L1L963 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[10]~83COUT1_204 at LC_X34_Y19_N3
--operation mode is arithmetic
L1L963 = AMPP_FUNCTION(L1_F_pc[10], L1L960);
--L1L119 is std_1s10:inst|cpu:the_cpu|Add1~279 at LC_X33_Y20_N3
--operation mode is arithmetic
L1L119 = AMPP_FUNCTION(L1_D_br_taken_waddr_partial[10]);
--L1L120 is std_1s10:inst|cpu:the_cpu|Add1~279COUT1_337 at LC_X33_Y20_N3
--operation mode is arithmetic
L1L120 = AMPP_FUNCTION(L1_D_br_taken_waddr_partial[10]);
--M1_registered_cpu_data_master_readdata[12] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[12] at LC_X50_Y14_N2
--operation mode is normal
M1_registered_cpu_data_master_readdata[12]_lut_out = !M1L280 & (WD2_b_non_empty # !EB1L2 # !U1L2);
M1_registered_cpu_data_master_readdata[12] = DFFEAS(M1_registered_cpu_data_master_readdata[12]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L119 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~4942 at LC_X50_Y14_N6
--operation mode is normal
M1L119 = M1_registered_cpu_data_master_readdata[12] # !J1_cpu_data_master_requests_clock_0_in & (!U1L2 # !EB1L2);
--M1L120 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~4943 at LC_X45_Y11_N6
--operation mode is normal
M1L120 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[12] & (BE1_q_a[12] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[12] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1L121 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~4944 at LC_X47_Y14_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[4]_qfbk = M1_dbs_8_reg_segment_1[4];
M1L121 = M1_registered_cpu_data_master_readdata[12] & (!M1_dbs_8_reg_segment_1[4]_qfbk & Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[12] & (GB1L24 # !M1_dbs_8_reg_segment_1[4]_qfbk & Q1_cpu_data_master_requests_ext_flash_s1);
--M1_dbs_8_reg_segment_1[4] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[4] at LC_X47_Y14_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[4] = DFFEAS(M1L121, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L309, Q1_internal_incoming_ext_ram_bus_data[4], , , VCC);
--M1L122 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~4945 at LC_X47_Y13_N2
--operation mode is normal
M1L122 = !M1L121 & (Q1_internal_incoming_ext_ram_bus_data[12] # !Q1L97 # !Q1L95);
--R1_readdata[12] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[12] at LC_X46_Y5_N2
--operation mode is normal
R1_readdata[12]_lut_out = L1_M_alu_result[4] & !L1_M_alu_result[3] & R1L207 # !L1_M_alu_result[4] & L1_M_alu_result[3] & (R1L208);
R1_readdata[12] = DFFEAS(R1_readdata[12]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L123 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~4946 at LC_X47_Y13_N1
--operation mode is normal
M1L123 = M1L122 & (R1_readdata[12] # !LB1L2 # !S1L2);
--KB1_readdata[12] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[12] at LC_X51_Y5_N1
--operation mode is normal
KB1_readdata[12]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & KB1L209 # !L1_M_alu_result[3] & L1_M_alu_result[4] & (KB1L208);
KB1_readdata[12] = DFFEAS(KB1_readdata[12]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L124 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~4947 at LC_X45_Y11_N2
--operation mode is normal
M1L124 = M1L120 & M1L123 & (KB1_readdata[12] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--M1L125 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[12]~4948 at LC_X45_Y11_N7
--operation mode is normal
M1L125 = !NB1_cpu_data_master_granted_sysid_control_slave & M1L119 & M1L112 & M1L124;
--FC1L15 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[12]~1217 at LC_X45_Y11_N5
--operation mode is normal
FC1L15 = AMPP_FUNCTION(P1L3, L1_M_alu_result[10], L1_ic_fill_line[5], PD1_q_a[12]);
--M1L206 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~4949 at LC_X44_Y20_N3
--operation mode is normal
M1L206 = Q1_internal_incoming_ext_ram_bus_data[28] & (BE1_q_a[28] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_internal_incoming_ext_ram_bus_data[28] & !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[28] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1_registered_cpu_data_master_readdata[28] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[28] at LC_X44_Y20_N1
--operation mode is normal
M1_registered_cpu_data_master_readdata[28]_lut_out = !J1_cpu_data_master_requests_clock_0_in & M1L294 & (!U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[28] = DFFEAS(M1_registered_cpu_data_master_readdata[28]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L207 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~4950 at LC_X44_Y20_N2
--operation mode is normal
M1L207 = Q1_cpu_data_master_requests_ext_flash_s1 & Q1_internal_incoming_ext_ram_bus_data[4] & (M1_registered_cpu_data_master_readdata[28] # !GB1L24) # !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[28] # !GB1L24);
--M1L208 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~4951 at LC_X44_Y20_N4
--operation mode is normal
M1L208 = M1L207 & M1L206 & (Q1_internal_incoming_ext_ram_bus_data[28] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L209 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~4952 at LC_X44_Y20_N9
--operation mode is normal
M1L209 = M1L208 & (M1_registered_cpu_data_master_readdata[28] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L210 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[28]~4953 at LC_X44_Y20_N7
--operation mode is normal
M1L210 = M1L209 & !NB1_cpu_data_master_granted_sysid_control_slave & M1L145;
--FC1L32 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[28]~1218 at LC_X35_Y15_N6
--operation mode is normal
FC1L32 = AMPP_FUNCTION(PD1_q_a[28], L1_M_alu_result[10], L1_ic_fill_line[5], P1L3);
--L1L958 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[9]~84 at LC_X34_Y19_N2
--operation mode is arithmetic
L1L958 = AMPP_FUNCTION(L1_F_pc[9], L1L951, L1L956, L1L957);
--L1_D_pc_plus_one[9] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[9] at LC_X34_Y19_N2
--operation mode is arithmetic
L1_D_pc_plus_one[9] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[9], E1_data_out, L1_W_stall, L1L951, L1L956, L1L957);
--L1L959 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[9]~85 at LC_X34_Y19_N2
--operation mode is arithmetic
L1L959 = AMPP_FUNCTION(L1_F_pc[9], L1L956);
--L1L960 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[9]~85COUT1_202 at LC_X34_Y19_N2
--operation mode is arithmetic
L1L960 = AMPP_FUNCTION(L1_F_pc[9], L1L957);
--M1_registered_cpu_data_master_readdata[11] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[11] at LC_X48_Y16_N2
--operation mode is normal
M1_registered_cpu_data_master_readdata[11]_lut_out = !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & M1L279 & (FB1_za_data[11] # !GB1L24);
M1_registered_cpu_data_master_readdata[11] = DFFEAS(M1_registered_cpu_data_master_readdata[11]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L113 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~4954 at LC_X48_Y16_N9
--operation mode is normal
M1L113 = M1_registered_cpu_data_master_readdata[11] # !J1_cpu_data_master_requests_clock_0_in & (!EB1L2 # !U1L2);
--M1L114 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~4955 at LC_X47_Y16_N9
--operation mode is normal
M1L114 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[11] & (BE1_q_a[11] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[11] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--KB1_readdata[11] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[11] at LC_X51_Y5_N9
--operation mode is normal
KB1_readdata[11]_lut_out = L1_M_alu_result[3] & KB1L207 & (!L1_M_alu_result[4]) # !L1_M_alu_result[3] & (KB1L206 & L1_M_alu_result[4]);
KB1_readdata[11] = DFFEAS(KB1_readdata[11]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L115 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~4956 at LC_X47_Y16_N2
--operation mode is normal
M1L115 = M1L114 & M1L113 & (KB1_readdata[11] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--R1_readdata[11] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[11] at LC_X46_Y5_N3
--operation mode is normal
R1_readdata[11]_lut_out = L1_M_alu_result[3] & R1L206 & (!L1_M_alu_result[4]) # !L1_M_alu_result[3] & (R1L205 & L1_M_alu_result[4]);
R1_readdata[11] = DFFEAS(R1_readdata[11]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L116 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~4957 at LC_X41_Y16_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[3]_qfbk = M1_dbs_8_reg_segment_1[3];
M1L116 = Q1_cpu_data_master_requests_ext_flash_s1 & (GB1L24 & !M1_registered_cpu_data_master_readdata[11] # !M1_dbs_8_reg_segment_1[3]_qfbk) # !Q1_cpu_data_master_requests_ext_flash_s1 & GB1L24 & (!M1_registered_cpu_data_master_readdata[11]);
--M1_dbs_8_reg_segment_1[3] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[3] at LC_X41_Y16_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[3] = DFFEAS(M1L116, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L309, Q1_internal_incoming_ext_ram_bus_data[3], , , VCC);
--M1L117 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~4958 at LC_X47_Y16_N8
--operation mode is normal
M1L117 = !M1L116 & (Q1_internal_incoming_ext_ram_bus_data[11] # !Q1L97 # !Q1L95);
--M1L118 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[11]~4959 at LC_X47_Y16_N3
--operation mode is normal
M1L118 = M1L117 & M1L112 & M1L228 & M1L115;
--FC1L14 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[11]~1219 at LC_X47_Y16_N6
--operation mode is normal
FC1L14 = AMPP_FUNCTION(L1_M_alu_result[10], PD1_q_a[11], L1_ic_fill_line[5], P1L3);
--M1L201 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~4960 at LC_X41_Y14_N3
--operation mode is normal
M1L201 = Q1_internal_incoming_ext_ram_bus_data[27] & (BE1_q_a[27] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_internal_incoming_ext_ram_bus_data[27] & !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[27] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1_registered_cpu_data_master_readdata[27] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[27] at LC_X46_Y14_N2
--operation mode is normal
M1_registered_cpu_data_master_readdata[27]_lut_out = !J1_cpu_data_master_requests_clock_0_in & M1L293 & (!U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[27] = DFFEAS(M1_registered_cpu_data_master_readdata[27]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L202 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~4961 at LC_X46_Y14_N9
--operation mode is normal
M1L202 = Q1_cpu_data_master_requests_ext_flash_s1 & Q1_internal_incoming_ext_ram_bus_data[3] & (M1_registered_cpu_data_master_readdata[27] # !GB1L24) # !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[27] # !GB1L24);
--M1L203 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~4962 at LC_X41_Y14_N0
--operation mode is normal
M1L203 = M1L202 & M1L201 & (Q1_internal_incoming_ext_ram_bus_data[27] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L204 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~4963 at LC_X46_Y14_N8
--operation mode is normal
M1L204 = M1L203 & (M1_registered_cpu_data_master_readdata[27] # !J1_cpu_data_master_requests_clock_0_in & !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
--FC1L31 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[27]~1220 at LC_X41_Y14_N1
--operation mode is normal
FC1L31 = AMPP_FUNCTION(L1_M_alu_result[10], P1L3, PD1_q_a[27], L1_ic_fill_line[5]);
--L1L955 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[8]~86 at LC_X34_Y19_N1
--operation mode is arithmetic
L1L955 = AMPP_FUNCTION(L1_F_pc[8], L1L951, L1L953, L1L954);
--L1_D_pc_plus_one[8] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[8] at LC_X34_Y19_N1
--operation mode is arithmetic
L1_D_pc_plus_one[8] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[8], E1_data_out, L1_W_stall, L1L951, L1L953, L1L954);
--L1L956 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[8]~87 at LC_X34_Y19_N1
--operation mode is arithmetic
L1L956 = AMPP_FUNCTION(L1_F_pc[8], L1L953);
--L1L957 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[8]~87COUT1_200 at LC_X34_Y19_N1
--operation mode is arithmetic
L1L957 = AMPP_FUNCTION(L1_F_pc[8], L1L954);
--M1_registered_cpu_data_master_readdata[10] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[10] at LC_X48_Y16_N6
--operation mode is normal
M1_registered_cpu_data_master_readdata[10]_lut_out = !M1L278 & (T1_ac # !EB1L2 # !U1L2);
M1_registered_cpu_data_master_readdata[10] = DFFEAS(M1_registered_cpu_data_master_readdata[10]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L105 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~4964 at LC_X48_Y16_N5
--operation mode is normal
M1L105 = M1_registered_cpu_data_master_readdata[10] # !J1_cpu_data_master_requests_clock_0_in & (!EB1L2 # !U1L2);
--M1L106 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~4965 at LC_X44_Y11_N5
--operation mode is normal
M1L106 = AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & BE1_q_a[10] & (Q1_internal_incoming_ext_ram_bus_data[10] # !Q1_cpu_data_master_requests_lan91c111_s1) # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[10] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1L107 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~4966 at LC_X41_Y16_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[2]_qfbk = M1_dbs_8_reg_segment_1[2];
M1L107 = Q1_cpu_data_master_requests_ext_flash_s1 & (GB1L24 & !M1_registered_cpu_data_master_readdata[10] # !M1_dbs_8_reg_segment_1[2]_qfbk) # !Q1_cpu_data_master_requests_ext_flash_s1 & GB1L24 & (!M1_registered_cpu_data_master_readdata[10]);
--M1_dbs_8_reg_segment_1[2] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[2] at LC_X41_Y16_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[2] = DFFEAS(M1L107, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L309, Q1_internal_incoming_ext_ram_bus_data[2], , , VCC);
--M1L108 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~4967 at LC_X46_Y9_N6
--operation mode is normal
M1L108 = !M1L107 & (Q1_internal_incoming_ext_ram_bus_data[10] # !Q1L97 # !Q1L95);
--R1_readdata[10] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[10] at LC_X46_Y9_N9
--operation mode is normal
R1_readdata[10]_lut_out = L1_M_alu_result[3] & R1L204 & !L1_M_alu_result[4] # !L1_M_alu_result[3] & (L1_M_alu_result[4] & R1L203);
R1_readdata[10] = DFFEAS(R1_readdata[10]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L109 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~4968 at LC_X46_Y9_N2
--operation mode is normal
M1L109 = M1L108 & (R1_readdata[10] # !S1L2 # !LB1L2);
--KB1_readdata[10] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[10] at LC_X51_Y5_N3
--operation mode is normal
KB1_readdata[10]_lut_out = L1_M_alu_result[3] & KB1L205 & (!L1_M_alu_result[4]) # !L1_M_alu_result[3] & (KB1L204 & L1_M_alu_result[4]);
KB1_readdata[10] = DFFEAS(KB1_readdata[10]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L110 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~4969 at LC_X44_Y11_N6
--operation mode is normal
M1L110 = M1L109 & M1L106 & (KB1_readdata[10] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--M1L111 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~4970 at LC_X44_Y11_N7
--operation mode is normal
M1L111 = !NB1_cpu_data_master_granted_sysid_control_slave & M1L105 & M1L112 & M1L110;
--FC1L13 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[10]~1221 at LC_X44_Y11_N4
--operation mode is normal
FC1L13 = AMPP_FUNCTION(P1L3, L1_M_alu_result[10], PD1_q_a[10], L1_ic_fill_line[5]);
--M1L196 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~4971 at LC_X41_Y20_N4
--operation mode is normal
M1L196 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[26] & (BE1_q_a[26] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[26] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1_registered_cpu_data_master_readdata[26] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[26] at LC_X47_Y15_N2
--operation mode is normal
M1_registered_cpu_data_master_readdata[26]_lut_out = !J1_cpu_data_master_requests_clock_0_in & M1L292 & (!EB1L2 # !U1L2);
M1_registered_cpu_data_master_readdata[26] = DFFEAS(M1_registered_cpu_data_master_readdata[26]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L197 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~4972 at LC_X47_Y15_N3
--operation mode is normal
M1L197 = Q1_internal_incoming_ext_ram_bus_data[2] & (M1_registered_cpu_data_master_readdata[26] # !GB1L24) # !Q1_internal_incoming_ext_ram_bus_data[2] & !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[26] # !GB1L24);
--M1L198 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~4973 at LC_X41_Y20_N7
--operation mode is normal
M1L198 = M1L197 & M1L196 & (Q1_internal_incoming_ext_ram_bus_data[26] # !Q1_cpu_data_master_requests_ext_ram_s1);
--M1L199 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~4974 at LC_X47_Y15_N5
--operation mode is normal
M1L199 = M1L198 & (M1_registered_cpu_data_master_readdata[26] # !J1_cpu_data_master_requests_clock_0_in & !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
--M1L200 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[26]~4975 at LC_X46_Y20_N5
--operation mode is normal
M1L200 = M1L199 & M1L145 & (L1_M_alu_result[2] # !NB1_cpu_data_master_granted_sysid_control_slave);
--FC1L30 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[26]~1222 at LC_X41_Y20_N1
--operation mode is normal
FC1L30 = AMPP_FUNCTION(L1_M_alu_result[10], P1L3, L1_ic_fill_line[5], PD1_q_a[26]);
--L1L952 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[7]~88 at LC_X34_Y19_N0
--operation mode is arithmetic
L1L952 = AMPP_FUNCTION(L1_F_pc[7], L1L951);
--L1_D_pc_plus_one[7] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[7] at LC_X34_Y19_N0
--operation mode is arithmetic
L1_D_pc_plus_one[7] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[7], E1_data_out, L1_W_stall, L1L951);
--L1L953 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[7]~89 at LC_X34_Y19_N0
--operation mode is arithmetic
L1L953 = AMPP_FUNCTION(L1_F_pc[7]);
--L1L954 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[7]~89COUT1_198 at LC_X34_Y19_N0
--operation mode is arithmetic
L1L954 = AMPP_FUNCTION(L1_F_pc[7]);
--M1_registered_cpu_data_master_readdata[9] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[9] at LC_X47_Y20_N2
--operation mode is normal
M1_registered_cpu_data_master_readdata[9]_lut_out = !M1L277 & (T1L64 # !EB1L2 # !U1L2);
M1_registered_cpu_data_master_readdata[9] = DFFEAS(M1_registered_cpu_data_master_readdata[9]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L98 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~4976 at LC_X47_Y20_N5
--operation mode is normal
M1L98 = M1_registered_cpu_data_master_readdata[9] # !J1_cpu_data_master_requests_clock_0_in & (!EB1L2 # !U1L2);
--M1L99 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~4977 at LC_X45_Y14_N2
--operation mode is normal
M1L99 = Q1_internal_incoming_ext_ram_bus_data[9] & (BE1_q_a[9] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_internal_incoming_ext_ram_bus_data[9] & !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[9] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1L100 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~4978 at LC_X45_Y14_N6
--operation mode is normal
M1L100 = M1L99 & (M1L97 & M1L98);
--R1_readdata[9] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[9] at LC_X47_Y10_N4
--operation mode is normal
R1_readdata[9]_lut_out = L1_M_alu_result[4] & R1L201 & !L1_M_alu_result[3] # !L1_M_alu_result[4] & (L1_M_alu_result[3] & R1L202);
R1_readdata[9] = DFFEAS(R1_readdata[9]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L101 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~4979 at LC_X47_Y14_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[1]_qfbk = M1_dbs_8_reg_segment_1[1];
M1L101 = M1_registered_cpu_data_master_readdata[9] & (M1_dbs_8_reg_segment_1[1]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[9] & !GB1L24 & (M1_dbs_8_reg_segment_1[1]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1_dbs_8_reg_segment_1[1] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[1] at LC_X47_Y14_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[1] = DFFEAS(M1L101, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L309, Q1_internal_incoming_ext_ram_bus_data[1], , , VCC);
--HE1_readdata[9] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[9] at LC_X47_Y10_N0
--operation mode is normal
HE1_readdata[9]_lut_out = !L1_M_alu_result[4] & HE1_control_reg[9] & L1_M_alu_result[3] & L1_M_alu_result[2];
HE1_readdata[9] = DFFEAS(HE1_readdata[9]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L102 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~4980 at LC_X47_Y10_N1
--operation mode is normal
M1L102 = M1L104 & M1L227 & (HE1_readdata[9] # !QB1_cpu_data_master_granted_uart1_s1);
--KB1_readdata[9] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[9] at LC_X51_Y6_N4
--operation mode is normal
KB1_readdata[9]_lut_out = L1_M_alu_result[3] & (KB1L203 & !L1_M_alu_result[4]) # !L1_M_alu_result[3] & KB1L202 & (L1_M_alu_result[4]);
KB1_readdata[9] = DFFEAS(KB1_readdata[9]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L103 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~4981 at LC_X45_Y14_N9
--operation mode is normal
M1L103 = M1L102 & M1L100 & (KB1_readdata[9] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--FC1L12 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[9]~1223 at LC_X45_Y14_N3
--operation mode is normal
FC1L12 = AMPP_FUNCTION(L1_M_alu_result[10], P1L3, L1_ic_fill_line[5], PD1_q_a[9]);
--L1L950 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[6]~90 at LC_X34_Y20_N9
--operation mode is arithmetic
L1L950 = AMPP_FUNCTION(L1_F_pc[6], L1L937, L1L948, L1L949);
--L1_D_pc_plus_one[6] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[6] at LC_X34_Y20_N9
--operation mode is arithmetic
L1_D_pc_plus_one[6] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[6], E1_data_out, L1_W_stall, L1L937, L1L948, L1L949);
--L1L951 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[6]~91 at LC_X34_Y20_N9
--operation mode is arithmetic
L1L951 = AMPP_FUNCTION(L1_F_pc[6], L1L937, L1L948, L1L949);
--M1_registered_cpu_data_master_readdata[8] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[8] at LC_X47_Y20_N8
--operation mode is normal
M1_registered_cpu_data_master_readdata[8]_lut_out = !M1L276 & (M1L304 # !EB1L2 # !U1L2);
M1_registered_cpu_data_master_readdata[8] = DFFEAS(M1_registered_cpu_data_master_readdata[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L89 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~4982 at LC_X47_Y20_N0
--operation mode is normal
M1L89 = M1_registered_cpu_data_master_readdata[8] # !J1_cpu_data_master_requests_clock_0_in & (!EB1L2 # !U1L2);
--M1L90 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~4983 at LC_X46_Y13_N7
--operation mode is normal
M1L90 = AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & BE1_q_a[8] & (Q1_internal_incoming_ext_ram_bus_data[8] # !Q1_cpu_data_master_requests_lan91c111_s1) # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[8] # !Q1_cpu_data_master_requests_lan91c111_s1);
--R1_readdata[8] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[8] at LC_X50_Y10_N8
--operation mode is normal
R1_readdata[8]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (R1L200) # !L1_M_alu_result[3] & L1_M_alu_result[4] & R1L199;
R1_readdata[8] = DFFEAS(R1_readdata[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L91 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~4984 at LC_X46_Y13_N8
--operation mode is normal
M1L91 = M1L89 & M1L90 & (R1_readdata[8] # !S1_cpu_data_master_requests_high_res_timer_s1);
--M1L92 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~4985 at LC_X47_Y14_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[0]_qfbk = M1_dbs_8_reg_segment_1[0];
M1L92 = M1_registered_cpu_data_master_readdata[8] & (M1_dbs_8_reg_segment_1[0]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[8] & !GB1L24 & (M1_dbs_8_reg_segment_1[0]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1_dbs_8_reg_segment_1[0] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_1[0] at LC_X47_Y14_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_1[0] = DFFEAS(M1L92, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L309, Q1_internal_incoming_ext_ram_bus_data[0], , , VCC);
--KB1_readdata[8] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[8] at LC_X48_Y11_N9
--operation mode is normal
KB1_readdata[8]_lut_out = L1_M_alu_result[3] & KB1L201 & !L1_M_alu_result[4] # !L1_M_alu_result[3] & (L1_M_alu_result[4] & KB1L200);
KB1_readdata[8] = DFFEAS(KB1_readdata[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L93 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~4986 at LC_X48_Y11_N5
--operation mode is normal
M1L93 = M1L95 & (KB1_readdata[8] # !LB1L3 # !LB1L2);
--HE1_readdata[8] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[8] at LC_X48_Y11_N8
--operation mode is normal
HE1_readdata[8]_lut_out = NB1L3 & (L1_M_alu_result[2] & HE1_control_reg[8] # !L1_M_alu_result[2] & (HE1L1));
HE1_readdata[8] = DFFEAS(HE1_readdata[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L94 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~4987 at LC_X46_Y13_N4
--operation mode is normal
M1L94 = M1L91 & M1L96 & M1L80 & M1L93;
--FC1L11 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[8]~1224 at LC_X46_Y13_N1
--operation mode is normal
FC1L11 = AMPP_FUNCTION(PD1_q_a[8], L1_M_alu_result[10], L1_ic_fill_line[5], P1L3);
--F1_edge_capture[3] is std_1s10:inst|button_pio:the_button_pio|edge_capture[3] at LC_X50_Y12_N6
--operation mode is normal
F1_edge_capture[3]_lut_out = !F1L17 & (F1_edge_capture[3] # F1_d1_data_in[3] $ F1_d2_data_in[3]);
F1_edge_capture[3] = DFFEAS(F1_edge_capture[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--F1_edge_capture[1] is std_1s10:inst|button_pio:the_button_pio|edge_capture[1] at LC_X50_Y13_N7
--operation mode is normal
F1_edge_capture[1]_lut_out = !F1L17 & (F1_edge_capture[1] # F1_d1_data_in[1] $ F1_d2_data_in[1]);
F1_edge_capture[1] = DFFEAS(F1_edge_capture[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--L1L1198 is std_1s10:inst|cpu:the_cpu|M_ipending_reg_nxt[5]~169 at LC_X50_Y12_N3
--operation mode is normal
L1L1198 = AMPP_FUNCTION(F1_irq_mask[3], F1_edge_capture[1], F1_irq_mask[1], F1_edge_capture[3]);
--F1_edge_capture[2] is std_1s10:inst|button_pio:the_button_pio|edge_capture[2] at LC_X50_Y13_N5
--operation mode is normal
F1_edge_capture[2]_lut_out = !F1L17 & (F1_edge_capture[2] # F1_d2_data_in[2] $ F1_d1_data_in[2]);
F1_edge_capture[2] = DFFEAS(F1_edge_capture[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--F1_edge_capture[0] is std_1s10:inst|button_pio:the_button_pio|edge_capture[0] at LC_X50_Y13_N9
--operation mode is normal
F1_edge_capture[0]_lut_out = !F1L17 & (F1_edge_capture[0] # F1_d2_data_in[0] $ F1_d1_data_in[0]);
F1_edge_capture[0] = DFFEAS(F1_edge_capture[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--L1L1199 is std_1s10:inst|cpu:the_cpu|M_ipending_reg_nxt[5]~170 at LC_X48_Y13_N8
--operation mode is normal
L1L1199 = AMPP_FUNCTION(F1_edge_capture[2], F1_edge_capture[0], F1_irq_mask[0], F1_irq_mask[2]);
--SC1_internal_oci_ienable1[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[5] at LC_X40_Y21_N0
--operation mode is normal
SC1_internal_oci_ienable1[5] = AMPP_FUNCTION(DE1__clk0, L1_M_st_data[5], E1_data_out, SC1L12);
--M1L64 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4988 at LC_X48_Y14_N0
--operation mode is normal
M1L64 = L1_M_alu_result[4] & A1L138 & L1_M_alu_result[7] # !L1_M_alu_result[4] & (!L1_M_alu_result[7]) # !EB1L3;
--M1_registered_cpu_data_master_readdata[5] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[5] at LC_X48_Y15_N6
--operation mode is normal
M1_registered_cpu_data_master_readdata[5]_lut_out = M1L273 & M1L301 & (FB1_za_data[5] # !GB1L24);
M1_registered_cpu_data_master_readdata[5] = DFFEAS(M1_registered_cpu_data_master_readdata[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L65 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4989 at LC_X48_Y12_N7
--operation mode is normal
M1L65 = M1L64 & (M1_registered_cpu_data_master_readdata[5] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--R1_readdata[5] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[5] at LC_X50_Y10_N2
--operation mode is normal
R1_readdata[5]_lut_out = L1_M_alu_result[4] & (!L1_M_alu_result[3] & R1L193) # !L1_M_alu_result[4] & R1L194 & L1_M_alu_result[3];
R1_readdata[5] = DFFEAS(R1_readdata[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L66 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4990 at LC_X48_Y12_N4
--operation mode is normal
M1L66 = !NB1_cpu_data_master_granted_sysid_control_slave & (R1_readdata[5] # !S1L2 # !LB1L2);
--M1L67 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4991 at LC_X48_Y12_N2
--operation mode is normal
M1L67 = BE1_q_a[5] & (Q1_internal_incoming_ext_ram_bus_data[5] # !Q1_cpu_data_master_requests_lan91c111_s1) # !BE1_q_a[5] & !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[5] # !Q1_cpu_data_master_requests_lan91c111_s1);
--HE1_readdata[5] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[5] at LC_X51_Y6_N1
--operation mode is normal
HE1_readdata[5]_lut_out = !L1_M_alu_result[4] & (L1_M_alu_result[2] & HE1L57 # !L1_M_alu_result[2] & (HE1L58));
HE1_readdata[5] = DFFEAS(HE1_readdata[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L68 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4992 at LC_X48_Y12_N0
--operation mode is normal
M1L68 = M1L67 & M1L66 & (HE1_readdata[5] # !QB1_cpu_data_master_granted_uart1_s1);
--KB1_readdata[5] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[5] at LC_X51_Y5_N5
--operation mode is normal
KB1_readdata[5]_lut_out = L1_M_alu_result[4] & KB1L194 & (!L1_M_alu_result[3]) # !L1_M_alu_result[4] & (KB1L195 & L1_M_alu_result[3]);
KB1_readdata[5] = DFFEAS(KB1_readdata[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L69 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4993 at LC_X47_Y12_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[5]_qfbk = M1_dbs_8_reg_segment_0[5];
M1L69 = Q1_cpu_data_master_requests_ext_flash_s1 & M1_dbs_8_reg_segment_0[5]_qfbk & (M1_registered_cpu_data_master_readdata[5] # !GB1L24) # !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[5] # !GB1L24);
--M1_dbs_8_reg_segment_0[5] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[5] at LC_X47_Y12_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[5] = DFFEAS(M1L69, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L308, Q1_internal_incoming_ext_ram_bus_data[5], , , VCC);
--M1L70 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4994 at LC_X48_Y12_N5
--operation mode is normal
M1L70 = M1L65 & M1L68 & M1L231 & M1L71;
--N1L106 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata~1863 at LC_X40_Y21_N1
--operation mode is normal
N1L106 = P1L23 & (SC1_internal_oci_ienable1[5] # !FC1L21) # !P1L23 & !PD1_q_a[5] & (SC1_internal_oci_ienable1[5] # !FC1L21);
--L1L941 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[3]~92 at LC_X34_Y20_N6
--operation mode is arithmetic
L1L941 = AMPP_FUNCTION(L1_F_pc[3], L1L937, L1L939, L1L940);
--L1_D_pc_plus_one[3] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[3] at LC_X34_Y20_N6
--operation mode is arithmetic
L1_D_pc_plus_one[3] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[3], E1_data_out, L1_W_stall, L1L937, L1L939, L1L940);
--L1L942 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[3]~93 at LC_X34_Y20_N6
--operation mode is arithmetic
L1L942 = AMPP_FUNCTION(L1_F_pc[3], L1L939);
--L1L943 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[3]~93COUT1_192 at LC_X34_Y20_N6
--operation mode is arithmetic
L1L943 = AMPP_FUNCTION(L1_F_pc[3], L1L940);
--L1L944 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[4]~94 at LC_X34_Y20_N7
--operation mode is arithmetic
L1L944 = AMPP_FUNCTION(L1_F_pc[4], L1L937, L1L942, L1L943);
--L1_D_pc_plus_one[4] is std_1s10:inst|cpu:the_cpu|D_pc_plus_one[4] at LC_X34_Y20_N7
--operation mode is arithmetic
L1_D_pc_plus_one[4] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[4], E1_data_out, L1_W_stall, L1L937, L1L942, L1L943);
--L1L945 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[4]~95 at LC_X34_Y20_N7
--operation mode is arithmetic
L1L945 = AMPP_FUNCTION(L1_F_pc[4], L1L942);
--L1L946 is std_1s10:inst|cpu:the_cpu|F_pc_plus_one[4]~95COUT1_194 at LC_X34_Y20_N7
--operation mode is arithmetic
L1L946 = AMPP_FUNCTION(L1_F_pc[4], L1L943);
--M1L72 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~4995 at LC_X48_Y14_N1
--operation mode is normal
M1L72 = L1_M_alu_result[4] & A1L137 & L1_M_alu_result[7] # !L1_M_alu_result[4] & (!L1_M_alu_result[7]) # !EB1L3;
--M1_registered_cpu_data_master_readdata[6] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[6] at LC_X50_Y16_N8
--operation mode is normal
M1_registered_cpu_data_master_readdata[6]_lut_out = M1L302 & M1L274 & (FB1_za_data[6] # !GB1L24);
M1_registered_cpu_data_master_readdata[6] = DFFEAS(M1_registered_cpu_data_master_readdata[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L73 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~4996 at LC_X48_Y14_N6
--operation mode is normal
M1L73 = M1L72 & (M1_registered_cpu_data_master_readdata[6] # !J1_cpu_data_master_requests_clock_0_in & !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
--M1L74 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~4997 at LC_X47_Y11_N2
--operation mode is normal
M1L74 = AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & BE1_q_a[6] & (Q1_internal_incoming_ext_ram_bus_data[6] # !Q1_cpu_data_master_requests_lan91c111_s1) # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & (Q1_internal_incoming_ext_ram_bus_data[6] # !Q1_cpu_data_master_requests_lan91c111_s1);
--M1L75 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~4998 at LC_X47_Y14_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[6]_qfbk = M1_dbs_8_reg_segment_0[6];
M1L75 = M1_registered_cpu_data_master_readdata[6] & (M1_dbs_8_reg_segment_0[6]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[6] & !GB1L24 & (M1_dbs_8_reg_segment_0[6]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1_dbs_8_reg_segment_0[6] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[6] at LC_X47_Y14_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[6] = DFFEAS(M1L75, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L308, Q1_internal_incoming_ext_ram_bus_data[6], , , VCC);
--R1_readdata[6] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[6] at LC_X47_Y9_N9
--operation mode is normal
R1_readdata[6]_lut_out = L1_M_alu_result[3] & R1L196 & !L1_M_alu_result[4] # !L1_M_alu_result[3] & (L1_M_alu_result[4] & R1L195);
R1_readdata[6] = DFFEAS(R1_readdata[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L76 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~4999 at LC_X47_Y9_N1
--operation mode is normal
M1L76 = M1L79 & (R1_readdata[6] # !LB1L2 # !S1L2);
--HE1_readdata[6] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[6] at LC_X50_Y10_N7
--operation mode is normal
HE1_readdata[6]_lut_out = !L1_M_alu_result[4] & (L1_M_alu_result[2] & HE1L59 # !L1_M_alu_result[2] & (HE1L60));
HE1_readdata[6] = DFFEAS(HE1_readdata[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L77 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5000 at LC_X47_Y11_N8
--operation mode is normal
M1L77 = M1L76 & M1L74 & (HE1_readdata[6] # !QB1_cpu_data_master_granted_uart1_s1);
--KB1_readdata[6] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[6] at LC_X51_Y5_N7
--operation mode is normal
KB1_readdata[6]_lut_out = L1_M_alu_result[3] & !L1_M_alu_result[4] & (KB1L197) # !L1_M_alu_result[3] & L1_M_alu_result[4] & KB1L196;
KB1_readdata[6] = DFFEAS(KB1_readdata[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L78 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5001 at LC_X47_Y11_N9
--operation mode is normal
M1L78 = M1L73 & M1L77 & (KB1_readdata[6] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--FC1L9 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[6]~1225 at LC_X47_Y11_N5
--operation mode is normal
FC1L9 = AMPP_FUNCTION(P1L3, L1_M_alu_result[10], L1_ic_fill_line[5], PD1_q_a[6]);
--L1L1253 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[0]~1369 at LC_X12_Y15_N1
--operation mode is normal
L1L1253 = AMPP_FUNCTION(QC1_result[0], QC1_result[32]);
--L1_d_readdata_d1[0] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[0] at LC_X40_Y20_N9
--operation mode is normal
L1_d_readdata_d1[0] = AMPP_FUNCTION(DE1__clk0, M1L26, FC1L2, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L1, E1_data_out);
--L1L1254 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[1]~1370 at LC_X12_Y13_N7
--operation mode is normal
L1L1254 = AMPP_FUNCTION(QC1_result[1], QC1_result[33]);
--L1_d_readdata_d1[1] is std_1s10:inst|cpu:the_cpu|d_readdata_d1[1] at LC_X45_Y20_N1
--operation mode is normal
L1_d_readdata_d1[1] = AMPP_FUNCTION(DE1__clk0, P1_cpu_data_master_requests_cpu_jtag_debug_module, FC1L4, FC1L3, M1L35, E1_data_out);
--KE1_do_load_shifter is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|do_load_shifter at LC_X52_Y7_N0
--operation mode is normal
KE1_do_load_shifter_lut_out = !KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] & KE1_internal_tx_ready & KE1L37;
KE1_do_load_shifter = DFFEAS(KE1_do_load_shifter_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--KE1_baud_clk_en is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_clk_en at LC_X52_Y7_N1
--operation mode is normal
KE1_baud_clk_en_lut_out = KE1L30 & KE1L31 & !KE1_baud_rate_counter[8];
KE1_baud_clk_en = DFFEAS(KE1_baud_clk_en_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--KE1L48 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]~2816 at LC_X51_Y7_N1
--operation mode is normal
KE1L48 = KE1_do_load_shifter # KE1_baud_clk_en & (KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] # !KE1L37);
--HE1_internal_tx_data[0] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[0] at LC_X51_Y9_N9
--operation mode is normal
HE1_internal_tx_data[0]_lut_out = L1_M_st_data[0];
HE1_internal_tx_data[0] = DFFEAS(HE1_internal_tx_data[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L64, , , , );
--L1_reset_d1 is std_1s10:inst|cpu:the_cpu|reset_d1 at LC_X35_Y15_N4
--operation mode is normal
L1_reset_d1 = AMPP_FUNCTION(DE1__clk0, E1_data_out);
--L1_M_bstatus_reg is std_1s10:inst|cpu:the_cpu|M_bstatus_reg at LC_X28_Y22_N9
--operation mode is normal
L1_M_bstatus_reg = AMPP_FUNCTION(DE1__clk0, L1_E_wrctl_bstatus, L1_M_bstatus_reg, L1_M_status_reg_pie, L1L425, E1_data_out, L1_E_ctrl_break, L1L1372);
--L1_M_estatus_reg is std_1s10:inst|cpu:the_cpu|M_estatus_reg at LC_X31_Y21_N5
--operation mode is normal
L1_M_estatus_reg = AMPP_FUNCTION(DE1__clk0, L1_E_wrctl_estatus, L1_M_estatus_reg, L1_M_status_reg_pie, L1L425, E1_data_out, L1_E_ctrl_exception, L1L1372);
--L1L203 is std_1s10:inst|cpu:the_cpu|D_control_rd_data_without_mmu_regs[0]~424 at LC_X29_Y21_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L203 = AMPP_FUNCTION(L1_D_iw[7], L1_D_iw[6], L1_M_estatus_reg);
--L1_M_ienable_reg[0] is std_1s10:inst|cpu:the_cpu|M_ienable_reg[0] at LC_X29_Y21_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_M_ienable_reg[0] = AMPP_FUNCTION(DE1__clk0, L1L425, E1_data_out, GND, L1L1187);
--L1L204 is std_1s10:inst|cpu:the_cpu|D_control_rd_data_without_mmu_regs[0]~425 at LC_X31_Y21_N6
--operation mode is normal
L1L204 = AMPP_FUNCTION(L1_M_status_reg_pie, L1L203, L1_D_iw[8], L1_M_ipending_reg[0]);
--DD1L118Q is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir_out[0]~reg0 at LC_X45_Y20_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1L118Q = AMPP_FUNCTION(!A1L6, VC1_internal_monitor_ready, !C1_CLR_SIGNAL, GND);
--ME3_Q[4] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[4] at LC_X29_Y28_N0
--operation mode is normal
ME3_Q[4] = AMPP_FUNCTION(!A1L6, ME3_Q[5], RE1_state[4], !C1_CLR_SIGNAL, ME3L4);
--ME3_Q[6] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[6] at LC_X29_Y29_N2
--operation mode is normal
ME3_Q[6] = AMPP_FUNCTION(!A1L6, A1L2, !C1_CLR_SIGNAL, RE1_state[4], C1_IRSR_ENA);
--SE1_dffe1a[3] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[3] at LC_X29_Y27_N2
--operation mode is normal
SE1_dffe1a[3] = AMPP_FUNCTION(!A1L6, ME3_Q[2], ME3_Q[3], C1L26, ME3_Q[1], !C1_CLR_SIGNAL, C1L5);
--C1L17 is sld_hub:sld_hub_inst|IR_MUX_SEL[1]~26 at LC_X28_Y28_N4
--operation mode is normal
C1L17 = AMPP_FUNCTION(SE1_dffe1a[3], ME3_Q[4], ME3_Q[6]);
--ME3_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] at LC_X29_Y28_N5
--operation mode is normal
ME3_Q[1] = AMPP_FUNCTION(!A1L6, C1L17, ME3_Q[2], DD1L119Q, !C1_CLR_SIGNAL, RE1_state[4], ME3L4);
--ME4_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0] at LC_X31_Y26_N9
--operation mode is normal
ME4_Q[0] = AMPP_FUNCTION(!A1L6, ME4L3, C1L21, ME4_Q[0], !C1_CLR_SIGNAL);
--ME3_Q[3] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[3] at LC_X29_Y28_N8
--operation mode is normal
ME3_Q[3] = AMPP_FUNCTION(!A1L6, ME3_Q[4], RE1_state[4], !C1_CLR_SIGNAL, ME3L4);
--ME3_Q[5] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[5] at LC_X28_Y28_N0
--operation mode is normal
ME3_Q[5] = AMPP_FUNCTION(!A1L6, C1_jtag_debug_mode_usr1, ME3_Q[6], ME3_Q[5], RE1_state[4], !C1_CLR_SIGNAL);
--C1L16 is sld_hub:sld_hub_inst|IR_MUX_SEL[0]~27 at LC_X28_Y28_N6
--operation mode is normal
C1L16 = AMPP_FUNCTION(ME3_Q[5], ME3_Q[3], SE1_dffe1a[3]);
--ME3L3 is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]~7772 at LC_X28_Y28_N5
--operation mode is normal
ME3L3 = AMPP_FUNCTION(C1L17, ME4_Q[0], C1L16);
--C1_IRSR_ENA is sld_hub:sld_hub_inst|IRSR_ENA at LC_X28_Y26_N3
--operation mode is normal
C1_IRSR_ENA = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, RE1_state[3], RE1_state[4]);
--ME3L4 is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]~7773 at LC_X28_Y28_N2
--operation mode is normal
ME3L4 = AMPP_FUNCTION(C1L17, C1L16, C1_IRSR_ENA, RE1_state[4]);
--C1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q at LC_X28_Y27_N2
--operation mode is normal
C1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(!A1L6, C1_jtag_debug_mode_usr1, C1_OK_TO_UPDATE_IR_Q, RE1_state[8], RE1_state[4], VCC);
--C1L18 is sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 at LC_X28_Y28_N9
--operation mode is normal
C1L18 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, C1_OK_TO_UPDATE_IR_Q, A1L8, RE1_state[4]);
--NE1_WORD_SR[1] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[1] at LC_X28_Y28_N3
--operation mode is normal
NE1_WORD_SR[1] = AMPP_FUNCTION(!A1L6, NE1L19, NE1_WORD_SR[2], NE1_clear_signal, RE1_state[4], VCC, NE1L24);
--NE1_word_counter[4] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[4] at LC_X27_Y27_N1
--operation mode is normal
NE1_word_counter[4] = AMPP_FUNCTION(!A1L6, NE1_word_counter[3], NE1L15, NE1_clear_signal, NE1L1, VCC, NE1L25);
--NE1_word_counter[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0] at LC_X27_Y27_N9
--operation mode is normal
NE1_word_counter[0] = AMPP_FUNCTION(!A1L6, NE1_word_counter[3], NE1L15, NE1_clear_signal, NE1L2, VCC, NE1L25);
--NE1_word_counter[1] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[1] at LC_X28_Y27_N0
--operation mode is normal
NE1_word_counter[1] = AMPP_FUNCTION(!A1L6, C1_jtag_debug_mode_usr1, RE1_state[8], NE1L5, VCC, NE1L25);
--NE1_word_counter[2] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[2] at LC_X28_Y27_N1
--operation mode is normal
NE1_word_counter[2] = AMPP_FUNCTION(!A1L6, RE1_state[8], NE1L8, C1_jtag_debug_mode_usr1, VCC, NE1L25);
--NE1_word_counter[3] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[3] at LC_X27_Y27_N2
--operation mode is normal
NE1_word_counter[3] = AMPP_FUNCTION(!A1L6, NE1_clear_signal, NE1L15, NE1L11, NE1_word_counter[3], VCC, NE1L25);
--NE1L20 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux3~33 at LC_X27_Y27_N3
--operation mode is normal
NE1L20 = AMPP_FUNCTION(NE1_word_counter[3], NE1_word_counter[0], NE1_word_counter[1], NE1_word_counter[2]);
--NE1L23 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1248 at LC_X27_Y27_N0
--operation mode is normal
NE1L23 = AMPP_FUNCTION(NE1_word_counter[4], NE1L20);
--NE1_clear_signal is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|clear_signal at LC_X28_Y27_N4
--operation mode is normal
NE1_clear_signal = AMPP_FUNCTION(RE1_state[8], C1_jtag_debug_mode_usr1);
--C1_jtag_debug_mode_usr0 is sld_hub:sld_hub_inst|jtag_debug_mode_usr0 at LC_X28_Y23_N7
--operation mode is normal
C1_jtag_debug_mode_usr0 = AMPP_FUNCTION(!A1L6, C1L6, C1L7, QE1_dffs[1], QE1_dffs[0], RE1_state[0], RE1_state[12]);
--NE1L24 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1250 at LC_X28_Y26_N7
--operation mode is normal
NE1L24 = AMPP_FUNCTION(NE1_clear_signal, C1_jtag_debug_mode_usr0, RE1_state[3], RE1_state[4]);
--C1L11 is sld_hub:sld_hub_inst|HUB_BYPASS_REG~9 at LC_X33_Y23_N6
--operation mode is normal
C1L11 = AMPP_FUNCTION(altera_internal_jtag, RE1_state[4]);
--C1L26 is sld_hub:sld_hub_inst|jtag_debug_mode~2 at LC_X29_Y27_N7
--operation mode is normal
C1L26 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, C1_jtag_debug_mode_usr0);
--ME3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] at LC_X29_Y28_N4
--operation mode is normal
ME3_Q[2] = AMPP_FUNCTION(!A1L6, ME3_Q[3], RE1_state[4], !C1_CLR_SIGNAL, ME3L4);
--C1L4 is sld_hub:sld_hub_inst|comb~96 at LC_X28_Y26_N2
--operation mode is normal
C1L4 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, C1_jtag_debug_mode_usr0, RE1_state[3], RE1_state[4]);
--QD1_td_shift[1] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[1] at LC_X34_Y24_N3
--operation mode is normal
QD1_td_shift[1] = AMPP_FUNCTION(!A1L6, QD1L63, QD1L53, QD1L54, !C1_CLR_SIGNAL, QD1L52);
--QD1_count[9] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[9] at LC_X33_Y30_N2
--operation mode is normal
QD1_count[9] = AMPP_FUNCTION(!A1L6, QD1L55, GND, VCC, C1_CLR_SIGNAL, QD1L52);
--QD1L65 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift~3494 at LC_X34_Y23_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1L65 = AMPP_FUNCTION(QD1_count[9], QD1_td_shift[1]);
--QD1_rvalid is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rvalid at LC_X34_Y23_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_rvalid = AMPP_FUNCTION(DE1__clk0, QD1_rvalid0, E1_data_out, GND);
--QD1_state is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|state at LC_X30_Y24_N2
--operation mode is normal
QD1_state = AMPP_FUNCTION(!A1L6, QD1L36, C1L11, QD1L1, QD1_state, !C1_CLR_SIGNAL);
--QD1L66 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift~3495 at LC_X33_Y23_N0
--operation mode is normal
QD1L66 = AMPP_FUNCTION(altera_internal_jtag, QD1_state);
--QD1_count[1] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[1] at LC_X35_Y23_N2
--operation mode is normal
QD1_count[1] = AMPP_FUNCTION(!A1L6, QD1_count[0], RE1_state[4], !C1_CLR_SIGNAL, QD1L52);
--QD1_td_shift[9] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9] at LC_X35_Y23_N8
--operation mode is normal
QD1_td_shift[9] = AMPP_FUNCTION(!A1L6, QD1_rdata[7], QD1_count[9], QD1_td_shift[10], !C1_CLR_SIGNAL, !RE1_state[4], QD1L52);
--QD1_user_saw_rvalid is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|user_saw_rvalid at LC_X31_Y26_N4
--operation mode is normal
QD1_user_saw_rvalid = AMPP_FUNCTION(!A1L6, QD1_user_saw_rvalid, QD1_count[0], QD1L69, QD1_td_shift[0], !C1_CLR_SIGNAL);
--QD1L67 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift~3496 at LC_X33_Y23_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1L67 = AMPP_FUNCTION(QD1L65, QD1L62, QD1L66);
--T1_t_dav is std_1s10:inst|jtag_uart:the_jtag_uart|t_dav at LC_X33_Y23_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
T1_t_dav = DFFEAS(QD1L67, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , WD2_b_full, , , VCC);
--QD1L1 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|always0~50 at LC_X30_Y26_N5
--operation mode is normal
QD1L1 = AMPP_FUNCTION(ME2_Q[0], C1_jtag_debug_mode_usr1, C1_jtag_debug_mode, ME8_Q[1]);
--QD1L52 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3497 at LC_X34_Y24_N2
--operation mode is normal
QD1L52 = AMPP_FUNCTION(QD1L1, RE1_state[3], RE1_state[4]);
--DD1_sr[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[1] at LC_X33_Y29_N4
--operation mode is normal
DD1_sr[1] = AMPP_FUNCTION(!A1L6, DD1L141, DD1_sr[2], DD1L130, DD1L143, !C1_CLR_SIGNAL, DD1L6);
--DD1_DRsize[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[2] at LC_X32_Y29_N9
--operation mode is normal
DD1_DRsize[2] = AMPP_FUNCTION(!A1L6, DD1L121, !C1_CLR_SIGNAL, DD1_st_updateir);
--DD1_DRsize[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0] at LC_X32_Y29_N5
--operation mode is normal
DD1_DRsize[0] = AMPP_FUNCTION(!A1L6, ME5_Q[0], ME5_Q[1], !C1_CLR_SIGNAL, DD1_st_updateir);
--DD1L139 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux45~157 at LC_X32_Y28_N5
--operation mode is normal
DD1L139 = AMPP_FUNCTION(DD1_DRsize[1], DD1_DRsize[0], DD1_DRsize[2]);
--DD1L140 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux45~158 at LC_X36_Y23_N1
--operation mode is normal
DD1L140 = AMPP_FUNCTION(altera_internal_jtag, DD1L139, DD1_sr[1]);
--VC1_internal_monitor_ready is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_ready at LC_X34_Y25_N1
--operation mode is normal
VC1_internal_monitor_ready = AMPP_FUNCTION(DE1__clk0, DD1L190, VC1L7, L1_M_st_data[0], SC1L13, VCC);
--DD1L5 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19888 at LC_X32_Y25_N3
--operation mode is normal
DD1L5 = AMPP_FUNCTION(DD1_ir[1], VC1_internal_monitor_ready, DD1_ir[0]);
--DD1_in_between_shiftdr_and_updatedr is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|in_between_shiftdr_and_updatedr at LC_X31_Y28_N1
--operation mode is normal
DD1_in_between_shiftdr_and_updatedr = AMPP_FUNCTION(!A1L6, DD1_st_updatedr, DD1_st_shiftdr, DD1_in_between_shiftdr_and_updatedr, !C1_CLR_SIGNAL);
--DD1L142 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process2~233 at LC_X31_Y28_N9
--operation mode is normal
DD1L142 = AMPP_FUNCTION(DD1_in_between_shiftdr_and_updatedr, A1L5);
--DD1L143 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process2~234 at LC_X31_Y27_N6
--operation mode is normal
DD1L143 = AMPP_FUNCTION(A1L5, DD1L144);
--DD1L6 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19890 at LC_X32_Y28_N0
--operation mode is normal
DD1L6 = AMPP_FUNCTION(DD1_in_between_shiftdr_and_updatedr, A1L5, DD1_st_updateir, DD1L144);
--QE1_dffs[1] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1] at LC_X28_Y23_N3
--operation mode is normal
QE1_dffs[1] = AMPP_FUNCTION(!A1L6, QE1_dffs[2], RE1_state[0], RE1_state[11]);
--QE1_dffs[9] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] at LC_X28_Y4_N0
--operation mode is normal
QE1_dffs[9] = AMPP_FUNCTION(!A1L6, altera_internal_jtag, RE1_state[0], RE1_state[11]);
--QE1_dffs[7] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7] at LC_X28_Y4_N8
--operation mode is normal
QE1_dffs[7] = AMPP_FUNCTION(!A1L6, QE1_dffs[8], RE1_state[0], RE1_state[11]);
--QE1_dffs[6] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6] at LC_X28_Y23_N5
--operation mode is normal
QE1_dffs[6] = AMPP_FUNCTION(!A1L6, QE1_dffs[7], RE1_state[0], RE1_state[11]);
--C1L6 is sld_hub:sld_hub_inst|Equal0~83 at LC_X28_Y23_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
C1L6 = AMPP_FUNCTION(QE1_dffs[9], QE1_dffs[6], QE1_dffs[7]);
--QE1_dffs[8] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8] at LC_X28_Y23_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QE1_dffs[8] = AMPP_FUNCTION(!A1L6, QE1_dffs[9], RE1_state[0], GND, RE1_state[11]);
--QE1_dffs[2] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2] at LC_X28_Y23_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QE1_dffs[2] = AMPP_FUNCTION(!A1L6, QE1_dffs[3], RE1_state[0], GND, RE1_state[11]);
--QE1_dffs[5] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[5] at LC_X28_Y23_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QE1_dffs[5] = AMPP_FUNCTION(!A1L6, QE1_dffs[6], RE1_state[0], GND, RE1_state[11]);
--QE1_dffs[4] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4] at LC_X28_Y23_N0
--operation mode is normal
QE1_dffs[4] = AMPP_FUNCTION(!A1L6, QE1_dffs[5], RE1_state[0], RE1_state[11]);
--C1L7 is sld_hub:sld_hub_inst|Equal0~84 at LC_X28_Y23_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
C1L7 = AMPP_FUNCTION(QE1_dffs[5], QE1_dffs[4], QE1_dffs[2]);
--QE1_dffs[3] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3] at LC_X28_Y23_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QE1_dffs[3] = AMPP_FUNCTION(!A1L6, QE1_dffs[4], RE1_state[0], GND, RE1_state[11]);
--QE1_dffs[0] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0] at LC_X28_Y23_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QE1_dffs[0] = AMPP_FUNCTION(!A1L6, QE1_dffs[1], RE1_state[0], GND, RE1_state[11]);
--RE1_state[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] at LC_X28_Y5_N4
--operation mode is normal
RE1_state[0] = AMPP_FUNCTION(!A1L6, A1L8, RE1_state[9], RE1L18, RE1_state[0], VCC);
--RE1_state[12] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12] at LC_X28_Y5_N5
--operation mode is normal
RE1_state[12] = AMPP_FUNCTION(!A1L6, RE1_state[10], RE1_state[11], VCC, A1L8);
--RE1_state[7] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[7] at LC_X28_Y26_N1
--operation mode is normal
RE1_state[7] = AMPP_FUNCTION(!A1L6, A1L8, RE1_state[6], VCC);
--RE1_state[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2] at LC_X28_Y5_N1
--operation mode is normal
RE1_state[2] = AMPP_FUNCTION(!A1L6, RE1_state[1], RE1_state[15], RE1_state[8], VCC, A1L8);
--RE1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5] at LC_X28_Y26_N8
--operation mode is normal
RE1_state[5] = AMPP_FUNCTION(!A1L6, A1L8, RE1_state[3], RE1_state[4], VCC);
--HE1L16 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~100 at LC_X41_Y15_N5
--operation mode is normal
HE1L16 = L1_M_alu_result[2] & !L1_M_alu_result[3];
--L1_M_st_data[31] is std_1s10:inst|cpu:the_cpu|M_st_data[31] at LC_X19_Y9_N2
--operation mode is normal
L1_M_st_data[31] = AMPP_FUNCTION(DE1__clk0, L1L816, L1L1339, L1L808, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--L1_M_st_data[30] is std_1s10:inst|cpu:the_cpu|M_st_data[30] at LC_X19_Y9_N5
--operation mode is normal
L1_M_st_data[30] = AMPP_FUNCTION(DE1__clk0, L1L1337, L1L815, L1L807, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--L1_M_st_data[29] is std_1s10:inst|cpu:the_cpu|M_st_data[29] at LC_X19_Y9_N9
--operation mode is normal
L1_M_st_data[29] = AMPP_FUNCTION(DE1__clk0, L1L1335, L1L814, L1L806, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--L1_M_st_data[28] is std_1s10:inst|cpu:the_cpu|M_st_data[28] at LC_X19_Y9_N8
--operation mode is normal
L1_M_st_data[28] = AMPP_FUNCTION(DE1__clk0, L1L1333, L1L813, L1L805, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--L1_M_st_data[27] is std_1s10:inst|cpu:the_cpu|M_st_data[27] at LC_X19_Y16_N5
--operation mode is normal
L1_M_st_data[27] = AMPP_FUNCTION(DE1__clk0, L1L812, L1_E_iw[3], L1L804, L1L1331, E1_data_out, L1_E_iw[4], L1_W_stall);
--L1_M_st_data[26] is std_1s10:inst|cpu:the_cpu|M_st_data[26] at LC_X19_Y9_N6
--operation mode is normal
L1_M_st_data[26] = AMPP_FUNCTION(DE1__clk0, L1L811, L1L1329, L1L803, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--L1_M_st_data[25] is std_1s10:inst|cpu:the_cpu|M_st_data[25] at LC_X19_Y9_N4
--operation mode is normal
L1_M_st_data[25] = AMPP_FUNCTION(DE1__clk0, L1L810, L1L1327, L1L802, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--L1_M_st_data[24] is std_1s10:inst|cpu:the_cpu|M_st_data[24] at LC_X22_Y22_N2
--operation mode is normal
L1_M_st_data[24] = AMPP_FUNCTION(DE1__clk0, L1L809, L1L1325, L1L801, L1_E_iw[3], E1_data_out, L1_E_iw[4], L1_W_stall);
--Q1L430 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[7]~2841 at LC_X32_Y23_N2
--operation mode is normal
Q1L430 = M1_internal_cpu_data_master_dbs_address[0] & (M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[31]) # !M1_internal_cpu_data_master_dbs_address[0] & (M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[23] # !M1_internal_cpu_data_master_dbs_address[1] & (L1_M_st_data[31]));
--Q1L431 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[7]~2842 at LC_X21_Y21_N9
--operation mode is normal
Q1L431 = Q1L430 # L1_M_st_data[15] & M1_internal_cpu_data_master_dbs_address[0] & !M1_internal_cpu_data_master_dbs_address[1];
--M1L260 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|Equal1~40 at LC_X21_Y23_N9
--operation mode is normal
M1L260 = M1_internal_cpu_data_master_dbs_address[1] # M1_internal_cpu_data_master_dbs_address[0];
--Q1L432 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[31]~2843 at LC_X39_Y17_N2
--operation mode is normal
Q1L432 = Q1L76 & !Q1L72 & (Q1L18 # Q1L15);
--Q1L428 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[6]~2845 at LC_X21_Y21_N1
--operation mode is normal
Q1L428 = M1_internal_cpu_data_master_dbs_address[0] & M1_internal_cpu_data_master_dbs_address[1] & (L1_M_st_data[30]) # !M1_internal_cpu_data_master_dbs_address[0] & (M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[22] # !M1_internal_cpu_data_master_dbs_address[1] & (L1_M_st_data[30]));
--Q1L429 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[6]~2846 at LC_X21_Y21_N2
--operation mode is normal
Q1L429 = Q1L428 # M1_internal_cpu_data_master_dbs_address[0] & !M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[14];
--Q1L426 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[5]~2848 at LC_X21_Y21_N5
--operation mode is normal
Q1L426 = M1_internal_cpu_data_master_dbs_address[0] & (M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[29]) # !M1_internal_cpu_data_master_dbs_address[0] & (M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[21] # !M1_internal_cpu_data_master_dbs_address[1] & (L1_M_st_data[29]));
--Q1L427 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[5]~2849 at LC_X21_Y21_N6
--operation mode is normal
Q1L427 = Q1L426 # L1_M_st_data[13] & M1_internal_cpu_data_master_dbs_address[0] & !M1_internal_cpu_data_master_dbs_address[1];
--Q1L424 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[4]~2851 at LC_X21_Y21_N7
--operation mode is normal
Q1L424 = M1_internal_cpu_data_master_dbs_address[0] & M1_internal_cpu_data_master_dbs_address[1] & (L1_M_st_data[28]) # !M1_internal_cpu_data_master_dbs_address[0] & (M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[20] # !M1_internal_cpu_data_master_dbs_address[1] & (L1_M_st_data[28]));
--Q1L425 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[4]~2852 at LC_X21_Y21_N8
--operation mode is normal
Q1L425 = Q1L424 # M1_internal_cpu_data_master_dbs_address[0] & !M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[12];
--Q1L422 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[3]~2854 at LC_X21_Y21_N3
--operation mode is normal
Q1L422 = M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & L1_M_st_data[27] # !M1_internal_cpu_data_master_dbs_address[0] & (L1_M_st_data[19])) # !M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[27] & !M1_internal_cpu_data_master_dbs_address[0];
--Q1L423 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[3]~2855 at LC_X21_Y21_N4
--operation mode is normal
Q1L423 = Q1L422 # M1_internal_cpu_data_master_dbs_address[0] & !M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[11];
--Q1L420 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[2]~2857 at LC_X40_Y6_N3
--operation mode is normal
Q1L420 = M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & L1_M_st_data[26] # !M1_internal_cpu_data_master_dbs_address[0] & (L1_M_st_data[18])) # !M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[26] & !M1_internal_cpu_data_master_dbs_address[0];
--Q1L421 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[2]~2858 at LC_X40_Y6_N2
--operation mode is normal
Q1L421 = Q1L420 # !M1_internal_cpu_data_master_dbs_address[1] & M1_internal_cpu_data_master_dbs_address[0] & L1_M_st_data[10];
--Q1L418 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[1]~2860 at LC_X36_Y8_N7
--operation mode is normal
Q1L418 = M1_internal_cpu_data_master_dbs_address[0] & (M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[25]) # !M1_internal_cpu_data_master_dbs_address[0] & (M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[17] # !M1_internal_cpu_data_master_dbs_address[1] & (L1_M_st_data[25]));
--Q1L419 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[1]~2861 at LC_X21_Y23_N3
--operation mode is normal
Q1L419 = Q1L418 # !M1_internal_cpu_data_master_dbs_address[1] & M1_internal_cpu_data_master_dbs_address[0] & L1_M_st_data[9];
--Q1L416 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[0]~2863 at LC_X36_Y8_N6
--operation mode is normal
Q1L416 = M1_internal_cpu_data_master_dbs_address[0] & (M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[24]) # !M1_internal_cpu_data_master_dbs_address[0] & (M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[16] # !M1_internal_cpu_data_master_dbs_address[1] & (L1_M_st_data[24]));
--Q1L417 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|outgoing_ext_ram_bus_data[0]~2864 at LC_X36_Y8_N0
--operation mode is normal
Q1L417 = Q1L416 # !M1_internal_cpu_data_master_dbs_address[1] & L1_M_st_data[8] & M1_internal_cpu_data_master_dbs_address[0];
--FB1_active_data[31] is std_1s10:inst|sdram:the_sdram|active_data[31] at LC_X39_Y5_N6
--operation mode is normal
FB1_active_data[31]_lut_out = FB1L12 & (FB1L14 & EE1L160 # !FB1L14 & (FB1_active_data[31])) # !FB1L12 & (FB1_active_data[31]);
FB1_active_data[31] = DFFEAS(FB1_active_data[31]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[31] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[31] at LC_X39_Y7_N0
--operation mode is normal
EE1_entry_0[31]_lut_out = L1_M_st_data[31];
EE1_entry_0[31] = DFFEAS(EE1_entry_0[31]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L160 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[31]~510 at LC_X39_Y7_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[31]_qfbk = EE1_entry_1[31];
EE1L160 = EE1_rd_address & EE1_entry_1[31]_qfbk # !EE1_rd_address & (EE1_entry_0[31]);
--EE1_entry_1[31] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[31] at LC_X39_Y7_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[31] = DFFEAS(EE1L160, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[31], , , VCC);
--FB1L679 is std_1s10:inst|sdram:the_sdram|Mux118~1212 at LC_X39_Y7_N7
--operation mode is normal
FB1L679 = FB1_m_state[1] & (FB1_active_data[31]) # !FB1_m_state[1] & (FB1_f_select & EE1L160 # !FB1_f_select & (FB1_active_data[31]));
--FB1L680 is std_1s10:inst|sdram:the_sdram|Mux118~1213 at LC_X36_Y1_N5
--operation mode is normal
FB1L680 = !FB1_m_state[3] & (FB1_m_state[1] $ FB1_m_state[4]);
--FB1L718 is std_1s10:inst|sdram:the_sdram|Mux154~541 at LC_X36_Y1_N8
--operation mode is normal
FB1L718 = FB1_m_state[4] & !FB1_m_state[3] & FB1L468;
--FB1_active_data[30] is std_1s10:inst|sdram:the_sdram|active_data[30] at LC_X36_Y3_N4
--operation mode is normal
FB1_active_data[30]_lut_out = FB1L66 & (FB1L65 & EE1L159 # !FB1L65 & (FB1_active_data[30])) # !FB1L66 & (FB1_active_data[30]);
FB1_active_data[30] = DFFEAS(FB1_active_data[30]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[30] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[30] at LC_X36_Y7_N4
--operation mode is normal
EE1_entry_0[30]_lut_out = L1_M_st_data[30];
EE1_entry_0[30] = DFFEAS(EE1_entry_0[30]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L159 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[30]~511 at LC_X36_Y3_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[30]_qfbk = EE1_entry_1[30];
EE1L159 = EE1_rd_address & EE1_entry_1[30]_qfbk # !EE1_rd_address & (EE1_entry_0[30]);
--EE1_entry_1[30] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[30] at LC_X36_Y3_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[30] = DFFEAS(EE1L159, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[30], , , VCC);
--FB1L682 is std_1s10:inst|sdram:the_sdram|Mux119~1170 at LC_X36_Y3_N9
--operation mode is normal
FB1L682 = FB1_m_state[1] & (FB1_active_data[30]) # !FB1_m_state[1] & (FB1_f_select & EE1L159 # !FB1_f_select & (FB1_active_data[30]));
--FB1_active_data[29] is std_1s10:inst|sdram:the_sdram|active_data[29] at LC_X36_Y3_N5
--operation mode is normal
FB1_active_data[29]_lut_out = FB1L12 & (FB1L14 & EE1L158 # !FB1L14 & (FB1_active_data[29])) # !FB1L12 & (FB1_active_data[29]);
FB1_active_data[29] = DFFEAS(FB1_active_data[29]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[29] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[29] at LC_X36_Y7_N2
--operation mode is normal
EE1_entry_0[29]_lut_out = L1_M_st_data[29];
EE1_entry_0[29] = DFFEAS(EE1_entry_0[29]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L158 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[29]~512 at LC_X36_Y3_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[29]_qfbk = EE1_entry_1[29];
EE1L158 = EE1_rd_address & EE1_entry_1[29]_qfbk # !EE1_rd_address & (EE1_entry_0[29]);
--EE1_entry_1[29] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[29] at LC_X36_Y3_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[29] = DFFEAS(EE1L158, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[29], , , VCC);
--FB1L683 is std_1s10:inst|sdram:the_sdram|Mux120~1170 at LC_X36_Y3_N3
--operation mode is normal
FB1L683 = FB1_m_state[1] & (FB1_active_data[29]) # !FB1_m_state[1] & (FB1_f_select & EE1L158 # !FB1_f_select & (FB1_active_data[29]));
--FB1_active_data[28] is std_1s10:inst|sdram:the_sdram|active_data[28] at LC_X40_Y5_N4
--operation mode is normal
FB1_active_data[28]_lut_out = FB1L66 & (FB1L65 & EE1L157 # !FB1L65 & (FB1_active_data[28])) # !FB1L66 & (FB1_active_data[28]);
FB1_active_data[28] = DFFEAS(FB1_active_data[28]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[28] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[28] at LC_X36_Y7_N6
--operation mode is normal
EE1_entry_0[28]_lut_out = L1_M_st_data[28];
EE1_entry_0[28] = DFFEAS(EE1_entry_0[28]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L157 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[28]~513 at LC_X40_Y5_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[28]_qfbk = EE1_entry_1[28];
EE1L157 = EE1_rd_address & EE1_entry_1[28]_qfbk # !EE1_rd_address & (EE1_entry_0[28]);
--EE1_entry_1[28] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[28] at LC_X40_Y5_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[28] = DFFEAS(EE1L157, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[28], , , VCC);
--FB1L684 is std_1s10:inst|sdram:the_sdram|Mux121~1170 at LC_X40_Y5_N3
--operation mode is normal
FB1L684 = FB1_m_state[1] & FB1_active_data[28] # !FB1_m_state[1] & (FB1_f_select & (EE1L157) # !FB1_f_select & FB1_active_data[28]);
--FB1_active_data[27] is std_1s10:inst|sdram:the_sdram|active_data[27] at LC_X39_Y6_N8
--operation mode is normal
FB1_active_data[27]_lut_out = FB1L14 & (FB1L12 & EE1L156 # !FB1L12 & (FB1_active_data[27])) # !FB1L14 & (FB1_active_data[27]);
FB1_active_data[27] = DFFEAS(FB1_active_data[27]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[27] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[27] at LC_X36_Y7_N1
--operation mode is normal
EE1_entry_0[27]_lut_out = L1_M_st_data[27];
EE1_entry_0[27] = DFFEAS(EE1_entry_0[27]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L156 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[27]~514 at LC_X39_Y6_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[27]_qfbk = EE1_entry_1[27];
EE1L156 = EE1_rd_address & (EE1_entry_1[27]_qfbk) # !EE1_rd_address & (EE1_entry_0[27]);
--EE1_entry_1[27] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[27] at LC_X39_Y6_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[27] = DFFEAS(EE1L156, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[27], , , VCC);
--FB1L685 is std_1s10:inst|sdram:the_sdram|Mux122~1170 at LC_X39_Y6_N6
--operation mode is normal
FB1L685 = FB1_m_state[1] & FB1_active_data[27] # !FB1_m_state[1] & (FB1_f_select & (EE1L156) # !FB1_f_select & FB1_active_data[27]);
--FB1_active_data[26] is std_1s10:inst|sdram:the_sdram|active_data[26] at LC_X39_Y6_N7
--operation mode is normal
FB1_active_data[26]_lut_out = FB1L65 & (FB1L66 & EE1L155 # !FB1L66 & (FB1_active_data[26])) # !FB1L65 & (FB1_active_data[26]);
FB1_active_data[26] = DFFEAS(FB1_active_data[26]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[26] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[26] at LC_X36_Y7_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[26]_lut_out = GND;
EE1_entry_0[26] = DFFEAS(EE1_entry_0[26]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, L1_M_st_data[26], , , VCC);
--EE1L155 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[26]~515 at LC_X39_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[26]_qfbk = EE1_entry_1[26];
EE1L155 = EE1_rd_address & (EE1_entry_1[26]_qfbk) # !EE1_rd_address & (EE1_entry_0[26]);
--EE1_entry_1[26] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[26] at LC_X39_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[26] = DFFEAS(EE1L155, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[26], , , VCC);
--FB1L686 is std_1s10:inst|sdram:the_sdram|Mux123~1170 at LC_X39_Y6_N4
--operation mode is normal
FB1L686 = FB1_m_state[1] & (FB1_active_data[26]) # !FB1_m_state[1] & (FB1_f_select & EE1L155 # !FB1_f_select & (FB1_active_data[26]));
--FB1_active_data[25] is std_1s10:inst|sdram:the_sdram|active_data[25] at LC_X36_Y6_N8
--operation mode is normal
FB1_active_data[25]_lut_out = FB1L12 & (FB1L14 & EE1L154 # !FB1L14 & (FB1_active_data[25])) # !FB1L12 & (FB1_active_data[25]);
FB1_active_data[25] = DFFEAS(FB1_active_data[25]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[25] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[25] at LC_X36_Y7_N3
--operation mode is normal
EE1_entry_0[25]_lut_out = L1_M_st_data[25];
EE1_entry_0[25] = DFFEAS(EE1_entry_0[25]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L154 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[25]~516 at LC_X36_Y6_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[25]_qfbk = EE1_entry_1[25];
EE1L154 = EE1_rd_address & EE1_entry_1[25]_qfbk # !EE1_rd_address & (EE1_entry_0[25]);
--EE1_entry_1[25] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[25] at LC_X36_Y6_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[25] = DFFEAS(EE1L154, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[25], , , VCC);
--FB1L687 is std_1s10:inst|sdram:the_sdram|Mux124~1170 at LC_X39_Y6_N9
--operation mode is normal
FB1L687 = FB1_m_state[1] & FB1_active_data[25] # !FB1_m_state[1] & (FB1_f_select & (EE1L154) # !FB1_f_select & FB1_active_data[25]);
--FB1_active_data[24] is std_1s10:inst|sdram:the_sdram|active_data[24] at LC_X41_Y4_N6
--operation mode is normal
FB1_active_data[24]_lut_out = FB1L66 & (FB1L65 & EE1L153 # !FB1L65 & (FB1_active_data[24])) # !FB1L66 & (FB1_active_data[24]);
FB1_active_data[24] = DFFEAS(FB1_active_data[24]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[24] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[24] at LC_X36_Y7_N7
--operation mode is normal
EE1_entry_0[24]_lut_out = L1_M_st_data[24];
EE1_entry_0[24] = DFFEAS(EE1_entry_0[24]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L153 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[24]~517 at LC_X41_Y4_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[24]_qfbk = EE1_entry_1[24];
EE1L153 = EE1_rd_address & (EE1_entry_1[24]_qfbk) # !EE1_rd_address & (EE1_entry_0[24]);
--EE1_entry_1[24] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[24] at LC_X41_Y4_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[24] = DFFEAS(EE1L153, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[24], , , VCC);
--FB1L688 is std_1s10:inst|sdram:the_sdram|Mux125~1170 at LC_X41_Y4_N7
--operation mode is normal
FB1L688 = FB1_f_select & (FB1_m_state[1] & (FB1_active_data[24]) # !FB1_m_state[1] & EE1L153) # !FB1_f_select & (FB1_active_data[24]);
--FB1_active_data[23] is std_1s10:inst|sdram:the_sdram|active_data[23] at LC_X41_Y4_N0
--operation mode is normal
FB1_active_data[23]_lut_out = FB1L12 & (FB1L14 & EE1L152 # !FB1L14 & (FB1_active_data[23])) # !FB1L12 & (FB1_active_data[23]);
FB1_active_data[23] = DFFEAS(FB1_active_data[23]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[23] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[23] at LC_X36_Y7_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[23]_lut_out = GND;
EE1_entry_0[23] = DFFEAS(EE1_entry_0[23]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, L1_M_st_data[23], , , VCC);
--EE1L152 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[23]~518 at LC_X41_Y4_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[23]_qfbk = EE1_entry_1[23];
EE1L152 = EE1_rd_address & (EE1_entry_1[23]_qfbk) # !EE1_rd_address & EE1_entry_0[23];
--EE1_entry_1[23] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[23] at LC_X41_Y4_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[23] = DFFEAS(EE1L152, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[23], , , VCC);
--FB1L689 is std_1s10:inst|sdram:the_sdram|Mux126~1170 at LC_X41_Y4_N8
--operation mode is normal
FB1L689 = FB1_f_select & (FB1_m_state[1] & (FB1_active_data[23]) # !FB1_m_state[1] & EE1L152) # !FB1_f_select & (FB1_active_data[23]);
--FB1_active_data[22] is std_1s10:inst|sdram:the_sdram|active_data[22] at LC_X40_Y5_N7
--operation mode is normal
FB1_active_data[22]_lut_out = FB1L66 & (FB1L65 & (EE1L151) # !FB1L65 & FB1_active_data[22]) # !FB1L66 & (FB1_active_data[22]);
FB1_active_data[22] = DFFEAS(FB1_active_data[22]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[22] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[22] at LC_X40_Y6_N7
--operation mode is normal
EE1_entry_0[22]_lut_out = L1_M_st_data[22];
EE1_entry_0[22] = DFFEAS(EE1_entry_0[22]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L151 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[22]~519 at LC_X40_Y5_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[22]_qfbk = EE1_entry_1[22];
EE1L151 = EE1_rd_address & EE1_entry_1[22]_qfbk # !EE1_rd_address & (EE1_entry_0[22]);
--EE1_entry_1[22] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[22] at LC_X40_Y5_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[22] = DFFEAS(EE1L151, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[22], , , VCC);
--FB1L690 is std_1s10:inst|sdram:the_sdram|Mux127~1170 at LC_X41_Y4_N3
--operation mode is normal
FB1L690 = FB1_m_state[1] & FB1_active_data[22] # !FB1_m_state[1] & (FB1_f_select & (EE1L151) # !FB1_f_select & FB1_active_data[22]);
--FB1_active_data[21] is std_1s10:inst|sdram:the_sdram|active_data[21] at LC_X40_Y3_N4
--operation mode is normal
FB1_active_data[21]_lut_out = FB1L14 & (FB1L12 & EE1L150 # !FB1L12 & (FB1_active_data[21])) # !FB1L14 & (FB1_active_data[21]);
FB1_active_data[21] = DFFEAS(FB1_active_data[21]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[21] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[21] at LC_X40_Y6_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[21]_lut_out = GND;
EE1_entry_0[21] = DFFEAS(EE1_entry_0[21]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, L1_M_st_data[21], , , VCC);
--EE1L150 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[21]~520 at LC_X40_Y3_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[21]_qfbk = EE1_entry_1[21];
EE1L150 = EE1_rd_address & (EE1_entry_1[21]_qfbk) # !EE1_rd_address & (EE1_entry_0[21]);
--EE1_entry_1[21] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[21] at LC_X40_Y3_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[21] = DFFEAS(EE1L150, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[21], , , VCC);
--FB1L691 is std_1s10:inst|sdram:the_sdram|Mux128~1170 at LC_X40_Y3_N3
--operation mode is normal
FB1L691 = FB1_f_select & (FB1_m_state[1] & FB1_active_data[21] # !FB1_m_state[1] & (EE1L150)) # !FB1_f_select & FB1_active_data[21];
--FB1_active_data[20] is std_1s10:inst|sdram:the_sdram|active_data[20] at LC_X40_Y3_N0
--operation mode is normal
FB1_active_data[20]_lut_out = FB1L65 & (FB1L66 & (EE1L149) # !FB1L66 & FB1_active_data[20]) # !FB1L65 & FB1_active_data[20];
FB1_active_data[20] = DFFEAS(FB1_active_data[20]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[20] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[20] at LC_X40_Y6_N8
--operation mode is normal
EE1_entry_0[20]_lut_out = L1_M_st_data[20];
EE1_entry_0[20] = DFFEAS(EE1_entry_0[20]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L149 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[20]~521 at LC_X40_Y3_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[20]_qfbk = EE1_entry_1[20];
EE1L149 = EE1_rd_address & (EE1_entry_1[20]_qfbk) # !EE1_rd_address & (EE1_entry_0[20]);
--EE1_entry_1[20] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[20] at LC_X40_Y3_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[20] = DFFEAS(EE1L149, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[20], , , VCC);
--FB1L692 is std_1s10:inst|sdram:the_sdram|Mux129~1170 at LC_X40_Y3_N6
--operation mode is normal
FB1L692 = FB1_m_state[1] & (FB1_active_data[20]) # !FB1_m_state[1] & (FB1_f_select & EE1L149 # !FB1_f_select & (FB1_active_data[20]));
--FB1_active_data[19] is std_1s10:inst|sdram:the_sdram|active_data[19] at LC_X36_Y6_N0
--operation mode is normal
FB1_active_data[19]_lut_out = FB1L14 & (FB1L12 & (EE1L148) # !FB1L12 & FB1_active_data[19]) # !FB1L14 & FB1_active_data[19];
FB1_active_data[19] = DFFEAS(FB1_active_data[19]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[19] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[19] at LC_X40_Y6_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[19]_lut_out = GND;
EE1_entry_0[19] = DFFEAS(EE1_entry_0[19]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, L1_M_st_data[19], , , VCC);
--EE1L148 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[19]~522 at LC_X36_Y6_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[19]_qfbk = EE1_entry_1[19];
EE1L148 = EE1_rd_address & EE1_entry_1[19]_qfbk # !EE1_rd_address & (EE1_entry_0[19]);
--EE1_entry_1[19] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[19] at LC_X36_Y6_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[19] = DFFEAS(EE1L148, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[19], , , VCC);
--FB1L693 is std_1s10:inst|sdram:the_sdram|Mux130~1170 at LC_X40_Y3_N5
--operation mode is normal
FB1L693 = FB1_m_state[1] & (FB1_active_data[19]) # !FB1_m_state[1] & (FB1_f_select & EE1L148 # !FB1_f_select & (FB1_active_data[19]));
--FB1_active_data[18] is std_1s10:inst|sdram:the_sdram|active_data[18] at LC_X41_Y6_N2
--operation mode is normal
FB1_active_data[18]_lut_out = FB1L66 & (FB1L65 & EE1L147 # !FB1L65 & (FB1_active_data[18])) # !FB1L66 & (FB1_active_data[18]);
FB1_active_data[18] = DFFEAS(FB1_active_data[18]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[18] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[18] at LC_X40_Y6_N6
--operation mode is normal
EE1_entry_0[18]_lut_out = L1_M_st_data[18];
EE1_entry_0[18] = DFFEAS(EE1_entry_0[18]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L147 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[18]~523 at LC_X41_Y6_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[18]_qfbk = EE1_entry_1[18];
EE1L147 = EE1_rd_address & (EE1_entry_1[18]_qfbk) # !EE1_rd_address & (EE1_entry_0[18]);
--EE1_entry_1[18] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[18] at LC_X41_Y6_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[18] = DFFEAS(EE1L147, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[18], , , VCC);
--FB1L694 is std_1s10:inst|sdram:the_sdram|Mux131~1170 at LC_X41_Y6_N6
--operation mode is normal
FB1L694 = FB1_m_state[1] & FB1_active_data[18] # !FB1_m_state[1] & (FB1_f_select & (EE1L147) # !FB1_f_select & FB1_active_data[18]);
--FB1_active_data[17] is std_1s10:inst|sdram:the_sdram|active_data[17] at LC_X41_Y6_N0
--operation mode is normal
FB1_active_data[17]_lut_out = FB1L14 & (FB1L12 & (EE1L146) # !FB1L12 & FB1_active_data[17]) # !FB1L14 & FB1_active_data[17];
FB1_active_data[17] = DFFEAS(FB1_active_data[17]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[17] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[17] at LC_X40_Y6_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[17]_lut_out = GND;
EE1_entry_0[17] = DFFEAS(EE1_entry_0[17]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, L1_M_st_data[17], , , VCC);
--EE1L146 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[17]~524 at LC_X41_Y6_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[17]_qfbk = EE1_entry_1[17];
EE1L146 = EE1_rd_address & (EE1_entry_1[17]_qfbk) # !EE1_rd_address & (EE1_entry_0[17]);
--EE1_entry_1[17] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[17] at LC_X41_Y6_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[17] = DFFEAS(EE1L146, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[17], , , VCC);
--FB1L695 is std_1s10:inst|sdram:the_sdram|Mux132~1170 at LC_X41_Y6_N5
--operation mode is normal
FB1L695 = FB1_m_state[1] & (FB1_active_data[17]) # !FB1_m_state[1] & (FB1_f_select & EE1L146 # !FB1_f_select & (FB1_active_data[17]));
--FB1_active_data[16] is std_1s10:inst|sdram:the_sdram|active_data[16] at LC_X40_Y5_N8
--operation mode is normal
FB1_active_data[16]_lut_out = FB1L65 & (FB1L66 & EE1L145 # !FB1L66 & (FB1_active_data[16])) # !FB1L65 & (FB1_active_data[16]);
FB1_active_data[16] = DFFEAS(FB1_active_data[16]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[16] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[16] at LC_X36_Y8_N5
--operation mode is normal
EE1_entry_0[16]_lut_out = L1_M_st_data[16];
EE1_entry_0[16] = DFFEAS(EE1_entry_0[16]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L145 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[16]~525 at LC_X36_Y6_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[16]_qfbk = EE1_entry_1[16];
EE1L145 = EE1_rd_address & EE1_entry_1[16]_qfbk # !EE1_rd_address & (EE1_entry_0[16]);
--EE1_entry_1[16] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[16] at LC_X36_Y6_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[16] = DFFEAS(EE1L145, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[16], , , VCC);
--FB1L696 is std_1s10:inst|sdram:the_sdram|Mux133~1170 at LC_X41_Y6_N8
--operation mode is normal
FB1L696 = FB1_m_state[1] & FB1_active_data[16] # !FB1_m_state[1] & (FB1_f_select & (EE1L145) # !FB1_f_select & FB1_active_data[16]);
--FB1_active_data[15] is std_1s10:inst|sdram:the_sdram|active_data[15] at LC_X44_Y4_N6
--operation mode is normal
FB1_active_data[15]_lut_out = FB1L12 & (FB1L14 & (EE1L144) # !FB1L14 & FB1_active_data[15]) # !FB1L12 & FB1_active_data[15];
FB1_active_data[15] = DFFEAS(FB1_active_data[15]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[15] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[15] at LC_X36_Y8_N2
--operation mode is normal
EE1_entry_0[15]_lut_out = L1_M_st_data[15];
EE1_entry_0[15] = DFFEAS(EE1_entry_0[15]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L144 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[15]~526 at LC_X44_Y4_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[15]_qfbk = EE1_entry_1[15];
EE1L144 = EE1_rd_address & (EE1_entry_1[15]_qfbk) # !EE1_rd_address & (EE1_entry_0[15]);
--EE1_entry_1[15] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[15] at LC_X44_Y4_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[15] = DFFEAS(EE1L144, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[15], , , VCC);
--FB1L697 is std_1s10:inst|sdram:the_sdram|Mux134~1170 at LC_X44_Y4_N5
--operation mode is normal
FB1L697 = FB1_m_state[1] & FB1_active_data[15] # !FB1_m_state[1] & (FB1_f_select & (EE1L144) # !FB1_f_select & FB1_active_data[15]);
--FB1_active_data[14] is std_1s10:inst|sdram:the_sdram|active_data[14] at LC_X44_Y4_N0
--operation mode is normal
FB1_active_data[14]_lut_out = FB1L65 & (FB1L66 & EE1L143 # !FB1L66 & (FB1_active_data[14])) # !FB1L65 & (FB1_active_data[14]);
FB1_active_data[14] = DFFEAS(FB1_active_data[14]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[14] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[14] at LC_X36_Y8_N9
--operation mode is normal
EE1_entry_0[14]_lut_out = L1_M_st_data[14];
EE1_entry_0[14] = DFFEAS(EE1_entry_0[14]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L143 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[14]~527 at LC_X44_Y4_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[14]_qfbk = EE1_entry_1[14];
EE1L143 = EE1_rd_address & (EE1_entry_1[14]_qfbk) # !EE1_rd_address & (EE1_entry_0[14]);
--EE1_entry_1[14] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[14] at LC_X44_Y4_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[14] = DFFEAS(EE1L143, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[14], , , VCC);
--FB1L698 is std_1s10:inst|sdram:the_sdram|Mux135~1170 at LC_X44_Y4_N3
--operation mode is normal
FB1L698 = FB1_m_state[1] & FB1_active_data[14] # !FB1_m_state[1] & (FB1_f_select & (EE1L143) # !FB1_f_select & FB1_active_data[14]);
--FB1_active_data[13] is std_1s10:inst|sdram:the_sdram|active_data[13] at LC_X39_Y5_N8
--operation mode is normal
FB1_active_data[13]_lut_out = FB1L12 & (FB1L14 & EE1L142 # !FB1L14 & (FB1_active_data[13])) # !FB1L12 & (FB1_active_data[13]);
FB1_active_data[13] = DFFEAS(FB1_active_data[13]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[13] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[13] at LC_X36_Y8_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[13]_lut_out = GND;
EE1_entry_0[13] = DFFEAS(EE1_entry_0[13]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, L1_M_st_data[13], , , VCC);
--EE1L142 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[13]~528 at LC_X36_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[13]_qfbk = EE1_entry_1[13];
EE1L142 = EE1_rd_address & EE1_entry_1[13]_qfbk # !EE1_rd_address & (EE1_entry_0[13]);
--EE1_entry_1[13] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[13] at LC_X36_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[13] = DFFEAS(EE1L142, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[13], , , VCC);
--FB1L699 is std_1s10:inst|sdram:the_sdram|Mux136~1170 at LC_X44_Y4_N8
--operation mode is normal
FB1L699 = FB1_m_state[1] & (FB1_active_data[13]) # !FB1_m_state[1] & (FB1_f_select & EE1L142 # !FB1_f_select & (FB1_active_data[13]));
--FB1_active_data[12] is std_1s10:inst|sdram:the_sdram|active_data[12] at LC_X44_Y6_N6
--operation mode is normal
FB1_active_data[12]_lut_out = FB1L66 & (FB1L65 & (EE1L141) # !FB1L65 & FB1_active_data[12]) # !FB1L66 & FB1_active_data[12];
FB1_active_data[12] = DFFEAS(FB1_active_data[12]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[12] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[12] at LC_X36_Y8_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[12]_lut_out = GND;
EE1_entry_0[12] = DFFEAS(EE1_entry_0[12]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, L1_M_st_data[12], , , VCC);
--EE1L141 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[12]~529 at LC_X44_Y6_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[12]_qfbk = EE1_entry_1[12];
EE1L141 = EE1_rd_address & (EE1_entry_1[12]_qfbk) # !EE1_rd_address & EE1_entry_0[12];
--EE1_entry_1[12] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[12] at LC_X44_Y6_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[12] = DFFEAS(EE1L141, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[12], , , VCC);
--FB1L700 is std_1s10:inst|sdram:the_sdram|Mux137~1170 at LC_X44_Y6_N5
--operation mode is normal
FB1L700 = FB1_m_state[1] & FB1_active_data[12] # !FB1_m_state[1] & (FB1_f_select & (EE1L141) # !FB1_f_select & FB1_active_data[12]);
--FB1_active_data[11] is std_1s10:inst|sdram:the_sdram|active_data[11] at LC_X44_Y6_N0
--operation mode is normal
FB1_active_data[11]_lut_out = FB1L12 & (FB1L14 & EE1L140 # !FB1L14 & (FB1_active_data[11])) # !FB1L12 & (FB1_active_data[11]);
FB1_active_data[11] = DFFEAS(FB1_active_data[11]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[11] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[11] at LC_X21_Y22_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[11]_lut_out = GND;
EE1_entry_0[11] = DFFEAS(EE1_entry_0[11]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, L1_M_st_data[11], , , VCC);
--EE1L140 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[11]~530 at LC_X44_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[11]_qfbk = EE1_entry_1[11];
EE1L140 = EE1_rd_address & (EE1_entry_1[11]_qfbk) # !EE1_rd_address & (EE1_entry_0[11]);
--EE1_entry_1[11] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[11] at LC_X44_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[11] = DFFEAS(EE1L140, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[11], , , VCC);
--FB1L701 is std_1s10:inst|sdram:the_sdram|Mux138~1170 at LC_X44_Y6_N3
--operation mode is normal
FB1L701 = FB1_m_state[1] & FB1_active_data[11] # !FB1_m_state[1] & (FB1_f_select & (EE1L140) # !FB1_f_select & FB1_active_data[11]);
--FB1_active_data[10] is std_1s10:inst|sdram:the_sdram|active_data[10] at LC_X45_Y6_N2
--operation mode is normal
FB1_active_data[10]_lut_out = FB1L65 & (FB1L66 & (EE1L139) # !FB1L66 & FB1_active_data[10]) # !FB1L65 & FB1_active_data[10];
FB1_active_data[10] = DFFEAS(FB1_active_data[10]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[10] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[10] at LC_X40_Y6_N9
--operation mode is normal
EE1_entry_0[10]_lut_out = L1_M_st_data[10];
EE1_entry_0[10] = DFFEAS(EE1_entry_0[10]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L139 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[10]~531 at LC_X40_Y6_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[10]_qfbk = EE1_entry_1[10];
EE1L139 = EE1_rd_address & EE1_entry_1[10]_qfbk # !EE1_rd_address & (EE1_entry_0[10]);
--EE1_entry_1[10] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[10] at LC_X40_Y6_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[10] = DFFEAS(EE1L139, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[10], , , VCC);
--FB1L702 is std_1s10:inst|sdram:the_sdram|Mux139~1170 at LC_X44_Y6_N7
--operation mode is normal
FB1L702 = FB1_m_state[1] & (FB1_active_data[10]) # !FB1_m_state[1] & (FB1_f_select & EE1L139 # !FB1_f_select & (FB1_active_data[10]));
--FB1_active_data[9] is std_1s10:inst|sdram:the_sdram|active_data[9] at LC_X44_Y3_N2
--operation mode is normal
FB1_active_data[9]_lut_out = FB1L12 & (FB1L14 & EE1L138 # !FB1L14 & (FB1_active_data[9])) # !FB1L12 & (FB1_active_data[9]);
FB1_active_data[9] = DFFEAS(FB1_active_data[9]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[9] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[9] at LC_X21_Y22_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[9]_lut_out = GND;
EE1_entry_0[9] = DFFEAS(EE1_entry_0[9]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, L1_M_st_data[9], , , VCC);
--EE1L138 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[9]~532 at LC_X44_Y3_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[9]_qfbk = EE1_entry_1[9];
EE1L138 = EE1_rd_address & (EE1_entry_1[9]_qfbk) # !EE1_rd_address & (EE1_entry_0[9]);
--EE1_entry_1[9] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[9] at LC_X44_Y3_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[9] = DFFEAS(EE1L138, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[9], , , VCC);
--FB1L703 is std_1s10:inst|sdram:the_sdram|Mux140~1170 at LC_X44_Y3_N8
--operation mode is normal
FB1L703 = FB1_m_state[1] & (FB1_active_data[9]) # !FB1_m_state[1] & (FB1_f_select & EE1L138 # !FB1_f_select & (FB1_active_data[9]));
--FB1_active_data[8] is std_1s10:inst|sdram:the_sdram|active_data[8] at LC_X44_Y3_N0
--operation mode is normal
FB1_active_data[8]_lut_out = FB1L66 & (FB1L65 & EE1L137 # !FB1L65 & (FB1_active_data[8])) # !FB1L66 & (FB1_active_data[8]);
FB1_active_data[8] = DFFEAS(FB1_active_data[8]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[8] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[8] at LC_X36_Y8_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[8]_lut_out = GND;
EE1_entry_0[8] = DFFEAS(EE1_entry_0[8]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, L1_M_st_data[8], , , VCC);
--EE1L137 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[8]~533 at LC_X44_Y3_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[8]_qfbk = EE1_entry_1[8];
EE1L137 = EE1_rd_address & (EE1_entry_1[8]_qfbk) # !EE1_rd_address & (EE1_entry_0[8]);
--EE1_entry_1[8] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[8] at LC_X44_Y3_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[8] = DFFEAS(EE1L137, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[8], , , VCC);
--FB1L704 is std_1s10:inst|sdram:the_sdram|Mux141~1170 at LC_X44_Y3_N6
--operation mode is normal
FB1L704 = FB1_m_state[1] & FB1_active_data[8] # !FB1_m_state[1] & (FB1_f_select & (EE1L137) # !FB1_f_select & FB1_active_data[8]);
--FB1_active_data[7] is std_1s10:inst|sdram:the_sdram|active_data[7] at LC_X39_Y5_N9
--operation mode is normal
FB1_active_data[7]_lut_out = FB1L12 & (FB1L14 & EE1L136 # !FB1L14 & (FB1_active_data[7])) # !FB1L12 & (FB1_active_data[7]);
FB1_active_data[7] = DFFEAS(FB1_active_data[7]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[7] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[7] at LC_X44_Y5_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[7]_lut_out = GND;
EE1_entry_0[7] = DFFEAS(EE1_entry_0[7]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, L1_M_st_data[7], , , VCC);
--EE1L136 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[7]~534 at LC_X44_Y5_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[7]_qfbk = EE1_entry_1[7];
EE1L136 = EE1_rd_address & (EE1_entry_1[7]_qfbk) # !EE1_rd_address & (EE1_entry_0[7]);
--EE1_entry_1[7] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[7] at LC_X44_Y5_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[7] = DFFEAS(EE1L136, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[7], , , VCC);
--FB1L705 is std_1s10:inst|sdram:the_sdram|Mux142~1170 at LC_X44_Y3_N3
--operation mode is normal
FB1L705 = FB1_m_state[1] & (FB1_active_data[7]) # !FB1_m_state[1] & (FB1_f_select & EE1L136 # !FB1_f_select & (FB1_active_data[7]));
--FB1_active_data[6] is std_1s10:inst|sdram:the_sdram|active_data[6] at LC_X45_Y5_N8
--operation mode is normal
FB1_active_data[6]_lut_out = FB1L66 & (FB1L65 & EE1L135 # !FB1L65 & (FB1_active_data[6])) # !FB1L66 & (FB1_active_data[6]);
FB1_active_data[6] = DFFEAS(FB1_active_data[6]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[6] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[6] at LC_X44_Y5_N4
--operation mode is normal
EE1_entry_0[6]_lut_out = L1_M_st_data[6];
EE1_entry_0[6] = DFFEAS(EE1_entry_0[6]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L135 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[6]~535 at LC_X45_Y5_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[6]_qfbk = EE1_entry_1[6];
EE1L135 = EE1_rd_address & (EE1_entry_1[6]_qfbk) # !EE1_rd_address & (EE1_entry_0[6]);
--EE1_entry_1[6] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[6] at LC_X45_Y5_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[6] = DFFEAS(EE1L135, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[6], , , VCC);
--FB1L706 is std_1s10:inst|sdram:the_sdram|Mux143~1170 at LC_X45_Y5_N5
--operation mode is normal
FB1L706 = FB1_m_state[1] & (FB1_active_data[6]) # !FB1_m_state[1] & (FB1_f_select & EE1L135 # !FB1_f_select & (FB1_active_data[6]));
--FB1_active_data[5] is std_1s10:inst|sdram:the_sdram|active_data[5] at LC_X45_Y5_N0
--operation mode is normal
FB1_active_data[5]_lut_out = FB1L12 & (FB1L14 & EE1L134 # !FB1L14 & (FB1_active_data[5])) # !FB1L12 & (FB1_active_data[5]);
FB1_active_data[5] = DFFEAS(FB1_active_data[5]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[5] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[5] at LC_X44_Y5_N2
--operation mode is normal
EE1_entry_0[5]_lut_out = L1_M_st_data[5];
EE1_entry_0[5] = DFFEAS(EE1_entry_0[5]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L134 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[5]~536 at LC_X45_Y5_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[5]_qfbk = EE1_entry_1[5];
EE1L134 = EE1_rd_address & (EE1_entry_1[5]_qfbk) # !EE1_rd_address & (EE1_entry_0[5]);
--EE1_entry_1[5] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[5] at LC_X45_Y5_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[5] = DFFEAS(EE1L134, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[5], , , VCC);
--FB1L707 is std_1s10:inst|sdram:the_sdram|Mux144~1170 at LC_X45_Y5_N4
--operation mode is normal
FB1L707 = FB1_f_select & (FB1_m_state[1] & (FB1_active_data[5]) # !FB1_m_state[1] & EE1L134) # !FB1_f_select & (FB1_active_data[5]);
--FB1_active_data[4] is std_1s10:inst|sdram:the_sdram|active_data[4] at LC_X45_Y6_N4
--operation mode is normal
FB1_active_data[4]_lut_out = FB1L65 & (FB1L66 & EE1L133 # !FB1L66 & (FB1_active_data[4])) # !FB1L65 & (FB1_active_data[4]);
FB1_active_data[4] = DFFEAS(FB1_active_data[4]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[4] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[4] at LC_X44_Y5_N0
--operation mode is normal
EE1_entry_0[4]_lut_out = L1_M_st_data[4];
EE1_entry_0[4] = DFFEAS(EE1_entry_0[4]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L133 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[4]~537 at LC_X44_Y5_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[4]_qfbk = EE1_entry_1[4];
EE1L133 = EE1_rd_address & (EE1_entry_1[4]_qfbk) # !EE1_rd_address & (EE1_entry_0[4]);
--EE1_entry_1[4] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[4] at LC_X44_Y5_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[4] = DFFEAS(EE1L133, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[4], , , VCC);
--FB1L708 is std_1s10:inst|sdram:the_sdram|Mux145~1170 at LC_X45_Y5_N2
--operation mode is normal
FB1L708 = FB1_f_select & (FB1_m_state[1] & (FB1_active_data[4]) # !FB1_m_state[1] & EE1L133) # !FB1_f_select & (FB1_active_data[4]);
--FB1_active_data[3] is std_1s10:inst|sdram:the_sdram|active_data[3] at LC_X45_Y4_N4
--operation mode is normal
FB1_active_data[3]_lut_out = FB1L14 & (FB1L12 & EE1L132 # !FB1L12 & (FB1_active_data[3])) # !FB1L14 & (FB1_active_data[3]);
FB1_active_data[3] = DFFEAS(FB1_active_data[3]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[3] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[3] at LC_X44_Y5_N1
--operation mode is normal
EE1_entry_0[3]_lut_out = L1_M_st_data[3];
EE1_entry_0[3] = DFFEAS(EE1_entry_0[3]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, , , , );
--EE1L132 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[3]~538 at LC_X45_Y4_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[3]_qfbk = EE1_entry_1[3];
EE1L132 = EE1_rd_address & EE1_entry_1[3]_qfbk # !EE1_rd_address & (EE1_entry_0[3]);
--EE1_entry_1[3] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[3] at LC_X45_Y4_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[3] = DFFEAS(EE1L132, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[3], , , VCC);
--FB1L709 is std_1s10:inst|sdram:the_sdram|Mux146~1170 at LC_X45_Y4_N5
--operation mode is normal
FB1L709 = FB1_m_state[1] & (FB1_active_data[3]) # !FB1_m_state[1] & (FB1_f_select & EE1L132 # !FB1_f_select & (FB1_active_data[3]));
--FB1_active_data[2] is std_1s10:inst|sdram:the_sdram|active_data[2] at LC_X45_Y4_N0
--operation mode is normal
FB1_active_data[2]_lut_out = FB1L65 & (FB1L66 & (EE1L131) # !FB1L66 & FB1_active_data[2]) # !FB1L65 & FB1_active_data[2];
FB1_active_data[2] = DFFEAS(FB1_active_data[2]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[2] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[2] at LC_X44_Y5_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[2]_lut_out = GND;
EE1_entry_0[2] = DFFEAS(EE1_entry_0[2]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, L1_M_st_data[2], , , VCC);
--EE1L131 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[2]~539 at LC_X45_Y4_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[2]_qfbk = EE1_entry_1[2];
EE1L131 = EE1_rd_address & EE1_entry_1[2]_qfbk # !EE1_rd_address & (EE1_entry_0[2]);
--EE1_entry_1[2] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[2] at LC_X45_Y4_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[2] = DFFEAS(EE1L131, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[2], , , VCC);
--FB1L710 is std_1s10:inst|sdram:the_sdram|Mux147~1170 at LC_X45_Y4_N9
--operation mode is normal
FB1L710 = FB1_m_state[1] & (FB1_active_data[2]) # !FB1_m_state[1] & (FB1_f_select & EE1L131 # !FB1_f_select & (FB1_active_data[2]));
--FB1_active_data[1] is std_1s10:inst|sdram:the_sdram|active_data[1] at LC_X39_Y5_N4
--operation mode is normal
FB1_active_data[1]_lut_out = FB1L14 & (FB1L12 & EE1L130 # !FB1L12 & (FB1_active_data[1])) # !FB1L14 & (FB1_active_data[1]);
FB1_active_data[1] = DFFEAS(FB1_active_data[1]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[1] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[1] at LC_X44_Y5_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[1]_lut_out = GND;
EE1_entry_0[1] = DFFEAS(EE1_entry_0[1]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, L1_M_st_data[1], , , VCC);
--EE1L130 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[1]~540 at LC_X44_Y5_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[1]_qfbk = EE1_entry_1[1];
EE1L130 = EE1_rd_address & (EE1_entry_1[1]_qfbk) # !EE1_rd_address & (EE1_entry_0[1]);
--EE1_entry_1[1] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[1] at LC_X44_Y5_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[1] = DFFEAS(EE1L130, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[1], , , VCC);
--FB1L711 is std_1s10:inst|sdram:the_sdram|Mux148~1170 at LC_X45_Y4_N1
--operation mode is normal
FB1L711 = FB1_m_state[1] & (FB1_active_data[1]) # !FB1_m_state[1] & (FB1_f_select & EE1L130 # !FB1_f_select & (FB1_active_data[1]));
--FB1_active_data[0] is std_1s10:inst|sdram:the_sdram|active_data[0] at LC_X40_Y5_N0
--operation mode is normal
FB1_active_data[0]_lut_out = FB1L66 & (FB1L65 & EE1L129 # !FB1L65 & (FB1_active_data[0])) # !FB1L66 & (FB1_active_data[0]);
FB1_active_data[0] = DFFEAS(FB1_active_data[0]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--EE1_entry_0[0] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[0] at LC_X21_Y28_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_0[0]_lut_out = GND;
EE1_entry_0[0] = DFFEAS(EE1_entry_0[0]_lut_out, GLOBAL(DE1__clk0), VCC, , EE1L62, L1_M_st_data[0], , , VCC);
--EE1L129 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_data[0]~541 at LC_X40_Y5_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[0]_qfbk = EE1_entry_1[0];
EE1L129 = EE1_rd_address & EE1_entry_1[0]_qfbk # !EE1_rd_address & (EE1_entry_0[0]);
--EE1_entry_1[0] is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[0] at LC_X40_Y5_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
EE1_entry_1[0] = DFFEAS(EE1L129, GLOBAL(DE1__clk0), VCC, , EE1L123, L1_M_st_data[0], , , VCC);
--FB1L712 is std_1s10:inst|sdram:the_sdram|Mux149~1170 at LC_X40_Y5_N6
--operation mode is normal
FB1L712 = FB1_f_select & (FB1_m_state[1] & (FB1_active_data[0]) # !FB1_m_state[1] & EE1L129) # !FB1_f_select & (FB1_active_data[0]);
--L1L124 is std_1s10:inst|cpu:the_cpu|Add6~104 at LC_X41_Y13_N7
--operation mode is normal
L1L124 = AMPP_FUNCTION(L1_ic_fill_ap_cnt[0], L1_ic_fill_ap_cnt[1]);
--GB1L63 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_counter_enable~42 at LC_X39_Y10_N0
--operation mode is normal
GB1L63 = GB1_WideOr1 # !GB1L28 & !GB1L24;
--L1L33 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12914 at LC_X27_Y20_N8
--operation mode is normal
L1L33 = AMPP_FUNCTION(L1_D_issue, L1L966, L1L172, L1L110);
--L1_M_pipe_flush_waddr[12] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[12] at LC_X33_Y16_N9
--operation mode is normal
L1_M_pipe_flush_waddr[12] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_jmp_indirect, L1L47, L1_E_pc[12], L1L617, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L34 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12915 at LC_X34_Y16_N9
--operation mode is normal
L1L34 = AMPP_FUNCTION(L1L92, L1_D_issue, L1L978, L1L172);
--L1_M_pipe_flush_waddr[16] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[16] at LC_X33_Y16_N3
--operation mode is normal
L1_M_pipe_flush_waddr[16] = AMPP_FUNCTION(DE1__clk0, L1L48, L1_E_ctrl_jmp_indirect, L1_E_pc[16], L1L621, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1_ic_tag_clr_valid_bits is std_1s10:inst|cpu:the_cpu|ic_tag_clr_valid_bits at LC_X36_Y18_N7
--operation mode is normal
L1_ic_tag_clr_valid_bits = AMPP_FUNCTION(DE1__clk0, L1_ic_tag_clr_valid_bits_nxt, E1_data_out);
--L1_ic_tag_wren is std_1s10:inst|cpu:the_cpu|ic_tag_wren at LC_X36_Y18_N6
--operation mode is normal
L1_ic_tag_wren = AMPP_FUNCTION(L1_i_readdatavalid_d1, L1_ic_tag_clr_valid_bits);
--L1_ic_tag_wraddress[0] is std_1s10:inst|cpu:the_cpu|ic_tag_wraddress[0] at LC_X35_Y21_N9
--operation mode is normal
L1_ic_tag_wraddress[0] = AMPP_FUNCTION(DE1__clk0, L1L1075, L1_M_alu_result[5], L1_reset_d1, L1L1077, E1_data_out);
--L1L882 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[0]~4242 at LC_X35_Y20_N0
--operation mode is normal
L1L882 = AMPP_FUNCTION(L1_D_issue, L1L941, L1L172, L1_D_br_taken_waddr_partial[3]);
--L1_M_pipe_flush_waddr[3] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[3] at LC_X33_Y16_N2
--operation mode is normal
L1_M_pipe_flush_waddr[3] = AMPP_FUNCTION(DE1__clk0, L1L608, L1_E_ctrl_jmp_indirect, L1_E_pc[3], L1L49, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L883 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[0]~4243 at LC_X33_Y16_N4
--operation mode is normal
L1L883 = AMPP_FUNCTION(L1_M_pipe_flush, L1L884, L1_M_pipe_flush_waddr[3]);
--L1_F_pc[3] is std_1s10:inst|cpu:the_cpu|F_pc[3] at LC_X33_Y16_N4
--operation mode is normal
L1_F_pc[3] = AMPP_FUNCTION(DE1__clk0, L1_M_pipe_flush, L1L884, L1_M_pipe_flush_waddr[3], E1_data_out, L1_W_stall);
--L1L885 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[1]~4244 at LC_X35_Y20_N1
--operation mode is normal
L1L885 = AMPP_FUNCTION(L1_D_issue, L1L944, L1L172, L1_D_br_taken_waddr_partial[4]);
--L1_M_pipe_flush_waddr[4] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[4] at LC_X33_Y21_N6
--operation mode is normal
L1_M_pipe_flush_waddr[4] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_jmp_indirect, L1L50, L1_E_pc[4], L1L609, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L886 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[1]~4245 at LC_X33_Y21_N4
--operation mode is normal
L1L886 = AMPP_FUNCTION(L1_M_pipe_flush, L1L887, L1_M_pipe_flush_waddr[4]);
--L1_F_pc[4] is std_1s10:inst|cpu:the_cpu|F_pc[4] at LC_X33_Y21_N4
--operation mode is normal
L1_F_pc[4] = AMPP_FUNCTION(DE1__clk0, L1_M_pipe_flush, L1L887, L1_M_pipe_flush_waddr[4], E1_data_out, L1_W_stall);
--L1L888 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[2]~4246 at LC_X35_Y19_N8
--operation mode is normal
L1L888 = AMPP_FUNCTION(L1_D_issue, L1L172, L1L947, L1_D_br_taken_waddr_partial[5]);
--L1_M_pipe_flush_waddr[5] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[5] at LC_X33_Y21_N5
--operation mode is normal
L1_M_pipe_flush_waddr[5] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_jmp_indirect, L1L610, L1_E_pc[5], L1L51, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L889 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[2]~4247 at LC_X35_Y18_N2
--operation mode is normal
L1L889 = AMPP_FUNCTION(L1_M_pipe_flush, L1L890, L1_M_pipe_flush_waddr[5]);
--L1_F_pc[5] is std_1s10:inst|cpu:the_cpu|F_pc[5] at LC_X35_Y18_N2
--operation mode is normal
L1_F_pc[5] = AMPP_FUNCTION(DE1__clk0, L1_M_pipe_flush, L1L890, L1_M_pipe_flush_waddr[5], E1_data_out, L1_W_stall);
--L1L891 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[3]~4248 at LC_X35_Y19_N9
--operation mode is normal
L1L891 = AMPP_FUNCTION(L1_D_issue, L1L172, L1L950, L1_D_br_taken_waddr_partial[6]);
--L1_M_pipe_flush_waddr[6] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[6] at LC_X33_Y21_N8
--operation mode is normal
L1_M_pipe_flush_waddr[6] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_jmp_indirect, L1L52, L1_E_pc[6], L1L611, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L892 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[3]~4249 at LC_X34_Y16_N4
--operation mode is normal
L1L892 = AMPP_FUNCTION(L1_M_pipe_flush, L1_M_pipe_flush_waddr[6], L1L893);
--L1_F_pc[6] is std_1s10:inst|cpu:the_cpu|F_pc[6] at LC_X34_Y16_N4
--operation mode is normal
L1_F_pc[6] = AMPP_FUNCTION(DE1__clk0, L1_M_pipe_flush, L1_M_pipe_flush_waddr[6], L1L893, E1_data_out, L1_W_stall);
--L1L894 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[4]~4250 at LC_X35_Y19_N7
--operation mode is normal
L1L894 = AMPP_FUNCTION(L1_D_issue, L1_D_br_taken_waddr_partial[7], L1L172, L1L952);
--L1_M_pipe_flush_waddr[7] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[7] at LC_X32_Y20_N7
--operation mode is normal
L1_M_pipe_flush_waddr[7] = AMPP_FUNCTION(DE1__clk0, L1L612, L1L53, L1_E_pc[7], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L895 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[4]~4251 at LC_X32_Y20_N6
--operation mode is normal
L1L895 = AMPP_FUNCTION(L1L896, L1_M_pipe_flush_waddr[7], L1_M_pipe_flush);
--L1_F_pc[7] is std_1s10:inst|cpu:the_cpu|F_pc[7] at LC_X32_Y20_N6
--operation mode is normal
L1_F_pc[7] = AMPP_FUNCTION(DE1__clk0, L1L896, L1_M_pipe_flush_waddr[7], L1_M_pipe_flush, E1_data_out, L1_W_stall);
--L1L897 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~4252 at LC_X35_Y19_N6
--operation mode is normal
L1L897 = AMPP_FUNCTION(L1_D_issue, L1L172, L1_D_br_taken_waddr_partial[8], L1L955);
--L1_M_pipe_flush_waddr[8] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[8] at LC_X33_Y21_N2
--operation mode is normal
L1_M_pipe_flush_waddr[8] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_jmp_indirect, L1L613, L1_E_pc[8], L1L54, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L898 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~4253 at LC_X35_Y18_N4
--operation mode is normal
L1L898 = AMPP_FUNCTION(L1L899, L1_M_pipe_flush, L1_M_pipe_flush_waddr[8]);
--L1_F_pc[8] is std_1s10:inst|cpu:the_cpu|F_pc[8] at LC_X35_Y18_N4
--operation mode is normal
L1_F_pc[8] = AMPP_FUNCTION(DE1__clk0, L1L899, L1_M_pipe_flush, L1_M_pipe_flush_waddr[8], E1_data_out, L1_W_stall);
--L1L900 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[6]~4254 at LC_X30_Y20_N9
--operation mode is normal
L1L900 = AMPP_FUNCTION(L1_D_issue, L1_D_br_taken_waddr_partial[9], L1L958, L1L172);
--L1_M_pipe_flush_waddr[9] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[9] at LC_X25_Y21_N5
--operation mode is normal
L1_M_pipe_flush_waddr[9] = AMPP_FUNCTION(DE1__clk0, L1L55, L1L614, L1_E_pc[9], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L901 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[6]~4255 at LC_X30_Y20_N7
--operation mode is normal
L1L901 = AMPP_FUNCTION(L1_M_pipe_flush_waddr[9], L1L902, L1_M_pipe_flush);
--L1_F_pc[9] is std_1s10:inst|cpu:the_cpu|F_pc[9] at LC_X30_Y20_N7
--operation mode is normal
L1_F_pc[9] = AMPP_FUNCTION(DE1__clk0, L1_M_pipe_flush_waddr[9], L1L902, L1_M_pipe_flush, E1_data_out, L1_W_stall);
--L1L35 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12916 at LC_X34_Y17_N1
--operation mode is normal
L1L35 = AMPP_FUNCTION(L1_D_issue, L1L172, L1L81, L1L989);
--L1_M_pipe_flush_waddr[20] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[20] at LC_X33_Y21_N1
--operation mode is normal
L1_M_pipe_flush_waddr[20] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_jmp_indirect, L1L56, L1_E_pc[20], L1L625, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L36 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12917 at LC_X33_Y18_N2
--operation mode is normal
L1L36 = AMPP_FUNCTION(L1L172, L1_D_issue, L1L83, L1L986);
--L1_M_pipe_flush_waddr[19] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[19] at LC_X33_Y12_N4
--operation mode is normal
L1_M_pipe_flush_waddr[19] = AMPP_FUNCTION(DE1__clk0, L1L624, L1_E_ctrl_jmp_indirect, L1_E_pc[19], L1L57, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L37 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12918 at LC_X33_Y17_N4
--operation mode is normal
L1L37 = AMPP_FUNCTION(L1L172, L1_D_issue, L1L983, L1L104);
--L1_M_pipe_flush_waddr[18] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[18] at LC_X33_Y12_N6
--operation mode is normal
L1_M_pipe_flush_waddr[18] = AMPP_FUNCTION(DE1__clk0, L1L58, L1_E_ctrl_jmp_indirect, L1_E_pc[18], L1L623, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L38 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12919 at LC_X33_Y17_N3
--operation mode is normal
L1L38 = AMPP_FUNCTION(L1L172, L1_D_issue, L1L89, L1L980);
--L1_M_pipe_flush_waddr[17] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[17] at LC_X33_Y12_N2
--operation mode is normal
L1_M_pipe_flush_waddr[17] = AMPP_FUNCTION(DE1__clk0, L1L622, L1L59, L1_E_pc[17], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L39 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12920 at LC_X33_Y15_N9
--operation mode is normal
L1L39 = AMPP_FUNCTION(L1L172, L1_D_issue, L1L100, L1L992);
--L1_M_pipe_flush_waddr[21] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[21] at LC_X33_Y12_N8
--operation mode is normal
L1_M_pipe_flush_waddr[21] = AMPP_FUNCTION(DE1__clk0, L1L626, L1L61, L1_E_pc[21], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L40 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12921 at LC_X28_Y20_N6
--operation mode is normal
L1L40 = AMPP_FUNCTION(L1L172, L1_D_issue, L1L972, L1L97);
--L1_M_pipe_flush_waddr[14] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[14] at LC_X33_Y16_N7
--operation mode is normal
L1_M_pipe_flush_waddr[14] = AMPP_FUNCTION(DE1__clk0, L1L619, L1_E_ctrl_jmp_indirect, L1_E_pc[14], L1L63, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L41 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12922 at LC_X34_Y14_N2
--operation mode is normal
L1L41 = AMPP_FUNCTION(L1_D_issue, L1L172, L1L113, L1L964);
--L1_M_pipe_flush_waddr[11] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[11] at LC_X33_Y12_N9
--operation mode is normal
L1_M_pipe_flush_waddr[11] = AMPP_FUNCTION(DE1__clk0, L1L616, L1L64, L1_E_pc[11], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L42 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12923 at LC_X33_Y15_N7
--operation mode is normal
L1L42 = AMPP_FUNCTION(L1L172, L1L994, L1L86, L1_D_issue);
--L1_M_pipe_flush_waddr[22] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[22] at LC_X33_Y12_N0
--operation mode is normal
L1_M_pipe_flush_waddr[22] = AMPP_FUNCTION(DE1__clk0, L1L627, L1L66, L1_E_pc[22], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L43 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12924 at LC_X33_Y14_N3
--operation mode is normal
L1L43 = AMPP_FUNCTION(L1L172, L1L997, L1_D_issue, L1L103);
--L1_M_pipe_flush_waddr[23] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[23] at LC_X18_Y13_N7
--operation mode is normal
L1_M_pipe_flush_waddr[23] = AMPP_FUNCTION(DE1__clk0, L1L67, L1_E_ctrl_jmp_indirect, L1_E_pc[23], L1L628, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L44 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12925 at LC_X33_Y18_N8
--operation mode is normal
L1L44 = AMPP_FUNCTION(L1L172, L1_D_issue, L1L975, L1L95);
--L1_M_pipe_flush_waddr[15] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[15] at LC_X33_Y10_N6
--operation mode is normal
L1_M_pipe_flush_waddr[15] = AMPP_FUNCTION(DE1__clk0, L1L620, L1L68, L1_E_pc[15], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L45 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12926 at LC_X34_Y17_N8
--operation mode is normal
L1L45 = AMPP_FUNCTION(L1_D_issue, L1L172, L1L969, L1L107);
--L1_M_pipe_flush_waddr[13] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[13] at LC_X33_Y10_N8
--operation mode is normal
L1_M_pipe_flush_waddr[13] = AMPP_FUNCTION(DE1__clk0, L1L69, L1L618, L1_E_pc[13], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L46 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12927 at LC_X34_Y17_N3
--operation mode is normal
L1L46 = AMPP_FUNCTION(L1_D_issue, L1L172, L1L116, L1L961);
--L1_M_pipe_flush_waddr[10] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[10] at LC_X25_Y21_N2
--operation mode is normal
L1_M_pipe_flush_waddr[10] = AMPP_FUNCTION(DE1__clk0, L1L70, L1L615, L1_E_pc[10], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1_ic_fill_valid_bits[5] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[5] at LC_X36_Y18_N9
--operation mode is normal
L1_ic_fill_valid_bits[5] = AMPP_FUNCTION(DE1__clk0, L1L1108, L1_ic_tag_clr_valid_bits_nxt, L1_D_ic_fill_starting_d1, L1_ic_fill_valid_bits[5], E1_data_out, L1_ic_fill_valid_bits_en);
--L1L856 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[2]~1818 at LC_X35_Y17_N7
--operation mode is normal
L1L856 = AMPP_FUNCTION(L1L938, L1L172, L1_D_br_taken_waddr_partial[2], L1_D_issue);
--L1_M_pipe_flush_waddr[2] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[2] at LC_X33_Y10_N3
--operation mode is normal
L1_M_pipe_flush_waddr[2] = AMPP_FUNCTION(DE1__clk0, L1L71, L1L607, L1_E_pc[2], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L857 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[2]~1819 at LC_X35_Y17_N5
--operation mode is normal
L1L857 = AMPP_FUNCTION(L1_M_pipe_flush, L1_M_pipe_flush_waddr[2], L1L858);
--L1_F_pc[2] is std_1s10:inst|cpu:the_cpu|F_pc[2] at LC_X35_Y17_N5
--operation mode is normal
L1_F_pc[2] = AMPP_FUNCTION(DE1__clk0, L1_M_pipe_flush, L1_M_pipe_flush_waddr[2], L1L858, E1_data_out, L1_W_stall);
--L1_ic_fill_valid_bits[3] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[3] at LC_X36_Y18_N3
--operation mode is normal
L1_ic_fill_valid_bits[3] = AMPP_FUNCTION(DE1__clk0, L1L1106, L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, L1_ic_fill_valid_bits[3], E1_data_out, L1_ic_fill_valid_bits_en);
--L1L853 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[1]~1820 at LC_X35_Y17_N9
--operation mode is normal
L1L853 = AMPP_FUNCTION(L1L936, L1_D_br_taken_waddr_partial[1], L1L172, L1_D_issue);
--L1_M_pipe_flush_waddr[1] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[1] at LC_X33_Y10_N9
--operation mode is normal
L1_M_pipe_flush_waddr[1] = AMPP_FUNCTION(DE1__clk0, L1L72, L1L606, L1_E_pc[1], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L854 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[1]~1821 at LC_X35_Y17_N6
--operation mode is normal
L1L854 = AMPP_FUNCTION(L1_M_pipe_flush, L1_M_pipe_flush_waddr[1], L1L855);
--L1_F_pc[1] is std_1s10:inst|cpu:the_cpu|F_pc[1] at LC_X35_Y17_N6
--operation mode is normal
L1_F_pc[1] = AMPP_FUNCTION(DE1__clk0, L1_M_pipe_flush, L1_M_pipe_flush_waddr[1], L1L855, E1_data_out, L1_W_stall);
--L1_ic_fill_valid_bits[1] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[1] at LC_X36_Y18_N2
--operation mode is normal
L1_ic_fill_valid_bits[1] = AMPP_FUNCTION(DE1__clk0, L1L1104, L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, L1_ic_fill_valid_bits[1], E1_data_out, L1_ic_fill_valid_bits_en);
--L1_ic_fill_valid_bits[7] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[7] at LC_X36_Y18_N1
--operation mode is normal
L1_ic_fill_valid_bits[7] = AMPP_FUNCTION(DE1__clk0, L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, L1_ic_fill_valid_bits[7], L1L1109, E1_data_out, L1_ic_fill_valid_bits_en);
--L1_ic_fill_valid_bits[2] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[2] at LC_X36_Y18_N4
--operation mode is normal
L1_ic_fill_valid_bits[2] = AMPP_FUNCTION(DE1__clk0, L1L1105, L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, L1_ic_fill_valid_bits[2], E1_data_out, L1_ic_fill_valid_bits_en);
--L1_ic_fill_valid_bits[4] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[4] at LC_X36_Y18_N5
--operation mode is normal
L1_ic_fill_valid_bits[4] = AMPP_FUNCTION(DE1__clk0, L1L1107, L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, L1_ic_fill_valid_bits[4], E1_data_out, L1_ic_fill_valid_bits_en);
--L1_ic_fill_valid_bits[0] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[0] at LC_X36_Y18_N8
--operation mode is normal
L1_ic_fill_valid_bits[0] = AMPP_FUNCTION(DE1__clk0, L1L1103, L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, L1_ic_fill_valid_bits[0], E1_data_out, L1_ic_fill_valid_bits_en);
--L1_ic_fill_valid_bits[6] is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits[6] at LC_X36_Y18_N0
--operation mode is normal
L1_ic_fill_valid_bits[6] = AMPP_FUNCTION(DE1__clk0, L1L847, L1_D_ic_fill_starting_d1, L1_ic_tag_clr_valid_bits_nxt, L1_ic_fill_valid_bits[6], E1_data_out, L1_ic_fill_valid_bits_en);
--L1L850 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[0]~1822 at LC_X35_Y16_N1
--operation mode is normal
L1L850 = AMPP_FUNCTION(L1_D_br_taken_waddr_partial[0], L1L172, L1L933, L1_D_issue);
--L1_M_pipe_flush_waddr[0] is std_1s10:inst|cpu:the_cpu|M_pipe_flush_waddr[0] at LC_X33_Y10_N2
--operation mode is normal
L1_M_pipe_flush_waddr[0] = AMPP_FUNCTION(DE1__clk0, L1L73, L1L605, L1_E_pc[0], L1_E_ctrl_jmp_indirect, E1_data_out, L1_E_hbreak_req, L1_W_stall);
--L1L851 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[0]~1823 at LC_X35_Y16_N3
--operation mode is normal
L1L851 = AMPP_FUNCTION(L1_M_pipe_flush_waddr[0], L1_M_pipe_flush, L1L852);
--L1_F_pc[0] is std_1s10:inst|cpu:the_cpu|F_pc[0] at LC_X35_Y16_N3
--operation mode is normal
L1_F_pc[0] = AMPP_FUNCTION(DE1__clk0, L1_M_pipe_flush_waddr[0], L1_M_pipe_flush, L1L852, E1_data_out, L1_W_stall);
--L1L452 is std_1s10:inst|cpu:the_cpu|E_ctrl_invalidate_i~117 at LC_X25_Y21_N8
--operation mode is normal
L1L452 = AMPP_FUNCTION(L1_E_iw[16], L1_E_iw[13], L1_E_iw[15], L1_E_iw[11]);
--N1_cpu_instruction_master_read_but_no_slave_selected is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected at LC_X41_Y13_N9
--operation mode is normal
N1_cpu_instruction_master_read_but_no_slave_selected_lut_out = L1_internal_i_read & N1L114 & N1L5 & N1L6;
N1_cpu_instruction_master_read_but_no_slave_selected = DFFEAS(N1_cpu_instruction_master_read_but_no_slave_selected_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--GB1_cpu_instruction_master_read_data_valid_sdram_s1 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_instruction_master_read_data_valid_sdram_s1 at LC_X44_Y16_N7
--operation mode is normal
GB1_cpu_instruction_master_read_data_valid_sdram_s1 = FB1_za_valid & GE1_fifo_contains_ones_n & GE1_stage_0;
--N1_cpu_instruction_master_dbs_rdv_counter[1] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_dbs_rdv_counter[1] at LC_X45_Y17_N5
--operation mode is normal
N1_cpu_instruction_master_dbs_rdv_counter[1]_lut_out = N1_cpu_instruction_master_dbs_rdv_counter[0] $ N1_cpu_instruction_master_dbs_rdv_counter[1];
N1_cpu_instruction_master_dbs_rdv_counter[1] = DFFEAS(N1_cpu_instruction_master_dbs_rdv_counter[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1], , , , );
--N1_cpu_instruction_master_dbs_rdv_counter[0] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_dbs_rdv_counter[0] at LC_X44_Y17_N5
--operation mode is normal
N1_cpu_instruction_master_dbs_rdv_counter[0]_lut_out = !N1_cpu_instruction_master_dbs_rdv_counter[0];
N1_cpu_instruction_master_dbs_rdv_counter[0] = DFFEAS(N1_cpu_instruction_master_dbs_rdv_counter[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1], , , , );
--N1L103 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~60 at LC_X41_Y13_N1
--operation mode is normal
N1L103 = AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register # Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_cpu_instruction_master_dbs_rdv_counter[0] & N1_cpu_instruction_master_dbs_rdv_counter[1];
--N1L104 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdatavalid~61 at LC_X41_Y13_N3
--operation mode is normal
N1L104 = Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] # N1L103 # GB1_cpu_instruction_master_read_data_valid_sdram_s1 # Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--L1L1061 is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[2]~153 at LC_X36_Y19_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L1061 = AMPP_FUNCTION(L1_D_ic_fill_starting_d1);
--L1_ic_fill_initial_offset[2] is std_1s10:inst|cpu:the_cpu|ic_fill_initial_offset[2] at LC_X36_Y19_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_initial_offset[2] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[2], E1_data_out, GND, L1_D_ic_fill_starting);
--L1L1057 is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset_en~1 at LC_X36_Y20_N8
--operation mode is normal
L1L1057 = AMPP_FUNCTION(L1_i_readdatavalid_d1, L1_D_ic_fill_starting_d1);
--L1L1058 is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[0]~154 at LC_X36_Y19_N4
--operation mode is normal
L1L1058 = AMPP_FUNCTION(L1_D_ic_fill_starting_d1, L1_ic_fill_initial_offset[0]);
--L1_ic_fill_dp_offset[0] is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset[0] at LC_X36_Y19_N4
--operation mode is normal
L1_ic_fill_dp_offset[0] = AMPP_FUNCTION(DE1__clk0, L1_D_ic_fill_starting_d1, L1_ic_fill_initial_offset[0], E1_data_out, L1L1057);
--L1L1059 is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset_nxt[1]~155 at LC_X36_Y19_N9
--operation mode is normal
L1L1059 = AMPP_FUNCTION(L1_ic_fill_dp_offset[0], L1_D_ic_fill_starting_d1, L1_ic_fill_initial_offset[1]);
--L1_ic_fill_dp_offset[1] is std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset[1] at LC_X36_Y19_N9
--operation mode is normal
L1_ic_fill_dp_offset[1] = AMPP_FUNCTION(DE1__clk0, L1_ic_fill_dp_offset[0], L1_D_ic_fill_starting_d1, L1_ic_fill_initial_offset[1], E1_data_out, L1L1057);
--Q1L340 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_share_counter_next_value[0]~83 at LC_X39_Y16_N3
--operation mode is normal
Q1L340 = !Q1_ext_ram_bus_avalon_slave_arb_share_counter[0] & Q1L349 & Q1_ext_ram_bus_avalon_slave_arb_share_counter[1];
--FB1_rd_valid[1] is std_1s10:inst|sdram:the_sdram|rd_valid[1] at LC_X40_Y8_N5
--operation mode is normal
FB1_rd_valid[1]_lut_out = FB1_rd_valid[0];
FB1_rd_valid[1] = DFFEAS(FB1_rd_valid[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--GE1_stage_2 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_2 at LC_X44_Y9_N4
--operation mode is normal
GE1_stage_2_lut_out = GE1_full_3 & GE1_stage_3 # !GE1_full_3 & (GB1L25);
GE1_stage_2 = DFFEAS(GE1_stage_2_lut_out, GLOBAL(DE1__clk0), VCC, , GE1L24, , , , );
--GE1_full_2 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_2 at LC_X45_Y9_N8
--operation mode is normal
GE1_full_2_lut_out = GB1L34 & (GE1_full_1) # !GB1L34 & (FB1_za_valid & GE1_full_3 # !FB1_za_valid & (GE1_full_1));
GE1_full_2 = DFFEAS(GE1_full_2_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FE1L13, , , , );
--GE1L25 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process10~1 at LC_X44_Y10_N3
--operation mode is normal
GE1L25 = FB1_za_valid # GB1L34 & !GE1_full_1;
--FE1L13 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|process1~3 at LC_X45_Y9_N3
--operation mode is normal
FE1L13 = FB1_za_valid & (!GE1_full_0 # !GB1L34) # !FB1_za_valid & GB1L34;
--FE1_stage_2 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_2 at LC_X44_Y9_N8
--operation mode is normal
FE1_stage_2_lut_out = GE1_full_3 & FE1_stage_3 # !GE1_full_3 & (GB1L20);
FE1_stage_2 = DFFEAS(FE1_stage_2_lut_out, GLOBAL(DE1__clk0), VCC, , GE1L24, , , , );
--WB1_internal_master_write_done is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_write_done at LC_X47_Y21_N2
--operation mode is normal
WB1_internal_master_write_done_lut_out = WB1_internal_master_write_done $ (WB1_master_state[2] & !WB1_master_state[1] & WB1_master_state[0]);
WB1_internal_master_write_done = DFFEAS(WB1_internal_master_write_done_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--WB1_internal_master_read_done is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read_done at LC_X48_Y21_N5
--operation mode is normal
WB1_internal_master_read_done_lut_out = WB1_internal_master_read_done $ (!WB1_master_state[2] & WB1L3 & WB1L2);
WB1_internal_master_read_done = DFFEAS(WB1_internal_master_read_done_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--DD1_sr[22] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[22] at LC_X32_Y27_N0
--operation mode is normal
DD1_sr[22] = AMPP_FUNCTION(!A1L6, DD1L21, DD1L22, DD1_sr[23], DD1L9, !C1_CLR_SIGNAL, DD1L12);
--FB1L550 is std_1s10:inst|sdram:the_sdram|Mux42~1467 at LC_X34_Y2_N0
--operation mode is normal
FB1L550 = FB1_m_count[0] & (!FB1L519 # !FB1L549) # !FB1_m_count[0] & FB1L549 & FB1L158 & FB1L519;
--FB1L551 is std_1s10:inst|sdram:the_sdram|Mux42~1468 at LC_X34_Y2_N6
--operation mode is normal
FB1L551 = FB1_m_count[0] # FB1L549 & FB1L392 & FB1L519;
--FB1L552 is std_1s10:inst|sdram:the_sdram|Mux42~1469 at LC_X34_Y1_N0
--operation mode is normal
FB1L552 = !FB1_m_state[1] & FB1_m_state[0] & !FB1_m_state[7] & !FB1_m_state[2];
--FB1L553 is std_1s10:inst|sdram:the_sdram|Mux42~1470 at LC_X34_Y1_N3
--operation mode is normal
FB1L553 = EE1L127 & FB1_refresh_request & !FB1L724 & FB1L552;
--FB1L554 is std_1s10:inst|sdram:the_sdram|Mux42~1471 at LC_X34_Y1_N5
--operation mode is normal
FB1L554 = FB1L469 & (FB1_m_state[0] & (FB1L158) # !FB1_m_state[0] & FB1L238);
--FB1L555 is std_1s10:inst|sdram:the_sdram|Mux42~1472 at LC_X34_Y1_N2
--operation mode is normal
FB1L555 = FB1_m_state[2] # FB1_m_state[0] & (FB1_m_state[1] $ !FB1_m_state[7]);
--FB1L556 is std_1s10:inst|sdram:the_sdram|Mux42~1473 at LC_X34_Y1_N1
--operation mode is normal
FB1L556 = FB1_m_state[0] & (FB1_m_state[2] # FB1_m_state[1] $ FB1_m_state[7]);
--FB1L557 is std_1s10:inst|sdram:the_sdram|Mux42~1474 at LC_X34_Y1_N7
--operation mode is normal
FB1L557 = FB1L556 & (FB1L554 $ FB1_m_count[0] # !FB1L555) # !FB1L556 & FB1_m_count[0] & (FB1L555 # !FB1L554);
--FB1L558 is std_1s10:inst|sdram:the_sdram|Mux42~1475 at LC_X34_Y2_N7
--operation mode is normal
FB1L558 = FB1_m_state[8] & (FB1_m_state[5] # FB1L551) # !FB1_m_state[8] & FB1L560 & !FB1_m_state[5];
--FB1_i_refs[0] is std_1s10:inst|sdram:the_sdram|i_refs[0] at LC_X40_Y4_N4
--operation mode is normal
FB1_i_refs[0]_lut_out = FB1_i_refs[0] & (!FB1L148) # !FB1_i_refs[0] & FB1L151;
FB1_i_refs[0] = DFFEAS(FB1_i_refs[0]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--CD1L35 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7313 at LC_X40_Y4_N6
--operation mode is normal
CD1L35 = AMPP_FUNCTION(FB1_i_state[1], FB1_i_refs[0]);
--FB1_i_refs[1] is std_1s10:inst|sdram:the_sdram|i_refs[1] at LC_X40_Y4_N1
--operation mode is normal
FB1_i_refs[1]_lut_out = FB1_i_refs[1] & (FB1L151 & !FB1_i_refs[0] # !FB1L148) # !FB1_i_refs[1] & (FB1L151 & FB1_i_refs[0]);
FB1_i_refs[1] = DFFEAS(FB1_i_refs[1]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--FB1_i_refs[2] is std_1s10:inst|sdram:the_sdram|i_refs[2] at LC_X40_Y4_N9
--operation mode is normal
FB1_i_refs[2]_lut_out = FB1_i_refs[2] & (FB1L151 & !FB1L108 # !FB1L148) # !FB1_i_refs[2] & (FB1L151 & FB1L108);
FB1_i_refs[2] = DFFEAS(FB1_i_refs[2]_lut_out, GLOBAL(DE1__clk0), VCC, , , , , , );
--CD1L36 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7315 at LC_X40_Y4_N8
--operation mode is normal
CD1L36 = AMPP_FUNCTION(FB1_i_state[2], FB1_i_state[1], FB1_i_state[0]);
--FB1_i_count[0] is std_1s10:inst|sdram:the_sdram|i_count[0] at LC_X41_Y3_N9
--operation mode is normal
FB1_i_count[0]_lut_out = FB1L410 & (FB1L157 $ FB1_i_count[0] # !FB1_i_state[0]);
FB1_i_count[0] = DFFEAS(FB1_i_count[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FB1L413, , , , );
--FB1L412 is std_1s10:inst|sdram:the_sdram|Mux10~92 at LC_X41_Y3_N1
--operation mode is normal
FB1L412 = FB1_i_count[2] & (FB1_i_count[1] # FB1_i_count[0]);
--FB1L413 is std_1s10:inst|sdram:the_sdram|Mux10~94 at LC_X40_Y2_N5
--operation mode is normal
FB1L413 = FB1_i_state[1] & (FB1_i_state[0] # !FB1_i_state[2]) # !FB1_i_state[1] & (FB1_i_state[0] & !FB1_i_state[2]);
--FB1L414 is std_1s10:inst|sdram:the_sdram|Mux11~65 at LC_X41_Y3_N5
--operation mode is normal
FB1L414 = FB1_i_count[1] & (FB1_i_count[0]) # !FB1_i_count[1] & (FB1_i_count[2] & !FB1_i_count[0]);
--T1L70 is std_1s10:inst|jtag_uart:the_jtag_uart|process2~43 at LC_X48_Y15_N4
--operation mode is normal
T1L70 = U1L2 & L1_internal_d_write & T1L69 & EB1L2;
--T1L61 is std_1s10:inst|jtag_uart:the_jtag_uart|ien_AE~15 at LC_X50_Y8_N4
--operation mode is normal
T1L61 = L1_M_alu_result[2] & (T1L70);
--ZD1_safe_q[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[5] at LC_X52_Y17_N6
--operation mode is normal
ZD1_safe_q[5]_carry_eqn = (!ZD1L11 & ZD1L15) # (ZD1L11 & ZD1L16);
ZD1_safe_q[5]_lut_out = ZD1_safe_q[5]_carry_eqn $ ZD1_safe_q[5];
ZD1_safe_q[5] = DFFEAS(ZD1_safe_q[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , WD1L1, , , , );
--ZD1_safe_q[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[4] at LC_X52_Y17_N5
--operation mode is arithmetic
ZD1_safe_q[4]_carry_eqn = (!ZD1L11 & GND) # (ZD1L11 & VCC);
ZD1_safe_q[4]_lut_out = ZD1_safe_q[4] $ (!ZD1_safe_q[4]_carry_eqn);
ZD1_safe_q[4] = DFFEAS(ZD1_safe_q[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , WD1L1, , , , );
--ZD1L15 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella4~COUT at LC_X52_Y17_N5
--operation mode is arithmetic
ZD1L15_cout_0 = !ZD1L11 & (ZD1_safe_q[4] $ !T1_fifo_wr);
ZD1L15 = CARRY(ZD1L15_cout_0);
--ZD1L16 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella4~COUTCOUT1_22 at LC_X52_Y17_N5
--operation mode is arithmetic
ZD1L16_cout_1 = !ZD1L11 & (ZD1_safe_q[4] $ !T1_fifo_wr);
ZD1L16 = CARRY(ZD1L16_cout_1);
--ZD1_safe_q[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[3] at LC_X52_Y17_N4
--operation mode is arithmetic
ZD1_safe_q[3]_lut_out = ZD1_safe_q[3] $ (ZD1L8);
ZD1_safe_q[3] = DFFEAS(ZD1_safe_q[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , WD1L1, , , , );
--ZD1L11 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella3~COUT at LC_X52_Y17_N4
--operation mode is arithmetic
--ZD1_safe_q[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[0] at LC_X52_Y17_N1
--operation mode is arithmetic
ZD1_safe_q[0]_lut_out = !ZD1_safe_q[0];
ZD1_safe_q[0] = DFFEAS(ZD1_safe_q[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , WD1L1, , , , );
--ZD1L2 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella0~COUT at LC_X52_Y17_N1
--operation mode is arithmetic
ZD1L2_cout_0 = ZD1_safe_q[0] $ !T1_fifo_wr;
ZD1L2 = CARRY(ZD1L2_cout_0);
--ZD1L3 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella0~COUTCOUT1_22 at LC_X52_Y17_N1
--operation mode is arithmetic
ZD1L3_cout_1 = ZD1_safe_q[0] $ !T1_fifo_wr;
ZD1L3 = CARRY(ZD1L3_cout_1);
--ZD1_safe_q[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[2] at LC_X52_Y17_N3
--operation mode is arithmetic
ZD1_safe_q[2]_lut_out = ZD1_safe_q[2] $ (!ZD1L5);
ZD1_safe_q[2] = DFFEAS(ZD1_safe_q[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , WD1L1, , , , );
--ZD1L8 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella2~COUT at LC_X52_Y17_N3
--operation mode is arithmetic
ZD1L8_cout_0 = !ZD1L5 & (ZD1_safe_q[2] $ !T1_fifo_wr);
ZD1L8 = CARRY(ZD1L8_cout_0);
--ZD1L9 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella2~COUTCOUT1_18 at LC_X52_Y17_N3
--operation mode is arithmetic
ZD1L9_cout_1 = !ZD1L6 & (ZD1_safe_q[2] $ !T1_fifo_wr);
ZD1L9 = CARRY(ZD1L9_cout_1);
--ZD1_safe_q[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[1] at LC_X52_Y17_N2
--operation mode is arithmetic
ZD1_safe_q[1]_lut_out = ZD1_safe_q[1] $ (ZD1L2);
ZD1_safe_q[1] = DFFEAS(ZD1_safe_q[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , WD1L1, , , , );
--ZD1L5 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella1~COUT at LC_X52_Y17_N2
--operation mode is arithmetic
ZD1L5_cout_0 = ZD1_safe_q[1] $ T1_fifo_wr # !ZD1L2;
ZD1L5 = CARRY(ZD1L5_cout_0);
--ZD1L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella1~COUTCOUT1_20 at LC_X52_Y17_N2
--operation mode is arithmetic
ZD1L6_cout_1 = ZD1_safe_q[1] $ T1_fifo_wr # !ZD1L3;
ZD1L6 = CARRY(ZD1L6_cout_1);
--T1L65 is std_1s10:inst|jtag_uart:the_jtag_uart|LessThan0~84 at LC_X50_Y17_N4
--operation mode is normal
T1L65 = ZD1_safe_q[3] & (ZD1_safe_q[0] # ZD1_safe_q[1] # ZD1_safe_q[2]);
--WD1_b_full is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_full at LC_X48_Y17_N3
--operation mode is normal
WD1_b_full_lut_out = !T1_rd_wfifo & (WD1_b_full # WD1L3 & WD1L4);
WD1_b_full = DFFEAS(WD1_b_full_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--T1L3 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~168 at LC_X51_Y16_N6
--operation mode is arithmetic
T1L3_carry_eqn = (!T1L16 & T1L20) # (T1L16 & T1L21);
T1L3 = WD2_b_full $ (T1L3_carry_eqn);
--T1L4 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~169 at LC_X51_Y16_N6
--operation mode is arithmetic
T1L4_cout_0 = WD2_b_full & (!T1L20);
T1L4 = CARRY(T1L4_cout_0);
--T1L5 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~169COUT1_215 at LC_X51_Y16_N6
--operation mode is arithmetic
T1L5_cout_1 = WD2_b_full & (!T1L21);
T1L5 = CARRY(T1L5_cout_1);
--T1L6 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~170 at LC_X51_Y16_N3
--operation mode is arithmetic
T1L6 = ZD2_safe_q[3] $ T1L13;
--T1L7 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~171 at LC_X51_Y16_N3
--operation mode is arithmetic
T1L7_cout_0 = !ZD2_safe_q[3] & !T1L13;
T1L7 = CARRY(T1L7_cout_0);
--T1L8 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~171COUT1_211 at LC_X51_Y16_N3
--operation mode is arithmetic
T1L8_cout_1 = !ZD2_safe_q[3] & !T1L14;
T1L8 = CARRY(T1L8_cout_1);
--ZD2_safe_q[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[0] at LC_X50_Y15_N1
--operation mode is arithmetic
ZD2_safe_q[0]_lut_out = !ZD2_safe_q[0];
ZD2_safe_q[0] = DFFEAS(ZD2_safe_q[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , WD2L1, , , , );
--ZD2L2 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella0~COUT at LC_X50_Y15_N1
--operation mode is arithmetic
ZD2L2_cout_0 = T1_wr_rfifo $ !ZD2_safe_q[0];
ZD2L2 = CARRY(ZD2L2_cout_0);
--ZD2L3 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella0~COUTCOUT1_22 at LC_X50_Y15_N1
--operation mode is arithmetic
ZD2L3_cout_1 = T1_wr_rfifo $ !ZD2_safe_q[0];
ZD2L3 = CARRY(ZD2L3_cout_1);
--T1L9 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~172 at LC_X51_Y16_N1
--operation mode is arithmetic
T1L9 = ZD2_safe_q[1] $ ZD2_safe_q[0];
--T1L10 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~173 at LC_X51_Y16_N1
--operation mode is arithmetic
T1L10_cout_0 = !ZD2_safe_q[1] & !ZD2_safe_q[0];
T1L10 = CARRY(T1L10_cout_0);
--T1L11 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~173COUT1_207 at LC_X51_Y16_N1
--operation mode is arithmetic
T1L11_cout_1 = !ZD2_safe_q[1] & !ZD2_safe_q[0];
T1L11 = CARRY(T1L11_cout_1);
--T1L12 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~174 at LC_X51_Y16_N2
--operation mode is arithmetic
T1L12 = ZD2_safe_q[2] $ !T1L10;
--T1L13 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~175 at LC_X51_Y16_N2
--operation mode is arithmetic
T1L13_cout_0 = ZD2_safe_q[2] # !T1L10;
T1L13 = CARRY(T1L13_cout_0);
--T1L14 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~175COUT1_209 at LC_X51_Y16_N2
--operation mode is arithmetic
T1L14_cout_1 = ZD2_safe_q[2] # !T1L11;
T1L14 = CARRY(T1L14_cout_1);
--T1L66 is std_1s10:inst|jtag_uart:the_jtag_uart|LessThan1~117 at LC_X51_Y16_N9
--operation mode is normal
T1L66 = T1L6 & (ZD2_safe_q[0] # T1L9 # T1L12);
--T1L15 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~176 at LC_X51_Y16_N4
--operation mode is arithmetic
T1L15 = ZD2_safe_q[4] $ (!T1L7);
--T1L16 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~177 at LC_X51_Y16_N4
--operation mode is arithmetic
--T1L19 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~178 at LC_X51_Y16_N5
--operation mode is arithmetic
T1L19_carry_eqn = (!T1L16 & GND) # (T1L16 & VCC);
T1L19 = ZD2_safe_q[5] $ (T1L19_carry_eqn);
--T1L20 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~179 at LC_X51_Y16_N5
--operation mode is arithmetic
T1L20_cout_0 = !ZD2_safe_q[5] & (!T1L16);
T1L20 = CARRY(T1L20_cout_0);
--T1L21 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~179COUT1_213 at LC_X51_Y16_N5
--operation mode is arithmetic
T1L21_cout_1 = !ZD2_safe_q[5] & (!T1L16);
T1L21 = CARRY(T1L21_cout_1);
--T1L67 is std_1s10:inst|jtag_uart:the_jtag_uart|LessThan1~118 at LC_X52_Y16_N2
--operation mode is normal
--T1L22 is std_1s10:inst|jtag_uart:the_jtag_uart|Add0~180 at LC_X51_Y16_N7
--operation mode is normal
T1L22_carry_eqn = (!T1L16 & T1L4) # (T1L16 & T1L5);
T1L22 = !T1L22_carry_eqn;
--WD2_b_non_empty is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty at LC_X51_Y15_N6
--operation mode is normal
WD2_b_non_empty_lut_out = WD2L8 # WD2_b_non_empty & (WD2L3 # !T1L58);
WD2_b_non_empty = DFFEAS(WD2_b_non_empty_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--QD1L39Q is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_pause~reg0 at LC_X34_Y23_N2
--operation mode is normal
QD1L39Q = AMPP_FUNCTION(DE1__clk0, QD1_jupdate2, QD1L2, QD1_jupdate1, QD1L38, E1_data_out);
--SC1L12 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|take_action_oci_intr_mask_reg~8 at LC_X40_Y21_N8
--operation mode is normal
SC1L12 = AMPP_FUNCTION(SC1L2, SC1L1, P1L15, CD1L70);
--L1_i_readdata_d1[8] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[8] at LC_X46_Y13_N9
--operation mode is normal
L1_i_readdata_d1[8] = AMPP_FUNCTION(DE1__clk0, FC1L21, FC1L11, P1L10, N1L33, E1_data_out);
--L1L566 is std_1s10:inst|cpu:the_cpu|E_op_eret~66 at LC_X25_Y22_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L566 = AMPP_FUNCTION(L1_E_iw[13], L1_E_iw[16]);
--L1_E_iw[15] is std_1s10:inst|cpu:the_cpu|E_iw[15] at LC_X25_Y22_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[15] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[15], E1_data_out, GND, L1_W_stall);
--L1L567 is std_1s10:inst|cpu:the_cpu|E_op_eret~67 at LC_X28_Y22_N3
--operation mode is normal
L1L567 = AMPP_FUNCTION(L1L566, L1L564, L1L565, L1_E_iw[11]);
--L1_E_wrctl_status is std_1s10:inst|cpu:the_cpu|E_wrctl_status at LC_X28_Y21_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_wrctl_status = AMPP_FUNCTION(L1_E_iw[7], L1_E_iw[8], L1_E_ctrl_wrctl_inst);
--L1_E_iw[6] is std_1s10:inst|cpu:the_cpu|E_iw[6] at LC_X28_Y21_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[6] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[6], E1_data_out, GND, L1_W_stall);
--L1_E_ctrl_exception is std_1s10:inst|cpu:the_cpu|E_ctrl_exception at LC_X19_Y7_N5
--operation mode is normal
L1_E_ctrl_exception = AMPP_FUNCTION(DE1__clk0, L1L830, L1_D_iw[12], L1L827, L1L228, E1_data_out, L1_W_stall);
--L1L1365 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie_inst_nxt~0 at LC_X31_Y21_N2
--operation mode is normal
L1L1365 = AMPP_FUNCTION(L1_E_ctrl_exception, L1_E_ctrl_break);
--L1L1366 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie~150 at LC_X28_Y22_N0
--operation mode is normal
L1L1366 = AMPP_FUNCTION(L1_M_status_reg_pie, L1L819, L1_W_stall, L1L1370);
--L1L1367 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie~151 at LC_X28_Y22_N5
--operation mode is normal
L1L1367 = AMPP_FUNCTION(L1L567, L1_E_wrctl_status);
--L1L1368 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie~152 at LC_X27_Y21_N8
--operation mode is normal
L1L1368 = AMPP_FUNCTION(L1L1367, L1_E_ctrl_dst_data_sel_cmp, L1L424, L1L435);
--L1L1369 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie~153 at LC_X28_Y22_N1
--operation mode is normal
L1L1369 = AMPP_FUNCTION(L1_M_estatus_reg, L1_M_bstatus_reg, L1L567, L1_E_iw[14]);
--KB1_timeout_occurred is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|timeout_occurred at LC_X50_Y6_N9
--operation mode is normal
KB1_timeout_occurred_lut_out = KB1L235 & (!KB1L7 # !LB1_cpu_data_master_requests_sys_clk_timer_s1 # !HE1L21);
KB1_timeout_occurred = DFFEAS(KB1_timeout_occurred_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--SC1_internal_oci_ienable1[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[1] at LC_X47_Y20_N6
--operation mode is normal
SC1_internal_oci_ienable1[1] = AMPP_FUNCTION(DE1__clk0, L1_M_st_data[1], E1_data_out, SC1L12);
--Q1_d1_irq_from_the_lan91c111 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_irq_from_the_lan91c111 at LC_X31_Y21_N3
--operation mode is normal
Q1_d1_irq_from_the_lan91c111_lut_out = irq_from_the_lan91c111;
Q1_d1_irq_from_the_lan91c111 = DFFEAS(Q1_d1_irq_from_the_lan91c111_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--SC1_internal_oci_ienable1[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|internal_oci_ienable1[0] at LC_X22_Y27_N4
--operation mode is normal
SC1_internal_oci_ienable1[0] = AMPP_FUNCTION(DE1__clk0, L1_M_st_data[0], E1_data_out, SC1L12);
--L1_i_readdata_d1[7] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[7] at LC_X48_Y18_N5
--operation mode is normal
L1_i_readdata_d1[7] = AMPP_FUNCTION(DE1__clk0, P1L10, N1L30, FC1L10, FC1L21, E1_data_out);
--L1_i_readdata_d1[6] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[6] at LC_X47_Y11_N7
--operation mode is normal
L1_i_readdata_d1[6] = AMPP_FUNCTION(DE1__clk0, P1L10, FC1L9, FC1L21, N1L27, E1_data_out);
--L1_i_readdata_d1[4] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[4] at LC_X47_Y18_N5
--operation mode is normal
L1_i_readdata_d1[4] = AMPP_FUNCTION(DE1__clk0, N1L105, P1L10, N1L21, E1_data_out);
--L1_i_readdata_d1[15] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[15] at LC_X45_Y13_N9
--operation mode is normal
L1_i_readdata_d1[15] = AMPP_FUNCTION(DE1__clk0, P1L10, FC1L21, FC1L18, N1L54, E1_data_out);
--L1_i_readdata_d1[5] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[5] at LC_X48_Y12_N6
--operation mode is normal
L1_i_readdata_d1[5] = AMPP_FUNCTION(DE1__clk0, P1L10, N1L24, N1L106, E1_data_out);
--L1_i_readdata_d1[0] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[0] at LC_X40_Y20_N1
--operation mode is normal
L1_i_readdata_d1[0] = AMPP_FUNCTION(DE1__clk0, N1L9, P1L10, FC1L2, FC1L1, E1_data_out);
--L1_i_readdata_d1[1] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[1] at LC_X45_Y20_N6
--operation mode is normal
L1_i_readdata_d1[1] = AMPP_FUNCTION(DE1__clk0, P1L10, FC1L3, N1L12, FC1L4, E1_data_out);
--L1_i_readdata_d1[2] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[2] at LC_X40_Y20_N7
--operation mode is normal
L1_i_readdata_d1[2] = AMPP_FUNCTION(DE1__clk0, N1L15, P1L10, FC1L5, FC1L6, E1_data_out);
--L1_i_readdata_d1[3] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[3] at LC_X44_Y21_N3
--operation mode is normal
L1_i_readdata_d1[3] = AMPP_FUNCTION(DE1__clk0, P1L10, N1L18, FC1L7, FC1L8, E1_data_out);
--L1_i_readdata_d1[27] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[27] at LC_X41_Y14_N7
--operation mode is normal
L1_i_readdata_d1[27] = AMPP_FUNCTION(DE1__clk0, P1L10, N1L90, FC1L31, FC1L21, E1_data_out);
--L1_i_readdata_d1[28] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[28] at LC_X44_Y20_N5
--operation mode is normal
L1_i_readdata_d1[28] = AMPP_FUNCTION(DE1__clk0, P1L10, N1L93, FC1L21, FC1L32, E1_data_out);
--L1_i_readdata_d1[29] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[29] at LC_X44_Y14_N1
--operation mode is normal
L1_i_readdata_d1[29] = AMPP_FUNCTION(DE1__clk0, FC1L33, P1L10, N1L96, FC1L21, E1_data_out);
--L1_i_readdata_d1[30] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[30] at LC_X48_Y18_N8
--operation mode is normal
L1_i_readdata_d1[30] = AMPP_FUNCTION(DE1__clk0, P1L10, N1L99, FC1L21, FC1L34, E1_data_out);
--L1_i_readdata_d1[31] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[31] at LC_X44_Y19_N4
--operation mode is normal
L1_i_readdata_d1[31] = AMPP_FUNCTION(DE1__clk0, N1L102, FC1L35, P1L10, FC1L21, E1_data_out);
--L1_E_ctrl_shift_rot_right is std_1s10:inst|cpu:the_cpu|E_ctrl_shift_rot_right at LC_X19_Y7_N1
--operation mode is normal
L1_E_ctrl_shift_rot_right = AMPP_FUNCTION(DE1__clk0, L1L838, L1L248, L1L840, L1L244, E1_data_out, L1_W_stall);
--L1L599 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_row[0]~40 at LC_X13_Y11_N9
--operation mode is normal
L1L599 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L672, L1L849, L1L673);
--L1L735 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[0]~2295 at LC_X13_Y11_N0
--operation mode is normal
L1L735 = AMPP_FUNCTION(L1_E_ctrl_shift_rot, L1L849, L1L599, L1L669);
--L1L593 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_col[1]~84 at LC_X14_Y13_N3
--operation mode is normal
L1L593 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L671, L1L669, L1L670);
--L1L736 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[1]~2296 at LC_X12_Y12_N8
--operation mode is normal
L1L736 = AMPP_FUNCTION(L1L593, L1_E_ctrl_shift_rot, L1L670, L1L599);
--L1L594 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_col[2]~85 at LC_X14_Y13_N2
--operation mode is normal
L1L594 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L671, L1L669, L1L670);
--L1L737 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[2]~2297 at LC_X12_Y12_N1
--operation mode is normal
L1L737 = AMPP_FUNCTION(L1L671, L1_E_ctrl_shift_rot, L1L594, L1L599);
--L1L595 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_col[3]~86 at LC_X13_Y12_N2
--operation mode is normal
L1L595 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L669, L1L670, L1L671);
--L1L738 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[3]~2298 at LC_X13_Y12_N5
--operation mode is normal
L1L738 = AMPP_FUNCTION(L1L595, L1L672, L1L599, L1_E_ctrl_shift_rot);
--L1L763 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[28]~2299 at LC_X12_Y12_N3
--operation mode is normal
L1L763 = AMPP_FUNCTION(L1L671, L1_E_ctrl_shift_rot, L1L669, L1L670);
--L1L739 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[4]~2300 at LC_X12_Y12_N2
--operation mode is normal
L1L739 = AMPP_FUNCTION(L1L763, L1_E_ctrl_shift_rot, L1L673, L1L599);
--L1L596 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_col[5]~87 at LC_X12_Y11_N7
--operation mode is normal
L1L596 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L669, L1L671, L1L670);
--L1L740 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[5]~2301 at LC_X12_Y11_N2
--operation mode is normal
L1L740 = AMPP_FUNCTION(L1_E_ctrl_shift_rot, L1L674, L1L599, L1L596);
--L1L597 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_col[6]~88 at LC_X12_Y11_N0
--operation mode is normal
L1L597 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L669, L1L671, L1L670);
--L1L741 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[6]~2302 at LC_X12_Y11_N6
--operation mode is normal
L1L741 = AMPP_FUNCTION(L1L675, L1L597, L1L599, L1_E_ctrl_shift_rot);
--L1L598 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_col[7]~89 at LC_X13_Y11_N6
--operation mode is normal
L1L598 = AMPP_FUNCTION(L1L671, L1L670, L1_E_ctrl_shift_rot_right, L1L669);
--L1L742 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[7]~2303 at LC_X13_Y11_N3
--operation mode is normal
L1L742 = AMPP_FUNCTION(L1_E_ctrl_shift_rot, L1L598, L1L676, L1L599);
--L1L600 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_row[1]~41 at LC_X13_Y12_N0
--operation mode is normal
L1L600 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L672, L1L849, L1L673);
--L1L743 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[8]~2304 at LC_X13_Y12_N8
--operation mode is normal
L1L743 = AMPP_FUNCTION(L1L677, L1_E_ctrl_shift_rot, L1L849, L1L600);
--L1L744 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[9]~2305 at LC_X12_Y12_N0
--operation mode is normal
L1L744 = AMPP_FUNCTION(L1L593, L1_E_ctrl_shift_rot, L1L600, L1L678);
--L1L745 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[10]~2306 at LC_X12_Y12_N7
--operation mode is normal
L1L745 = AMPP_FUNCTION(L1L679, L1L600, L1L594, L1_E_ctrl_shift_rot);
--L1L746 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[11]~2307 at LC_X13_Y12_N1
--operation mode is normal
L1L746 = AMPP_FUNCTION(L1L680, L1_E_ctrl_shift_rot, L1L595, L1L600);
--L1L747 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[12]~2308 at LC_X17_Y11_N8
--operation mode is normal
L1L747 = AMPP_FUNCTION(L1_E_ctrl_shift_rot, L1L763, L1L600, L1L681);
--L1L748 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[13]~2309 at LC_X12_Y11_N4
--operation mode is normal
L1L748 = AMPP_FUNCTION(L1L596, L1L682, L1L600, L1_E_ctrl_shift_rot);
--L1L749 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[14]~2310 at LC_X12_Y11_N9
--operation mode is normal
L1L749 = AMPP_FUNCTION(L1L683, L1L597, L1L600, L1_E_ctrl_shift_rot);
--L1_E_src1_prelim[26] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[26] at LC_X17_Y16_N9
--operation mode is normal
L1_E_src1_prelim[26] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[26], MC1_q_b[26], L1L1455, L1_D_src1_hazard_W, E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[26] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[26] at LC_X13_Y14_N4
--operation mode is normal
L1_M_mul_shift_rot_result[26] = AMPP_FUNCTION(DE1__clk0, QC1_result[58], QC1_result[26], L1L1279, L1L1284, E1_data_out, L1_M_ctrl_rot);
--L1L1453 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[26]~3697 at LC_X13_Y14_N2
--operation mode is normal
L1L1453 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[26]);
--L1_av_ld_data_aligned_or_div[26] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[26] at LC_X21_Y20_N2
--operation mode is normal
L1_av_ld_data_aligned_or_div[26] = AMPP_FUNCTION(DE1__clk0, L1_M_iw[4], L1L171, L1_M_ctrl_ld_signed, L1_d_readdata_d1[26], E1_data_out);
--L1_M_alu_result[26] is std_1s10:inst|cpu:the_cpu|M_alu_result[26] at LC_X19_Y13_N2
--operation mode is normal
L1_M_alu_result[26] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L558, A1L275, L1L74, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1L1454 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[26]~3698 at LC_X21_Y20_N4
--operation mode is normal
L1L1454 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[26], L1_M_alu_result[26], L1_M_ctrl_mul_shift_rot, L1_av_ld_or_div_done);
--L1L629 is std_1s10:inst|cpu:the_cpu|E_src1[26]~1991 at LC_X13_Y14_N5
--operation mode is normal
L1L629 = AMPP_FUNCTION(L1L1453, L1L1454, L1_E_src1_hazard_M, L1_E_src1_prelim[26]);
--L1_E_src1_prelim[27] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[27] at LC_X17_Y16_N6
--operation mode is normal
L1_E_src1_prelim[27] = AMPP_FUNCTION(DE1__clk0, L1_D_src1_hazard_W, MC1_q_b[27], L1L1458, L1_W_wr_data[27], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[27] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[27] at LC_X12_Y15_N6
--operation mode is normal
L1_M_mul_shift_rot_result[27] = AMPP_FUNCTION(DE1__clk0, QC1_result[59], L1L1284, L1L1280, QC1_result[27], E1_data_out, L1_M_ctrl_rot);
--L1L1456 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[27]~3699 at LC_X19_Y16_N9
--operation mode is normal
L1L1456 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[27]);
--L1_av_ld_data_aligned_or_div[27] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[27] at LC_X21_Y20_N0
--operation mode is normal
L1_av_ld_data_aligned_or_div[27] = AMPP_FUNCTION(DE1__clk0, L1_M_iw[4], L1_d_readdata_d1[27], L1_M_ctrl_ld_signed, L1L171, E1_data_out);
--L1_M_alu_result[27] is std_1s10:inst|cpu:the_cpu|M_alu_result[27] at LC_X19_Y13_N4
--operation mode is normal
L1_M_alu_result[27] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L75, A1L275, L1L559, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1L1457 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[27]~3700 at LC_X21_Y20_N1
--operation mode is normal
L1L1457 = AMPP_FUNCTION(L1_av_ld_data_aligned_or_div[27], L1_av_ld_or_div_done, L1_M_ctrl_mul_shift_rot, L1_M_alu_result[27]);
--L1L630 is std_1s10:inst|cpu:the_cpu|E_src1[27]~1992 at LC_X19_Y16_N3
--operation mode is normal
L1L630 = AMPP_FUNCTION(L1L1457, L1L1456, L1_E_src1_hazard_M, L1_E_src1_prelim[27]);
--L1_E_src1_prelim[28] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[28] at LC_X17_Y16_N4
--operation mode is normal
L1_E_src1_prelim[28] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[28], L1_D_src1_hazard_W, L1L1461, MC1_q_b[28], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[28] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[28] at LC_X12_Y13_N8
--operation mode is normal
L1_M_mul_shift_rot_result[28] = AMPP_FUNCTION(DE1__clk0, QC1_result[28], L1L1284, L1L1281, QC1_result[60], E1_data_out, L1_M_ctrl_rot);
--L1L1459 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[28]~3701 at LC_X18_Y15_N4
--operation mode is normal
L1L1459 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[28]);
--L1_av_ld_data_aligned_or_div[28] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[28] at LC_X21_Y20_N6
--operation mode is normal
L1_av_ld_data_aligned_or_div[28] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[28], L1L171, L1_M_ctrl_ld_signed, L1_M_iw[4], E1_data_out);
--L1_M_alu_result[28] is std_1s10:inst|cpu:the_cpu|M_alu_result[28] at LC_X19_Y13_N1
--operation mode is normal
L1_M_alu_result[28] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L76, A1L275, L1L560, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1L1460 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[28]~3702 at LC_X21_Y20_N7
--operation mode is normal
L1L1460 = AMPP_FUNCTION(L1_M_alu_result[28], L1_av_ld_data_aligned_or_div[28], L1_M_ctrl_mul_shift_rot, L1_av_ld_or_div_done);
--L1L631 is std_1s10:inst|cpu:the_cpu|E_src1[28]~1993 at LC_X18_Y15_N5
--operation mode is normal
L1L631 = AMPP_FUNCTION(L1_E_src1_prelim[28], L1L1459, L1_E_src1_hazard_M, L1L1460);
--L1_E_src1_prelim[29] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[29] at LC_X19_Y19_N0
--operation mode is normal
L1_E_src1_prelim[29] = AMPP_FUNCTION(DE1__clk0, L1_D_src1_hazard_W, MC1_q_b[29], L1L1464, L1_W_wr_data[29], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[29] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[29] at LC_X12_Y13_N9
--operation mode is normal
L1_M_mul_shift_rot_result[29] = AMPP_FUNCTION(DE1__clk0, QC1_result[29], L1L1284, L1L1282, QC1_result[61], E1_data_out, L1_M_ctrl_rot);
--L1L1462 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[29]~3703 at LC_X19_Y14_N3
--operation mode is normal
L1L1462 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[29]);
--L1_av_ld_data_aligned_or_div[29] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[29] at LC_X19_Y14_N1
--operation mode is normal
L1_av_ld_data_aligned_or_div[29] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[29], L1_M_ctrl_ld_signed, L1_M_iw[4], L1L171, E1_data_out);
--L1_M_alu_result[29] is std_1s10:inst|cpu:the_cpu|M_alu_result[29] at LC_X19_Y14_N9
--operation mode is normal
L1_M_alu_result[29] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L561, A1L275, L1L77, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1L1463 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[29]~3704 at LC_X19_Y14_N7
--operation mode is normal
L1L1463 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_alu_result[29], L1_av_ld_or_div_done, L1_av_ld_data_aligned_or_div[29]);
--L1L632 is std_1s10:inst|cpu:the_cpu|E_src1[29]~1994 at LC_X19_Y14_N2
--operation mode is normal
L1L632 = AMPP_FUNCTION(L1_E_src1_hazard_M, L1L1462, L1L1463, L1_E_src1_prelim[29]);
--L1_E_src1_prelim[30] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[30] at LC_X19_Y19_N3
--operation mode is normal
L1_E_src1_prelim[30] = AMPP_FUNCTION(DE1__clk0, L1_D_src1_hazard_W, MC1_q_b[30], L1L1467, L1_W_wr_data[30], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[30] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[30] at LC_X12_Y13_N6
--operation mode is normal
L1_M_mul_shift_rot_result[30] = AMPP_FUNCTION(DE1__clk0, QC1_result[30], L1L1284, L1L1283, QC1_result[62], E1_data_out, L1_M_ctrl_rot);
--L1L1465 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3705 at LC_X18_Y15_N0
--operation mode is normal
L1L1465 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[30]);
--L1_av_ld_data_aligned_or_div[30] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[30] at LC_X21_Y20_N3
--operation mode is normal
L1_av_ld_data_aligned_or_div[30] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[30], L1L171, L1_M_ctrl_ld_signed, L1_M_iw[4], E1_data_out);
--L1_M_alu_result[30] is std_1s10:inst|cpu:the_cpu|M_alu_result[30] at LC_X22_Y20_N3
--operation mode is normal
L1_M_alu_result[30] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L78, A1L275, L1L562, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1L1466 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3706 at LC_X21_Y20_N9
--operation mode is normal
L1L1466 = AMPP_FUNCTION(L1_M_alu_result[30], L1_M_ctrl_mul_shift_rot, L1_av_ld_data_aligned_or_div[30], L1_av_ld_or_div_done);
--L1L633 is std_1s10:inst|cpu:the_cpu|E_src1[30]~1995 at LC_X18_Y15_N2
--operation mode is normal
L1L633 = AMPP_FUNCTION(L1_E_src1_prelim[30], L1_E_src1_hazard_M, L1L1465, L1L1466);
--L1_E_src1_prelim[31] is std_1s10:inst|cpu:the_cpu|E_src1_prelim[31] at LC_X17_Y13_N7
--operation mode is normal
L1_E_src1_prelim[31] = AMPP_FUNCTION(DE1__clk0, L1_D_src1_hazard_W, MC1_q_b[31], L1L1470, L1_W_wr_data[31], E1_data_out, L1_D_src1_hazard_M, L1_W_stall);
--L1_M_mul_shift_rot_result[31] is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result[31] at LC_X12_Y13_N2
--operation mode is normal
L1_M_mul_shift_rot_result[31] = AMPP_FUNCTION(DE1__clk0, QC1_result[63], QC1_result[31], L1L1285, L1L1284, E1_data_out, L1_M_ctrl_rot);
--L1L1468 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3707 at LC_X17_Y13_N8
--operation mode is normal
L1L1468 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[31]);
--L1_av_ld_data_aligned_or_div[31] is std_1s10:inst|cpu:the_cpu|av_ld_data_aligned_or_div[31] at LC_X21_Y20_N5
--operation mode is normal
L1_av_ld_data_aligned_or_div[31] = AMPP_FUNCTION(DE1__clk0, L1_d_readdata_d1[31], L1L171, L1_M_ctrl_ld_signed, L1_M_iw[4], E1_data_out);
--L1_M_alu_result[31] is std_1s10:inst|cpu:the_cpu|M_alu_result[31] at LC_X19_Y13_N7
--operation mode is normal
L1_M_alu_result[31] = AMPP_FUNCTION(DE1__clk0, L1_E_ctrl_dst_data_sel_logic_result, L1L79, A1L275, L1L563, E1_data_out, L1_E_ctrl_dst_data_sel_cmp, L1_E_ctrl_rdctl_inst, L1_W_stall);
--L1L1469 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3708 at LC_X17_Y13_N5
--operation mode is normal
L1L1469 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_av_ld_or_div_done, L1_M_alu_result[31], L1_av_ld_data_aligned_or_div[31]);
--L1L634 is std_1s10:inst|cpu:the_cpu|E_src1[31]~1996 at LC_X17_Y13_N2
--operation mode is normal
L1L634 = AMPP_FUNCTION(L1_E_src1_hazard_M, L1L1468, L1_E_src1_prelim[31], L1L1469);
--L1_E_ctrl_mul_cell_src1_signed is std_1s10:inst|cpu:the_cpu|E_ctrl_mul_cell_src1_signed at LC_X17_Y13_N1
--operation mode is normal
L1_E_ctrl_mul_cell_src1_signed = AMPP_FUNCTION(DE1__clk0, L1L248, L1_D_iw[15], L1L239, E1_data_out, L1_W_stall);
--QC1_w7w[32] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|w7w[32] at LC_X17_Y13_N3
--operation mode is normal
QC1_w7w[32] = AMPP_FUNCTION(L1_E_ctrl_mul_cell_src1_signed, L1L634);
--L1L750 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[15]~2311 at LC_X13_Y11_N4
--operation mode is normal
L1L750 = AMPP_FUNCTION(L1_E_ctrl_shift_rot, L1L598, L1L684, L1L600);
--L1L601 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_row[2]~42 at LC_X13_Y12_N6
--operation mode is normal
L1L601 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L672, L1L849, L1L673);
--L1L751 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[16]~2312 at LC_X13_Y12_N3
--operation mode is normal
L1L751 = AMPP_FUNCTION(L1L685, L1_E_ctrl_shift_rot, L1L849, L1L601);
--L1L752 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[17]~2313 at LC_X12_Y12_N6
--operation mode is normal
L1L752 = AMPP_FUNCTION(L1L686, L1_E_ctrl_shift_rot, L1L601, L1L593);
--L1L753 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[18]~2314 at LC_X12_Y12_N5
--operation mode is normal
L1L753 = AMPP_FUNCTION(L1L687, L1L601, L1L594, L1_E_ctrl_shift_rot);
--L1L754 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[19]~2315 at LC_X13_Y12_N7
--operation mode is normal
L1L754 = AMPP_FUNCTION(L1L595, L1_E_ctrl_shift_rot, L1L688, L1L601);
--L1L755 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[20]~2316 at LC_X17_Y11_N7
--operation mode is normal
L1L755 = AMPP_FUNCTION(L1L689, L1L763, L1_E_ctrl_shift_rot, L1L601);
--L1L756 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[21]~2317 at LC_X12_Y11_N8
--operation mode is normal
L1L756 = AMPP_FUNCTION(L1_E_ctrl_shift_rot, L1L690, L1L596, L1L601);
--L1L757 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[22]~2318 at LC_X12_Y11_N1
--operation mode is normal
L1L757 = AMPP_FUNCTION(L1_E_ctrl_shift_rot, L1L601, L1L691, L1L597);
--L1L758 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[23]~2319 at LC_X13_Y11_N5
--operation mode is normal
L1L758 = AMPP_FUNCTION(L1_E_ctrl_shift_rot, L1L598, L1L601, L1L692);
--L1L602 is std_1s10:inst|cpu:the_cpu|E_sh_cnt_row[3]~43 at LC_X13_Y11_N7
--operation mode is normal
L1L602 = AMPP_FUNCTION(L1_E_ctrl_shift_rot_right, L1L672, L1L849, L1L673);
--L1L759 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[24]~2320 at LC_X13_Y11_N2
--operation mode is normal
L1L759 = AMPP_FUNCTION(L1L602, L1L849, L1L693, L1_E_ctrl_shift_rot);
--L1L760 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[25]~2321 at LC_X12_Y12_N4
--operation mode is normal
L1L760 = AMPP_FUNCTION(L1L602, L1_E_ctrl_shift_rot, L1L694, L1L593);
--L1_E_src2_imm[26] is std_1s10:inst|cpu:the_cpu|E_src2_imm[26] at LC_X17_Y8_N3
--operation mode is normal
L1_E_src2_imm[26] = AMPP_FUNCTION(DE1__clk0, L1L222, L1L247, L1L414, L1L246, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[26] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[26] at LC_X14_Y14_N6
--operation mode is normal
L1_E_src2_prelim[26] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[26], L1_W_wr_data[26], L1L1455, L1L403, E1_data_out, L1L399, L1_W_stall);
--L1L803 is std_1s10:inst|cpu:the_cpu|E_src2_reg[26]~474 at LC_X14_Y14_N5
--operation mode is normal
L1L803 = AMPP_FUNCTION(L1_E_src2_hazard_M, L1L1453, L1L1454, L1_E_src2_prelim[26]);
--L1L695 is std_1s10:inst|cpu:the_cpu|E_src2[26]~1517 at LC_X17_Y8_N7
--operation mode is normal
L1L695 = AMPP_FUNCTION(L1_E_ctrl_src2_is_imm, L1_E_src2_imm[26], L1L803);
--L1L761 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[26]~2322 at LC_X12_Y12_N9
--operation mode is normal
L1L761 = AMPP_FUNCTION(L1L695, L1_E_ctrl_shift_rot, L1L594, L1L602);
--L1_E_src2_imm[27] is std_1s10:inst|cpu:the_cpu|E_src2_imm[27] at LC_X19_Y16_N4
--operation mode is normal
L1_E_src2_imm[27] = AMPP_FUNCTION(DE1__clk0, L1L415, L1L247, L1L246, L1L222, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[27] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[27] at LC_X17_Y18_N4
--operation mode is normal
L1_E_src2_prelim[27] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[27], NC1_q_b[27], L1L1458, L1L403, E1_data_out, L1L399, L1_W_stall);
--L1L804 is std_1s10:inst|cpu:the_cpu|E_src2_reg[27]~475 at LC_X19_Y16_N2
--operation mode is normal
L1L804 = AMPP_FUNCTION(L1_E_src2_hazard_M, L1L1456, L1_E_src2_prelim[27], L1L1457);
--L1L696 is std_1s10:inst|cpu:the_cpu|E_src2[27]~1518 at LC_X19_Y16_N0
--operation mode is normal
L1L696 = AMPP_FUNCTION(L1_E_src2_imm[27], L1_E_ctrl_src2_is_imm, L1L804);
--L1L762 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[27]~2323 at LC_X13_Y12_N4
--operation mode is normal
L1L762 = AMPP_FUNCTION(L1L595, L1_E_ctrl_shift_rot, L1L696, L1L602);
--L1_E_src2_imm[28] is std_1s10:inst|cpu:the_cpu|E_src2_imm[28] at LC_X27_Y20_N9
--operation mode is normal
L1_E_src2_imm[28] = AMPP_FUNCTION(DE1__clk0, L1L222, L1L247, L1L416, L1L246, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[28] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[28] at LC_X18_Y15_N9
--operation mode is normal
L1_E_src2_prelim[28] = AMPP_FUNCTION(DE1__clk0, L1_W_wr_data[28], NC1_q_b[28], L1L1461, L1L403, E1_data_out, L1L399, L1_W_stall);
--L1L805 is std_1s10:inst|cpu:the_cpu|E_src2_reg[28]~476 at LC_X18_Y15_N7
--operation mode is normal
L1L805 = AMPP_FUNCTION(L1L1459, L1_E_src2_prelim[28], L1_E_src2_hazard_M, L1L1460);
--L1L697 is std_1s10:inst|cpu:the_cpu|E_src2[28]~1519 at LC_X27_Y20_N6
--operation mode is normal
L1L697 = AMPP_FUNCTION(L1_E_src2_imm[28], L1L805, L1_E_ctrl_src2_is_imm);
--L1L764 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[28]~2324 at LC_X17_Y11_N9
--operation mode is normal
L1L764 = AMPP_FUNCTION(L1_E_ctrl_shift_rot, L1L697, L1L602, L1L763);
--L1_E_src2_imm[29] is std_1s10:inst|cpu:the_cpu|E_src2_imm[29] at LC_X19_Y16_N6
--operation mode is normal
L1_E_src2_imm[29] = AMPP_FUNCTION(DE1__clk0, L1L247, L1L246, L1L417, L1L222, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[29] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[29] at LC_X18_Y18_N4
--operation mode is normal
L1_E_src2_prelim[29] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[29], L1L403, L1L1464, L1_W_wr_data[29], E1_data_out, L1L399, L1_W_stall);
--L1L806 is std_1s10:inst|cpu:the_cpu|E_src2_reg[29]~477 at LC_X19_Y14_N4
--operation mode is normal
L1L806 = AMPP_FUNCTION(L1_E_src2_hazard_M, L1_E_src2_prelim[29], L1L1463, L1L1462);
--L1L698 is std_1s10:inst|cpu:the_cpu|E_src2[29]~1520 at LC_X19_Y14_N5
--operation mode is normal
L1L698 = AMPP_FUNCTION(L1_E_ctrl_src2_is_imm, L1_E_src2_imm[29], L1L806);
--L1L765 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[29]~2325 at LC_X12_Y11_N5
--operation mode is normal
L1L765 = AMPP_FUNCTION(L1L596, L1L602, L1L698, L1_E_ctrl_shift_rot);
--L1_E_src2_imm[30] is std_1s10:inst|cpu:the_cpu|E_src2_imm[30] at LC_X28_Y20_N7
--operation mode is normal
L1_E_src2_imm[30] = AMPP_FUNCTION(DE1__clk0, L1L247, L1L418, L1L222, L1L246, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[30] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[30] at LC_X18_Y15_N3
--operation mode is normal
L1_E_src2_prelim[30] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[30], L1L403, L1L1467, L1_W_wr_data[30], E1_data_out, L1L399, L1_W_stall);
--L1L807 is std_1s10:inst|cpu:the_cpu|E_src2_reg[30]~478 at LC_X18_Y15_N1
--operation mode is normal
L1L807 = AMPP_FUNCTION(L1_E_src2_prelim[30], L1L1465, L1_E_src2_hazard_M, L1L1466);
--L1L699 is std_1s10:inst|cpu:the_cpu|E_src2[30]~1521 at LC_X18_Y9_N7
--operation mode is normal
L1L699 = AMPP_FUNCTION(L1_E_src2_imm[30], L1_E_ctrl_src2_is_imm, L1L807);
--L1L766 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[30]~2326 at LC_X12_Y11_N3
--operation mode is normal
L1L766 = AMPP_FUNCTION(L1_E_ctrl_shift_rot, L1L699, L1L602, L1L597);
--L1_E_src2_imm[31] is std_1s10:inst|cpu:the_cpu|E_src2_imm[31] at LC_X18_Y8_N0
--operation mode is normal
L1_E_src2_imm[31] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[21], L1L222, L1L246, L1L247, E1_data_out, L1_W_stall);
--L1_E_src2_prelim[31] is std_1s10:inst|cpu:the_cpu|E_src2_prelim[31] at LC_X18_Y18_N8
--operation mode is normal
L1_E_src2_prelim[31] = AMPP_FUNCTION(DE1__clk0, NC1_q_b[31], L1L403, L1L1470, L1_W_wr_data[31], E1_data_out, L1L399, L1_W_stall);
--L1L808 is std_1s10:inst|cpu:the_cpu|E_src2_reg[31]~479 at LC_X17_Y13_N9
--operation mode is normal
L1L808 = AMPP_FUNCTION(L1L1469, L1_E_src2_prelim[31], L1_E_src2_hazard_M, L1L1468);
--L1L700 is std_1s10:inst|cpu:the_cpu|E_src2[31]~1522 at LC_X18_Y8_N4
--operation mode is normal
L1L700 = AMPP_FUNCTION(L1_E_ctrl_src2_is_imm, L1_E_src2_imm[31], L1L808);
--L1L767 is std_1s10:inst|cpu:the_cpu|E_src2_mul_cell[31]~2327 at LC_X13_Y11_N8
--operation mode is normal
L1L767 = AMPP_FUNCTION(L1_E_ctrl_shift_rot, L1L700, L1L602, L1L598);
--L1_E_ctrl_mul_cell_src2_signed is std_1s10:inst|cpu:the_cpu|E_ctrl_mul_cell_src2_signed at LC_X18_Y7_N3
--operation mode is normal
L1_E_ctrl_mul_cell_src2_signed = AMPP_FUNCTION(DE1__clk0, L1L248, L1L841, L1_D_iw[11], E1_data_out, L1_W_stall);
--QC1_w23w[32] is std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|w23w[32] at LC_X13_Y11_N1
--operation mode is normal
QC1_w23w[32] = AMPP_FUNCTION(L1_E_ctrl_mul_cell_src2_signed, L1L767);
--L1L242 is std_1s10:inst|cpu:the_cpu|D_ctrl_mulx~31 at LC_X17_Y11_N5
--operation mode is normal
L1L242 = AMPP_FUNCTION(L1_D_iw[11], L1_D_iw[13], L1_D_iw[16]);
--L1L243 is std_1s10:inst|cpu:the_cpu|D_ctrl_rot~32 at LC_X17_Y11_N2
--operation mode is normal
L1L243 = AMPP_FUNCTION(L1L830, L1_D_iw[13], L1_D_iw[12], L1L827);
--L1_E_ctrl_shift_rot is std_1s10:inst|cpu:the_cpu|E_ctrl_shift_rot at LC_X17_Y11_N2
--operation mode is normal
L1_E_ctrl_shift_rot = AMPP_FUNCTION(DE1__clk0, L1L830, L1_D_iw[13], L1_D_iw[12], L1L827, E1_data_out, L1_W_stall);
--F1L26 is std_1s10:inst|button_pio:the_button_pio|read_mux_out[2]~376 at LC_X48_Y13_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
F1_irq_mask[2]_qfbk = F1_irq_mask[2];
F1L26 = L1_M_alu_result[2] & F1_edge_capture[2] # !L1_M_alu_result[2] & (F1_irq_mask[2]_qfbk);
--F1_irq_mask[2] is std_1s10:inst|button_pio:the_button_pio|irq_mask[2] at LC_X48_Y13_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
F1_irq_mask[2] = DFFEAS(F1L26, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , F1L23, L1_M_st_data[2], , , VCC);
--AE2_q_b[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[2] at M512_X49_Y18
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 8, Port B Depth: 64, Port B Width: 8
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE2_q_b[2]_PORT_A_data_in = BUS(QD1_wdata[2], QD1_wdata[3], QD1_wdata[7], QD1_wdata[4], QD1_wdata[5], QD1_wdata[6], QD1_wdata[0], QD1_wdata[1]);
AE2_q_b[2]_PORT_A_data_in_reg = DFFE(AE2_q_b[2]_PORT_A_data_in, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[2]_PORT_A_address_reg = DFFE(AE2_q_b[2]_PORT_A_address, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[2]_PORT_B_address_reg = DFFE(AE2_q_b[2]_PORT_B_address, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_PORT_A_write_enable = VCC;
AE2_q_b[2]_PORT_A_write_enable_reg = DFFE(AE2_q_b[2]_PORT_A_write_enable, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_read_enable = VCC;
AE2_q_b[2]_PORT_B_read_enable_reg = DFFE(AE2_q_b[2]_PORT_B_read_enable, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_clock_0 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_1 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[2]_clock_enable_1 = T1L76;
AE2_q_b[2]_PORT_B_data_out = MEMORY(AE2_q_b[2]_PORT_A_data_in_reg, , AE2_q_b[2]_PORT_A_address_reg, AE2_q_b[2]_PORT_B_address_reg, AE2_q_b[2]_PORT_A_write_enable_reg, AE2_q_b[2]_PORT_B_read_enable_reg, , , AE2_q_b[2]_clock_0, AE2_q_b[2]_clock_1, AE2_q_b[2]_clock_enable_0, AE2_q_b[2]_clock_enable_1, , );
AE2_q_b[2] = AE2_q_b[2]_PORT_B_data_out[0];
--AE2_q_b[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[1] at M512_X49_Y18
AE2_q_b[2]_PORT_A_data_in = BUS(QD1_wdata[2], QD1_wdata[3], QD1_wdata[7], QD1_wdata[4], QD1_wdata[5], QD1_wdata[6], QD1_wdata[0], QD1_wdata[1]);
AE2_q_b[2]_PORT_A_data_in_reg = DFFE(AE2_q_b[2]_PORT_A_data_in, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[2]_PORT_A_address_reg = DFFE(AE2_q_b[2]_PORT_A_address, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[2]_PORT_B_address_reg = DFFE(AE2_q_b[2]_PORT_B_address, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_PORT_A_write_enable = VCC;
AE2_q_b[2]_PORT_A_write_enable_reg = DFFE(AE2_q_b[2]_PORT_A_write_enable, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_read_enable = VCC;
AE2_q_b[2]_PORT_B_read_enable_reg = DFFE(AE2_q_b[2]_PORT_B_read_enable, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_clock_0 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_1 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[2]_clock_enable_1 = T1L76;
AE2_q_b[2]_PORT_B_data_out = MEMORY(AE2_q_b[2]_PORT_A_data_in_reg, , AE2_q_b[2]_PORT_A_address_reg, AE2_q_b[2]_PORT_B_address_reg, AE2_q_b[2]_PORT_A_write_enable_reg, AE2_q_b[2]_PORT_B_read_enable_reg, , , AE2_q_b[2]_clock_0, AE2_q_b[2]_clock_1, AE2_q_b[2]_clock_enable_0, AE2_q_b[2]_clock_enable_1, , );
AE2_q_b[1] = AE2_q_b[2]_PORT_B_data_out[7];
--AE2_q_b[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[0] at M512_X49_Y18
AE2_q_b[2]_PORT_A_data_in = BUS(QD1_wdata[2], QD1_wdata[3], QD1_wdata[7], QD1_wdata[4], QD1_wdata[5], QD1_wdata[6], QD1_wdata[0], QD1_wdata[1]);
AE2_q_b[2]_PORT_A_data_in_reg = DFFE(AE2_q_b[2]_PORT_A_data_in, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[2]_PORT_A_address_reg = DFFE(AE2_q_b[2]_PORT_A_address, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[2]_PORT_B_address_reg = DFFE(AE2_q_b[2]_PORT_B_address, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_PORT_A_write_enable = VCC;
AE2_q_b[2]_PORT_A_write_enable_reg = DFFE(AE2_q_b[2]_PORT_A_write_enable, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_read_enable = VCC;
AE2_q_b[2]_PORT_B_read_enable_reg = DFFE(AE2_q_b[2]_PORT_B_read_enable, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_clock_0 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_1 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[2]_clock_enable_1 = T1L76;
AE2_q_b[2]_PORT_B_data_out = MEMORY(AE2_q_b[2]_PORT_A_data_in_reg, , AE2_q_b[2]_PORT_A_address_reg, AE2_q_b[2]_PORT_B_address_reg, AE2_q_b[2]_PORT_A_write_enable_reg, AE2_q_b[2]_PORT_B_read_enable_reg, , , AE2_q_b[2]_clock_0, AE2_q_b[2]_clock_1, AE2_q_b[2]_clock_enable_0, AE2_q_b[2]_clock_enable_1, , );
AE2_q_b[0] = AE2_q_b[2]_PORT_B_data_out[6];
--AE2_q_b[6] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[6] at M512_X49_Y18
AE2_q_b[2]_PORT_A_data_in = BUS(QD1_wdata[2], QD1_wdata[3], QD1_wdata[7], QD1_wdata[4], QD1_wdata[5], QD1_wdata[6], QD1_wdata[0], QD1_wdata[1]);
AE2_q_b[2]_PORT_A_data_in_reg = DFFE(AE2_q_b[2]_PORT_A_data_in, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[2]_PORT_A_address_reg = DFFE(AE2_q_b[2]_PORT_A_address, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[2]_PORT_B_address_reg = DFFE(AE2_q_b[2]_PORT_B_address, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_PORT_A_write_enable = VCC;
AE2_q_b[2]_PORT_A_write_enable_reg = DFFE(AE2_q_b[2]_PORT_A_write_enable, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_read_enable = VCC;
AE2_q_b[2]_PORT_B_read_enable_reg = DFFE(AE2_q_b[2]_PORT_B_read_enable, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_clock_0 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_1 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[2]_clock_enable_1 = T1L76;
AE2_q_b[2]_PORT_B_data_out = MEMORY(AE2_q_b[2]_PORT_A_data_in_reg, , AE2_q_b[2]_PORT_A_address_reg, AE2_q_b[2]_PORT_B_address_reg, AE2_q_b[2]_PORT_A_write_enable_reg, AE2_q_b[2]_PORT_B_read_enable_reg, , , AE2_q_b[2]_clock_0, AE2_q_b[2]_clock_1, AE2_q_b[2]_clock_enable_0, AE2_q_b[2]_clock_enable_1, , );
AE2_q_b[6] = AE2_q_b[2]_PORT_B_data_out[5];
--AE2_q_b[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[5] at M512_X49_Y18
AE2_q_b[2]_PORT_A_data_in = BUS(QD1_wdata[2], QD1_wdata[3], QD1_wdata[7], QD1_wdata[4], QD1_wdata[5], QD1_wdata[6], QD1_wdata[0], QD1_wdata[1]);
AE2_q_b[2]_PORT_A_data_in_reg = DFFE(AE2_q_b[2]_PORT_A_data_in, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[2]_PORT_A_address_reg = DFFE(AE2_q_b[2]_PORT_A_address, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[2]_PORT_B_address_reg = DFFE(AE2_q_b[2]_PORT_B_address, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_PORT_A_write_enable = VCC;
AE2_q_b[2]_PORT_A_write_enable_reg = DFFE(AE2_q_b[2]_PORT_A_write_enable, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_read_enable = VCC;
AE2_q_b[2]_PORT_B_read_enable_reg = DFFE(AE2_q_b[2]_PORT_B_read_enable, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_clock_0 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_1 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[2]_clock_enable_1 = T1L76;
AE2_q_b[2]_PORT_B_data_out = MEMORY(AE2_q_b[2]_PORT_A_data_in_reg, , AE2_q_b[2]_PORT_A_address_reg, AE2_q_b[2]_PORT_B_address_reg, AE2_q_b[2]_PORT_A_write_enable_reg, AE2_q_b[2]_PORT_B_read_enable_reg, , , AE2_q_b[2]_clock_0, AE2_q_b[2]_clock_1, AE2_q_b[2]_clock_enable_0, AE2_q_b[2]_clock_enable_1, , );
AE2_q_b[5] = AE2_q_b[2]_PORT_B_data_out[4];
--AE2_q_b[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[4] at M512_X49_Y18
AE2_q_b[2]_PORT_A_data_in = BUS(QD1_wdata[2], QD1_wdata[3], QD1_wdata[7], QD1_wdata[4], QD1_wdata[5], QD1_wdata[6], QD1_wdata[0], QD1_wdata[1]);
AE2_q_b[2]_PORT_A_data_in_reg = DFFE(AE2_q_b[2]_PORT_A_data_in, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[2]_PORT_A_address_reg = DFFE(AE2_q_b[2]_PORT_A_address, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[2]_PORT_B_address_reg = DFFE(AE2_q_b[2]_PORT_B_address, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_PORT_A_write_enable = VCC;
AE2_q_b[2]_PORT_A_write_enable_reg = DFFE(AE2_q_b[2]_PORT_A_write_enable, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_read_enable = VCC;
AE2_q_b[2]_PORT_B_read_enable_reg = DFFE(AE2_q_b[2]_PORT_B_read_enable, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_clock_0 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_1 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[2]_clock_enable_1 = T1L76;
AE2_q_b[2]_PORT_B_data_out = MEMORY(AE2_q_b[2]_PORT_A_data_in_reg, , AE2_q_b[2]_PORT_A_address_reg, AE2_q_b[2]_PORT_B_address_reg, AE2_q_b[2]_PORT_A_write_enable_reg, AE2_q_b[2]_PORT_B_read_enable_reg, , , AE2_q_b[2]_clock_0, AE2_q_b[2]_clock_1, AE2_q_b[2]_clock_enable_0, AE2_q_b[2]_clock_enable_1, , );
AE2_q_b[4] = AE2_q_b[2]_PORT_B_data_out[3];
--AE2_q_b[7] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[7] at M512_X49_Y18
AE2_q_b[2]_PORT_A_data_in = BUS(QD1_wdata[2], QD1_wdata[3], QD1_wdata[7], QD1_wdata[4], QD1_wdata[5], QD1_wdata[6], QD1_wdata[0], QD1_wdata[1]);
AE2_q_b[2]_PORT_A_data_in_reg = DFFE(AE2_q_b[2]_PORT_A_data_in, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[2]_PORT_A_address_reg = DFFE(AE2_q_b[2]_PORT_A_address, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[2]_PORT_B_address_reg = DFFE(AE2_q_b[2]_PORT_B_address, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_PORT_A_write_enable = VCC;
AE2_q_b[2]_PORT_A_write_enable_reg = DFFE(AE2_q_b[2]_PORT_A_write_enable, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_read_enable = VCC;
AE2_q_b[2]_PORT_B_read_enable_reg = DFFE(AE2_q_b[2]_PORT_B_read_enable, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_clock_0 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_1 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[2]_clock_enable_1 = T1L76;
AE2_q_b[2]_PORT_B_data_out = MEMORY(AE2_q_b[2]_PORT_A_data_in_reg, , AE2_q_b[2]_PORT_A_address_reg, AE2_q_b[2]_PORT_B_address_reg, AE2_q_b[2]_PORT_A_write_enable_reg, AE2_q_b[2]_PORT_B_read_enable_reg, , , AE2_q_b[2]_clock_0, AE2_q_b[2]_clock_1, AE2_q_b[2]_clock_enable_0, AE2_q_b[2]_clock_enable_1, , );
AE2_q_b[7] = AE2_q_b[2]_PORT_B_data_out[2];
--AE2_q_b[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[3] at M512_X49_Y18
AE2_q_b[2]_PORT_A_data_in = BUS(QD1_wdata[2], QD1_wdata[3], QD1_wdata[7], QD1_wdata[4], QD1_wdata[5], QD1_wdata[6], QD1_wdata[0], QD1_wdata[1]);
AE2_q_b[2]_PORT_A_data_in_reg = DFFE(AE2_q_b[2]_PORT_A_data_in, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_A_address = BUS(YD4_safe_q[0], YD4_safe_q[1], YD4_safe_q[2], YD4_safe_q[3], YD4_safe_q[4], YD4_safe_q[5]);
AE2_q_b[2]_PORT_A_address_reg = DFFE(AE2_q_b[2]_PORT_A_address, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_address = BUS(YD3_safe_q[0], YD3_safe_q[1], YD3_safe_q[2], YD3_safe_q[3], YD3_safe_q[4], YD3_safe_q[5]);
AE2_q_b[2]_PORT_B_address_reg = DFFE(AE2_q_b[2]_PORT_B_address, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_PORT_A_write_enable = VCC;
AE2_q_b[2]_PORT_A_write_enable_reg = DFFE(AE2_q_b[2]_PORT_A_write_enable, AE2_q_b[2]_clock_0, , , AE2_q_b[2]_clock_enable_0);
AE2_q_b[2]_PORT_B_read_enable = VCC;
AE2_q_b[2]_PORT_B_read_enable_reg = DFFE(AE2_q_b[2]_PORT_B_read_enable, AE2_q_b[2]_clock_1, , , AE2_q_b[2]_clock_enable_1);
AE2_q_b[2]_clock_0 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_1 = GLOBAL(DE1__clk0);
AE2_q_b[2]_clock_enable_0 = T1_wr_rfifo;
AE2_q_b[2]_clock_enable_1 = T1L76;
AE2_q_b[2]_PORT_B_data_out = MEMORY(AE2_q_b[2]_PORT_A_data_in_reg, , AE2_q_b[2]_PORT_A_address_reg, AE2_q_b[2]_PORT_B_address_reg, AE2_q_b[2]_PORT_A_write_enable_reg, AE2_q_b[2]_PORT_B_read_enable_reg, , , AE2_q_b[2]_clock_0, AE2_q_b[2]_clock_1, AE2_q_b[2]_clock_enable_0, AE2_q_b[2]_clock_enable_1, , );
AE2_q_b[3] = AE2_q_b[2]_PORT_B_data_out[1];
--M1L298 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~18 at LC_X48_Y15_N1
--operation mode is normal
M1L298 = T1_read_0 & AE2_q_b[2] # !EB1L2 # !U1L2;
--M1L270 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[2]~2078 at LC_X48_Y15_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[2]_qfbk = H1_slave_readdata[2];
M1L270 = H1_slave_readdata[2]_qfbk # !J1_cpu_data_master_requests_clock_0_in;
--H1_slave_readdata[2] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[2] at LC_X48_Y15_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[2] = DFFEAS(M1L270, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[2], , , VCC);
--KB1_counter_snapshot[2] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[2] at LC_X52_Y2_N8
--operation mode is normal
KB1_counter_snapshot[2]_lut_out = !KB1_internal_counter[2];
KB1_counter_snapshot[2] = DFFEAS(KB1_counter_snapshot[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--HE1L17 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~101 at LC_X50_Y8_N3
--operation mode is normal
HE1L17 = !L1_M_alu_result[3] & L1_M_alu_result[4] & !L1_M_alu_result[2];
--KB1_period_h_register[2] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[2] at LC_X50_Y4_N0
--operation mode is normal
KB1_period_h_register[2]_lut_out = !L1_M_st_data[2];
KB1_period_h_register[2] = DFFEAS(KB1_period_h_register[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, , , , );
--KB1L188 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[2]~1238 at LC_X50_Y4_N1
--operation mode is normal
KB1L188 = HE1L17 & (KB1_counter_snapshot[2] # HE1L15 & !KB1_period_h_register[2]) # !HE1L17 & HE1L15 & (!KB1_period_h_register[2]);
--KB1_counter_snapshot[18] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[18] at LC_X50_Y2_N2
--operation mode is normal
KB1_counter_snapshot[18]_lut_out = !KB1_internal_counter[18];
KB1_counter_snapshot[18] = DFFEAS(KB1_counter_snapshot[18]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--HE1L18 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~102 at LC_X50_Y8_N8
--operation mode is normal
HE1L18 = !L1_M_alu_result[3] & L1_M_alu_result[4] & L1_M_alu_result[2];
--HE1L19 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~103 at LC_X50_Y8_N9
--operation mode is normal
HE1L19 = !L1_M_alu_result[3] & !L1_M_alu_result[4] & L1_M_alu_result[2];
--KB1L189 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[2]~1239 at LC_X50_Y5_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_control_register[2]_qfbk = KB1_control_register[2];
KB1L189 = HE1L19 & (KB1_control_register[2]_qfbk # HE1L18 & KB1_counter_snapshot[18]) # !HE1L19 & HE1L18 & (KB1_counter_snapshot[18]);
--KB1_control_register[2] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|control_register[2] at LC_X50_Y5_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_control_register[2] = DFFEAS(KB1L189, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_control_wr_strobe, L1_M_st_data[2], , , VCC);
--HE1L20 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~104 at LC_X50_Y8_N2
--operation mode is normal
HE1L20 = L1_M_alu_result[3] & !L1_M_alu_result[4] & !L1_M_alu_result[2];
--KB1_period_l_register[2] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[2] at LC_X48_Y5_N2
--operation mode is normal
KB1_period_l_register[2]_lut_out = !L1_M_st_data[2];
KB1_period_l_register[2] = DFFEAS(KB1_period_l_register[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, , , , );
--Z1L1 is std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|wren~1 at LC_X34_Y11_N9
--operation mode is normal
Z1L1 = L1_internal_d_write & AB1L3 & (AB1_onchip_ram_64_kbytes_s1_arb_addend[1] # !AB1L11);
--AB1L18 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[0]~98 at LC_X34_Y10_N4
--operation mode is normal
AB1L18 = AB1L3 & (AB1L1 & (L1_ic_fill_ap_offset[0]) # !AB1L1 & L1_M_alu_result[2]) # !AB1L3 & (L1_ic_fill_ap_offset[0]);
--AB1L19 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[1]~99 at LC_X36_Y10_N5
--operation mode is normal
AB1L19 = AB1L1 & L1_ic_fill_ap_offset[1] # !AB1L1 & (AB1L3 & (L1_M_alu_result[3]) # !AB1L3 & L1_ic_fill_ap_offset[1]);
--AB1L20 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[2]~100 at LC_X36_Y10_N6
--operation mode is normal
AB1L20 = AB1L3 & (AB1L1 & (L1_ic_fill_ap_offset[2]) # !AB1L1 & L1_M_alu_result[4]) # !AB1L3 & (L1_ic_fill_ap_offset[2]);
--AB1L21 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[3]~101 at LC_X34_Y10_N1
--operation mode is normal
AB1L21 = AB1L1 & (L1_ic_fill_line[0]) # !AB1L1 & (AB1L3 & L1_M_alu_result[5] # !AB1L3 & (L1_ic_fill_line[0]));
--AB1L22 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[4]~102 at LC_X34_Y9_N2
--operation mode is normal
AB1L22 = AB1L3 & (AB1L1 & (L1_ic_fill_line[1]) # !AB1L1 & L1_M_alu_result[6]) # !AB1L3 & (L1_ic_fill_line[1]);
--AB1L23 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[5]~103 at LC_X34_Y9_N9
--operation mode is normal
AB1L23 = AB1L1 & (L1_ic_fill_line[2]) # !AB1L1 & (AB1L3 & L1_M_alu_result[7] # !AB1L3 & (L1_ic_fill_line[2]));
--AB1L24 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[6]~104 at LC_X34_Y10_N3
--operation mode is normal
AB1L24 = AB1L3 & (AB1L1 & L1_ic_fill_line[3] # !AB1L1 & (L1_M_alu_result[8])) # !AB1L3 & L1_ic_fill_line[3];
--AB1L25 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[7]~105 at LC_X34_Y9_N0
--operation mode is normal
AB1L25 = AB1L3 & (AB1L1 & (L1_ic_fill_line[4]) # !AB1L1 & L1_M_alu_result[9]) # !AB1L3 & (L1_ic_fill_line[4]);
--AB1L26 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[8]~106 at LC_X34_Y10_N0
--operation mode is normal
AB1L26 = AB1L3 & (AB1L1 & L1_ic_fill_line[5] # !AB1L1 & (L1_M_alu_result[10])) # !AB1L3 & L1_ic_fill_line[5];
--AB1L27 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[9]~107 at LC_X35_Y13_N6
--operation mode is normal
AB1L27 = AB1L1 & L1_ic_fill_line[6] # !AB1L1 & (AB1L3 & (L1_M_alu_result[11]) # !AB1L3 & L1_ic_fill_line[6]);
--AB1L28 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[10]~108 at LC_X34_Y10_N9
--operation mode is normal
AB1L28 = AB1L3 & (AB1L1 & (L1_ic_fill_tag[0]) # !AB1L1 & L1_M_alu_result[12]) # !AB1L3 & (L1_ic_fill_tag[0]);
--AB1L29 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[11]~109 at LC_X34_Y10_N5
--operation mode is normal
AB1L29 = AB1L3 & (AB1L1 & (L1_ic_fill_tag[1]) # !AB1L1 & L1_M_alu_result[13]) # !AB1L3 & (L1_ic_fill_tag[1]);
--AB1L30 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[12]~110 at LC_X34_Y8_N5
--operation mode is normal
AB1L30 = AB1L1 & L1_ic_fill_tag[2] # !AB1L1 & (AB1L3 & (L1_M_alu_result[14]) # !AB1L3 & L1_ic_fill_tag[2]);
--AB1L31 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_address[13]~111 at LC_X35_Y13_N7
--operation mode is normal
AB1L31 = AB1L1 & (L1_ic_fill_tag[3]) # !AB1L1 & (AB1L3 & L1_M_alu_result[15] # !AB1L3 & (L1_ic_fill_tag[3]));
--AB1L34 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_byteenable[0]~4 at LC_X34_Y11_N6
--operation mode is normal
AB1L34 = L1_M_mem_byte_en[0] # AB1L11 & !AB1_onchip_ram_64_kbytes_s1_arb_addend[1] # !AB1L3;
--R1_counter_snapshot[2] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[2] at LC_X47_Y4_N9
--operation mode is normal
R1_counter_snapshot[2]_lut_out = !R1_internal_counter[2];
R1_counter_snapshot[2] = DFFEAS(R1_counter_snapshot[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, , , , );
--R1L187 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[2]~1249 at LC_X47_Y4_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[2]_qfbk = R1_period_h_register[2];
R1L187 = HE1L15 & (R1_period_h_register[2]_qfbk # R1_counter_snapshot[2] & HE1L17) # !HE1L15 & R1_counter_snapshot[2] & (HE1L17);
--R1_period_h_register[2] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[2] at LC_X47_Y4_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[2] = DFFEAS(R1L187, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[2], , , VCC);
--R1_control_register[2] is std_1s10:inst|high_res_timer:the_high_res_timer|control_register[2] at LC_X51_Y8_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_control_register[2]_lut_out = GND;
R1_control_register[2] = DFFEAS(R1_control_register[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_control_wr_strobe, L1_M_st_data[2], , , VCC);
--R1L188 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[2]~1250 at LC_X48_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[18]_qfbk = R1_counter_snapshot[18];
R1L188 = HE1L19 & (R1_control_register[2] # HE1L18 & R1_counter_snapshot[18]_qfbk) # !HE1L19 & HE1L18 & R1_counter_snapshot[18]_qfbk;
--R1_counter_snapshot[18] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[18] at LC_X48_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[18] = DFFEAS(R1L188, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[18], , , VCC);
--R1_period_l_register[2] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[2] at LC_X48_Y5_N5
--operation mode is normal
R1_period_l_register[2]_lut_out = !L1_M_st_data[2];
R1_period_l_register[2] = DFFEAS(R1_period_l_register[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, , , , );
--HE1_control_reg[2] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[2] at LC_X51_Y8_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_control_reg[2]_lut_out = GND;
HE1_control_reg[2] = DFFEAS(HE1_control_reg[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L13, L1_M_st_data[2], , , VCC);
--HE1L51 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[2]~675 at LC_X50_Y8_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_internal_tx_data[2]_qfbk = HE1_internal_tx_data[2];
HE1L51 = L1_M_alu_result[3] & HE1_control_reg[2] # !L1_M_alu_result[3] & (HE1_internal_tx_data[2]_qfbk);
--HE1_internal_tx_data[2] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[2] at LC_X50_Y8_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_internal_tx_data[2] = DFFEAS(HE1L51, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L64, L1_M_st_data[2], , , VCC);
--JE1_break_detect is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|break_detect at LC_X50_Y9_N6
--operation mode is normal
JE1_break_detect_lut_out = !HE1L63 & (JE1_break_detect # !JE1L80 & JE1_got_new_char);
JE1_break_detect = DFFEAS(JE1_break_detect_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--HE1L52 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[2]~676 at LC_X51_Y9_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[2]_qfbk = JE1_rx_data[2];
HE1L52 = L1_M_alu_result[3] & (JE1_break_detect) # !L1_M_alu_result[3] & JE1_rx_data[2]_qfbk;
--JE1_rx_data[2] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[2] at LC_X51_Y9_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[2] = DFFEAS(HE1L52, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1_got_new_char, JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3], , , VCC);
--DD1_internal_jdo1[23] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[23] at LC_X34_Y25_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[23] = AMPP_FUNCTION(!A1L9, DD1_sr[23], VCC, GND, DD1L144);
--VC1L5 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_go~102 at LC_X34_Y25_N8
--operation mode is normal
VC1L5 = AMPP_FUNCTION(VC1_internal_monitor_go, DD1_internal_jdo1[34], A1L4, DD1L189);
--CD1_MonWr is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonWr at LC_X36_Y21_N4
--operation mode is normal
CD1_MonWr = AMPP_FUNCTION(DE1__clk0, P1L30, VC1_resetrequest, GND, CD1_MonWr, !C1_CLR_SIGNAL, DD1L191, DD1L189);
--P1L31 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[0]~4 at LC_X36_Y21_N0
--operation mode is normal
P1L31 = L1_M_mem_byte_en[0] # !P1L3;
--CD1_internal_MonDReg[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[0] at LC_X36_Y24_N0
--operation mode is normal
CD1_internal_MonDReg[0] = AMPP_FUNCTION(DE1__clk0, DD1L191, CD1L37, DD1_internal_jdo1[3], CD1_MonRd1, !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1] at LC_X36_Y26_N6
--operation mode is normal
CD1_internal_MonDReg[1] = AMPP_FUNCTION(DE1__clk0, CD1L28, PD1_q_b[1], DD1_internal_jdo1[4], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L39, CD1L38);
--CD1_internal_MonDReg[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[2] at LC_X36_Y26_N2
--operation mode is normal
CD1_internal_MonDReg[2] = AMPP_FUNCTION(DE1__clk0, CD1_MonAReg[10], PD1_q_b[2], DD1_internal_jdo1[5], CD1L29, !C1_CLR_SIGNAL, CD1L39, CD1L38);
--CD1_internal_MonDReg[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[3] at LC_X36_Y25_N6
--operation mode is normal
CD1_internal_MonDReg[3] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[3], CD1L1, DD1_internal_jdo1[6], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L39, CD1L38);
--CD1_internal_MonDReg[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[4] at LC_X36_Y26_N9
--operation mode is normal
CD1_internal_MonDReg[4] = AMPP_FUNCTION(DE1__clk0, CD1L28, PD1_q_b[4], DD1_internal_jdo1[7], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L39, CD1L38);
--CD1_internal_MonDReg[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[5] at LC_X36_Y25_N5
--operation mode is normal
CD1_internal_MonDReg[5] = AMPP_FUNCTION(DE1__clk0, CD1L30, PD1_q_b[5], DD1_internal_jdo1[8], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L39, CD1L38);
--CD1_internal_MonDReg[6] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[6] at LC_X36_Y24_N4
--operation mode is normal
CD1_internal_MonDReg[6] = AMPP_FUNCTION(DE1__clk0, CD1L39, DD1_internal_jdo1[9], CD1_MonAReg[10], PD1_q_b[6], !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[7] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[7] at LC_X36_Y24_N5
--operation mode is normal
CD1_internal_MonDReg[7] = AMPP_FUNCTION(DE1__clk0, CD1L39, PD1_q_b[7], CD1_MonAReg[10], DD1_internal_jdo1[10], !C1_CLR_SIGNAL, CD1L38);
--CD1_MonAReg[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[2] at LC_X35_Y26_N2
--operation mode is normal
CD1_MonAReg[2] = AMPP_FUNCTION(DE1__clk0, DD1L190, DD1_internal_jdo1[26], CD1L2, CD1L82, !C1_CLR_SIGNAL, DD1L192);
--CD1_MonAReg[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[3] at LC_X35_Y26_N3
--operation mode is normal
CD1_MonAReg[3] = AMPP_FUNCTION(DE1__clk0, DD1L190, CD1L83, CD1L5, DD1_internal_jdo1[27], !C1_CLR_SIGNAL, DD1L192);
--CD1_MonAReg[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[4] at LC_X35_Y26_N8
--operation mode is normal
CD1_MonAReg[4] = AMPP_FUNCTION(DE1__clk0, DD1L190, DD1_internal_jdo1[28], CD1L8, CD1L84, !C1_CLR_SIGNAL, DD1L192);
--CD1_MonAReg[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[5] at LC_X35_Y26_N0
--operation mode is normal
CD1_MonAReg[5] = AMPP_FUNCTION(DE1__clk0, DD1L190, DD1_internal_jdo1[29], CD1L11, CD1L85, !C1_CLR_SIGNAL, DD1L192);
--CD1_MonAReg[6] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[6] at LC_X34_Y27_N5
--operation mode is normal
CD1_MonAReg[6] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[30], CD1L86, CD1L14, DD1L190, !C1_CLR_SIGNAL, DD1L192);
--CD1_MonAReg[7] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[7] at LC_X35_Y26_N6
--operation mode is normal
CD1_MonAReg[7] = AMPP_FUNCTION(DE1__clk0, DD1L190, CD1L87, CD1L18, DD1_internal_jdo1[31], !C1_CLR_SIGNAL, DD1L192);
--CD1_MonAReg[8] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[8] at LC_X34_Y27_N6
--operation mode is normal
CD1_MonAReg[8] = AMPP_FUNCTION(DE1__clk0, CD1L88, DD1L190, CD1L21, DD1_internal_jdo1[32], !C1_CLR_SIGNAL, DD1L192);
--CD1_MonAReg[9] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[9] at LC_X34_Y27_N3
--operation mode is normal
CD1_MonAReg[9] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[33], DD1L190, CD1L24, CD1L89, !C1_CLR_SIGNAL, DD1L192);
--AB1L36 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_byteenable[2]~5 at LC_X34_Y11_N0
--operation mode is normal
AB1L36 = L1_M_mem_byte_en[2] # AB1L11 & !AB1_onchip_ram_64_kbytes_s1_arb_addend[1] # !AB1L3;
--M1L284 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[18]~2080 at LC_X44_Y13_N9
--operation mode is normal
M1L284 = FB1_za_data[18] # L1_M_alu_result[25] # !L1_M_alu_result[24] # !QB1L4;
--ZD2_safe_q[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[2] at LC_X50_Y15_N3
--operation mode is arithmetic
ZD2_safe_q[2]_lut_out = ZD2_safe_q[2] $ (!ZD2L5);
ZD2_safe_q[2] = DFFEAS(ZD2_safe_q[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , WD2L1, , , , );
--ZD2L8 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella2~COUT at LC_X50_Y15_N3
--operation mode is arithmetic
ZD2L8_cout_0 = !ZD2L5 & (ZD2_safe_q[2] $ !T1_wr_rfifo);
ZD2L8 = CARRY(ZD2L8_cout_0);
--ZD2L9 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella2~COUTCOUT1_13 at LC_X50_Y15_N3
--operation mode is arithmetic
ZD2L9_cout_1 = !ZD2L6 & (ZD2_safe_q[2] $ !T1_wr_rfifo);
ZD2L9 = CARRY(ZD2L9_cout_1);
--T1L23 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~294 at LC_X51_Y17_N2
--operation mode is arithmetic
T1L23 = ZD1_safe_q[2] $ (T1L46);
--T1L24 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~295 at LC_X51_Y17_N2
--operation mode is arithmetic
T1L24_cout_0 = !ZD1_safe_q[2] & (!T1L46);
T1L24 = CARRY(T1L24_cout_0);
--T1L25 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~295COUT1_353 at LC_X51_Y17_N2
--operation mode is arithmetic
T1L25_cout_1 = !ZD1_safe_q[2] & (!T1L47);
T1L25 = CARRY(T1L25_cout_1);
--T1L26 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~296 at LC_X51_Y16_N0
--operation mode is normal
T1L26 = T1_read_0 & (ZD2_safe_q[2]) # !T1_read_0 & T1L23;
--M1L310 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|process5~0 at LC_X41_Y16_N0
--operation mode is normal
M1L310 = M1_internal_cpu_data_master_dbs_address[1] & (!M1_internal_cpu_data_master_dbs_address[0] & M1L307);
--P1L33 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[2]~5 at LC_X36_Y21_N3
--operation mode is normal
P1L33 = L1_M_mem_byte_en[2] # !P1L3;
--CD1_internal_MonDReg[16] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[16] at LC_X36_Y24_N6
--operation mode is normal
CD1_internal_MonDReg[16] = AMPP_FUNCTION(DE1__clk0, CD1L39, DD1_internal_jdo1[19], CD1_MonAReg[10], PD1_q_b[16], !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[17] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[17] at LC_X36_Y24_N3
--operation mode is normal
CD1_internal_MonDReg[17] = AMPP_FUNCTION(DE1__clk0, CD1L39, DD1_internal_jdo1[20], CD1_MonAReg[10], PD1_q_b[17], !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[18] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[18] at LC_X36_Y25_N9
--operation mode is normal
CD1_internal_MonDReg[18] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[18], CD1L31, DD1_internal_jdo1[21], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L39, CD1L38);
--CD1_internal_MonDReg[19] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[19] at LC_X36_Y25_N2
--operation mode is normal
CD1_internal_MonDReg[19] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[19], DD1_internal_jdo1[22], CD1L39, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[20] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[20] at LC_X36_Y25_N7
--operation mode is normal
CD1_internal_MonDReg[20] = AMPP_FUNCTION(DE1__clk0, CD1_MonAReg[10], CD1L39, PD1_q_b[20], DD1_internal_jdo1[23], !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[21] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[21] at LC_X36_Y25_N3
--operation mode is normal
CD1_internal_MonDReg[21] = AMPP_FUNCTION(DE1__clk0, CD1_MonAReg[10], CD1L39, PD1_q_b[21], DD1_internal_jdo1[24], !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[22] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[22] at LC_X36_Y25_N4
--operation mode is normal
CD1_internal_MonDReg[22] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[22], DD1_internal_jdo1[25], CD1L39, CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[23] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[23] at LC_X35_Y25_N1
--operation mode is normal
CD1_internal_MonDReg[23] = AMPP_FUNCTION(DE1__clk0, CD1_MonAReg[10], PD1_q_b[23], DD1_internal_jdo1[26], CD1L39, !C1_CLR_SIGNAL, CD1L38);
--L1_i_readdata_d1[12] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[12] at LC_X45_Y11_N9
--operation mode is normal
L1_i_readdata_d1[12] = AMPP_FUNCTION(DE1__clk0, P1L10, FC1L15, N1L45, FC1L21, E1_data_out);
--L1_i_readdata_d1[11] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[11] at LC_X47_Y16_N7
--operation mode is normal
L1_i_readdata_d1[11] = AMPP_FUNCTION(DE1__clk0, FC1L21, N1L42, P1L10, FC1L14, E1_data_out);
--L1_i_readdata_d1[16] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[16] at LC_X41_Y19_N5
--operation mode is normal
L1_i_readdata_d1[16] = AMPP_FUNCTION(DE1__clk0, FC1L21, N1L57, P1L10, FC1L19, E1_data_out);
--L1_i_readdata_d1[14] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[14] at LC_X44_Y12_N9
--operation mode is normal
L1_i_readdata_d1[14] = AMPP_FUNCTION(DE1__clk0, FC1L21, P1L10, FC1L17, N1L51, E1_data_out);
--L1_i_readdata_d1[13] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[13] at LC_X47_Y17_N4
--operation mode is normal
L1_i_readdata_d1[13] = AMPP_FUNCTION(DE1__clk0, N1L48, FC1L16, P1L10, FC1L21, E1_data_out);
--L1_i_readdata_d1[21] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[21] at LC_X47_Y19_N5
--operation mode is normal
L1_i_readdata_d1[21] = AMPP_FUNCTION(DE1__clk0, N1L72, FC1L21, P1L10, FC1L25, E1_data_out);
--KE1_tx_overrun is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_overrun at LC_X50_Y9_N4
--operation mode is normal
KE1_tx_overrun_lut_out = !HE1L63 & (KE1_tx_overrun # KE1_internal_tx_ready & KE1L41);
KE1_tx_overrun = DFFEAS(KE1_tx_overrun_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--HE1_control_reg[5] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[5] at LC_X51_Y8_N1
--operation mode is normal
HE1_control_reg[5]_lut_out = L1_M_st_data[5];
HE1_control_reg[5] = DFFEAS(HE1_control_reg[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L13, , , , );
--KE1_tx_shift_empty is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_shift_empty at LC_X52_Y7_N4
--operation mode is normal
KE1_tx_shift_empty_lut_out = KE1_unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] # KE1_internal_tx_ready # !KE1L37;
KE1_tx_shift_empty = DFFEAS(KE1_tx_shift_empty_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--HE1L33 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~115 at LC_X51_Y8_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_control_reg[4]_qfbk = HE1_control_reg[4];
HE1L33 = KE1_tx_overrun & (HE1_control_reg[4]_qfbk # HE1_control_reg[5] & !KE1_tx_shift_empty) # !KE1_tx_overrun & HE1_control_reg[5] & (!KE1_tx_shift_empty);
--HE1_control_reg[4] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[4] at LC_X51_Y8_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_control_reg[4] = DFFEAS(HE1L33, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L13, L1_M_st_data[4], , , VCC);
--JE1_framing_error is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|framing_error at LC_X50_Y9_N8
--operation mode is normal
JE1_framing_error_lut_out = !HE1L63 & JE1L48;
JE1_framing_error = DFFEAS(JE1_framing_error_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--HE1_control_reg[6] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[6] at LC_X51_Y8_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_control_reg[6]_lut_out = GND;
HE1_control_reg[6] = DFFEAS(HE1_control_reg[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L13, L1_M_st_data[6], , , VCC);
--KE1_internal_tx_ready is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|internal_tx_ready at LC_X48_Y10_N8
--operation mode is normal
KE1_internal_tx_ready_lut_out = L1_internal_d_write & HE1L19 & JE1L63 # !KE1L33;
KE1_internal_tx_ready = DFFEAS(KE1_internal_tx_ready_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--HE1L34 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~116 at LC_X51_Y8_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_control_reg[1]_qfbk = HE1_control_reg[1];
HE1L34 = KE1_internal_tx_ready & JE1_framing_error & HE1_control_reg[1]_qfbk # !KE1_internal_tx_ready & (HE1_control_reg[6] # JE1_framing_error & HE1_control_reg[1]_qfbk);
--HE1_control_reg[1] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[1] at LC_X51_Y8_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_control_reg[1] = DFFEAS(HE1L34, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L13, L1_M_st_data[1], , , VCC);
--JE1_rx_overrun is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_overrun at LC_X50_Y9_N7
--operation mode is normal
JE1_rx_overrun_lut_out = !HE1L63 & (JE1_rx_overrun # JE1_got_new_char & JE1_internal_rx_char_ready);
JE1_rx_overrun = DFFEAS(JE1_rx_overrun_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--HE1L1 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|any_error~21 at LC_X51_Y8_N8
--operation mode is normal
HE1L1 = KE1_tx_overrun # JE1_rx_overrun # JE1_framing_error # JE1_break_detect;
--HE1L35 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~117 at LC_X51_Y8_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_control_reg[8]_qfbk = HE1_control_reg[8];
HE1L35 = HE1L33 # HE1L34 # HE1_control_reg[8]_qfbk & HE1L1;
--HE1_control_reg[8] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[8] at LC_X51_Y8_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_control_reg[8] = DFFEAS(HE1L35, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L13, L1_M_st_data[8], , , VCC);
--HE1L36 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|qualified_irq~118 at LC_X51_Y8_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_control_reg[3]_qfbk = HE1_control_reg[3];
HE1L36 = HE1_control_reg[2] & (JE1_break_detect # JE1_rx_overrun & HE1_control_reg[3]_qfbk) # !HE1_control_reg[2] & JE1_rx_overrun & HE1_control_reg[3]_qfbk;
--HE1_control_reg[3] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[3] at LC_X51_Y8_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_control_reg[3] = DFFEAS(HE1L36, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L13, L1_M_st_data[3], , , VCC);
--HE1_control_reg[7] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[7] at LC_X50_Y9_N9
--operation mode is normal
HE1_control_reg[7]_lut_out = L1_M_st_data[7];
HE1_control_reg[7] = DFFEAS(HE1_control_reg[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L13, , , , );
--JE1_internal_rx_char_ready is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|internal_rx_char_ready at LC_X48_Y10_N5
--operation mode is normal
JE1_internal_rx_char_ready_lut_out = JE1L51 & (!L1_internal_d_read # !HE1L21 # !JE1L63);
JE1_internal_rx_char_ready = DFFEAS(JE1_internal_rx_char_ready_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--F1L27 is std_1s10:inst|button_pio:the_button_pio|read_mux_out[3]~378 at LC_X50_Y12_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
F1_irq_mask[3]_qfbk = F1_irq_mask[3];
F1L27 = L1_M_alu_result[2] & (F1_edge_capture[3]) # !L1_M_alu_result[2] & F1_irq_mask[3]_qfbk;
--F1_irq_mask[3] is std_1s10:inst|button_pio:the_button_pio|irq_mask[3] at LC_X50_Y12_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
F1_irq_mask[3] = DFFEAS(F1L27, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , F1L23, L1_M_st_data[3], , , VCC);
--M1L299 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~19 at LC_X41_Y12_N3
--operation mode is normal
M1L299 = T1_read_0 & AE2_q_b[3] # !EB1L2 # !U1L2;
--M1L271 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[3]~2082 at LC_X50_Y19_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[3]_qfbk = H1_slave_readdata[3];
M1L271 = H1_slave_readdata[3]_qfbk # !J1_cpu_data_master_requests_clock_0_in;
--H1_slave_readdata[3] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[3] at LC_X50_Y19_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[3] = DFFEAS(M1L271, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[3], , , VCC);
--KB1_counter_snapshot[3] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[3] at LC_X52_Y2_N2
--operation mode is normal
KB1_counter_snapshot[3]_lut_out = !KB1_internal_counter[3];
KB1_counter_snapshot[3] = DFFEAS(KB1_counter_snapshot[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--KB1L190 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[3]~1240 at LC_X50_Y4_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[3]_qfbk = KB1_period_h_register[3];
KB1L190 = HE1L17 & (KB1_counter_snapshot[3] # HE1L15 & KB1_period_h_register[3]_qfbk) # !HE1L17 & HE1L15 & KB1_period_h_register[3]_qfbk;
--KB1_period_h_register[3] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[3] at LC_X50_Y4_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[3] = DFFEAS(KB1L190, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, L1_M_st_data[3], , , VCC);
--KB1_control_register[3] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|control_register[3] at LC_X50_Y7_N6
--operation mode is normal
KB1_control_register[3]_lut_out = L1_M_st_data[3];
KB1_control_register[3] = DFFEAS(KB1_control_register[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_control_wr_strobe, , , , );
--KB1L191 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[3]~1241 at LC_X50_Y2_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[19]_qfbk = KB1_counter_snapshot[19];
KB1L191 = HE1L18 & (KB1_counter_snapshot[19]_qfbk # KB1_control_register[3] & HE1L19) # !HE1L18 & KB1_control_register[3] & (HE1L19);
--KB1_counter_snapshot[19] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[19] at LC_X50_Y2_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[19] = DFFEAS(KB1L191, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[19], , , VCC);
--KB1_period_l_register[3] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[3] at LC_X48_Y5_N9
--operation mode is normal
KB1_period_l_register[3]_lut_out = !L1_M_st_data[3];
KB1_period_l_register[3] = DFFEAS(KB1_period_l_register[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, , , , );
--R1_counter_snapshot[3] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[3] at LC_X47_Y4_N4
--operation mode is normal
R1_counter_snapshot[3]_lut_out = !R1_internal_counter[3];
R1_counter_snapshot[3] = DFFEAS(R1_counter_snapshot[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, , , , );
--R1L189 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[3]~1251 at LC_X46_Y8_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[3]_qfbk = R1_period_h_register[3];
R1L189 = HE1L15 & (R1_period_h_register[3]_qfbk # HE1L17 & R1_counter_snapshot[3]) # !HE1L15 & HE1L17 & (R1_counter_snapshot[3]);
--R1_period_h_register[3] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[3] at LC_X46_Y8_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[3] = DFFEAS(R1L189, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[3], , , VCC);
--R1_control_register[3] is std_1s10:inst|high_res_timer:the_high_res_timer|control_register[3] at LC_X51_Y8_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_control_register[3]_lut_out = GND;
R1_control_register[3] = DFFEAS(R1_control_register[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_control_wr_strobe, L1_M_st_data[3], , , VCC);
--R1L190 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[3]~1252 at LC_X48_Y6_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[19]_qfbk = R1_counter_snapshot[19];
R1L190 = HE1L19 & (R1_control_register[3] # HE1L18 & R1_counter_snapshot[19]_qfbk) # !HE1L19 & HE1L18 & R1_counter_snapshot[19]_qfbk;
--R1_counter_snapshot[19] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[19] at LC_X48_Y6_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[19] = DFFEAS(R1L190, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[19], , , VCC);
--R1_period_l_register[3] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[3] at LC_X48_Y5_N8
--operation mode is normal
R1_period_l_register[3]_lut_out = !L1_M_st_data[3];
R1_period_l_register[3] = DFFEAS(R1_period_l_register[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, , , , );
--HE1L53 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[3]~678 at LC_X50_Y8_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_internal_tx_data[3]_qfbk = HE1_internal_tx_data[3];
HE1L53 = L1_M_alu_result[3] & (HE1_control_reg[3]) # !L1_M_alu_result[3] & HE1_internal_tx_data[3]_qfbk;
--HE1_internal_tx_data[3] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[3] at LC_X50_Y8_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_internal_tx_data[3] = DFFEAS(HE1L53, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L64, L1_M_st_data[3], , , VCC);
--HE1L54 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[3]~679 at LC_X51_Y10_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[3]_qfbk = JE1_rx_data[3];
HE1L54 = L1_M_alu_result[3] & (JE1_rx_overrun) # !L1_M_alu_result[3] & (JE1_rx_data[3]_qfbk);
--JE1_rx_data[3] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[3] at LC_X51_Y10_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[3] = DFFEAS(HE1L54, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1_got_new_char, JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4], , , VCC);
--M1L285 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[19]~2084 at LC_X46_Y19_N5
--operation mode is normal
M1L285 = L1_M_alu_result[25] # FB1_za_data[19] # !L1_M_alu_result[24] # !QB1L4;
--ZD2_safe_q[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[3] at LC_X50_Y15_N4
--operation mode is arithmetic
ZD2_safe_q[3]_lut_out = ZD2_safe_q[3] $ (ZD2L8);
ZD2_safe_q[3] = DFFEAS(ZD2_safe_q[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , WD2L1, , , , );
--ZD2L11 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella3~COUT at LC_X50_Y15_N4
--operation mode is arithmetic
--T1L27 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~297 at LC_X51_Y17_N3
--operation mode is arithmetic
T1L27 = ZD1_safe_q[3] $ (!T1L24);
--T1L28 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~298 at LC_X51_Y17_N3
--operation mode is arithmetic
T1L28_cout_0 = ZD1_safe_q[3] # !T1L24;
T1L28 = CARRY(T1L28_cout_0);
--T1L29 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~298COUT1_355 at LC_X51_Y17_N3
--operation mode is arithmetic
T1L29_cout_1 = ZD1_safe_q[3] # !T1L25;
T1L29 = CARRY(T1L29_cout_1);
--T1L30 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~299 at LC_X51_Y17_N9
--operation mode is normal
T1L30 = T1_read_0 & ZD2_safe_q[3] # !T1_read_0 & (T1L27);
--L1_i_readdata_d1[9] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[9] at LC_X45_Y14_N8
--operation mode is normal
L1_i_readdata_d1[9] = AMPP_FUNCTION(DE1__clk0, FC1L12, P1L10, FC1L21, N1L36, E1_data_out);
--M1L303 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~23 at LC_X48_Y18_N7
--operation mode is normal
M1L303 = AE2_q_b[7] & T1_read_0 # !EB1L2 # !U1L2;
--M1L275 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[7]~2086 at LC_X48_Y18_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[7]_qfbk = H1_slave_readdata[7];
M1L275 = H1_slave_readdata[7]_qfbk # !J1_cpu_data_master_requests_clock_0_in;
--H1_slave_readdata[7] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[7] at LC_X48_Y18_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[7] = DFFEAS(M1L275, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[7], , , VCC);
--HE1L61 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[7]~681 at LC_X50_Y8_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_internal_tx_data[7]_qfbk = HE1_internal_tx_data[7];
HE1L61 = L1_M_alu_result[3] & (HE1_control_reg[7]) # !L1_M_alu_result[3] & HE1_internal_tx_data[7]_qfbk;
--HE1_internal_tx_data[7] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[7] at LC_X50_Y8_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_internal_tx_data[7] = DFFEAS(HE1L61, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L64, L1_M_st_data[7], , , VCC);
--HE1L62 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[7]~682 at LC_X51_Y9_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[7]_qfbk = JE1_rx_data[7];
HE1L62 = L1_M_alu_result[3] & (JE1_internal_rx_char_ready) # !L1_M_alu_result[3] & JE1_rx_data[7]_qfbk;
--JE1_rx_data[7] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[7] at LC_X51_Y9_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[7] = DFFEAS(HE1L62, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1_got_new_char, JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8], , , VCC);
--R1_counter_snapshot[23] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[23] at LC_X46_Y7_N9
--operation mode is normal
R1_counter_snapshot[23]_lut_out = R1_internal_counter[23];
R1_counter_snapshot[23] = DFFEAS(R1_counter_snapshot[23]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, , , , );
--R1L197 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[7]~1253 at LC_X46_Y7_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[7]_qfbk = R1_counter_snapshot[7];
R1L197 = L1_M_alu_result[4] & (L1_M_alu_result[2] & (R1_counter_snapshot[23]) # !L1_M_alu_result[2] & R1_counter_snapshot[7]_qfbk) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--R1_counter_snapshot[7] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[7] at LC_X46_Y7_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[7] = DFFEAS(R1L197, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[7], , , VCC);
--R1_period_l_register[7] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[7] at LC_X48_Y5_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_l_register[7]_lut_out = GND;
R1_period_l_register[7] = DFFEAS(R1_period_l_register[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, L1_M_st_data[7], , , VCC);
--R1L198 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[7]~1254 at LC_X47_Y9_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[7]_qfbk = R1_period_h_register[7];
R1L198 = R1L197 & (R1_period_h_register[7]_qfbk) # !R1L197 & R1_period_l_register[7];
--R1_period_h_register[7] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[7] at LC_X47_Y9_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[7] = DFFEAS(R1L198, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[7], , , VCC);
--KB1_counter_snapshot[23] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[23] at LC_X52_Y3_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[23]_lut_out = GND;
KB1_counter_snapshot[23] = DFFEAS(KB1_counter_snapshot[23]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[23], , , VCC);
--KB1L198 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[7]~1242 at LC_X52_Y3_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[7]_qfbk = KB1_counter_snapshot[7];
KB1L198 = L1_M_alu_result[4] & (L1_M_alu_result[2] & (KB1_counter_snapshot[23]) # !L1_M_alu_result[2] & KB1_counter_snapshot[7]_qfbk) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--KB1_counter_snapshot[7] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[7] at LC_X52_Y3_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[7] = DFFEAS(KB1L198, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[7], , , VCC);
--KB1_period_l_register[7] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[7] at LC_X48_Y5_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_l_register[7]_lut_out = GND;
KB1_period_l_register[7] = DFFEAS(KB1_period_l_register[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, L1_M_st_data[7], , , VCC);
--KB1L199 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[7]~1243 at LC_X50_Y6_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[7]_qfbk = KB1_period_h_register[7];
KB1L199 = KB1L198 & KB1_period_h_register[7]_qfbk # !KB1L198 & (KB1_period_l_register[7]);
--KB1_period_h_register[7] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[7] at LC_X50_Y6_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[7] = DFFEAS(KB1L199, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, L1_M_st_data[7], , , VCC);
--T1L31 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~300 at LC_X51_Y17_N7
--operation mode is normal
T1L31_carry_eqn = (!T1L33 & T1L38) # (T1L33 & T1L39);
T1L31 = !T1L31_carry_eqn;
--M1L289 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[23]~2088 at LC_X50_Y16_N4
--operation mode is normal
M1L289 = T1L31 & !T1_read_0 # !EB1L2 # !U1L2;
--GC1L6 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~563 at LC_X14_Y10_N4
--operation mode is arithmetic
GC1L6 = AMPP_FUNCTION(L1L699, L1L633, GC1L20, GC1L8, GC1L9);
--L1_E_ctrl_alu_signed_cmp is std_1s10:inst|cpu:the_cpu|E_ctrl_alu_signed_cmp at LC_X22_Y21_N5
--operation mode is normal
L1_E_ctrl_alu_signed_cmp = AMPP_FUNCTION(DE1__clk0, L1L838, L1L209, L1L224, L1L839, E1_data_out, L1_W_stall);
--L1L434 is std_1s10:inst|cpu:the_cpu|E_arith_src2~0 at LC_X18_Y8_N1
--operation mode is normal
L1L434 = AMPP_FUNCTION(L1_E_ctrl_src2_is_imm, L1L808, L1_E_ctrl_alu_signed_cmp, L1_E_src2_imm[31]);
--L1L433 is std_1s10:inst|cpu:the_cpu|E_arith_src1~0 at LC_X18_Y9_N9
--operation mode is normal
L1L433 = AMPP_FUNCTION(L1L634, L1_E_ctrl_alu_signed_cmp);
--HC1_result[30] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[30] at LC_X18_Y9_N0
--operation mode is arithmetic
HC1_result[30] = AMPP_FUNCTION(L1L699, L1L633, HC1L85, L1_E_ctrl_alu_subtract);
--HC1L87 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[30]~COUT at LC_X18_Y9_N0
--operation mode is arithmetic
HC1L87 = AMPP_FUNCTION(L1L699, L1L633, L1_E_ctrl_alu_subtract);
--HC1L88 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[30]~COUTCOUT1_195 at LC_X18_Y9_N0
--operation mode is arithmetic
HC1L88 = AMPP_FUNCTION(L1L699, L1L633, L1_E_ctrl_alu_subtract);
--DD1_sr[19] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[19] at LC_X32_Y25_N2
--operation mode is normal
DD1_sr[19] = AMPP_FUNCTION(!A1L6, DD1L70, DD1L23, DD1L24, DD1_sr[20], !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[18] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[18] at LC_X33_Y25_N3
--operation mode is normal
DD1_sr[18] = AMPP_FUNCTION(!A1L6, DD1L27, DD1_sr[19], DD1L26, DD1L9, !C1_CLR_SIGNAL, DD1L12);
--TC1_break_readreg[20] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[20] at LC_X32_Y26_N7
--operation mode is normal
TC1_break_readreg[20] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[20], DD1_internal_jdo1[36], DD1L188, DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L7 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19891 at LC_X31_Y27_N1
--operation mode is normal
DD1L7 = AMPP_FUNCTION(CD1_internal_MonDReg[20], DD1_ir[1], TC1_break_readreg[20]);
--DD1L8 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19892 at LC_X31_Y27_N4
--operation mode is normal
DD1L8 = AMPP_FUNCTION(DD1_ir[0], DD1L7, DD1L142, DD1L144);
--DD1L9 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19893 at LC_X32_Y25_N4
--operation mode is normal
DD1L9 = AMPP_FUNCTION(DD1_ir[1], DD1L144, A1L5, DD1_ir[0]);
--DD1L10 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19894 at LC_X31_Y27_N0
--operation mode is normal
DD1L10 = AMPP_FUNCTION(DD1L144, DD1L7, DD1_ir[0], A1L5);
--DD1L11 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19896 at LC_X32_Y25_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1L11 = AMPP_FUNCTION(DD1_ir[1]);
--DD1_ir[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0] at LC_X32_Y25_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_ir[0] = AMPP_FUNCTION(!A1L6, ME5_Q[0], VCC, GND, DD1L116);
--DD1L12 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19897 at LC_X32_Y25_N1
--operation mode is normal
DD1L12 = AMPP_FUNCTION(DD1L141, DD1L11, DD1_st_updateir, DD1L143);
--C1L27 is sld_hub:sld_hub_inst|jtag_debug_mode~171 at LC_X28_Y5_N7
--operation mode is normal
C1L27 = AMPP_FUNCTION(A1L8, RE1_state[12], RE1_state[2]);
--RE1_state[15] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] at LC_X28_Y5_N0
--operation mode is normal
RE1_state[15] = AMPP_FUNCTION(!A1L6, RE1_state[14], RE1_state[12], VCC, A1L8);
--SE1_dffe1a[1] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[1] at LC_X29_Y27_N1
--operation mode is normal
SE1_dffe1a[1] = AMPP_FUNCTION(!A1L6, ME3_Q[2], ME3_Q[3], C1L26, ME3_Q[1], !C1_CLR_SIGNAL, C1L5);
--SE1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[2] at LC_X29_Y27_N8
--operation mode is normal
SE1_dffe1a[2] = AMPP_FUNCTION(!A1L6, ME3_Q[2], ME3_Q[3], C1L26, ME3_Q[1], !C1_CLR_SIGNAL, C1L5);
--C1L1 is sld_hub:sld_hub_inst|BROADCAST_ENA~28 at LC_X28_Y27_N3
--operation mode is normal
C1L1 = AMPP_FUNCTION(SE1_dffe1a[1], SE1_dffe1a[2], RE1_state[8], C1_OK_TO_UPDATE_IR_Q);
--TC1_break_readreg[19] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[19] at LC_X32_Y26_N2
--operation mode is normal
TC1_break_readreg[19] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[19], DD1_internal_jdo1[36], DD1L188, DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L13 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19898 at LC_X31_Y27_N2
--operation mode is normal
DD1L13 = AMPP_FUNCTION(CD1_internal_MonDReg[19], DD1_ir[1], TC1_break_readreg[19]);
--DD1L14 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19899 at LC_X31_Y27_N3
--operation mode is normal
DD1L14 = AMPP_FUNCTION(DD1_ir[0], DD1L142, DD1L144, DD1L13);
--DD1L15 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19900 at LC_X31_Y27_N7
--operation mode is normal
DD1L15 = AMPP_FUNCTION(DD1L144, A1L5, DD1_ir[0], DD1L13);
--SE1_dffe1a[7] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated|dffe1a[7] at LC_X29_Y27_N4
--operation mode is normal
SE1_dffe1a[7] = AMPP_FUNCTION(!A1L6, ME3_Q[2], ME3_Q[3], C1L26, ME3_Q[1], !C1_CLR_SIGNAL, C1L5);
--C1L2 is sld_hub:sld_hub_inst|BROADCAST_ENA~29 at LC_X29_Y27_N3
--operation mode is normal
C1L2 = AMPP_FUNCTION(C1_OK_TO_UPDATE_IR_Q, RE1_state[8]);
--VC1_internal_monitor_error is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_error at LC_X34_Y25_N3
--operation mode is normal
VC1_internal_monitor_error = AMPP_FUNCTION(DE1__clk0, DD1L190, L1_M_st_data[1], SC1L13, VC1L3, VCC);
--DD1L16 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19902 at LC_X33_Y24_N4
--operation mode is normal
DD1L16 = AMPP_FUNCTION(DD1_ir[0], DD1_ir[1], VC1_internal_monitor_error);
--DD1L17 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19903 at LC_X33_Y24_N3
--operation mode is normal
DD1L17 = AMPP_FUNCTION(A1L5, DD1L144, DD1_ir[0], DD1_ir[1]);
--DD1_st_updatedr is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updatedr at LC_X35_Y29_N5
--operation mode is normal
DD1_st_updatedr = AMPP_FUNCTION(!A1L6, DD1L144, VCC, !A1L9);
--DD1L131 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux41~108 at LC_X33_Y28_N1
--operation mode is normal
DD1L131 = AMPP_FUNCTION(altera_internal_jtag, DD1_DRsize[1], DD1_DRsize[0], DD1_DRsize[2]);
--DD1_sr[36] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[36] at LC_X32_Y28_N3
--operation mode is normal
DD1_sr[36] = AMPP_FUNCTION(!A1L6, A1L5, DD1L28, DD1_sr[37], DD1L144, !C1_CLR_SIGNAL, DD1L30);
--DD1L132 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux41~109 at LC_X32_Y28_N2
--operation mode is normal
DD1L132 = AMPP_FUNCTION(DD1_sr[36], DD1_DRsize[1], DD1_DRsize[0], DD1_DRsize[2]);
--DD1L18 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19905 at LC_X33_Y28_N9
--operation mode is normal
DD1L18 = AMPP_FUNCTION(A1L5, DD1L144, DD1L131, DD1L132);
--DD1L133 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux41~110 at LC_X33_Y28_N2
--operation mode is normal
DD1L133 = AMPP_FUNCTION(DD1L132, DD1L131);
--DD1L19 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19906 at LC_X33_Y28_N3
--operation mode is normal
DD1L19 = AMPP_FUNCTION(L1_hbreak_enabled, DD1L143, DD1_ir[1], DD1L133);
--ME7_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[0] at LC_X30_Y28_N4
--operation mode is normal
ME7_Q[0] = AMPP_FUNCTION(!A1L6, ME3_Q[0], !C1_CLR_SIGNAL, C1L8);
--C1L9 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~18 at LC_X29_Y27_N0
--operation mode is normal
C1L9 = AMPP_FUNCTION(C1_OK_TO_UPDATE_IR_Q, RE1_state[5]);
--C1L19 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~125 at LC_X31_Y26_N8
--operation mode is normal
C1L19 = AMPP_FUNCTION(ME2_Q[0], SE1_dffe1a[2], ME9_Q[0]);
--C1L20 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~126 at LC_X30_Y26_N4
--operation mode is normal
C1L20 = AMPP_FUNCTION(ME2_Q[0], ME8_Q[0], C1L19, C1L9);
--DD1L145 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process4~0 at LC_X30_Y26_N7
--operation mode is normal
DD1L145 = AMPP_FUNCTION(ME2_Q[0], C1_jtag_debug_mode_usr1, C1_jtag_debug_mode, ME8_Q[0]);
--ME7_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[1] at LC_X30_Y28_N6
--operation mode is normal
ME7_Q[1] = AMPP_FUNCTION(!A1L6, ME3_Q[1], !C1_CLR_SIGNAL, C1L8);
--R1_control_wr_strobe is std_1s10:inst|high_res_timer:the_high_res_timer|control_wr_strobe at LC_X46_Y9_N5
--operation mode is normal
R1_control_wr_strobe = S1L2 & HE1L19 & KB1L7 & LB1L2;
--R1_internal_counter[0] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[0] at LC_X47_Y8_N4
--operation mode is arithmetic
R1_internal_counter[0]_lut_out = !R1_internal_counter[0];
R1_internal_counter[0] = DFFEAS(R1_internal_counter[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[0], , , R1L180);
--R1L57 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[0]~2944 at LC_X47_Y8_N4
--operation mode is arithmetic
R1L57 = CARRY(!R1_internal_counter[0]);
--R1_internal_counter[1] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[1] at LC_X47_Y8_N5
--operation mode is arithmetic
R1_internal_counter[1]_carry_eqn = R1L57;
R1_internal_counter[1]_lut_out = R1_internal_counter[1] $ !R1_internal_counter[1]_carry_eqn;
R1_internal_counter[1] = DFFEAS(R1_internal_counter[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[1], , , R1L180);
--R1L59 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[1]~2945 at LC_X47_Y8_N5
--operation mode is arithmetic
R1L59_cout_0 = R1_internal_counter[1] & !R1L57;
R1L59 = CARRY(R1L59_cout_0);
--R1L60 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[1]~2945COUT1_3098 at LC_X47_Y8_N5
--operation mode is arithmetic
R1L60_cout_1 = R1_internal_counter[1] & !R1L57;
R1L60 = CARRY(R1L60_cout_1);
--R1_internal_counter[2] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[2] at LC_X47_Y8_N6
--operation mode is arithmetic
R1_internal_counter[2]_carry_eqn = (!R1L57 & R1L59) # (R1L57 & R1L60);
R1_internal_counter[2]_lut_out = R1_internal_counter[2] $ R1_internal_counter[2]_carry_eqn;
R1_internal_counter[2] = DFFEAS(R1_internal_counter[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[2], , , R1L180);
--R1L62 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[2]~2946 at LC_X47_Y8_N6
--operation mode is arithmetic
R1L62_cout_0 = !R1L59 # !R1_internal_counter[2];
R1L62 = CARRY(R1L62_cout_0);
--R1L63 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[2]~2946COUT1_3100 at LC_X47_Y8_N6
--operation mode is arithmetic
R1L63_cout_1 = !R1L60 # !R1_internal_counter[2];
R1L63 = CARRY(R1L63_cout_1);
--R1_internal_counter[3] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[3] at LC_X47_Y8_N7
--operation mode is arithmetic
R1_internal_counter[3]_carry_eqn = (!R1L57 & R1L62) # (R1L57 & R1L63);
R1_internal_counter[3]_lut_out = R1_internal_counter[3] $ (!R1_internal_counter[3]_carry_eqn);
R1_internal_counter[3] = DFFEAS(R1_internal_counter[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[3], , , R1L180);
--R1L65 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[3]~2947 at LC_X47_Y8_N7
--operation mode is arithmetic
R1L65_cout_0 = R1_internal_counter[3] & (!R1L62);
R1L65 = CARRY(R1L65_cout_0);
--R1L66 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[3]~2947COUT1_3102 at LC_X47_Y8_N7
--operation mode is arithmetic
R1L66_cout_1 = R1_internal_counter[3] & (!R1L63);
R1L66 = CARRY(R1L66_cout_1);
--R1L44 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~364 at LC_X47_Y4_N7
--operation mode is normal
R1L44 = R1_internal_counter[1] & R1_internal_counter[2] & R1_internal_counter[0] & R1_internal_counter[3];
--R1_internal_counter[6] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[6] at LC_X47_Y7_N0
--operation mode is arithmetic
R1_internal_counter[6]_carry_eqn = R1L71;
R1_internal_counter[6]_lut_out = R1_internal_counter[6] $ R1_internal_counter[6]_carry_eqn;
R1_internal_counter[6] = DFFEAS(R1_internal_counter[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[6], , , R1L180);
--R1L73 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[6]~2948 at LC_X47_Y7_N0
--operation mode is arithmetic
R1L73_cout_0 = !R1L71 # !R1_internal_counter[6];
R1L73 = CARRY(R1L73_cout_0);
--R1L74 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[6]~2948COUT1_3106 at LC_X47_Y7_N0
--operation mode is arithmetic
R1L74_cout_1 = !R1L71 # !R1_internal_counter[6];
R1L74 = CARRY(R1L74_cout_1);
--R1_internal_counter[4] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[4] at LC_X47_Y8_N8
--operation mode is arithmetic
R1_internal_counter[4]_carry_eqn = (!R1L57 & R1L65) # (R1L57 & R1L66);
R1_internal_counter[4]_lut_out = R1_internal_counter[4] $ (R1_internal_counter[4]_carry_eqn);
R1_internal_counter[4] = DFFEAS(R1_internal_counter[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[4], , , R1L180);
--R1L68 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[4]~2949 at LC_X47_Y8_N8
--operation mode is arithmetic
R1L68_cout_0 = R1_internal_counter[4] # !R1L65;
R1L68 = CARRY(R1L68_cout_0);
--R1L69 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[4]~2949COUT1_3104 at LC_X47_Y8_N8
--operation mode is arithmetic
R1L69_cout_1 = R1_internal_counter[4] # !R1L66;
R1L69 = CARRY(R1L69_cout_1);
--R1_internal_counter[5] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[5] at LC_X47_Y8_N9
--operation mode is arithmetic
R1_internal_counter[5]_carry_eqn = (!R1L57 & R1L68) # (R1L57 & R1L69);
R1_internal_counter[5]_lut_out = R1_internal_counter[5] $ !R1_internal_counter[5]_carry_eqn;
R1_internal_counter[5] = DFFEAS(R1_internal_counter[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[5], , , R1L180);
--R1L71 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[5]~2950 at LC_X47_Y8_N9
--operation mode is arithmetic
R1L71 = CARRY(!R1_internal_counter[5] & !R1L69);
--R1_internal_counter[7] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[7] at LC_X47_Y7_N1
--operation mode is arithmetic
R1_internal_counter[7]_carry_eqn = (!R1L71 & R1L73) # (R1L71 & R1L74);
R1_internal_counter[7]_lut_out = R1_internal_counter[7] $ !R1_internal_counter[7]_carry_eqn;
R1_internal_counter[7] = DFFEAS(R1_internal_counter[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[7], , , R1L180);
--R1L76 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[7]~2951 at LC_X47_Y7_N1
--operation mode is arithmetic
R1L76_cout_0 = !R1_internal_counter[7] & !R1L73;
R1L76 = CARRY(R1L76_cout_0);
--R1L77 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[7]~2951COUT1_3108 at LC_X47_Y7_N1
--operation mode is arithmetic
R1L77_cout_1 = !R1_internal_counter[7] & !R1L74;
R1L77 = CARRY(R1L77_cout_1);
--R1L45 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~365 at LC_X46_Y7_N5
--operation mode is normal
R1L45 = !R1_internal_counter[5] & !R1_internal_counter[4] & R1_internal_counter[6] & !R1_internal_counter[7];
--R1_internal_counter[8] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[8] at LC_X47_Y7_N2
--operation mode is arithmetic
R1_internal_counter[8]_carry_eqn = (!R1L71 & R1L76) # (R1L71 & R1L77);
R1_internal_counter[8]_lut_out = R1_internal_counter[8] $ (R1_internal_counter[8]_carry_eqn);
R1_internal_counter[8] = DFFEAS(R1_internal_counter[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[8], , , R1L180);
--R1L79 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[8]~2952 at LC_X47_Y7_N2
--operation mode is arithmetic
R1L79_cout_0 = !R1L76 # !R1_internal_counter[8];
R1L79 = CARRY(R1L79_cout_0);
--R1L80 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[8]~2952COUT1_3110 at LC_X47_Y7_N2
--operation mode is arithmetic
R1L80_cout_1 = !R1L77 # !R1_internal_counter[8];
R1L80 = CARRY(R1L80_cout_1);
--R1_internal_counter[9] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[9] at LC_X47_Y7_N3
--operation mode is arithmetic
R1_internal_counter[9]_carry_eqn = (!R1L71 & R1L79) # (R1L71 & R1L80);
R1_internal_counter[9]_lut_out = R1_internal_counter[9] $ (!R1_internal_counter[9]_carry_eqn);
R1_internal_counter[9] = DFFEAS(R1_internal_counter[9]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[9], , , R1L180);
--R1L82 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[9]~2953 at LC_X47_Y7_N3
--operation mode is arithmetic
R1L82_cout_0 = R1_internal_counter[9] & (!R1L79);
R1L82 = CARRY(R1L82_cout_0);
--R1L83 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[9]~2953COUT1_3112 at LC_X47_Y7_N3
--operation mode is arithmetic
R1L83_cout_1 = R1_internal_counter[9] & (!R1L80);
R1L83 = CARRY(R1L83_cout_1);
--R1_internal_counter[10] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[10] at LC_X47_Y7_N4
--operation mode is arithmetic
R1_internal_counter[10]_carry_eqn = (!R1L71 & R1L82) # (R1L71 & R1L83);
R1_internal_counter[10]_lut_out = R1_internal_counter[10] $ (R1_internal_counter[10]_carry_eqn);
R1_internal_counter[10] = DFFEAS(R1_internal_counter[10]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[10], , , R1L180);
--R1L85 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[10]~2954 at LC_X47_Y7_N4
--operation mode is arithmetic
R1L85 = CARRY(R1_internal_counter[10] # !R1L83);
--R1_internal_counter[11] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[11] at LC_X47_Y7_N5
--operation mode is arithmetic
R1_internal_counter[11]_carry_eqn = R1L85;
R1_internal_counter[11]_lut_out = R1_internal_counter[11] $ !R1_internal_counter[11]_carry_eqn;
R1_internal_counter[11] = DFFEAS(R1_internal_counter[11]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[11], , , R1L180);
--R1L87 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[11]~2955 at LC_X47_Y7_N5
--operation mode is arithmetic
R1L87_cout_0 = !R1_internal_counter[11] & !R1L85;
R1L87 = CARRY(R1L87_cout_0);
--R1L88 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[11]~2955COUT1_3114 at LC_X47_Y7_N5
--operation mode is arithmetic
R1L88_cout_1 = !R1_internal_counter[11] & !R1L85;
R1L88 = CARRY(R1L88_cout_1);
--R1L46 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~366 at LC_X48_Y4_N6
--operation mode is normal
R1L46 = !R1_internal_counter[11] & R1_internal_counter[8] & R1_internal_counter[9] & !R1_internal_counter[10];
--R1_internal_counter[14] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[14] at LC_X47_Y7_N8
--operation mode is arithmetic
R1_internal_counter[14]_carry_eqn = (!R1L85 & R1L93) # (R1L85 & R1L94);
R1_internal_counter[14]_lut_out = R1_internal_counter[14] $ (R1_internal_counter[14]_carry_eqn);
R1_internal_counter[14] = DFFEAS(R1_internal_counter[14]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[14], , , R1L180);
--R1L96 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[14]~2956 at LC_X47_Y7_N8
--operation mode is arithmetic
R1L96_cout_0 = !R1L93 # !R1_internal_counter[14];
R1L96 = CARRY(R1L96_cout_0);
--R1L97 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[14]~2956COUT1_3120 at LC_X47_Y7_N8
--operation mode is arithmetic
R1L97_cout_1 = !R1L94 # !R1_internal_counter[14];
R1L97 = CARRY(R1L97_cout_1);
--R1_internal_counter[15] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[15] at LC_X47_Y7_N9
--operation mode is arithmetic
R1_internal_counter[15]_carry_eqn = (!R1L85 & R1L96) # (R1L85 & R1L97);
R1_internal_counter[15]_lut_out = R1_internal_counter[15] $ !R1_internal_counter[15]_carry_eqn;
R1_internal_counter[15] = DFFEAS(R1_internal_counter[15]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[15], , , R1L180);
--R1L99 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[15]~2957 at LC_X47_Y7_N9
--operation mode is arithmetic
R1L99 = CARRY(R1_internal_counter[15] & !R1L97);
--R1_internal_counter[12] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[12] at LC_X47_Y7_N6
--operation mode is arithmetic
R1_internal_counter[12]_carry_eqn = (!R1L85 & R1L87) # (R1L85 & R1L88);
R1_internal_counter[12]_lut_out = R1_internal_counter[12] $ R1_internal_counter[12]_carry_eqn;
R1_internal_counter[12] = DFFEAS(R1_internal_counter[12]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[12], , , R1L180);
--R1L90 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[12]~2958 at LC_X47_Y7_N6
--operation mode is arithmetic
R1L90_cout_0 = R1_internal_counter[12] # !R1L87;
R1L90 = CARRY(R1L90_cout_0);
--R1L91 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[12]~2958COUT1_3116 at LC_X47_Y7_N6
--operation mode is arithmetic
R1L91_cout_1 = R1_internal_counter[12] # !R1L88;
R1L91 = CARRY(R1L91_cout_1);
--R1_internal_counter[13] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[13] at LC_X47_Y7_N7
--operation mode is arithmetic
R1_internal_counter[13]_carry_eqn = (!R1L85 & R1L90) # (R1L85 & R1L91);
R1_internal_counter[13]_lut_out = R1_internal_counter[13] $ (!R1_internal_counter[13]_carry_eqn);
R1_internal_counter[13] = DFFEAS(R1_internal_counter[13]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_l_register[13], , , R1L180);
--R1L93 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[13]~2959 at LC_X47_Y7_N7
--operation mode is arithmetic
R1L93_cout_0 = !R1_internal_counter[13] & (!R1L90);
R1L93 = CARRY(R1L93_cout_0);
--R1L94 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[13]~2959COUT1_3118 at LC_X47_Y7_N7
--operation mode is arithmetic
R1L94_cout_1 = !R1_internal_counter[13] & (!R1L91);
R1L94 = CARRY(R1L94_cout_1);
--R1L47 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~367 at LC_X46_Y6_N7
--operation mode is normal
R1L47 = R1_internal_counter[15] & !R1_internal_counter[13] & !R1_internal_counter[12] & R1_internal_counter[14];
--R1L48 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~368 at LC_X48_Y7_N0
--operation mode is normal
R1L48 = R1L46 & R1L47 & R1L44 & R1L45;
--R1_internal_counter[16] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[16] at LC_X47_Y6_N0
--operation mode is arithmetic
R1_internal_counter[16]_carry_eqn = R1L99;
R1_internal_counter[16]_lut_out = R1_internal_counter[16] $ R1_internal_counter[16]_carry_eqn;
R1_internal_counter[16] = DFFEAS(R1_internal_counter[16]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[0], , , R1L180);
--R1L101 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[16]~2960 at LC_X47_Y6_N0
--operation mode is arithmetic
R1L101_cout_0 = R1_internal_counter[16] # !R1L99;
R1L101 = CARRY(R1L101_cout_0);
--R1L102 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[16]~2960COUT1_3122 at LC_X47_Y6_N0
--operation mode is arithmetic
R1L102_cout_1 = R1_internal_counter[16] # !R1L99;
R1L102 = CARRY(R1L102_cout_1);
--R1_internal_counter[17] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[17] at LC_X47_Y6_N1
--operation mode is arithmetic
R1_internal_counter[17]_carry_eqn = (!R1L99 & R1L101) # (R1L99 & R1L102);
R1_internal_counter[17]_lut_out = R1_internal_counter[17] $ !R1_internal_counter[17]_carry_eqn;
R1_internal_counter[17] = DFFEAS(R1_internal_counter[17]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[1], , , R1L180);
--R1L104 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[17]~2961 at LC_X47_Y6_N1
--operation mode is arithmetic
R1L104_cout_0 = !R1_internal_counter[17] & !R1L101;
R1L104 = CARRY(R1L104_cout_0);
--R1L105 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[17]~2961COUT1_3124 at LC_X47_Y6_N1
--operation mode is arithmetic
R1L105_cout_1 = !R1_internal_counter[17] & !R1L102;
R1L105 = CARRY(R1L105_cout_1);
--R1_internal_counter[18] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[18] at LC_X47_Y6_N2
--operation mode is arithmetic
R1_internal_counter[18]_carry_eqn = (!R1L99 & R1L104) # (R1L99 & R1L105);
R1_internal_counter[18]_lut_out = R1_internal_counter[18] $ (R1_internal_counter[18]_carry_eqn);
R1_internal_counter[18] = DFFEAS(R1_internal_counter[18]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[2], , , R1L180);
--R1L107 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[18]~2962 at LC_X47_Y6_N2
--operation mode is arithmetic
R1L107_cout_0 = R1_internal_counter[18] # !R1L104;
R1L107 = CARRY(R1L107_cout_0);
--R1L108 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[18]~2962COUT1_3126 at LC_X47_Y6_N2
--operation mode is arithmetic
R1L108_cout_1 = R1_internal_counter[18] # !R1L105;
R1L108 = CARRY(R1L108_cout_1);
--R1_internal_counter[19] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[19] at LC_X47_Y6_N3
--operation mode is arithmetic
R1_internal_counter[19]_carry_eqn = (!R1L99 & R1L107) # (R1L99 & R1L108);
R1_internal_counter[19]_lut_out = R1_internal_counter[19] $ (!R1_internal_counter[19]_carry_eqn);
R1_internal_counter[19] = DFFEAS(R1_internal_counter[19]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[3], , , R1L180);
--R1L110 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[19]~2963 at LC_X47_Y6_N3
--operation mode is arithmetic
R1L110_cout_0 = !R1_internal_counter[19] & (!R1L107);
R1L110 = CARRY(R1L110_cout_0);
--R1L111 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[19]~2963COUT1_3128 at LC_X47_Y6_N3
--operation mode is arithmetic
R1L111_cout_1 = !R1_internal_counter[19] & (!R1L108);
R1L111 = CARRY(R1L111_cout_1);
--R1L49 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~369 at LC_X48_Y6_N1
--operation mode is normal
R1L49 = !R1_internal_counter[16] & !R1_internal_counter[17] & !R1_internal_counter[19] & !R1_internal_counter[18];
--R1_internal_counter[20] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[20] at LC_X47_Y6_N4
--operation mode is arithmetic
R1_internal_counter[20]_carry_eqn = (!R1L99 & R1L110) # (R1L99 & R1L111);
R1_internal_counter[20]_lut_out = R1_internal_counter[20] $ (R1_internal_counter[20]_carry_eqn);
R1_internal_counter[20] = DFFEAS(R1_internal_counter[20]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[4], , , R1L180);
--R1L113 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[20]~2964 at LC_X47_Y6_N4
--operation mode is arithmetic
R1L113 = CARRY(R1_internal_counter[20] # !R1L111);
--R1_internal_counter[21] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[21] at LC_X47_Y6_N5
--operation mode is arithmetic
R1_internal_counter[21]_carry_eqn = R1L113;
R1_internal_counter[21]_lut_out = R1_internal_counter[21] $ !R1_internal_counter[21]_carry_eqn;
R1_internal_counter[21] = DFFEAS(R1_internal_counter[21]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[5], , , R1L180);
--R1L115 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[21]~2965 at LC_X47_Y6_N5
--operation mode is arithmetic
R1L115_cout_0 = !R1_internal_counter[21] & !R1L113;
R1L115 = CARRY(R1L115_cout_0);
--R1L116 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[21]~2965COUT1_3130 at LC_X47_Y6_N5
--operation mode is arithmetic
R1L116_cout_1 = !R1_internal_counter[21] & !R1L113;
R1L116 = CARRY(R1L116_cout_1);
--R1_internal_counter[22] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[22] at LC_X47_Y6_N6
--operation mode is arithmetic
R1_internal_counter[22]_carry_eqn = (!R1L113 & R1L115) # (R1L113 & R1L116);
R1_internal_counter[22]_lut_out = R1_internal_counter[22] $ R1_internal_counter[22]_carry_eqn;
R1_internal_counter[22] = DFFEAS(R1_internal_counter[22]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[6], , , R1L180);
--R1L118 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[22]~2966 at LC_X47_Y6_N6
--operation mode is arithmetic
R1L118_cout_0 = R1_internal_counter[22] # !R1L115;
R1L118 = CARRY(R1L118_cout_0);
--R1L119 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[22]~2966COUT1_3132 at LC_X47_Y6_N6
--operation mode is arithmetic
R1L119_cout_1 = R1_internal_counter[22] # !R1L116;
R1L119 = CARRY(R1L119_cout_1);
--R1_internal_counter[23] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[23] at LC_X47_Y6_N7
--operation mode is arithmetic
R1_internal_counter[23]_carry_eqn = (!R1L113 & R1L118) # (R1L113 & R1L119);
R1_internal_counter[23]_lut_out = R1_internal_counter[23] $ (!R1_internal_counter[23]_carry_eqn);
R1_internal_counter[23] = DFFEAS(R1_internal_counter[23]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[7], , , R1L180);
--R1L121 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[23]~2967 at LC_X47_Y6_N7
--operation mode is arithmetic
R1L121_cout_0 = !R1_internal_counter[23] & (!R1L118);
R1L121 = CARRY(R1L121_cout_0);
--R1L122 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[23]~2967COUT1_3134 at LC_X47_Y6_N7
--operation mode is arithmetic
R1L122_cout_1 = !R1_internal_counter[23] & (!R1L119);
R1L122 = CARRY(R1L122_cout_1);
--R1L50 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~370 at LC_X48_Y6_N4
--operation mode is normal
R1L50 = !R1_internal_counter[23] & !R1_internal_counter[22] & !R1_internal_counter[21] & !R1_internal_counter[20];
--R1_internal_counter[24] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[24] at LC_X47_Y6_N8
--operation mode is arithmetic
R1_internal_counter[24]_carry_eqn = (!R1L113 & R1L121) # (R1L113 & R1L122);
R1_internal_counter[24]_lut_out = R1_internal_counter[24] $ (R1_internal_counter[24]_carry_eqn);
R1_internal_counter[24] = DFFEAS(R1_internal_counter[24]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[8], , , R1L180);
--R1L124 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[24]~2968 at LC_X47_Y6_N8
--operation mode is arithmetic
R1L124_cout_0 = R1_internal_counter[24] # !R1L121;
R1L124 = CARRY(R1L124_cout_0);
--R1L125 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[24]~2968COUT1_3136 at LC_X47_Y6_N8
--operation mode is arithmetic
R1L125_cout_1 = R1_internal_counter[24] # !R1L122;
R1L125 = CARRY(R1L125_cout_1);
--R1_internal_counter[25] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[25] at LC_X47_Y6_N9
--operation mode is arithmetic
R1_internal_counter[25]_carry_eqn = (!R1L113 & R1L124) # (R1L113 & R1L125);
R1_internal_counter[25]_lut_out = R1_internal_counter[25] $ !R1_internal_counter[25]_carry_eqn;
R1_internal_counter[25] = DFFEAS(R1_internal_counter[25]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[9], , , R1L180);
--R1L127 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[25]~2969 at LC_X47_Y6_N9
--operation mode is arithmetic
R1L127 = CARRY(!R1_internal_counter[25] & !R1L125);
--R1_internal_counter[26] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[26] at LC_X47_Y5_N0
--operation mode is arithmetic
R1_internal_counter[26]_carry_eqn = R1L127;
R1_internal_counter[26]_lut_out = R1_internal_counter[26] $ R1_internal_counter[26]_carry_eqn;
R1_internal_counter[26] = DFFEAS(R1_internal_counter[26]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[10], , , R1L180);
--R1L129 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[26]~2970 at LC_X47_Y5_N0
--operation mode is arithmetic
R1L129_cout_0 = R1_internal_counter[26] # !R1L127;
R1L129 = CARRY(R1L129_cout_0);
--R1L130 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[26]~2970COUT1_3138 at LC_X47_Y5_N0
--operation mode is arithmetic
R1L130_cout_1 = R1_internal_counter[26] # !R1L127;
R1L130 = CARRY(R1L130_cout_1);
--R1_internal_counter[27] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[27] at LC_X47_Y5_N1
--operation mode is arithmetic
R1_internal_counter[27]_carry_eqn = (!R1L127 & R1L129) # (R1L127 & R1L130);
R1_internal_counter[27]_lut_out = R1_internal_counter[27] $ !R1_internal_counter[27]_carry_eqn;
R1_internal_counter[27] = DFFEAS(R1_internal_counter[27]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[11], , , R1L180);
--R1L132 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[27]~2971 at LC_X47_Y5_N1
--operation mode is arithmetic
R1L132_cout_0 = !R1_internal_counter[27] & !R1L129;
R1L132 = CARRY(R1L132_cout_0);
--R1L133 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[27]~2971COUT1_3140 at LC_X47_Y5_N1
--operation mode is arithmetic
R1L133_cout_1 = !R1_internal_counter[27] & !R1L130;
R1L133 = CARRY(R1L133_cout_1);
--R1L51 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~371 at LC_X48_Y6_N3
--operation mode is normal
R1L51 = !R1_internal_counter[26] & !R1_internal_counter[27] & !R1_internal_counter[25] & !R1_internal_counter[24];
--R1_internal_counter[28] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[28] at LC_X47_Y5_N2
--operation mode is arithmetic
R1_internal_counter[28]_carry_eqn = (!R1L127 & R1L132) # (R1L127 & R1L133);
R1_internal_counter[28]_lut_out = R1_internal_counter[28] $ (R1_internal_counter[28]_carry_eqn);
R1_internal_counter[28] = DFFEAS(R1_internal_counter[28]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[12], , , R1L180);
--R1L135 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[28]~2972 at LC_X47_Y5_N2
--operation mode is arithmetic
R1L135_cout_0 = R1_internal_counter[28] # !R1L132;
R1L135 = CARRY(R1L135_cout_0);
--R1L136 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[28]~2972COUT1_3142 at LC_X47_Y5_N2
--operation mode is arithmetic
R1L136_cout_1 = R1_internal_counter[28] # !R1L133;
R1L136 = CARRY(R1L136_cout_1);
--R1_internal_counter[29] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[29] at LC_X47_Y5_N3
--operation mode is arithmetic
R1_internal_counter[29]_carry_eqn = (!R1L127 & R1L135) # (R1L127 & R1L136);
R1_internal_counter[29]_lut_out = R1_internal_counter[29] $ (!R1_internal_counter[29]_carry_eqn);
R1_internal_counter[29] = DFFEAS(R1_internal_counter[29]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[13], , , R1L180);
--R1L138 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[29]~2973 at LC_X47_Y5_N3
--operation mode is arithmetic
R1L138_cout_0 = !R1_internal_counter[29] & (!R1L135);
R1L138 = CARRY(R1L138_cout_0);
--R1L139 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[29]~2973COUT1_3144 at LC_X47_Y5_N3
--operation mode is arithmetic
R1L139_cout_1 = !R1_internal_counter[29] & (!R1L136);
R1L139 = CARRY(R1L139_cout_1);
--R1_internal_counter[30] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[30] at LC_X47_Y5_N4
--operation mode is arithmetic
R1_internal_counter[30]_carry_eqn = (!R1L127 & R1L138) # (R1L127 & R1L139);
R1_internal_counter[30]_lut_out = R1_internal_counter[30] $ (R1_internal_counter[30]_carry_eqn);
R1_internal_counter[30] = DFFEAS(R1_internal_counter[30]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[14], , , R1L180);
--R1L141 is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[30]~2974 at LC_X47_Y5_N4
--operation mode is arithmetic
R1L141 = CARRY(R1_internal_counter[30] # !R1L139);
--R1_internal_counter[31] is std_1s10:inst|high_res_timer:the_high_res_timer|internal_counter[31] at LC_X47_Y5_N5
--operation mode is normal
R1_internal_counter[31]_carry_eqn = R1L141;
R1_internal_counter[31]_lut_out = R1_internal_counter[31] $ !R1_internal_counter[31]_carry_eqn;
R1_internal_counter[31] = DFFEAS(R1_internal_counter[31]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L179, R1_period_h_register[15], , , R1L180);
--R1L52 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~372 at LC_X46_Y6_N8
--operation mode is normal
R1L52 = !R1_internal_counter[28] & !R1_internal_counter[29] & !R1_internal_counter[30] & !R1_internal_counter[31];
--R1L53 is std_1s10:inst|high_res_timer:the_high_res_timer|Equal0~373 at LC_X48_Y6_N8
--operation mode is normal
R1L53 = R1L51 & R1L49 & R1L52 & R1L50;
--R1_delayed_unxcounter_is_zeroxx0 is std_1s10:inst|high_res_timer:the_high_res_timer|delayed_unxcounter_is_zeroxx0 at LC_X48_Y7_N9
--operation mode is normal
R1_delayed_unxcounter_is_zeroxx0_lut_out = R1L53 & R1L48;
R1_delayed_unxcounter_is_zeroxx0 = DFFEAS(R1_delayed_unxcounter_is_zeroxx0_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--R1L234 is std_1s10:inst|high_res_timer:the_high_res_timer|timeout_occurred~37 at LC_X48_Y7_N2
--operation mode is normal
R1L234 = R1_timeout_occurred # R1L48 & R1L53 & !R1_delayed_unxcounter_is_zeroxx0;
--HE1L21 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~105 at LC_X50_Y8_N7
--operation mode is normal
HE1L21 = !L1_M_alu_result[3] & !L1_M_alu_result[4] & !L1_M_alu_result[2];
--M1L300 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~20 at LC_X47_Y18_N6
--operation mode is normal
M1L300 = AE2_q_b[4] & T1_read_0 # !EB1L2 # !U1L2;
--M1L272 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[4]~2090 at LC_X47_Y18_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[4]_qfbk = H1_slave_readdata[4];
M1L272 = H1_slave_readdata[4]_qfbk # !J1_cpu_data_master_requests_clock_0_in;
--H1_slave_readdata[4] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[4] at LC_X47_Y18_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[4] = DFFEAS(M1L272, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[4], , , VCC);
--HE1L55 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[4]~684 at LC_X51_Y9_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_internal_tx_data[4]_qfbk = HE1_internal_tx_data[4];
HE1L55 = L1_M_alu_result[3] & (HE1_control_reg[4]) # !L1_M_alu_result[3] & HE1_internal_tx_data[4]_qfbk;
--HE1_internal_tx_data[4] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[4] at LC_X51_Y9_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_internal_tx_data[4] = DFFEAS(HE1L55, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L64, L1_M_st_data[4], , , VCC);
--HE1L56 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[4]~685 at LC_X51_Y10_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[4]_qfbk = JE1_rx_data[4];
HE1L56 = L1_M_alu_result[3] & (KE1_tx_overrun) # !L1_M_alu_result[3] & (JE1_rx_data[4]_qfbk);
--JE1_rx_data[4] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[4] at LC_X51_Y10_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[4] = DFFEAS(HE1L56, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1_got_new_char, JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5], , , VCC);
--R1_counter_snapshot[20] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[20] at LC_X46_Y7_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[20]_lut_out = GND;
R1_counter_snapshot[20] = DFFEAS(R1_counter_snapshot[20]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[20], , , VCC);
--R1L191 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[4]~1256 at LC_X46_Y7_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[4]_qfbk = R1_counter_snapshot[4];
R1L191 = L1_M_alu_result[4] & (L1_M_alu_result[2] & (R1_counter_snapshot[20]) # !L1_M_alu_result[2] & R1_counter_snapshot[4]_qfbk) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--R1_counter_snapshot[4] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[4] at LC_X46_Y7_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[4] = DFFEAS(R1L191, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[4], , , VCC);
--R1_period_l_register[4] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[4] at LC_X48_Y5_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_l_register[4]_lut_out = GND;
R1_period_l_register[4] = DFFEAS(R1_period_l_register[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, L1_M_st_data[4], , , VCC);
--R1L192 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[4]~1257 at LC_X47_Y9_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[4]_qfbk = R1_period_h_register[4];
R1L192 = R1L191 & R1_period_h_register[4]_qfbk # !R1L191 & (R1_period_l_register[4]);
--R1_period_h_register[4] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[4] at LC_X47_Y9_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[4] = DFFEAS(R1L192, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[4], , , VCC);
--KB1_counter_snapshot[4] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[4] at LC_X52_Y3_N9
--operation mode is normal
KB1_counter_snapshot[4]_lut_out = !KB1_internal_counter[4];
KB1_counter_snapshot[4] = DFFEAS(KB1_counter_snapshot[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--KB1L192 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[4]~1245 at LC_X52_Y3_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[20]_qfbk = KB1_counter_snapshot[20];
KB1L192 = L1_M_alu_result[4] & (L1_M_alu_result[2] & KB1_counter_snapshot[20]_qfbk # !L1_M_alu_result[2] & (KB1_counter_snapshot[4])) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--KB1_counter_snapshot[20] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[20] at LC_X52_Y3_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[20] = DFFEAS(KB1L192, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[20], , , VCC);
--KB1_period_l_register[4] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[4] at LC_X52_Y5_N2
--operation mode is normal
KB1_period_l_register[4]_lut_out = !L1_M_st_data[4];
KB1_period_l_register[4] = DFFEAS(KB1_period_l_register[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, , , , );
--KB1L193 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[4]~1246 at LC_X50_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[4]_qfbk = KB1_period_h_register[4];
KB1L193 = KB1L192 & KB1_period_h_register[4]_qfbk # !KB1L192 & (!KB1_period_l_register[4]);
--KB1_period_h_register[4] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[4] at LC_X50_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[4] = DFFEAS(KB1L193, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, L1_M_st_data[4], , , VCC);
--M1L286 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[20]~2092 at LC_X46_Y19_N2
--operation mode is normal
M1L286 = L1_M_alu_result[25] # FB1_za_data[20] # !L1_M_alu_result[24] # !QB1L4;
--ZD2_safe_q[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[4] at LC_X50_Y15_N5
--operation mode is arithmetic
ZD2_safe_q[4]_carry_eqn = (!ZD2L11 & GND) # (ZD2L11 & VCC);
ZD2_safe_q[4]_lut_out = ZD2_safe_q[4] $ !ZD2_safe_q[4]_carry_eqn;
ZD2_safe_q[4] = DFFEAS(ZD2_safe_q[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , WD2L1, , , , );
--ZD2L15 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella4~COUT at LC_X50_Y15_N5
--operation mode is arithmetic
ZD2L15_cout_0 = !ZD2L11 & (T1_wr_rfifo $ !ZD2_safe_q[4]);
ZD2L15 = CARRY(ZD2L15_cout_0);
--ZD2L16 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella4~COUTCOUT1_15 at LC_X50_Y15_N5
--operation mode is arithmetic
ZD2L16_cout_1 = !ZD2L11 & (T1_wr_rfifo $ !ZD2_safe_q[4]);
ZD2L16 = CARRY(ZD2L16_cout_1);
--T1L32 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~302 at LC_X51_Y17_N4
--operation mode is arithmetic
T1L32 = ZD1_safe_q[4] $ (T1L28);
--T1L33 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~303 at LC_X51_Y17_N4
--operation mode is arithmetic
--T1L36 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~304 at LC_X46_Y19_N0
--operation mode is normal
T1L36 = T1_read_0 & (ZD2_safe_q[4]) # !T1_read_0 & T1L32;
--L1_i_readdata_d1[10] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[10] at LC_X44_Y11_N9
--operation mode is normal
L1_i_readdata_d1[10] = AMPP_FUNCTION(DE1__clk0, FC1L13, P1L10, FC1L21, N1L39, E1_data_out);
--M1L288 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[22]~2094 at LC_X44_Y18_N5
--operation mode is normal
M1L288 = L1_M_alu_result[25] # FB1_za_data[22] # !L1_M_alu_result[24] # !QB1L4;
--WD2_b_full is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_full at LC_X51_Y15_N0
--operation mode is normal
WD2_b_full_lut_out = WD2_b_non_empty & !T1L58 & (WD2L6 # WD2_b_full) # !WD2_b_non_empty & (WD2_b_full);
WD2_b_full = DFFEAS(WD2_b_full_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--T1L37 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~305 at LC_X51_Y17_N6
--operation mode is arithmetic
T1L37_carry_eqn = (!T1L33 & T1L42) # (T1L33 & T1L43);
T1L37 = WD1_b_full $ (!T1L37_carry_eqn);
--T1L38 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~306 at LC_X51_Y17_N6
--operation mode is arithmetic
T1L38_cout_0 = !T1L42 # !WD1_b_full;
T1L38 = CARRY(T1L38_cout_0);
--T1L39 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~306COUT1_359 at LC_X51_Y17_N6
--operation mode is arithmetic
T1L39_cout_1 = !T1L43 # !WD1_b_full;
T1L39 = CARRY(T1L39_cout_1);
--T1L40 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~307 at LC_X44_Y18_N7
--operation mode is normal
T1L40 = T1_read_0 & WD2_b_full # !T1_read_0 & (T1L37);
--T1_rvalid is std_1s10:inst|jtag_uart:the_jtag_uart|rvalid at LC_X51_Y15_N2
--operation mode is normal
T1_rvalid_lut_out = T1L58 & WD2_b_non_empty # !T1L58 & (T1_rvalid);
T1_rvalid = DFFEAS(T1_rvalid_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L283 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[15]~2096 at LC_X50_Y14_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[15]_qfbk = H1_slave_readdata[15];
M1L283 = FB1_za_data[15] & J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[15]_qfbk # !FB1_za_data[15] & (GB1L24 # J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[15]_qfbk);
--H1_slave_readdata[15] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[15] at LC_X50_Y14_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[15] = DFFEAS(M1L283, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[15], , , VCC);
--AB1L35 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_byteenable[1]~6 at LC_X34_Y11_N8
--operation mode is normal
AB1L35 = L1_M_mem_byte_en[1] # !AB1_onchip_ram_64_kbytes_s1_arb_addend[1] & AB1L11 # !AB1L3;
--KB1_counter_snapshot[15] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[15] at LC_X52_Y3_N8
--operation mode is normal
KB1_counter_snapshot[15]_lut_out = !KB1_internal_counter[15];
KB1_counter_snapshot[15] = DFFEAS(KB1_counter_snapshot[15]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--KB1L214 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[15]~1248 at LC_X52_Y3_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[31]_qfbk = KB1_counter_snapshot[31];
KB1L214 = L1_M_alu_result[4] & (L1_M_alu_result[2] & KB1_counter_snapshot[31]_qfbk # !L1_M_alu_result[2] & (KB1_counter_snapshot[15])) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--KB1_counter_snapshot[31] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[31] at LC_X52_Y3_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[31] = DFFEAS(KB1L214, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[31], , , VCC);
--KB1_period_l_register[15] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[15] at LC_X50_Y4_N2
--operation mode is normal
KB1_period_l_register[15]_lut_out = !L1_M_st_data[15];
KB1_period_l_register[15] = DFFEAS(KB1_period_l_register[15]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, , , , );
--KB1L215 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[15]~1249 at LC_X50_Y4_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[15]_qfbk = KB1_period_h_register[15];
KB1L215 = KB1L214 & KB1_period_h_register[15]_qfbk # !KB1L214 & (!KB1_period_l_register[15]);
--KB1_period_h_register[15] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[15] at LC_X50_Y4_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[15] = DFFEAS(KB1L215, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, L1_M_st_data[15], , , VCC);
--R1_counter_snapshot[15] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[15] at LC_X46_Y7_N0
--operation mode is normal
R1_counter_snapshot[15]_lut_out = !R1_internal_counter[15];
R1_counter_snapshot[15] = DFFEAS(R1_counter_snapshot[15]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, , , , );
--R1L213 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[15]~1259 at LC_X46_Y7_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[31]_qfbk = R1_counter_snapshot[31];
R1L213 = L1_M_alu_result[4] & (L1_M_alu_result[2] & R1_counter_snapshot[31]_qfbk # !L1_M_alu_result[2] & (R1_counter_snapshot[15])) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--R1_counter_snapshot[31] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[31] at LC_X46_Y7_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[31] = DFFEAS(R1L213, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[31], , , VCC);
--R1_period_l_register[15] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[15] at LC_X48_Y5_N3
--operation mode is normal
R1_period_l_register[15]_lut_out = !L1_M_st_data[15];
R1_period_l_register[15] = DFFEAS(R1_period_l_register[15]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, , , , );
--R1L214 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[15]~1260 at LC_X46_Y8_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[15]_qfbk = R1_period_h_register[15];
R1L214 = R1L213 & R1_period_h_register[15]_qfbk # !R1L213 & (!R1_period_l_register[15]);
--R1_period_h_register[15] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[15] at LC_X46_Y8_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[15] = DFFEAS(R1L214, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[15], , , VCC);
--M1L309 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|process4~0 at LC_X41_Y16_N1
--operation mode is normal
M1L309 = !M1_internal_cpu_data_master_dbs_address[1] & (M1_internal_cpu_data_master_dbs_address[0] & M1L307);
--P1L32 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[1]~6 at LC_X34_Y12_N6
--operation mode is normal
P1L32 = L1_M_mem_byte_en[1] # !P1L3;
--CD1_internal_MonDReg[8] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[8] at LC_X35_Y25_N0
--operation mode is normal
CD1_internal_MonDReg[8] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[8], CD1L39, DD1_internal_jdo1[11], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[9] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[9] at LC_X36_Y26_N8
--operation mode is normal
CD1_internal_MonDReg[9] = AMPP_FUNCTION(DE1__clk0, CD1_MonAReg[10], PD1_q_b[9], DD1_internal_jdo1[12], CD1L28, !C1_CLR_SIGNAL, CD1L39, CD1L38);
--CD1_internal_MonDReg[10] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[10] at LC_X35_Y25_N3
--operation mode is normal
CD1_internal_MonDReg[10] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[10], CD1L39, DD1_internal_jdo1[13], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[11] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[11] at LC_X36_Y26_N4
--operation mode is normal
CD1_internal_MonDReg[11] = AMPP_FUNCTION(DE1__clk0, CD1L28, PD1_q_b[11], DD1_internal_jdo1[14], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L39, CD1L38);
--CD1_internal_MonDReg[12] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[12] at LC_X36_Y26_N5
--operation mode is normal
CD1_internal_MonDReg[12] = AMPP_FUNCTION(DE1__clk0, CD1L28, PD1_q_b[12], DD1_internal_jdo1[15], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L39, CD1L38);
--CD1_internal_MonDReg[13] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[13] at LC_X35_Y25_N7
--operation mode is normal
CD1_internal_MonDReg[13] = AMPP_FUNCTION(DE1__clk0, CD1_MonAReg[10], CD1L39, PD1_q_b[13], DD1_internal_jdo1[16], !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[14] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[14] at LC_X35_Y25_N2
--operation mode is normal
CD1_internal_MonDReg[14] = AMPP_FUNCTION(DE1__clk0, CD1_MonAReg[10], CD1L39, DD1_internal_jdo1[17], PD1_q_b[14], !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[15] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[15] at LC_X35_Y25_N4
--operation mode is normal
CD1_internal_MonDReg[15] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[15], CD1L39, DD1_internal_jdo1[18], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L38);
--AB1L37 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|onchip_ram_64_kbytes_s1_byteenable[3]~7 at LC_X34_Y12_N2
--operation mode is normal
AB1L37 = L1_M_mem_byte_en[3] # AB1L11 & !AB1_onchip_ram_64_kbytes_s1_arb_addend[1] # !AB1L3;
--M1L297 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[31]~2098 at LC_X44_Y18_N8
--operation mode is normal
M1L297 = L1_M_alu_result[25] # FB1_za_data[31] # !L1_M_alu_result[24] # !QB1L4;
--P1L34 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_byteenable[3]~7 at LC_X34_Y12_N3
--operation mode is normal
P1L34 = L1_M_mem_byte_en[3] # !P1L3;
--CD1_internal_MonDReg[24] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[24] at LC_X36_Y25_N8
--operation mode is normal
CD1_internal_MonDReg[24] = AMPP_FUNCTION(DE1__clk0, CD1L30, PD1_q_b[24], DD1_internal_jdo1[27], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L39, CD1L38);
--CD1_internal_MonDReg[25] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[25] at LC_X35_Y25_N8
--operation mode is normal
CD1_internal_MonDReg[25] = AMPP_FUNCTION(DE1__clk0, CD1_MonAReg[10], DD1_internal_jdo1[28], PD1_q_b[25], CD1L39, !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[26] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[26] at LC_X35_Y25_N6
--operation mode is normal
CD1_internal_MonDReg[26] = AMPP_FUNCTION(DE1__clk0, CD1_MonAReg[10], DD1_internal_jdo1[29], PD1_q_b[26], CD1L39, !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[27] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[27] at LC_X36_Y26_N1
--operation mode is normal
CD1_internal_MonDReg[27] = AMPP_FUNCTION(DE1__clk0, CD1_MonAReg[10], PD1_q_b[27], DD1_internal_jdo1[30], CD1L29, !C1_CLR_SIGNAL, CD1L39, CD1L38);
--CD1_internal_MonDReg[28] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[28] at LC_X35_Y25_N5
--operation mode is normal
CD1_internal_MonDReg[28] = AMPP_FUNCTION(DE1__clk0, CD1_MonAReg[10], CD1L39, PD1_q_b[28], DD1_internal_jdo1[31], !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[29] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[29] at LC_X36_Y26_N3
--operation mode is normal
CD1_internal_MonDReg[29] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[29], CD1L29, DD1_internal_jdo1[32], CD1_MonAReg[10], !C1_CLR_SIGNAL, CD1L39, CD1L38);
--CD1_internal_MonDReg[30] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[30] at LC_X34_Y26_N8
--operation mode is normal
CD1_internal_MonDReg[30] = AMPP_FUNCTION(DE1__clk0, PD1_q_b[30], CD1L39, CD1_MonAReg[10], DD1_internal_jdo1[33], !C1_CLR_SIGNAL, CD1L38);
--CD1_internal_MonDReg[31] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[31] at LC_X34_Y26_N6
--operation mode is normal
CD1_internal_MonDReg[31] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[34], PD1_q_b[31], CD1_MonAReg[10], CD1L39, !C1_CLR_SIGNAL, CD1L38);
--M1L287 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[21]~2100 at LC_X46_Y19_N6
--operation mode is normal
M1L287 = FB1_za_data[21] # L1_M_alu_result[25] # !QB1L4 # !L1_M_alu_result[24];
--ZD2_safe_q[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[5] at LC_X50_Y15_N6
--operation mode is normal
ZD2_safe_q[5]_carry_eqn = (!ZD2L11 & ZD2L15) # (ZD2L11 & ZD2L16);
ZD2_safe_q[5]_lut_out = ZD2_safe_q[5]_carry_eqn $ ZD2_safe_q[5];
ZD2_safe_q[5] = DFFEAS(ZD2_safe_q[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , WD2L1, , , , );
--T1L41 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~308 at LC_X51_Y17_N5
--operation mode is arithmetic
T1L41_carry_eqn = (!T1L33 & GND) # (T1L33 & VCC);
T1L41 = ZD1_safe_q[5] $ !T1L41_carry_eqn;
--T1L42 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~309 at LC_X51_Y17_N5
--operation mode is arithmetic
T1L42_cout_0 = ZD1_safe_q[5] # !T1L33;
T1L42 = CARRY(T1L42_cout_0);
--T1L43 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~309COUT1_357 at LC_X51_Y17_N5
--operation mode is arithmetic
T1L43_cout_1 = ZD1_safe_q[5] # !T1L33;
T1L43 = CARRY(T1L43_cout_1);
--T1L44 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~310 at LC_X51_Y17_N8
--operation mode is normal
T1L44 = T1_read_0 & ZD2_safe_q[5] # !T1_read_0 & (T1L41);
--L1_i_readdata_d1[22] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[22] at LC_X46_Y17_N5
--operation mode is normal
L1_i_readdata_d1[22] = AMPP_FUNCTION(DE1__clk0, FC1L26, N1L75, P1L10, FC1L21, E1_data_out);
--L1_i_readdata_d1[23] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[23] at LC_X45_Y19_N8
--operation mode is normal
L1_i_readdata_d1[23] = AMPP_FUNCTION(DE1__clk0, P1L10, FC1L27, N1L78, FC1L21, E1_data_out);
--L1_i_readdata_d1[24] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[24] at LC_X44_Y15_N3
--operation mode is normal
L1_i_readdata_d1[24] = AMPP_FUNCTION(DE1__clk0, FC1L21, P1L10, FC1L28, N1L81, E1_data_out);
--L1_i_readdata_d1[25] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[25] at LC_X44_Y17_N8
--operation mode is normal
L1_i_readdata_d1[25] = AMPP_FUNCTION(DE1__clk0, FC1L21, P1L10, FC1L29, N1L84, E1_data_out);
--L1_i_readdata_d1[26] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[26] at LC_X41_Y20_N6
--operation mode is normal
L1_i_readdata_d1[26] = AMPP_FUNCTION(DE1__clk0, P1L10, N1L87, FC1L30, FC1L21, E1_data_out);
--M1L290 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[24]~2102 at LC_X44_Y18_N0
--operation mode is normal
M1L290 = L1_M_alu_result[25] # FB1_za_data[24] # !L1_M_alu_result[24] # !QB1L4;
--ZD2_safe_q[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|safe_q[1] at LC_X50_Y15_N2
--operation mode is arithmetic
ZD2_safe_q[1]_lut_out = ZD2_safe_q[1] $ (ZD2L2);
ZD2_safe_q[1] = DFFEAS(ZD2_safe_q[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , WD2L1, , , , );
--ZD2L5 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella1~COUT at LC_X50_Y15_N2
--operation mode is arithmetic
ZD2L5_cout_0 = ZD2_safe_q[1] $ T1_wr_rfifo # !ZD2L2;
ZD2L5 = CARRY(ZD2L5_cout_0);
--ZD2L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw|counter_cella1~COUTCOUT1_15 at LC_X50_Y15_N2
--operation mode is arithmetic
ZD2L6_cout_1 = ZD2_safe_q[1] $ T1_wr_rfifo # !ZD2L3;
ZD2L6 = CARRY(ZD2L6_cout_1);
--T1L45 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~311 at LC_X51_Y17_N1
--operation mode is arithmetic
T1L45 = ZD1_safe_q[1] $ !T1L51;
--T1L46 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~312 at LC_X51_Y17_N1
--operation mode is arithmetic
T1L46_cout_0 = ZD1_safe_q[1] # !T1L51;
T1L46 = CARRY(T1L46_cout_0);
--T1L47 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~312COUT1_351 at LC_X51_Y17_N1
--operation mode is arithmetic
T1L47_cout_1 = ZD1_safe_q[1] # !T1L52;
T1L47 = CARRY(T1L47_cout_1);
--T1L48 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~313 at LC_X50_Y15_N7
--operation mode is normal
T1L48 = T1_read_0 & (ZD2_safe_q[1]) # !T1_read_0 & T1L45;
--T1L49 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~314 at LC_X48_Y13_N3
--operation mode is normal
T1L49 = T1_read_0 & ZD2_safe_q[0] # !T1_read_0 & (ZD1_safe_q[0]);
--M1L291 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[25]~2106 at LC_X44_Y16_N5
--operation mode is normal
M1L291 = L1_M_alu_result[25] # FB1_za_data[25] # !QB1L4 # !L1_M_alu_result[24];
--L1_i_readdata_d1[20] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[20] at LC_X45_Y18_N5
--operation mode is normal
L1_i_readdata_d1[20] = AMPP_FUNCTION(DE1__clk0, FC1L24, FC1L21, P1L10, N1L69, E1_data_out);
--T1_woverflow is std_1s10:inst|jtag_uart:the_jtag_uart|woverflow at LC_X50_Y14_N4
--operation mode is normal
T1_woverflow_lut_out = T1L70 & (L1_M_alu_result[2] & T1_woverflow # !L1_M_alu_result[2] & (WD1_b_full)) # !T1L70 & T1_woverflow;
T1_woverflow = DFFEAS(T1_woverflow_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L282 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[14]~2108 at LC_X50_Y14_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[14]_qfbk = H1_slave_readdata[14];
M1L282 = FB1_za_data[14] & J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[14]_qfbk # !FB1_za_data[14] & (GB1L24 # J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[14]_qfbk);
--H1_slave_readdata[14] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[14] at LC_X50_Y14_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[14] = DFFEAS(M1L282, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[14], , , VCC);
--KB1_counter_snapshot[30] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[30] at LC_X50_Y3_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[30]_lut_out = GND;
KB1_counter_snapshot[30] = DFFEAS(KB1_counter_snapshot[30]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[30], , , VCC);
--KB1L212 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[14]~1251 at LC_X50_Y3_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[14]_qfbk = KB1_counter_snapshot[14];
KB1L212 = L1_M_alu_result[2] & (KB1_counter_snapshot[30] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & (KB1_counter_snapshot[14]_qfbk & L1_M_alu_result[4]);
--KB1_counter_snapshot[14] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[14] at LC_X50_Y3_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[14] = DFFEAS(KB1L212, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[14], , , VCC);
--KB1_period_l_register[14] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[14] at LC_X50_Y4_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_l_register[14]_lut_out = GND;
KB1_period_l_register[14] = DFFEAS(KB1_period_l_register[14]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, L1_M_st_data[14], , , VCC);
--KB1L213 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[14]~1252 at LC_X50_Y4_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[14]_qfbk = KB1_period_h_register[14];
KB1L213 = KB1L212 & KB1_period_h_register[14]_qfbk # !KB1L212 & (KB1_period_l_register[14]);
--KB1_period_h_register[14] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[14] at LC_X50_Y4_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[14] = DFFEAS(KB1L213, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, L1_M_st_data[14], , , VCC);
--R1_counter_snapshot[14] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[14] at LC_X47_Y4_N1
--operation mode is normal
R1_counter_snapshot[14]_lut_out = !R1_internal_counter[14];
R1_counter_snapshot[14] = DFFEAS(R1_counter_snapshot[14]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, , , , );
--R1L211 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[14]~1262 at LC_X46_Y7_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[30]_qfbk = R1_counter_snapshot[30];
R1L211 = L1_M_alu_result[4] & (L1_M_alu_result[2] & R1_counter_snapshot[30]_qfbk # !L1_M_alu_result[2] & (R1_counter_snapshot[14])) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--R1_counter_snapshot[30] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[30] at LC_X46_Y7_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[30] = DFFEAS(R1L211, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[30], , , VCC);
--R1_period_l_register[14] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[14] at LC_X48_Y8_N5
--operation mode is normal
R1_period_l_register[14]_lut_out = !L1_M_st_data[14];
R1_period_l_register[14] = DFFEAS(R1_period_l_register[14]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, , , , );
--R1L212 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[14]~1263 at LC_X47_Y10_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[14]_qfbk = R1_period_h_register[14];
R1L212 = R1L211 & (R1_period_h_register[14]_qfbk) # !R1L211 & !R1_period_l_register[14];
--R1_period_h_register[14] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[14] at LC_X47_Y10_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[14] = DFFEAS(R1L212, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[14], , , VCC);
--M1L296 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[30]~2110 at LC_X47_Y13_N8
--operation mode is normal
M1L296 = L1_M_alu_result[25] # FB1_za_data[30] # !L1_M_alu_result[24] # !QB1L4;
--L1_i_readdata_d1[19] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[19] at LC_X46_Y20_N0
--operation mode is normal
L1_i_readdata_d1[19] = AMPP_FUNCTION(DE1__clk0, P1L10, FC1L23, N1L66, FC1L21, E1_data_out);
--M1L281 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[13]~2112 at LC_X48_Y17_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[13]_qfbk = H1_slave_readdata[13];
M1L281 = FB1_za_data[13] & J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[13]_qfbk # !FB1_za_data[13] & (GB1L24 # J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[13]_qfbk);
--H1_slave_readdata[13] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[13] at LC_X48_Y17_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[13] = DFFEAS(M1L281, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[13], , , VCC);
--KB1_counter_snapshot[13] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[13] at LC_X50_Y3_N5
--operation mode is normal
KB1_counter_snapshot[13]_lut_out = !KB1_internal_counter[13];
KB1_counter_snapshot[13] = DFFEAS(KB1_counter_snapshot[13]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--KB1L210 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[13]~1254 at LC_X50_Y3_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[29]_qfbk = KB1_counter_snapshot[29];
KB1L210 = L1_M_alu_result[2] & (KB1_counter_snapshot[29]_qfbk # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & KB1_counter_snapshot[13] & (L1_M_alu_result[4]);
--KB1_counter_snapshot[29] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[29] at LC_X50_Y3_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[29] = DFFEAS(KB1L210, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[29], , , VCC);
--KB1_period_l_register[13] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[13] at LC_X50_Y4_N9
--operation mode is normal
KB1_period_l_register[13]_lut_out = !L1_M_st_data[13];
KB1_period_l_register[13] = DFFEAS(KB1_period_l_register[13]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, , , , );
--KB1L211 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[13]~1255 at LC_X50_Y4_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[13]_qfbk = KB1_period_h_register[13];
KB1L211 = KB1L210 & KB1_period_h_register[13]_qfbk # !KB1L210 & (!KB1_period_l_register[13]);
--KB1_period_h_register[13] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[13] at LC_X50_Y4_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[13] = DFFEAS(KB1L211, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, L1_M_st_data[13], , , VCC);
--R1_counter_snapshot[29] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[29] at LC_X46_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[29]_lut_out = GND;
R1_counter_snapshot[29] = DFFEAS(R1_counter_snapshot[29]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[29], , , VCC);
--R1L209 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[13]~1265 at LC_X46_Y6_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[13]_qfbk = R1_counter_snapshot[13];
R1L209 = L1_M_alu_result[4] & (L1_M_alu_result[2] & (R1_counter_snapshot[29]) # !L1_M_alu_result[2] & R1_counter_snapshot[13]_qfbk) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--R1_counter_snapshot[13] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[13] at LC_X46_Y6_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[13] = DFFEAS(R1L209, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[13], , , VCC);
--R1_period_l_register[13] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[13] at LC_X48_Y8_N4
--operation mode is normal
R1_period_l_register[13]_lut_out = L1_M_st_data[13];
R1_period_l_register[13] = DFFEAS(R1_period_l_register[13]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, , , , );
--R1L210 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[13]~1266 at LC_X46_Y5_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[13]_qfbk = R1_period_h_register[13];
R1L210 = R1L209 & R1_period_h_register[13]_qfbk # !R1L209 & (R1_period_l_register[13]);
--R1_period_h_register[13] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[13] at LC_X46_Y5_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[13] = DFFEAS(R1L210, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[13], , , VCC);
--M1L295 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[29]~2114 at LC_X44_Y13_N4
--operation mode is normal
M1L295 = L1_M_alu_result[25] # FB1_za_data[29] # !QB1L4 # !L1_M_alu_result[24];
--L1_D_br_taken_waddr_partial[10] is std_1s10:inst|cpu:the_cpu|D_br_taken_waddr_partial[10] at LC_X35_Y19_N5
--operation mode is normal
L1_D_br_taken_waddr_partial[10] = AMPP_FUNCTION(DE1__clk0, E1_data_out, L1_W_stall, L1L201);
--L1_i_readdata_d1[18] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[18] at LC_X45_Y16_N0
--operation mode is normal
L1_i_readdata_d1[18] = AMPP_FUNCTION(DE1__clk0, N1L63, P1L10, FC1L22, FC1L21, E1_data_out);
--M1L280 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[12]~2116 at LC_X50_Y19_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[12]_qfbk = H1_slave_readdata[12];
M1L280 = FB1_za_data[12] & J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[12]_qfbk # !FB1_za_data[12] & (GB1L24 # J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[12]_qfbk);
--H1_slave_readdata[12] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[12] at LC_X50_Y19_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[12] = DFFEAS(M1L280, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[12], , , VCC);
--R1_counter_snapshot[28] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[28] at LC_X46_Y6_N0
--operation mode is normal
R1_counter_snapshot[28]_lut_out = R1_internal_counter[28];
R1_counter_snapshot[28] = DFFEAS(R1_counter_snapshot[28]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, , , , );
--R1L207 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[12]~1268 at LC_X46_Y6_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[12]_qfbk = R1_counter_snapshot[12];
R1L207 = L1_M_alu_result[4] & (L1_M_alu_result[2] & (R1_counter_snapshot[28]) # !L1_M_alu_result[2] & R1_counter_snapshot[12]_qfbk) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--R1_counter_snapshot[12] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[12] at LC_X46_Y6_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[12] = DFFEAS(R1L207, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[12], , , VCC);
--R1_period_l_register[12] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[12] at LC_X48_Y8_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_l_register[12]_lut_out = GND;
R1_period_l_register[12] = DFFEAS(R1_period_l_register[12]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, L1_M_st_data[12], , , VCC);
--R1L208 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[12]~1269 at LC_X46_Y5_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[12]_qfbk = R1_period_h_register[12];
R1L208 = R1L207 & R1_period_h_register[12]_qfbk # !R1L207 & (R1_period_l_register[12]);
--R1_period_h_register[12] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[12] at LC_X46_Y5_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[12] = DFFEAS(R1L208, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[12], , , VCC);
--KB1_counter_snapshot[28] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[28] at LC_X50_Y2_N1
--operation mode is normal
KB1_counter_snapshot[28]_lut_out = KB1_internal_counter[28];
KB1_counter_snapshot[28] = DFFEAS(KB1_counter_snapshot[28]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--KB1L208 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[12]~1257 at LC_X50_Y3_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[12]_qfbk = KB1_counter_snapshot[12];
KB1L208 = L1_M_alu_result[2] & (KB1_counter_snapshot[28] # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & KB1_counter_snapshot[12]_qfbk;
--KB1_counter_snapshot[12] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[12] at LC_X50_Y3_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[12] = DFFEAS(KB1L208, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[12], , , VCC);
--KB1_period_l_register[12] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[12] at LC_X52_Y5_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_l_register[12]_lut_out = GND;
KB1_period_l_register[12] = DFFEAS(KB1_period_l_register[12]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, L1_M_st_data[12], , , VCC);
--KB1L209 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[12]~1258 at LC_X50_Y4_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[12]_qfbk = KB1_period_h_register[12];
KB1L209 = KB1L208 & (KB1_period_h_register[12]_qfbk) # !KB1L208 & KB1_period_l_register[12];
--KB1_period_h_register[12] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[12] at LC_X50_Y4_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[12] = DFFEAS(KB1L209, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, L1_M_st_data[12], , , VCC);
--M1L294 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[28]~2118 at LC_X44_Y18_N9
--operation mode is normal
M1L294 = FB1_za_data[28] # L1_M_alu_result[25] # !L1_M_alu_result[24] # !QB1L4;
--L1_i_readdata_d1[17] is std_1s10:inst|cpu:the_cpu|i_readdata_d1[17] at LC_X46_Y16_N3
--operation mode is normal
L1_i_readdata_d1[17] = AMPP_FUNCTION(DE1__clk0, P1L10, N1L60, FC1L20, FC1L21, E1_data_out);
--M1L279 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[11]~2120 at LC_X48_Y16_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[11]_qfbk = H1_slave_readdata[11];
M1L279 = H1_slave_readdata[11]_qfbk # !J1_cpu_data_master_requests_clock_0_in;
--H1_slave_readdata[11] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[11] at LC_X48_Y16_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[11] = DFFEAS(M1L279, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[11], , , VCC);
--KB1_counter_snapshot[27] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[27] at LC_X51_Y6_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[27]_lut_out = GND;
KB1_counter_snapshot[27] = DFFEAS(KB1_counter_snapshot[27]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[27], , , VCC);
--KB1L206 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[11]~1260 at LC_X51_Y6_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[11]_qfbk = KB1_counter_snapshot[11];
KB1L206 = L1_M_alu_result[4] & (L1_M_alu_result[2] & (KB1_counter_snapshot[27]) # !L1_M_alu_result[2] & KB1_counter_snapshot[11]_qfbk) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--KB1_counter_snapshot[11] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[11] at LC_X51_Y6_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[11] = DFFEAS(KB1L206, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[11], , , VCC);
--KB1_period_l_register[11] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[11] at LC_X48_Y5_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_l_register[11]_lut_out = GND;
KB1_period_l_register[11] = DFFEAS(KB1_period_l_register[11]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, L1_M_st_data[11], , , VCC);
--KB1L207 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[11]~1261 at LC_X51_Y5_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[11]_qfbk = KB1_period_h_register[11];
KB1L207 = KB1L206 & KB1_period_h_register[11]_qfbk # !KB1L206 & (KB1_period_l_register[11]);
--KB1_period_h_register[11] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[11] at LC_X51_Y5_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[11] = DFFEAS(KB1L207, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, L1_M_st_data[11], , , VCC);
--R1_counter_snapshot[27] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[27] at LC_X46_Y6_N9
--operation mode is normal
R1_counter_snapshot[27]_lut_out = R1_internal_counter[27];
R1_counter_snapshot[27] = DFFEAS(R1_counter_snapshot[27]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, , , , );
--R1L205 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[11]~1271 at LC_X46_Y6_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[11]_qfbk = R1_counter_snapshot[11];
R1L205 = L1_M_alu_result[4] & (L1_M_alu_result[2] & (R1_counter_snapshot[27]) # !L1_M_alu_result[2] & R1_counter_snapshot[11]_qfbk) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--R1_counter_snapshot[11] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[11] at LC_X46_Y6_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[11] = DFFEAS(R1L205, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[11], , , VCC);
--R1_period_l_register[11] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[11] at LC_X48_Y5_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_l_register[11]_lut_out = GND;
R1_period_l_register[11] = DFFEAS(R1_period_l_register[11]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, L1_M_st_data[11], , , VCC);
--R1L206 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[11]~1272 at LC_X46_Y5_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[11]_qfbk = R1_period_h_register[11];
R1L206 = R1L205 & R1_period_h_register[11]_qfbk # !R1L205 & (R1_period_l_register[11]);
--R1_period_h_register[11] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[11] at LC_X46_Y5_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[11] = DFFEAS(R1L206, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[11], , , VCC);
--M1L293 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[27]~2122 at LC_X46_Y14_N1
--operation mode is normal
M1L293 = FB1_za_data[27] # L1_M_alu_result[25] # !QB1L4 # !L1_M_alu_result[24];
--T1_ac is std_1s10:inst|jtag_uart:the_jtag_uart|ac at LC_X48_Y16_N4
--operation mode is normal
T1_ac_lut_out = T1L2 # T1_ac & (!T1L61 # !L1_M_st_data[10]);
T1_ac = DFFEAS(T1_ac_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L278 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[10]~2124 at LC_X48_Y16_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[10]_qfbk = H1_slave_readdata[10];
M1L278 = FB1_za_data[10] & J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[10]_qfbk # !FB1_za_data[10] & (GB1L24 # J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[10]_qfbk);
--H1_slave_readdata[10] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[10] at LC_X48_Y16_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[10] = DFFEAS(M1L278, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[10], , , VCC);
--R1_counter_snapshot[26] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[26] at LC_X47_Y4_N6
--operation mode is normal
R1_counter_snapshot[26]_lut_out = R1_internal_counter[26];
R1_counter_snapshot[26] = DFFEAS(R1_counter_snapshot[26]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, , , , );
--R1L203 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[10]~1274 at LC_X47_Y4_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[10]_qfbk = R1_counter_snapshot[10];
R1L203 = L1_M_alu_result[4] & (L1_M_alu_result[2] & (R1_counter_snapshot[26]) # !L1_M_alu_result[2] & R1_counter_snapshot[10]_qfbk) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--R1_counter_snapshot[10] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[10] at LC_X47_Y4_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[10] = DFFEAS(R1L203, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[10], , , VCC);
--R1_period_l_register[10] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[10] at LC_X48_Y8_N7
--operation mode is normal
R1_period_l_register[10]_lut_out = L1_M_st_data[10];
R1_period_l_register[10] = DFFEAS(R1_period_l_register[10]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, , , , );
--R1L204 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[10]~1275 at LC_X46_Y9_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[10]_qfbk = R1_period_h_register[10];
R1L204 = R1L203 & R1_period_h_register[10]_qfbk # !R1L203 & (R1_period_l_register[10]);
--R1_period_h_register[10] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[10] at LC_X46_Y9_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[10] = DFFEAS(R1L204, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[10], , , VCC);
--KB1_counter_snapshot[26] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[26] at LC_X51_Y6_N9
--operation mode is normal
KB1_counter_snapshot[26]_lut_out = KB1_internal_counter[26];
KB1_counter_snapshot[26] = DFFEAS(KB1_counter_snapshot[26]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--KB1L204 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[10]~1263 at LC_X51_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[10]_qfbk = KB1_counter_snapshot[10];
KB1L204 = L1_M_alu_result[4] & (L1_M_alu_result[2] & (KB1_counter_snapshot[26]) # !L1_M_alu_result[2] & KB1_counter_snapshot[10]_qfbk) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--KB1_counter_snapshot[10] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[10] at LC_X51_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[10] = DFFEAS(KB1L204, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[10], , , VCC);
--KB1_period_l_register[10] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[10] at LC_X52_Y5_N6
--operation mode is normal
KB1_period_l_register[10]_lut_out = L1_M_st_data[10];
KB1_period_l_register[10] = DFFEAS(KB1_period_l_register[10]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, , , , );
--KB1L205 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[10]~1264 at LC_X52_Y5_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[10]_qfbk = KB1_period_h_register[10];
KB1L205 = KB1L204 & KB1_period_h_register[10]_qfbk # !KB1L204 & (KB1_period_l_register[10]);
--KB1_period_h_register[10] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[10] at LC_X52_Y5_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[10] = DFFEAS(KB1L205, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, L1_M_st_data[10], , , VCC);
--M1L292 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[26]~2126 at LC_X47_Y15_N1
--operation mode is normal
M1L292 = L1_M_alu_result[25] # FB1_za_data[26] # !L1_M_alu_result[24] # !QB1L4;
--M1L277 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[9]~2128 at LC_X47_Y20_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[9]_qfbk = H1_slave_readdata[9];
M1L277 = GB1L24 & (J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[9]_qfbk # !FB1_za_data[9]) # !GB1L24 & J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[9]_qfbk;
--H1_slave_readdata[9] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[9] at LC_X47_Y20_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[9] = DFFEAS(M1L277, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[9], , , VCC);
--R1_counter_snapshot[9] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[9] at LC_X48_Y4_N8
--operation mode is normal
R1_counter_snapshot[9]_lut_out = !R1_internal_counter[9];
R1_counter_snapshot[9] = DFFEAS(R1_counter_snapshot[9]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, , , , );
--R1L201 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[9]~1277 at LC_X48_Y4_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[25]_qfbk = R1_counter_snapshot[25];
R1L201 = L1_M_alu_result[2] & (R1_counter_snapshot[25]_qfbk # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & (R1_counter_snapshot[9]);
--R1_counter_snapshot[25] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[25] at LC_X48_Y4_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[25] = DFFEAS(R1L201, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[25], , , VCC);
--R1_period_l_register[9] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[9] at LC_X48_Y8_N1
--operation mode is normal
R1_period_l_register[9]_lut_out = !L1_M_st_data[9];
R1_period_l_register[9] = DFFEAS(R1_period_l_register[9]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, , , , );
--R1L202 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[9]~1278 at LC_X48_Y8_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[9]_qfbk = R1_period_h_register[9];
R1L202 = R1L201 & (R1_period_h_register[9]_qfbk) # !R1L201 & !R1_period_l_register[9];
--R1_period_h_register[9] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[9] at LC_X48_Y8_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[9] = DFFEAS(R1L202, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[9], , , VCC);
--KB1_counter_snapshot[25] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[25] at LC_X51_Y6_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[25]_lut_out = GND;
KB1_counter_snapshot[25] = DFFEAS(KB1_counter_snapshot[25]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[25], , , VCC);
--KB1L202 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[9]~1266 at LC_X51_Y6_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[9]_qfbk = KB1_counter_snapshot[9];
KB1L202 = L1_M_alu_result[4] & (L1_M_alu_result[2] & (KB1_counter_snapshot[25]) # !L1_M_alu_result[2] & KB1_counter_snapshot[9]_qfbk) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--KB1_counter_snapshot[9] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[9] at LC_X51_Y6_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[9] = DFFEAS(KB1L202, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[9], , , VCC);
--KB1_period_l_register[9] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[9] at LC_X52_Y5_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_l_register[9]_lut_out = GND;
KB1_period_l_register[9] = DFFEAS(KB1_period_l_register[9]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, L1_M_st_data[9], , , VCC);
--KB1L203 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[9]~1267 at LC_X52_Y5_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[9]_qfbk = KB1_period_h_register[9];
KB1L203 = KB1L202 & KB1_period_h_register[9]_qfbk # !KB1L202 & (KB1_period_l_register[9]);
--KB1_period_h_register[9] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[9] at LC_X52_Y5_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[9] = DFFEAS(KB1L203, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, L1_M_st_data[9], , , VCC);
--M1L276 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[8]~2130 at LC_X47_Y20_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[8]_qfbk = H1_slave_readdata[8];
M1L276 = GB1L24 & (J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[8]_qfbk # !FB1_za_data[8]) # !GB1L24 & J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[8]_qfbk;
--H1_slave_readdata[8] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[8] at LC_X47_Y20_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[8] = DFFEAS(M1L276, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[8], , , VCC);
--R1_counter_snapshot[8] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[8] at LC_X48_Y4_N4
--operation mode is normal
R1_counter_snapshot[8]_lut_out = !R1_internal_counter[8];
R1_counter_snapshot[8] = DFFEAS(R1_counter_snapshot[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, , , , );
--R1L199 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[8]~1280 at LC_X48_Y4_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[24]_qfbk = R1_counter_snapshot[24];
R1L199 = L1_M_alu_result[2] & (R1_counter_snapshot[24]_qfbk # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & L1_M_alu_result[4] & (R1_counter_snapshot[8]);
--R1_counter_snapshot[24] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[24] at LC_X48_Y4_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[24] = DFFEAS(R1L199, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[24], , , VCC);
--R1_period_l_register[8] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[8] at LC_X48_Y8_N9
--operation mode is normal
R1_period_l_register[8]_lut_out = !L1_M_st_data[8];
R1_period_l_register[8] = DFFEAS(R1_period_l_register[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, , , , );
--R1L200 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[8]~1281 at LC_X48_Y8_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[8]_qfbk = R1_period_h_register[8];
R1L200 = R1L199 & R1_period_h_register[8]_qfbk # !R1L199 & (!R1_period_l_register[8]);
--R1_period_h_register[8] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[8] at LC_X48_Y8_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[8] = DFFEAS(R1L200, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[8], , , VCC);
--KB1_counter_snapshot[8] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[8] at LC_X50_Y3_N0
--operation mode is normal
KB1_counter_snapshot[8]_lut_out = !KB1_internal_counter[8];
KB1_counter_snapshot[8] = DFFEAS(KB1_counter_snapshot[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--KB1L200 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[8]~1269 at LC_X50_Y3_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[24]_qfbk = KB1_counter_snapshot[24];
KB1L200 = L1_M_alu_result[2] & (KB1_counter_snapshot[24]_qfbk # !L1_M_alu_result[4]) # !L1_M_alu_result[2] & KB1_counter_snapshot[8] & (L1_M_alu_result[4]);
--KB1_counter_snapshot[24] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[24] at LC_X50_Y3_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[24] = DFFEAS(KB1L200, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[24], , , VCC);
--KB1_period_l_register[8] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[8] at LC_X52_Y5_N8
--operation mode is normal
KB1_period_l_register[8]_lut_out = !L1_M_st_data[8];
KB1_period_l_register[8] = DFFEAS(KB1_period_l_register[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, , , , );
--KB1L201 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[8]~1270 at LC_X48_Y11_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[8]_qfbk = KB1_period_h_register[8];
KB1L201 = KB1L200 & (KB1_period_h_register[8]_qfbk) # !KB1L200 & (!KB1_period_l_register[8]);
--KB1_period_h_register[8] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[8] at LC_X48_Y11_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[8] = DFFEAS(KB1L201, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, L1_M_st_data[8], , , VCC);
--F1_d2_data_in[3] is std_1s10:inst|button_pio:the_button_pio|d2_data_in[3] at LC_X51_Y12_N2
--operation mode is normal
F1_d2_data_in[3]_lut_out = F1_d1_data_in[3];
F1_d2_data_in[3] = DFFEAS(F1_d2_data_in[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--F1_d1_data_in[3] is std_1s10:inst|button_pio:the_button_pio|d1_data_in[3] at LC_X51_Y12_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
F1_d1_data_in[3]_lut_out = GND;
F1_d1_data_in[3] = DFFEAS(F1_d1_data_in[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , in_port_to_the_button_pio[3], , , VCC);
--F1L16 is std_1s10:inst|button_pio:the_button_pio|edge_capture_wr_strobe~27 at LC_X41_Y15_N0
--operation mode is normal
F1L16 = !M1_internal_cpu_data_master_waitrequest & L1_internal_d_write & L1_M_alu_result[3];
--F1L17 is std_1s10:inst|button_pio:the_button_pio|edge_capture_wr_strobe~28 at LC_X50_Y12_N5
--operation mode is normal
F1L17 = !L1_M_alu_result[7] & L1_M_alu_result[2] & F1L16 & G1L1;
--F1_d2_data_in[1] is std_1s10:inst|button_pio:the_button_pio|d2_data_in[1] at LC_X50_Y13_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
F1_d2_data_in[1]_lut_out = GND;
F1_d2_data_in[1] = DFFEAS(F1_d2_data_in[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , F1_d1_data_in[1], , , VCC);
--F1_d1_data_in[1] is std_1s10:inst|button_pio:the_button_pio|d1_data_in[1] at LC_X50_Y13_N3
--operation mode is normal
F1_d1_data_in[1]_lut_out = in_port_to_the_button_pio[1];
F1_d1_data_in[1] = DFFEAS(F1_d1_data_in[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--F1L23 is std_1s10:inst|button_pio:the_button_pio|process1~12 at LC_X50_Y12_N4
--operation mode is normal
F1L23 = !L1_M_alu_result[7] & !L1_M_alu_result[2] & F1L16 & G1L1;
--F1_d2_data_in[2] is std_1s10:inst|button_pio:the_button_pio|d2_data_in[2] at LC_X50_Y13_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
F1_d2_data_in[2]_lut_out = GND;
F1_d2_data_in[2] = DFFEAS(F1_d2_data_in[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , F1_d1_data_in[2], , , VCC);
--F1_d1_data_in[2] is std_1s10:inst|button_pio:the_button_pio|d1_data_in[2] at LC_X50_Y13_N1
--operation mode is normal
F1_d1_data_in[2]_lut_out = in_port_to_the_button_pio[2];
F1_d1_data_in[2] = DFFEAS(F1_d1_data_in[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--F1_d2_data_in[0] is std_1s10:inst|button_pio:the_button_pio|d2_data_in[0] at LC_X50_Y10_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
F1_d2_data_in[0]_lut_out = GND;
F1_d2_data_in[0] = DFFEAS(F1_d2_data_in[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , F1_d1_data_in[0], , , VCC);
--F1_d1_data_in[0] is std_1s10:inst|button_pio:the_button_pio|d1_data_in[0] at LC_X50_Y10_N3
--operation mode is normal
F1_d1_data_in[0]_lut_out = in_port_to_the_button_pio[0];
F1_d1_data_in[0] = DFFEAS(F1_d1_data_in[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L301 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~21 at LC_X48_Y15_N5
--operation mode is normal
M1L301 = AE2_q_b[5] & T1_read_0 # !EB1L2 # !U1L2;
--M1L273 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[5]~2132 at LC_X48_Y15_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[5]_qfbk = H1_slave_readdata[5];
M1L273 = H1_slave_readdata[5]_qfbk # !J1_cpu_data_master_requests_clock_0_in;
--H1_slave_readdata[5] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[5] at LC_X48_Y15_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[5] = DFFEAS(M1L273, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[5], , , VCC);
--R1_counter_snapshot[21] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[21] at LC_X46_Y7_N6
--operation mode is normal
R1_counter_snapshot[21]_lut_out = R1_internal_counter[21];
R1_counter_snapshot[21] = DFFEAS(R1_counter_snapshot[21]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, , , , );
--R1L193 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[5]~1283 at LC_X46_Y7_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[5]_qfbk = R1_counter_snapshot[5];
R1L193 = L1_M_alu_result[4] & (L1_M_alu_result[2] & (R1_counter_snapshot[21]) # !L1_M_alu_result[2] & R1_counter_snapshot[5]_qfbk) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--R1_counter_snapshot[5] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[5] at LC_X46_Y7_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[5] = DFFEAS(R1L193, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[5], , , VCC);
--R1_period_l_register[5] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[5] at LC_X48_Y8_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_l_register[5]_lut_out = GND;
R1_period_l_register[5] = DFFEAS(R1_period_l_register[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, L1_M_st_data[5], , , VCC);
--R1L194 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[5]~1284 at LC_X48_Y8_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[5]_qfbk = R1_period_h_register[5];
R1L194 = R1L193 & R1_period_h_register[5]_qfbk # !R1L193 & (R1_period_l_register[5]);
--R1_period_h_register[5] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[5] at LC_X48_Y8_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[5] = DFFEAS(R1L194, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[5], , , VCC);
--HE1L57 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[5]~687 at LC_X51_Y9_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_internal_tx_data[5]_qfbk = HE1_internal_tx_data[5];
HE1L57 = L1_M_alu_result[3] & (HE1_control_reg[5]) # !L1_M_alu_result[3] & HE1_internal_tx_data[5]_qfbk;
--HE1_internal_tx_data[5] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[5] at LC_X51_Y9_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_internal_tx_data[5] = DFFEAS(HE1L57, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L64, L1_M_st_data[5], , , VCC);
--HE1L58 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[5]~688 at LC_X51_Y10_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[5]_qfbk = JE1_rx_data[5];
HE1L58 = L1_M_alu_result[3] & !KE1_tx_shift_empty # !L1_M_alu_result[3] & (JE1_rx_data[5]_qfbk);
--JE1_rx_data[5] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[5] at LC_X51_Y10_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[5] = DFFEAS(HE1L58, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1_got_new_char, JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6], , , VCC);
--KB1_counter_snapshot[21] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[21] at LC_X52_Y2_N9
--operation mode is normal
KB1_counter_snapshot[21]_lut_out = KB1_internal_counter[21];
KB1_counter_snapshot[21] = DFFEAS(KB1_counter_snapshot[21]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--KB1L194 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[5]~1272 at LC_X52_Y3_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[5]_qfbk = KB1_counter_snapshot[5];
KB1L194 = L1_M_alu_result[4] & (L1_M_alu_result[2] & (KB1_counter_snapshot[21]) # !L1_M_alu_result[2] & KB1_counter_snapshot[5]_qfbk) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--KB1_counter_snapshot[5] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[5] at LC_X52_Y3_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[5] = DFFEAS(KB1L194, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[5], , , VCC);
--KB1_period_l_register[5] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[5] at LC_X52_Y5_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_l_register[5]_lut_out = GND;
KB1_period_l_register[5] = DFFEAS(KB1_period_l_register[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, L1_M_st_data[5], , , VCC);
--KB1L195 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[5]~1273 at LC_X51_Y5_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[5]_qfbk = KB1_period_h_register[5];
KB1L195 = KB1L194 & (KB1_period_h_register[5]_qfbk) # !KB1L194 & (KB1_period_l_register[5]);
--KB1_period_h_register[5] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[5] at LC_X51_Y5_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[5] = DFFEAS(KB1L195, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, L1_M_st_data[5], , , VCC);
--M1L302 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata~22 at LC_X50_Y16_N5
--operation mode is normal
M1L302 = AE2_q_b[6] & T1_read_0 # !EB1L2 # !U1L2;
--M1L274 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[6]~2134 at LC_X50_Y16_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[6]_qfbk = H1_slave_readdata[6];
M1L274 = H1_slave_readdata[6]_qfbk # !J1_cpu_data_master_requests_clock_0_in;
--H1_slave_readdata[6] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[6] at LC_X50_Y16_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[6] = DFFEAS(M1L274, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[6], , , VCC);
--R1_counter_snapshot[6] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[6] at LC_X46_Y6_N6
--operation mode is normal
R1_counter_snapshot[6]_lut_out = !R1_internal_counter[6];
R1_counter_snapshot[6] = DFFEAS(R1_counter_snapshot[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, , , , );
--R1L195 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[6]~1286 at LC_X46_Y6_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[22]_qfbk = R1_counter_snapshot[22];
R1L195 = L1_M_alu_result[4] & (L1_M_alu_result[2] & R1_counter_snapshot[22]_qfbk # !L1_M_alu_result[2] & (R1_counter_snapshot[6])) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--R1_counter_snapshot[22] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[22] at LC_X46_Y6_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[22] = DFFEAS(R1L195, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[22], , , VCC);
--R1_period_l_register[6] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[6] at LC_X52_Y6_N5
--operation mode is normal
R1_period_l_register[6]_lut_out = !L1_M_st_data[6];
R1_period_l_register[6] = DFFEAS(R1_period_l_register[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, , , , );
--R1L196 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[6]~1287 at LC_X47_Y9_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[6]_qfbk = R1_period_h_register[6];
R1L196 = R1L195 & (R1_period_h_register[6]_qfbk) # !R1L195 & !R1_period_l_register[6];
--R1_period_h_register[6] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[6] at LC_X47_Y9_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[6] = DFFEAS(R1L196, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[6], , , VCC);
--HE1L59 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[6]~690 at LC_X51_Y9_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_internal_tx_data[6]_qfbk = HE1_internal_tx_data[6];
HE1L59 = L1_M_alu_result[3] & HE1_control_reg[6] # !L1_M_alu_result[3] & (HE1_internal_tx_data[6]_qfbk);
--HE1_internal_tx_data[6] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[6] at LC_X51_Y9_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_internal_tx_data[6] = DFFEAS(HE1L59, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L64, L1_M_st_data[6], , , VCC);
--HE1L60 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[6]~691 at LC_X51_Y10_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[6]_qfbk = JE1_rx_data[6];
HE1L60 = L1_M_alu_result[3] & (!KE1_internal_tx_ready) # !L1_M_alu_result[3] & (JE1_rx_data[6]_qfbk);
--JE1_rx_data[6] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[6] at LC_X51_Y10_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[6] = DFFEAS(HE1L60, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1_got_new_char, JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7], , , VCC);
--KB1_counter_snapshot[22] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[22] at LC_X52_Y3_N0
--operation mode is normal
KB1_counter_snapshot[22]_lut_out = KB1_internal_counter[22];
KB1_counter_snapshot[22] = DFFEAS(KB1_counter_snapshot[22]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--KB1L196 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[6]~1275 at LC_X52_Y3_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[6]_qfbk = KB1_counter_snapshot[6];
KB1L196 = L1_M_alu_result[4] & (L1_M_alu_result[2] & (KB1_counter_snapshot[22]) # !L1_M_alu_result[2] & KB1_counter_snapshot[6]_qfbk) # !L1_M_alu_result[4] & L1_M_alu_result[2];
--KB1_counter_snapshot[6] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[6] at LC_X52_Y3_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_counter_snapshot[6] = DFFEAS(KB1L196, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, KB1_internal_counter[6], , , VCC);
--KB1_period_l_register[6] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[6] at LC_X52_Y6_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_l_register[6]_lut_out = GND;
KB1_period_l_register[6] = DFFEAS(KB1_period_l_register[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, L1_M_st_data[6], , , VCC);
--KB1L197 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[6]~1276 at LC_X51_Y5_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[6]_qfbk = KB1_period_h_register[6];
KB1L197 = KB1L196 & (KB1_period_h_register[6]_qfbk) # !KB1L196 & KB1_period_l_register[6];
--KB1_period_h_register[6] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[6] at LC_X51_Y5_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_period_h_register[6] = DFFEAS(KB1L197, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, L1_M_st_data[6], , , VCC);
--F1_readdata[0] is std_1s10:inst|button_pio:the_button_pio|readdata[0] at LC_X50_Y10_N9
--operation mode is normal
F1_readdata[0]_lut_out = L1_M_alu_result[3] & (F1L24) # !L1_M_alu_result[3] & !L1_M_alu_result[2] & (in_port_to_the_button_pio[0]);
F1_readdata[0] = DFFEAS(F1_readdata[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L19 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5002 at LC_X48_Y14_N2
--operation mode is normal
M1L19 = L1_M_alu_result[7] & (A1L143) # !L1_M_alu_result[7] & F1_readdata[0] # !G1L1;
--M1_registered_cpu_data_master_readdata[0] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[0] at LC_X50_Y16_N7
--operation mode is normal
M1_registered_cpu_data_master_readdata[0]_lut_out = !M1L267 & (M1L266 # !U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[0] = DFFEAS(M1_registered_cpu_data_master_readdata[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L20 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5003 at LC_X48_Y14_N3
--operation mode is normal
M1L20 = M1L19 & (M1_registered_cpu_data_master_readdata[0] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave & !J1_cpu_data_master_requests_clock_0_in);
--M1L21 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5004 at LC_X46_Y15_N7
--operation mode is normal
M1L21 = Q1_internal_incoming_ext_ram_bus_data[0] & (BE1_q_a[0] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_internal_incoming_ext_ram_bus_data[0] & !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[0] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1L22 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5005 at LC_X46_Y15_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[0]_qfbk = M1_dbs_8_reg_segment_0[0];
M1L22 = Q1_cpu_data_master_requests_ext_flash_s1 & M1_dbs_8_reg_segment_0[0]_qfbk & (M1_registered_cpu_data_master_readdata[0] # !GB1L24) # !Q1_cpu_data_master_requests_ext_flash_s1 & (M1_registered_cpu_data_master_readdata[0] # !GB1L24);
--M1_dbs_8_reg_segment_0[0] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[0] at LC_X46_Y15_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[0] = DFFEAS(M1L22, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L308, Q1_internal_incoming_ext_ram_bus_data[0], , , VCC);
--DB1_readdata is std_1s10:inst|reconfig_request_pio:the_reconfig_request_pio|readdata at LC_X41_Y15_N6
--operation mode is normal
DB1_readdata_lut_out = !L1_M_alu_result[3] & (L1_M_alu_result[2] & DB1_data_dir # !L1_M_alu_result[2] & (A1L22));
DB1_readdata = DFFEAS(DB1_readdata_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L23 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5006 at LC_X46_Y15_N3
--operation mode is normal
M1L23 = M1L27 & (DB1_readdata # !L1_M_alu_result[7] # !EB1L2);
--HE1_readdata[0] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[0] at LC_X50_Y10_N6
--operation mode is normal
HE1_readdata[0]_lut_out = HE1L48 & (HE1_control_reg[0] & HE1L15 # !L1_M_alu_result[4]) # !HE1L48 & (HE1_control_reg[0] & HE1L15);
HE1_readdata[0] = DFFEAS(HE1_readdata[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L24 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5007 at LC_X46_Y15_N8
--operation mode is normal
M1L24 = M1L23 & M1L21 & (HE1_readdata[0] # !QB1_cpu_data_master_granted_uart1_s1);
--R1_readdata[0] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[0] at LC_X50_Y7_N8
--operation mode is normal
R1_readdata[0]_lut_out = R1L182 # R1L181 # R1L183;
R1_readdata[0] = DFFEAS(R1_readdata[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--KB1_readdata[0] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[0] at LC_X50_Y7_N1
--operation mode is normal
KB1_readdata[0]_lut_out = KB1L183 # KB1L182 # KB1L184;
KB1_readdata[0] = DFFEAS(KB1_readdata[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L25 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5008 at LC_X50_Y7_N5
--operation mode is normal
M1L25 = R1_readdata[0] & (KB1_readdata[0] # !LB1_cpu_data_master_requests_sys_clk_timer_s1) # !R1_readdata[0] & !S1_cpu_data_master_requests_high_res_timer_s1 & (KB1_readdata[0] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--M1L26 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5009 at LC_X46_Y15_N0
--operation mode is normal
M1L26 = M1L20 & M1L25 & M1L24;
--FC1L1 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[0]~1226 at LC_X40_Y20_N0
--operation mode is normal
FC1L1 = AMPP_FUNCTION(SC1_internal_oci_ienable1[0], FC1L21, SC1L3);
--FC1L2 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[0]~1227 at LC_X40_Y20_N5
--operation mode is normal
FC1L2 = AMPP_FUNCTION(PD1_q_a[0], P1L23, VC1_internal_monitor_error, SC1L3);
--F1_readdata[1] is std_1s10:inst|button_pio:the_button_pio|readdata[1] at LC_X50_Y13_N2
--operation mode is normal
F1_readdata[1]_lut_out = L1_M_alu_result[3] & (F1L25) # !L1_M_alu_result[3] & !L1_M_alu_result[2] & (in_port_to_the_button_pio[1]);
F1_readdata[1] = DFFEAS(F1_readdata[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L28 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5010 at LC_X50_Y13_N8
--operation mode is normal
M1L28 = L1_M_alu_result[7] & (A1L142) # !L1_M_alu_result[7] & F1_readdata[1] # !G1L1;
--M1_registered_cpu_data_master_readdata[1] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[1] at LC_X50_Y17_N7
--operation mode is normal
M1_registered_cpu_data_master_readdata[1]_lut_out = !M1L269 & (M1L268 # !U1L2 # !EB1L2);
M1_registered_cpu_data_master_readdata[1] = DFFEAS(M1_registered_cpu_data_master_readdata[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L29 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5011 at LC_X50_Y13_N0
--operation mode is normal
M1L29 = !EB1_cpu_data_master_requests_reconfig_request_pio_s1 & M1L28 & (M1_registered_cpu_data_master_readdata[1] # !U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave);
--M1L30 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5012 at LC_X45_Y20_N7
--operation mode is normal
M1L30 = Q1_cpu_data_master_requests_lan91c111_s1 & Q1_internal_incoming_ext_ram_bus_data[1] & (BE1_q_a[1] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1) # !Q1_cpu_data_master_requests_lan91c111_s1 & (BE1_q_a[1] # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--M1L31 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5013 at LC_X47_Y14_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[1]_qfbk = M1_dbs_8_reg_segment_0[1];
M1L31 = M1_registered_cpu_data_master_readdata[1] & (M1_dbs_8_reg_segment_0[1]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1) # !M1_registered_cpu_data_master_readdata[1] & !GB1L24 & (M1_dbs_8_reg_segment_0[1]_qfbk # !Q1_cpu_data_master_requests_ext_flash_s1);
--M1_dbs_8_reg_segment_0[1] is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|dbs_8_reg_segment_0[1] at LC_X47_Y14_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
M1_dbs_8_reg_segment_0[1] = DFFEAS(M1L31, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , M1L308, Q1_internal_incoming_ext_ram_bus_data[1], , , VCC);
--HE1_readdata[1] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|readdata[1] at LC_X48_Y9_N1
--operation mode is normal
HE1_readdata[1]_lut_out = !L1_M_alu_result[4] & (L1_M_alu_result[2] & (HE1L49) # !L1_M_alu_result[2] & HE1L50);
HE1_readdata[1] = DFFEAS(HE1_readdata[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L32 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5014 at LC_X48_Y9_N3
--operation mode is normal
M1L32 = M1L36 & (HE1_readdata[1] # !LB1L2 # !QB1L2);
--KB1_readdata[1] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|readdata[1] at LC_X50_Y5_N4
--operation mode is normal
KB1_readdata[1]_lut_out = KB1L186 # KB1L185 # KB1L187;
KB1_readdata[1] = DFFEAS(KB1_readdata[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L33 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5015 at LC_X45_Y20_N4
--operation mode is normal
M1L33 = M1L30 & M1L32 & (KB1_readdata[1] # !LB1_cpu_data_master_requests_sys_clk_timer_s1);
--R1_readdata[1] is std_1s10:inst|high_res_timer:the_high_res_timer|readdata[1] at LC_X48_Y3_N2
--operation mode is normal
R1_readdata[1]_lut_out = R1L185 # R1L184 # R1L186;
R1_readdata[1] = DFFEAS(R1_readdata[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--M1L34 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5016 at LC_X50_Y17_N8
--operation mode is normal
M1L34 = M1_registered_cpu_data_master_readdata[1] & (R1_readdata[1] # !S1_cpu_data_master_requests_high_res_timer_s1) # !M1_registered_cpu_data_master_readdata[1] & !J1_cpu_data_master_requests_clock_0_in & (R1_readdata[1] # !S1_cpu_data_master_requests_high_res_timer_s1);
--M1L35 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5017 at LC_X45_Y20_N0
--operation mode is normal
M1L35 = M1L33 & (M1L34 & M1L29);
--FC1L3 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[1]~1228 at LC_X45_Y20_N9
--operation mode is normal
FC1L3 = AMPP_FUNCTION(SC1_internal_oci_ienable1[1], FC1L21, SC1L3);
--FC1L4 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[1]~1229 at LC_X45_Y20_N5
--operation mode is normal
FC1L4 = AMPP_FUNCTION(PD1_q_a[1], VC1_internal_monitor_ready, SC1L3, P1L23);
--KE1_baud_rate_counter[0] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[0] at LC_X52_Y8_N0
--operation mode is arithmetic
KE1_baud_rate_counter[0]_lut_out = !KE1_baud_rate_counter[0];
KE1_baud_rate_counter[0] = DFFEAS(KE1_baud_rate_counter[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , A1L275, , , KE1L38);
--KE1L4 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[0]~54 at LC_X52_Y8_N0
--operation mode is arithmetic
KE1L4_cout_0 = KE1_baud_rate_counter[0];
KE1L4 = CARRY(KE1L4_cout_0);
--KE1L5 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[0]~54COUT1_98 at LC_X52_Y8_N0
--operation mode is arithmetic
KE1L5_cout_1 = KE1_baud_rate_counter[0];
KE1L5 = CARRY(KE1L5_cout_1);
--KE1_baud_rate_counter[1] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[1] at LC_X52_Y8_N1
--operation mode is arithmetic
KE1_baud_rate_counter[1]_lut_out = KE1_baud_rate_counter[1] $ !KE1L4;
KE1_baud_rate_counter[1] = DFFEAS(KE1_baud_rate_counter[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , VCC, , , KE1L38);
--KE1L7 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[1]~55 at LC_X52_Y8_N1
--operation mode is arithmetic
KE1L7_cout_0 = !KE1_baud_rate_counter[1] & !KE1L4;
KE1L7 = CARRY(KE1L7_cout_0);
--KE1L8 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[1]~55COUT1_100 at LC_X52_Y8_N1
--operation mode is arithmetic
KE1L8_cout_1 = !KE1_baud_rate_counter[1] & !KE1L5;
KE1L8 = CARRY(KE1L8_cout_1);
--KE1_baud_rate_counter[2] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[2] at LC_X52_Y8_N2
--operation mode is arithmetic
KE1_baud_rate_counter[2]_lut_out = KE1_baud_rate_counter[2] $ (KE1L7);
KE1_baud_rate_counter[2] = DFFEAS(KE1_baud_rate_counter[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , A1L275, , , KE1L38);
--KE1L10 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[2]~56 at LC_X52_Y8_N2
--operation mode is arithmetic
KE1L10_cout_0 = KE1_baud_rate_counter[2] # !KE1L7;
KE1L10 = CARRY(KE1L10_cout_0);
--KE1L11 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[2]~56COUT1_102 at LC_X52_Y8_N2
--operation mode is arithmetic
KE1L11_cout_1 = KE1_baud_rate_counter[2] # !KE1L8;
KE1L11 = CARRY(KE1L11_cout_1);
--KE1_baud_rate_counter[3] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[3] at LC_X52_Y8_N3
--operation mode is arithmetic
KE1_baud_rate_counter[3]_lut_out = KE1_baud_rate_counter[3] $ (!KE1L10);
KE1_baud_rate_counter[3] = DFFEAS(KE1_baud_rate_counter[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , A1L275, , , KE1L38);
--KE1L13 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[3]~57 at LC_X52_Y8_N3
--operation mode is arithmetic
KE1L13_cout_0 = !KE1_baud_rate_counter[3] & (!KE1L10);
KE1L13 = CARRY(KE1L13_cout_0);
--KE1L14 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[3]~57COUT1_104 at LC_X52_Y8_N3
--operation mode is arithmetic
KE1L14_cout_1 = !KE1_baud_rate_counter[3] & (!KE1L11);
KE1L14 = CARRY(KE1L14_cout_1);
--KE1L30 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|Equal0~133 at LC_X52_Y7_N6
--operation mode is normal
KE1L30 = !KE1_baud_rate_counter[2] & !KE1_baud_rate_counter[1] & !KE1_baud_rate_counter[3] & !KE1_baud_rate_counter[0];
--KE1_baud_rate_counter[4] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[4] at LC_X52_Y8_N4
--operation mode is arithmetic
KE1_baud_rate_counter[4]_lut_out = KE1_baud_rate_counter[4] $ (KE1L13);
KE1_baud_rate_counter[4] = DFFEAS(KE1_baud_rate_counter[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , VCC, , , KE1L38);
--KE1L16 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[4]~58 at LC_X52_Y8_N4
--operation mode is arithmetic
--KE1_baud_rate_counter[5] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[5] at LC_X52_Y8_N5
--operation mode is arithmetic
KE1_baud_rate_counter[5]_carry_eqn = (!KE1L16 & GND) # (KE1L16 & VCC);
KE1_baud_rate_counter[5]_lut_out = KE1_baud_rate_counter[5] $ !KE1_baud_rate_counter[5]_carry_eqn;
KE1_baud_rate_counter[5] = DFFEAS(KE1_baud_rate_counter[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , VCC, , , KE1L38);
--KE1L20 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[5]~59 at LC_X52_Y8_N5
--operation mode is arithmetic
KE1L20_cout_0 = !KE1_baud_rate_counter[5] & !KE1L16;
KE1L20 = CARRY(KE1L20_cout_0);
--KE1L21 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[5]~59COUT1_106 at LC_X52_Y8_N5
--operation mode is arithmetic
KE1L21_cout_1 = !KE1_baud_rate_counter[5] & !KE1L16;
KE1L21 = CARRY(KE1L21_cout_1);
--KE1_baud_rate_counter[6] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[6] at LC_X52_Y8_N6
--operation mode is arithmetic
KE1_baud_rate_counter[6]_carry_eqn = (!KE1L16 & KE1L20) # (KE1L16 & KE1L21);
KE1_baud_rate_counter[6]_lut_out = KE1_baud_rate_counter[6] $ KE1_baud_rate_counter[6]_carry_eqn;
KE1_baud_rate_counter[6] = DFFEAS(KE1_baud_rate_counter[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , A1L275, , , KE1L38);
--KE1L23 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[6]~60 at LC_X52_Y8_N6
--operation mode is arithmetic
KE1L23_cout_0 = KE1_baud_rate_counter[6] # !KE1L20;
KE1L23 = CARRY(KE1L23_cout_0);
--KE1L24 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[6]~60COUT1_108 at LC_X52_Y8_N6
--operation mode is arithmetic
KE1L24_cout_1 = KE1_baud_rate_counter[6] # !KE1L21;
KE1L24 = CARRY(KE1L24_cout_1);
--KE1_baud_rate_counter[7] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[7] at LC_X52_Y8_N7
--operation mode is arithmetic
KE1_baud_rate_counter[7]_carry_eqn = (!KE1L16 & KE1L23) # (KE1L16 & KE1L24);
KE1_baud_rate_counter[7]_lut_out = KE1_baud_rate_counter[7] $ (!KE1_baud_rate_counter[7]_carry_eqn);
KE1_baud_rate_counter[7] = DFFEAS(KE1_baud_rate_counter[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , VCC, , , KE1L38);
--KE1L26 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[7]~61 at LC_X52_Y8_N7
--operation mode is arithmetic
KE1L26_cout_0 = !KE1_baud_rate_counter[7] & (!KE1L23);
KE1L26 = CARRY(KE1L26_cout_0);
--KE1L27 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[7]~61COUT1_110 at LC_X52_Y8_N7
--operation mode is arithmetic
KE1L27_cout_1 = !KE1_baud_rate_counter[7] & (!KE1L24);
KE1L27 = CARRY(KE1L27_cout_1);
--KE1L31 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|Equal0~134 at LC_X52_Y7_N3
--operation mode is normal
KE1L31 = !KE1_baud_rate_counter[7] & !KE1_baud_rate_counter[6] & !KE1_baud_rate_counter[5] & !KE1_baud_rate_counter[4];
--KE1_baud_rate_counter[8] is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|baud_rate_counter[8] at LC_X52_Y8_N8
--operation mode is normal
KE1_baud_rate_counter[8]_carry_eqn = (!KE1L16 & KE1L26) # (KE1L16 & KE1L27);
KE1_baud_rate_counter[8]_lut_out = KE1_baud_rate_counter[8]_carry_eqn $ KE1_baud_rate_counter[8];
KE1_baud_rate_counter[8] = DFFEAS(KE1_baud_rate_counter[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , VCC, , , KE1L38);
--HE1L64 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|tx_wr_strobe~10 at LC_X48_Y9_N6
--operation mode is normal
HE1L64 = QB1L2 & HE1L19 & L1_internal_d_write & LB1L2;
--L1_E_wrctl_bstatus is std_1s10:inst|cpu:the_cpu|E_wrctl_bstatus at LC_X28_Y22_N2
--operation mode is normal
L1_E_wrctl_bstatus = AMPP_FUNCTION(L1_E_ctrl_wrctl_inst, L1_E_iw[8], L1_E_iw[7], L1_E_iw[6]);
--L1_E_wrctl_estatus is std_1s10:inst|cpu:the_cpu|E_wrctl_estatus at LC_X28_Y22_N7
--operation mode is normal
L1_E_wrctl_estatus = AMPP_FUNCTION(L1_E_ctrl_wrctl_inst, L1_E_iw[8], L1_E_iw[7], L1_E_iw[6]);
--DD1L119Q is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir_out[1]~reg0 at LC_X29_Y28_N6
--operation mode is normal
DD1L119Q = AMPP_FUNCTION(!A1L6, L1_hbreak_enabled, !C1_CLR_SIGNAL);
--ME6_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF|Q[0] at LC_X31_Y26_N2
--operation mode is normal
ME6_Q[0] = AMPP_FUNCTION(!A1L6, ME6_Q[0], C1L9, ME3_Q[0], ME8_Q[1], !C1_CLR_SIGNAL);
--ME4L3 is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0]~203 at LC_X31_Y26_N1
--operation mode is normal
ME4L3 = AMPP_FUNCTION(ME2_Q[0], ME3_Q[0], ME6_Q[0]);
--C1L21 is sld_hub:sld_hub_inst|IRF_ENABLE[2]~127 at LC_X30_Y26_N9
--operation mode is normal
C1L21 = AMPP_FUNCTION(C1L9, ME8_Q[1], C1L19, ME2_Q[0]);
--NE1_WORD_SR[2] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[2] at LC_X28_Y28_N1
--operation mode is normal
NE1_WORD_SR[2] = AMPP_FUNCTION(!A1L6, NE1L16, NE1L17, NE1_WORD_SR[3], NE1_word_counter[2], VCC, NE1_clear_signal, RE1_state[4], NE1L24);
--NE1L19 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux2~28 at LC_X27_Y27_N8
--operation mode is normal
NE1L19 = AMPP_FUNCTION(NE1_word_counter[3], NE1_word_counter[0], NE1_word_counter[1], NE1_word_counter[2]);
--NE1L1 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~72 at LC_X28_Y27_N9
--operation mode is normal
NE1L1 = AMPP_FUNCTION(NE1_word_counter[4], NE1L12, NE1L13);
--NE1L15 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Equal0~41 at LC_X27_Y27_N6
--operation mode is normal
NE1L15 = AMPP_FUNCTION(NE1_word_counter[2], NE1_word_counter[0], NE1_word_counter[1], NE1_word_counter[4]);
--NE1L25 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1253 at LC_X28_Y26_N5
--operation mode is normal
NE1L25 = AMPP_FUNCTION(NE1_clear_signal, C1_jtag_debug_mode_usr0, RE1_state[3], RE1_state[4]);
--NE1L2 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~74 at LC_X28_Y27_N5
--operation mode is arithmetic
NE1L2 = AMPP_FUNCTION(NE1_word_counter[0]);
--NE1L3 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~75 at LC_X28_Y27_N5
--operation mode is arithmetic
NE1L3 = AMPP_FUNCTION(NE1_word_counter[0]);
--NE1L4 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~75COUT1_102 at LC_X28_Y27_N5
--operation mode is arithmetic
NE1L4 = AMPP_FUNCTION(NE1_word_counter[0]);
--NE1L5 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~76 at LC_X28_Y27_N6
--operation mode is arithmetic
NE1L5 = AMPP_FUNCTION(NE1_word_counter[1], NE1L3, NE1L4);
--NE1L6 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~77 at LC_X28_Y27_N6
--operation mode is arithmetic
NE1L6 = AMPP_FUNCTION(NE1_word_counter[1], NE1L3);
--NE1L7 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~77COUT1_104 at LC_X28_Y27_N6
--operation mode is arithmetic
NE1L7 = AMPP_FUNCTION(NE1_word_counter[1], NE1L4);
--NE1L8 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~78 at LC_X28_Y27_N7
--operation mode is arithmetic
NE1L8 = AMPP_FUNCTION(NE1_word_counter[2], NE1L6, NE1L7);
--NE1L9 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~79 at LC_X28_Y27_N7
--operation mode is arithmetic
NE1L9 = AMPP_FUNCTION(NE1_word_counter[2], NE1L6);
--NE1L10 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~79COUT1_106 at LC_X28_Y27_N7
--operation mode is arithmetic
NE1L10 = AMPP_FUNCTION(NE1_word_counter[2], NE1L7);
--NE1L11 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~80 at LC_X28_Y27_N8
--operation mode is arithmetic
NE1L11 = AMPP_FUNCTION(NE1_word_counter[3], NE1L9, NE1L10);
--NE1L12 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~81 at LC_X28_Y27_N8
--operation mode is arithmetic
NE1L12 = AMPP_FUNCTION(NE1_word_counter[3], NE1L9);
--NE1L13 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Add0~81COUT1_108 at LC_X28_Y27_N8
--operation mode is arithmetic
NE1L13 = AMPP_FUNCTION(NE1_word_counter[3], NE1L10);
--QD1_rvalid0 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rvalid0 at LC_X34_Y23_N7
--operation mode is normal
QD1_rvalid0 = AMPP_FUNCTION(DE1__clk0, QD1_user_saw_rvalid, QD1L2, QD1L19, QD1_read_req, E1_data_out);
--QD1L53 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3498 at LC_X34_Y24_N1
--operation mode is normal
QD1L53 = AMPP_FUNCTION(RE1_state[3], ME4_Q[0], RE1_state[4]);
--QD1_write_stalled is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|write_stalled at LC_X33_Y23_N7
--operation mode is normal
QD1_write_stalled = AMPP_FUNCTION(!A1L6, altera_internal_jtag, QD1_td_shift[10], QD1_write_stalled, T1_t_dav, !C1_CLR_SIGNAL, QD1L72);
--QD1_td_shift[2] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[2] at LC_X35_Y24_N2
--operation mode is normal
QD1_td_shift[2] = AMPP_FUNCTION(!A1L6, QD1L63, QD1L56, QD1L53, !C1_CLR_SIGNAL, QD1L52);
--QD1L54 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3499 at LC_X34_Y24_N0
--operation mode is normal
QD1L54 = AMPP_FUNCTION(QD1_count[9], QD1_td_shift[2], QD1_write_stalled);
--QD1_count[8] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[8] at LC_X31_Y26_N6
--operation mode is normal
QD1_count[8] = AMPP_FUNCTION(!A1L6, QD1_count[7], RE1_state[4], !C1_CLR_SIGNAL, QD1L52);
--QD1L55 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3501 at LC_X33_Y23_N5
--operation mode is normal
QD1L55 = AMPP_FUNCTION(RE1_state[4], QD1_count[8], ME4_Q[0], QD1L66);
--QD1L36 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|state~198 at LC_X34_Y24_N4
--operation mode is normal
QD1L36 = AMPP_FUNCTION(QD1_state, ME4_Q[0], RE1_state[3]);
--QD1_count[0] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[0] at LC_X35_Y23_N3
--operation mode is normal
QD1_count[0] = AMPP_FUNCTION(!A1L6, QD1_count[9], RE1_state[4], !C1_CLR_SIGNAL, QD1L52);
--QD1_td_shift[10] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[10] at LC_X36_Y23_N5
--operation mode is normal
QD1_td_shift[10] = AMPP_FUNCTION(!A1L6, C1L11, !C1_CLR_SIGNAL, QD1L52);
--QD1_rdata[7] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[7] at LC_X35_Y23_N0
--operation mode is normal
QD1_rdata[7] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[7], E1_data_out, QD1L18);
--QD1L69 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|user_saw_rvalid~142 at LC_X34_Y24_N9
--operation mode is normal
QD1L69 = AMPP_FUNCTION(QD1L1, ME4_Q[0], RE1_state[4], QD1_state);
--TC1_break_readreg[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[0] at LC_X32_Y26_N8
--operation mode is normal
TC1_break_readreg[0] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[0], DD1L188, DD1_internal_jdo1[36], DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L130 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux39~14 at LC_X36_Y24_N8
--operation mode is normal
DD1L130 = AMPP_FUNCTION(DD1_ir[1], TC1_break_readreg[0], DD1_ir[0], CD1_internal_MonDReg[0]);
--DD1_sr[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[2] at LC_X33_Y29_N6
--operation mode is normal
DD1_sr[2] = AMPP_FUNCTION(!A1L6, DD1L141, DD1_sr[3], DD1L129, DD1L143, !C1_CLR_SIGNAL, DD1L6);
--DD1L121 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux0~33 at LC_X32_Y29_N8
--operation mode is normal
DD1L121 = AMPP_FUNCTION(ME5_Q[0], ME5_Q[1]);
--DD1_DRsize[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[1] at LC_X32_Y29_N8
--operation mode is normal
DD1_DRsize[1] = AMPP_FUNCTION(!A1L6, ME5_Q[0], ME5_Q[1], !C1_CLR_SIGNAL, DD1_st_updateir);
--VC1L7 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_ready~119 at LC_X34_Y25_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
VC1L7 = AMPP_FUNCTION(DD1_internal_jdo1[34], VC1_internal_monitor_ready, DD1L189);
--DD1_internal_jdo1[25] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[25] at LC_X34_Y25_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[25] = AMPP_FUNCTION(!A1L9, DD1_sr[25], VCC, GND, DD1L144);
--DD1_st_shiftdr is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_shiftdr at LC_X31_Y28_N0
--operation mode is normal
DD1_st_shiftdr = AMPP_FUNCTION(!A1L6, DD1L143, A1L9);
--RE1_state[11] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11] at LC_X28_Y4_N7
--operation mode is normal
RE1_state[11] = AMPP_FUNCTION(!A1L6, RE1_state[11], RE1_state[10], RE1_state[14], VCC, !A1L8);
--RE1_state[9] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9] at LC_X28_Y5_N9
--operation mode is normal
RE1_state[9] = AMPP_FUNCTION(!A1L6, A1L8, RE1_state[2], VCC);
--RE1_tms_cnt[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[2] at LC_X28_Y6_N2
--operation mode is normal
RE1_tms_cnt[2] = AMPP_FUNCTION(!A1L6, RE1_tms_cnt[2], RE1_tms_cnt[1], RE1_tms_cnt[0], VCC, A1L8);
--RE1_tms_cnt[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[1] at LC_X28_Y6_N5
--operation mode is normal
RE1_tms_cnt[1] = AMPP_FUNCTION(!A1L6, RE1_tms_cnt[1], RE1_tms_cnt[0], VCC, A1L8);
--RE1_tms_cnt[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] at LC_X28_Y4_N3
--operation mode is normal
RE1_tms_cnt[0] = AMPP_FUNCTION(!A1L6, RE1_tms_cnt[0], A1L8, VCC);
--RE1L18 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~214 at LC_X28_Y5_N3
--operation mode is normal
RE1L18 = AMPP_FUNCTION(RE1_tms_cnt[2], RE1_tms_cnt[1], RE1_tms_cnt[0]);
--RE1_state[10] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[10] at LC_X28_Y5_N8
--operation mode is normal
RE1_state[10] = AMPP_FUNCTION(!A1L6, A1L8, RE1_state[9], VCC);
--RE1_state[6] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[6] at LC_X28_Y26_N6
--operation mode is normal
RE1_state[6] = AMPP_FUNCTION(!A1L6, RE1_state[6], RE1_state[5], VCC, !A1L8);
--FB1L65 is std_1s10:inst|sdram:the_sdram|active_data[30]~6664 at LC_X34_Y4_N5
--operation mode is normal
FB1L65 = FB1L565 & E1_data_out & (FB1L593 # !FB1L563);
--FB1L66 is std_1s10:inst|sdram:the_sdram|active_data[30]~6665 at LC_X35_Y4_N3
--operation mode is normal
FB1L66 = FB1_m_state[0] & (FB1L563 & (!FB1L724) # !FB1L563 & FB1L566) # !FB1_m_state[0] & (FB1L563);
--L1L47 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12928 at LC_X27_Y20_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L47 = AMPP_FUNCTION(L1_E_ctrl_jmp_direct, L1_E_extra_pc[12], L1L1365);
--L1_E_iw[18] is std_1s10:inst|cpu:the_cpu|E_iw[18] at LC_X27_Y20_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[18] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[18], E1_data_out, GND, L1_W_stall);
--L1_E_pc[12] is std_1s10:inst|cpu:the_cpu|E_pc[12] at LC_X34_Y16_N8
--operation mode is normal
L1_E_pc[12] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[12], E1_data_out, L1_W_stall);
--L1_E_ctrl_jmp_indirect is std_1s10:inst|cpu:the_cpu|E_ctrl_jmp_indirect at LC_X33_Y10_N4
--operation mode is normal
L1_E_ctrl_jmp_indirect = AMPP_FUNCTION(DE1__clk0, L1L827, L1_D_iw[12], L1L237, L1L830, E1_data_out, L1_W_stall);
--L1L48 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12929 at LC_X33_Y17_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L48 = AMPP_FUNCTION(L1_E_ctrl_jmp_direct, L1L1365, L1_E_extra_pc[16]);
--L1_E_iw[22] is std_1s10:inst|cpu:the_cpu|E_iw[22] at LC_X33_Y17_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[22] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[22], E1_data_out, GND, L1_W_stall);
--L1_E_pc[16] is std_1s10:inst|cpu:the_cpu|E_pc[16] at LC_X34_Y16_N0
--operation mode is normal
L1_E_pc[16] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[16], E1_data_out, L1_W_stall);
--L1_ic_tag_clr_valid_bits_nxt is std_1s10:inst|cpu:the_cpu|ic_tag_clr_valid_bits_nxt at LC_X35_Y21_N7
--operation mode is normal
L1_ic_tag_clr_valid_bits_nxt = AMPP_FUNCTION(L1_reset_d1, L1L1077, L1L259, L1L260);
--L1L49 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12930 at LC_X31_Y20_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L49 = AMPP_FUNCTION(L1L1365, L1_E_ctrl_jmp_direct, L1_E_extra_pc[3]);
--L1_E_iw[9] is std_1s10:inst|cpu:the_cpu|E_iw[9] at LC_X31_Y20_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[9] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[9], E1_data_out, GND, L1_W_stall);
--L1_E_pc[3] is std_1s10:inst|cpu:the_cpu|E_pc[3] at LC_X33_Y16_N5
--operation mode is normal
L1_E_pc[3] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[3], E1_data_out, L1_W_stall);
--L1L50 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12931 at LC_X31_Y20_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L50 = AMPP_FUNCTION(L1_E_extra_pc[4], L1_E_ctrl_jmp_direct, L1L1365);
--L1_E_iw[10] is std_1s10:inst|cpu:the_cpu|E_iw[10] at LC_X31_Y20_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[10] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[10], E1_data_out, GND, L1_W_stall);
--L1_E_pc[4] is std_1s10:inst|cpu:the_cpu|E_pc[4] at LC_X33_Y21_N3
--operation mode is normal
L1_E_pc[4] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[4], E1_data_out, L1_W_stall);
--L1L51 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12932 at LC_X33_Y18_N6
--operation mode is normal
L1L51 = AMPP_FUNCTION(L1_E_ctrl_jmp_direct, L1_E_iw[11], L1L1365, L1_E_extra_pc[5]);
--L1_E_pc[5] is std_1s10:inst|cpu:the_cpu|E_pc[5] at LC_X35_Y18_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_pc[5] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[5], E1_data_out, GND, L1_W_stall);
--L1L52 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12933 at LC_X31_Y20_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L52 = AMPP_FUNCTION(L1L1365, L1_E_extra_pc[6], L1_E_ctrl_jmp_direct);
--L1_E_iw[12] is std_1s10:inst|cpu:the_cpu|E_iw[12] at LC_X31_Y20_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[12] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[12], E1_data_out, GND, L1_W_stall);
--L1_E_pc[6] is std_1s10:inst|cpu:the_cpu|E_pc[6] at LC_X35_Y18_N1
--operation mode is normal
L1_E_pc[6] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[6], E1_data_out, L1_W_stall);
--L1L53 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12934 at LC_X32_Y20_N1
--operation mode is normal
L1L53 = AMPP_FUNCTION(L1L1365, L1_E_ctrl_jmp_direct, L1_E_iw[13], L1_E_extra_pc[7]);
--L1_E_pc[7] is std_1s10:inst|cpu:the_cpu|E_pc[7] at LC_X32_Y20_N5
--operation mode is normal
L1_E_pc[7] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[7], E1_data_out, L1_W_stall);
--L1L54 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12935 at LC_X30_Y20_N8
--operation mode is normal
L1L54 = AMPP_FUNCTION(L1_E_iw[14], L1_E_ctrl_jmp_direct, L1L1365, L1_E_extra_pc[8]);
--L1_E_pc[8] is std_1s10:inst|cpu:the_cpu|E_pc[8] at LC_X35_Y18_N8
--operation mode is normal
L1_E_pc[8] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[8], E1_data_out, L1_W_stall);
--L1L55 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12936 at LC_X25_Y21_N4
--operation mode is normal
L1L55 = AMPP_FUNCTION(L1_E_iw[15], L1L1365, L1_E_ctrl_jmp_direct, L1_E_extra_pc[9]);
--L1_E_pc[9] is std_1s10:inst|cpu:the_cpu|E_pc[9] at LC_X30_Y20_N3
--operation mode is normal
L1_E_pc[9] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[9], E1_data_out, L1_W_stall);
--L1L56 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12937 at LC_X34_Y18_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L56 = AMPP_FUNCTION(L1_E_extra_pc[20], L1L1365, L1_E_ctrl_jmp_direct);
--L1_E_iw[26] is std_1s10:inst|cpu:the_cpu|E_iw[26] at LC_X34_Y18_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[26] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[26], E1_data_out, GND, L1_W_stall);
--L1_E_pc[20] is std_1s10:inst|cpu:the_cpu|E_pc[20] at LC_X33_Y21_N7
--operation mode is normal
L1_E_pc[20] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[20], E1_data_out, L1_W_stall);
--L1L57 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12938 at LC_X33_Y18_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L57 = AMPP_FUNCTION(L1_E_ctrl_jmp_direct, L1L1365, L1_E_extra_pc[19]);
--L1_E_iw[25] is std_1s10:inst|cpu:the_cpu|E_iw[25] at LC_X33_Y18_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[25] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[25], E1_data_out, GND, L1_W_stall);
--L1_E_pc[19] is std_1s10:inst|cpu:the_cpu|E_pc[19] at LC_X33_Y14_N6
--operation mode is normal
L1_E_pc[19] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[19], E1_data_out, L1_W_stall);
--L1L58 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12939 at LC_X33_Y17_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L58 = AMPP_FUNCTION(L1_E_ctrl_jmp_direct, L1L1365, L1_E_extra_pc[18]);
--L1_E_iw[24] is std_1s10:inst|cpu:the_cpu|E_iw[24] at LC_X33_Y17_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[24] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[24], E1_data_out, GND, L1_W_stall);
--L1_E_pc[18] is std_1s10:inst|cpu:the_cpu|E_pc[18] at LC_X34_Y15_N4
--operation mode is normal
L1_E_pc[18] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[18], E1_data_out, L1_W_stall);
--L1L59 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12940 at LC_X33_Y17_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L59 = AMPP_FUNCTION(L1_E_ctrl_jmp_direct, L1L1365, L1_E_extra_pc[17]);
--L1_E_iw[23] is std_1s10:inst|cpu:the_cpu|E_iw[23] at LC_X33_Y17_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[23] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[23], E1_data_out, GND, L1_W_stall);
--L1_E_pc[17] is std_1s10:inst|cpu:the_cpu|E_pc[17] at LC_X33_Y12_N3
--operation mode is normal
L1_E_pc[17] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[17], E1_data_out, L1_W_stall);
--L1L60 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12941 at LC_X33_Y15_N4
--operation mode is normal
L1L60 = AMPP_FUNCTION(L1_E_ctrl_break, L1_E_extra_pc[21]);
--L1L61 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12942 at LC_X33_Y15_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L61 = AMPP_FUNCTION(L1L60, L1_E_ctrl_jmp_direct, L1_E_ctrl_exception);
--L1_E_iw[27] is std_1s10:inst|cpu:the_cpu|E_iw[27] at LC_X33_Y15_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[27] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[27], E1_data_out, GND, L1_W_stall);
--L1_E_pc[21] is std_1s10:inst|cpu:the_cpu|E_pc[21] at LC_X33_Y12_N7
--operation mode is normal
L1_E_pc[21] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[21], E1_data_out, L1_W_stall);
--L1L62 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12943 at LC_X28_Y20_N5
--operation mode is normal
L1L62 = AMPP_FUNCTION(L1_E_ctrl_break, L1_E_extra_pc[14]);
--L1L63 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12944 at LC_X28_Y20_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L63 = AMPP_FUNCTION(L1_E_ctrl_jmp_direct, L1_E_ctrl_exception, L1L62);
--L1_E_iw[20] is std_1s10:inst|cpu:the_cpu|E_iw[20] at LC_X28_Y20_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[20] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[20], E1_data_out, GND, L1_W_stall);
--L1_E_pc[14] is std_1s10:inst|cpu:the_cpu|E_pc[14] at LC_X33_Y16_N1
--operation mode is normal
L1_E_pc[14] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[14], E1_data_out, L1_W_stall);
--L1L64 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12945 at LC_X27_Y20_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L64 = AMPP_FUNCTION(L1_E_ctrl_jmp_direct, L1_E_extra_pc[11], L1L1365);
--L1_E_iw[17] is std_1s10:inst|cpu:the_cpu|E_iw[17] at LC_X27_Y20_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[17] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[17], E1_data_out, GND, L1_W_stall);
--L1_E_pc[11] is std_1s10:inst|cpu:the_cpu|E_pc[11] at LC_X33_Y12_N1
--operation mode is normal
L1_E_pc[11] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[11], E1_data_out, L1_W_stall);
--L1L65 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12946 at LC_X33_Y15_N8
--operation mode is normal
L1L65 = AMPP_FUNCTION(L1_E_ctrl_break, L1_E_extra_pc[22]);
--L1L66 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12947 at LC_X33_Y15_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L66 = AMPP_FUNCTION(L1L65, L1_E_ctrl_jmp_direct, L1_E_ctrl_exception);
--L1_E_iw[28] is std_1s10:inst|cpu:the_cpu|E_iw[28] at LC_X33_Y15_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[28] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[28], E1_data_out, GND, L1_W_stall);
--L1_E_pc[22] is std_1s10:inst|cpu:the_cpu|E_pc[22] at LC_X34_Y14_N9
--operation mode is normal
L1_E_pc[22] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[22], E1_data_out, L1_W_stall);
--L1L67 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12948 at LC_X31_Y20_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L67 = AMPP_FUNCTION(L1L1365, L1_E_ctrl_jmp_direct, L1_E_extra_pc[23]);
--L1_E_iw[29] is std_1s10:inst|cpu:the_cpu|E_iw[29] at LC_X31_Y20_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[29] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[29], E1_data_out, GND, L1_W_stall);
--L1_E_pc[23] is std_1s10:inst|cpu:the_cpu|E_pc[23] at LC_X18_Y13_N3
--operation mode is normal
L1_E_pc[23] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[23], E1_data_out, L1_W_stall);
--L1L68 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12949 at LC_X33_Y18_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L68 = AMPP_FUNCTION(L1_E_ctrl_jmp_direct, L1L1365, L1_E_extra_pc[15]);
--L1_E_iw[21] is std_1s10:inst|cpu:the_cpu|E_iw[21] at LC_X33_Y18_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[21] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[21], E1_data_out, GND, L1_W_stall);
--L1_E_pc[15] is std_1s10:inst|cpu:the_cpu|E_pc[15] at LC_X19_Y19_N1
--operation mode is normal
L1_E_pc[15] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[15], E1_data_out, L1_W_stall);
--L1L69 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12950 at LC_X31_Y20_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L69 = AMPP_FUNCTION(L1L1365, L1_E_ctrl_jmp_direct, L1_E_extra_pc[13]);
--L1_E_iw[19] is std_1s10:inst|cpu:the_cpu|E_iw[19] at LC_X31_Y20_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[19] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[19], E1_data_out, GND, L1_W_stall);
--L1_E_pc[13] is std_1s10:inst|cpu:the_cpu|E_pc[13] at LC_X33_Y10_N0
--operation mode is normal
L1_E_pc[13] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[13], E1_data_out, L1_W_stall);
--L1L70 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12951 at LC_X25_Y21_N9
--operation mode is normal
L1L70 = AMPP_FUNCTION(L1_E_iw[16], L1_E_extra_pc[10], L1_E_ctrl_jmp_direct, L1L1365);
--L1_E_pc[10] is std_1s10:inst|cpu:the_cpu|E_pc[10] at LC_X25_Y21_N3
--operation mode is normal
L1_E_pc[10] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[10], E1_data_out, L1_W_stall);
--L1L1108 is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[5]~301 at LC_X36_Y19_N8
--operation mode is normal
L1L1108 = AMPP_FUNCTION(L1L1061, L1L1059, L1L1060, L1L1058);
--L1L1112 is std_1s10:inst|cpu:the_cpu|ic_tag_clr_valid_bits_nxt~32 at LC_X35_Y21_N3
--operation mode is normal
L1L1112 = AMPP_FUNCTION(L1_M_valid_from_E, L1_reset_d1, L1_M_ctrl_invalidate_i);
--L1_ic_fill_valid_bits_en is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_en at LC_X35_Y21_N6
--operation mode is normal
L1_ic_fill_valid_bits_en = AMPP_FUNCTION(L1L1112, L1L1057, L1L260, L1L259);
--L1L71 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12952 at LC_X29_Y20_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L71 = AMPP_FUNCTION(L1_E_ctrl_jmp_direct, L1L1365, L1_E_extra_pc[2]);
--L1_E_iw[8] is std_1s10:inst|cpu:the_cpu|E_iw[8] at LC_X29_Y20_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[8] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[8], E1_data_out, GND, L1_W_stall);
--L1_E_pc[2] is std_1s10:inst|cpu:the_cpu|E_pc[2] at LC_X36_Y10_N0
--operation mode is normal
L1_E_pc[2] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[2], E1_data_out, L1_W_stall);
--L1L1106 is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[3]~303 at LC_X36_Y19_N3
--operation mode is normal
L1L1106 = AMPP_FUNCTION(L1L1061, L1L1059, L1L1060, L1L1058);
--L1L72 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12953 at LC_X28_Y21_N3
--operation mode is normal
L1L72 = AMPP_FUNCTION(L1_E_ctrl_jmp_direct, L1_E_extra_pc[1], L1L1365, L1_E_iw[7]);
--L1_E_pc[1] is std_1s10:inst|cpu:the_cpu|E_pc[1] at LC_X33_Y10_N1
--operation mode is normal
L1_E_pc[1] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[1], E1_data_out, L1_W_stall);
--L1L1104 is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[1]~305 at LC_X36_Y19_N1
--operation mode is normal
L1L1104 = AMPP_FUNCTION(L1L1061, L1L1059, L1L1060, L1L1058);
--L1L1109 is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[7]~307 at LC_X36_Y19_N5
--operation mode is normal
L1L1109 = AMPP_FUNCTION(L1L1061, L1L1059, L1L1060, L1L1058);
--L1L1105 is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[2]~309 at LC_X36_Y20_N2
--operation mode is normal
L1L1105 = AMPP_FUNCTION(L1L1061, L1L1058, L1L1060, L1L1059);
--L1L1107 is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[4]~311 at LC_X36_Y20_N7
--operation mode is normal
L1L1107 = AMPP_FUNCTION(L1L1061, L1L1058, L1L1060, L1L1059);
--L1L1103 is std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_nxt[0]~313 at LC_X36_Y20_N6
--operation mode is normal
L1L1103 = AMPP_FUNCTION(L1L1059, L1L1061, L1L1058, L1L1060);
--L1L847 is std_1s10:inst|cpu:the_cpu|Equal158~57 at LC_X36_Y20_N4
--operation mode is normal
L1L847 = AMPP_FUNCTION(L1L1061, L1L1058, L1L1060, L1L1059);
--L1L73 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12954 at LC_X28_Y21_N5
--operation mode is normal
L1L73 = AMPP_FUNCTION(L1_E_ctrl_jmp_direct, L1_E_extra_pc[0], L1L1365, L1_E_iw[6]);
--L1_E_pc[0] is std_1s10:inst|cpu:the_cpu|E_pc[0] at LC_X33_Y10_N7
--operation mode is normal
L1_E_pc[0] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[0], E1_data_out, L1_W_stall);
--AB1L10 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_granted_onchip_ram_64_kbytes_s1~84 at LC_X41_Y13_N5
--operation mode is normal
AB1L10 = AB1L11 & (!AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 # !AB1_onchip_ram_64_kbytes_s1_arb_addend[1] # !AB1L2);
--AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register at LC_X41_Y13_N5
--operation mode is normal
AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register = DFFEAS(AB1L10, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--N1L6 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_read_but_no_slave_selected~43 at LC_X41_Y13_N8
--operation mode is normal
N1L6 = !P1L9 & !GB1L25 & !AB1L10;
--Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0] at LC_X46_Y13_N3
--operation mode is normal
Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0]_lut_out = Q1L105;
Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0] = DFFEAS(Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0] at LC_X40_Y18_N8
--operation mode is normal
Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0]_lut_out = Q1L403 & Q1L117 & (Q1L6 # Q1L4);
Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0] = DFFEAS(Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0] at LC_X44_Y13_N3
--operation mode is normal
Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0]_lut_out = N1L146 & Q1L110 & (Q1L24 # Q1L21);
Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0] = DFFEAS(Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1_rd_valid[0] is std_1s10:inst|sdram:the_sdram|rd_valid[0] at LC_X35_Y2_N4
--operation mode is normal
FB1_rd_valid[0]_lut_out = FB1L223Q & (!FB1L227Q & !FB1L219Q);
FB1_rd_valid[0] = DFFEAS(FB1_rd_valid[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--GE1_stage_3 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_3 at LC_X44_Y9_N5
--operation mode is normal
GE1_stage_3_lut_out = GE1_full_4 & (GE1_stage_4) # !GE1_full_4 & (GB1L25);
GE1_stage_3 = DFFEAS(GE1_stage_3_lut_out, GLOBAL(DE1__clk0), VCC, , GE1L23, , , , );
--GE1_full_3 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_3 at LC_X45_Y9_N1
--operation mode is normal
GE1_full_3_lut_out = GB1L34 & (GE1_full_2) # !GB1L34 & (FB1_za_valid & GE1_full_4 # !FB1_za_valid & (GE1_full_2));
GE1_full_3 = DFFEAS(GE1_full_3_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FE1L13, , , , );
--GE1L24 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process8~1 at LC_X44_Y10_N2
--operation mode is normal
GE1L24 = FB1_za_valid # GB1L34 & !GE1_full_2;
--FE1_stage_3 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_3 at LC_X44_Y9_N9
--operation mode is normal
FE1_stage_3_lut_out = GE1_full_4 & FE1_stage_4 # !GE1_full_4 & (GB1L20);
FE1_stage_3 = DFFEAS(FE1_stage_3_lut_out, GLOBAL(DE1__clk0), VCC, , GE1L23, , , , );
--WB1_master_state[1] is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[1] at LC_X48_Y21_N1
--operation mode is normal
WB1_master_state[1]_lut_out = !WB1_master_state[2] & (WB1L10 # !WB1L3 & WB1L2);
WB1_master_state[1] = DFFEAS(WB1_master_state[1]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--WB1_master_state[2] is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[2] at LC_X50_Y20_N3
--operation mode is normal
WB1_master_state[2]_lut_out = !WB1_master_state[0] & !WB1L9 & (UB1_data_out $ XB4_data_in_d1);
WB1_master_state[2] = DFFEAS(WB1_master_state[2]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--WB1_master_state[0] is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state[0] at LC_X48_Y21_N9
--operation mode is normal
WB1_master_state[0]_lut_out = !WB1L11 & (WB1_master_state[1] # !WB1L12 & !WB1_master_state[0]);
WB1_master_state[0] = DFFEAS(WB1_master_state[0]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--D1_data_out is std_1s10:inst|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch|data_out at LC_X27_Y1_N2
--operation mode is normal
D1_data_out_lut_out = D1_data_in_d1;
D1_data_out = DFFEAS(D1_data_out_lut_out, GLOBAL(PLD_CLOCKINPUT), !GLOBAL(B1L1), , , , , , );
--WB1L2 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read_done~49 at LC_X48_Y21_N6
--operation mode is normal
WB1L2 = WB1_master_state[1] & WB1_master_state[0];
--CB1_d1_reasons_to_wait is std_1s10:inst|pll_s1_arbitrator:the_pll_s1|d1_reasons_to_wait at LC_X48_Y21_N2
--operation mode is normal
CB1_d1_reasons_to_wait_lut_out = !WB1L3;
CB1_d1_reasons_to_wait = DFFEAS(CB1_d1_reasons_to_wait_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--WB1L3 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|internal_master_read_done~50 at LC_X48_Y21_N0
--operation mode is normal
WB1L3 = CB1_d1_reasons_to_wait # !WB1_master_state[1];
--TC1_break_readreg[21] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[21] at LC_X32_Y26_N1
--operation mode is normal
TC1_break_readreg[21] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[21], DD1_internal_jdo1[36], DD1L188, DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L20 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19908 at LC_X31_Y27_N9
--operation mode is normal
DD1L20 = AMPP_FUNCTION(CD1_internal_MonDReg[21], TC1_break_readreg[21], DD1_ir[1]);
--DD1L21 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19909 at LC_X31_Y27_N5
--operation mode is normal
DD1L21 = AMPP_FUNCTION(DD1_ir[0], DD1L20, DD1L142, DD1L144);
--DD1_sr[23] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[23] at LC_X32_Y27_N1
--operation mode is normal
DD1_sr[23] = AMPP_FUNCTION(!A1L6, DD1L32, DD1L33, DD1_sr[24], DD1L9, !C1_CLR_SIGNAL, DD1L12);
--DD1L22 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19910 at LC_X31_Y27_N8
--operation mode is normal
DD1L22 = AMPP_FUNCTION(DD1L144, A1L5, DD1_ir[0], DD1L20);
--FB1L151 is std_1s10:inst|sdram:the_sdram|i_refs[2]~279 at LC_X40_Y4_N0
--operation mode is normal
FB1L151 = !FB1_i_state[2] & !FB1_i_state[0] & FB1_i_state[1] & E1_data_out;
--FB1L148 is std_1s10:inst|sdram:the_sdram|i_refs[0]~280 at LC_X40_Y4_N7
--operation mode is normal
FB1L148 = !FB1_i_state[2] & !FB1_i_state[0] & (E1_data_out);
--FB1L108 is std_1s10:inst|sdram:the_sdram|Add1~37 at LC_X40_Y4_N5
--operation mode is normal
FB1L108 = FB1_i_refs[0] & (FB1_i_refs[1]);
--T1_fifo_wr is std_1s10:inst|jtag_uart:the_jtag_uart|fifo_wr at LC_X50_Y14_N3
--operation mode is normal
T1_fifo_wr_lut_out = T1L70 & !WD1_b_full & !L1_M_alu_result[2];
T1_fifo_wr = DFFEAS(T1_fifo_wr_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--WD1_b_non_empty is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty at LC_X48_Y17_N9
--operation mode is normal
WD1_b_non_empty_lut_out = WD1_b_full # T1_fifo_wr # WD1_b_non_empty & WD1L7;
WD1_b_non_empty = DFFEAS(WD1_b_non_empty_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--QD1_r_ena1 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena1 at LC_X34_Y23_N4
--operation mode is normal
QD1_r_ena1 = AMPP_FUNCTION(DE1__clk0, QD1L19, E1_data_out);
--T1_rd_wfifo is std_1s10:inst|jtag_uart:the_jtag_uart|rd_wfifo at LC_X48_Y17_N5
--operation mode is normal
T1_r_val_qfbk = T1_r_val;
T1_rd_wfifo = !QD1_rvalid0 & WD1_b_non_empty & (!T1_r_val_qfbk # !QD1_r_ena1);
--T1_r_val is std_1s10:inst|jtag_uart:the_jtag_uart|r_val at LC_X48_Y17_N5
--operation mode is normal
T1_r_val = DFFEAS(T1_rd_wfifo, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--WD1L1 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|_~28 at LC_X52_Y17_N7
--operation mode is normal
WD1L1 = T1_fifo_wr $ T1_rd_wfifo;
--WD1L3 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_full~122 at LC_X50_Y17_N3
--operation mode is normal
WD1L3 = ZD1_safe_q[3] & ZD1_safe_q[0] & ZD1_safe_q[1] & ZD1_safe_q[2];
--WD1L4 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_full~123 at LC_X48_Y17_N2
--operation mode is normal
WD1L4 = ZD1_safe_q[4] & WD1_b_non_empty & ZD1_safe_q[5] & T1_fifo_wr;
--QD1L37Q is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_ena~reg0 at LC_X33_Y23_N3
--operation mode is normal
QD1L37Q = AMPP_FUNCTION(DE1__clk0, QD1_read_write2, QD1L38, QD1_read_write1, QD1L37Q, E1_data_out);
--T1_wr_rfifo is std_1s10:inst|jtag_uart:the_jtag_uart|wr_rfifo at LC_X51_Y15_N9
--operation mode is normal
T1_wr_rfifo = QD1L37Q & !WD2_b_full;
--T1L57 is std_1s10:inst|jtag_uart:the_jtag_uart|fifo_rd~32 at LC_X27_Y21_N4
--operation mode is normal
T1L57 = L1_internal_d_read & !L1_M_alu_result[2];
--T1L58 is std_1s10:inst|jtag_uart:the_jtag_uart|fifo_rd~33 at LC_X48_Y15_N9
--operation mode is normal
T1L58 = U1L2 & T1L69 & T1L57 & EB1L2;
--T1_read_0 is std_1s10:inst|jtag_uart:the_jtag_uart|read_0 at LC_X48_Y15_N9
--operation mode is normal
T1_read_0 = DFFEAS(T1L58, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--WD2L8 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~98 at LC_X51_Y15_N1
--operation mode is normal
WD2L8 = WD2_b_full # QD1L37Q & !WD2_b_non_empty;
--WD2L2 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|_~85 at LC_X50_Y15_N0
--operation mode is normal
WD2L2 = ZD2_safe_q[3] # ZD2_safe_q[5] # ZD2_safe_q[4] # ZD2_safe_q[1];
--WD2L3 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|_~86 at LC_X51_Y15_N8
--operation mode is normal
WD2L3 = T1_wr_rfifo # ZD2_safe_q[2] # WD2L2 # !ZD2_safe_q[0];
--QD1L38 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_pause~71 at LC_X33_Y23_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1L38 = AMPP_FUNCTION(QD1_write_stalled, T1_t_dav);
--QD1_write_valid is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|write_valid at LC_X33_Y23_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_write_valid = AMPP_FUNCTION(!A1L6, QD1_td_shift[10], !C1_CLR_SIGNAL, GND, QD1L72);
--QD1_read_write2 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write2 at LC_X33_Y23_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_read_write2 = AMPP_FUNCTION(DE1__clk0, QD1_read_write1, E1_data_out, GND);
--QD1L2 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|always2~2 at LC_X34_Y23_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1L2 = AMPP_FUNCTION(QD1_read_write2);
--QD1_read_write1 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write1 at LC_X34_Y23_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_read_write1 = AMPP_FUNCTION(DE1__clk0, QD1_read_write, E1_data_out, GND);
--QD1_jupdate1 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate1 at LC_X30_Y26_N8
--operation mode is normal
QD1_jupdate1 = AMPP_FUNCTION(DE1__clk0, QD1_jupdate, E1_data_out);
--QD1_jupdate2 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate2 at LC_X30_Y26_N2
--operation mode is normal
QD1_jupdate2 = AMPP_FUNCTION(DE1__clk0, QD1_jupdate1, E1_data_out);
--N1L31 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[8]~1864 at LC_X45_Y15_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[0]_qfbk = N1_dbs_latent_8_reg_segment_1[0];
N1L31 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_1[0]_qfbk & (BE1_q_a[8] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[8] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_1[0] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[0] at LC_X45_Y15_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[0] = DFFEAS(N1L31, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L155, Q1_internal_incoming_ext_ram_bus_data[0], , , VCC);
--N1L32 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[8]~1865 at LC_X46_Y13_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]_qfbk = Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
N1L32 = Q1_internal_incoming_ext_ram_bus_data[8] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1]_qfbk;
--Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] at LC_X46_Y13_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] = DFFEAS(N1L32, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[0], , , VCC);
--N1L33 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[8]~1866 at LC_X46_Y13_N6
--operation mode is normal
N1L33 = N1L32 & N1L31 & (FB1_za_data[8] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--L1L228 is std_1s10:inst|cpu:the_cpu|D_ctrl_exception~33 at LC_X19_Y7_N2
--operation mode is normal
L1L228 = AMPP_FUNCTION(L1_D_iw[15], L1_D_iw[13], L1_D_iw[16], L1_D_iw[14]);
--KB1_control_wr_strobe is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|control_wr_strobe at LC_X48_Y9_N2
--operation mode is normal
KB1_control_wr_strobe = LB1L3 & HE1L19 & KB1L7 & LB1L2;
--KB1_internal_counter[0] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[0] at LC_X51_Y4_N4
--operation mode is arithmetic
KB1_internal_counter[0]_lut_out = !KB1_internal_counter[0];
KB1_internal_counter[0] = DFFEAS(KB1_internal_counter[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[0], , , KB1L181);
--KB1L58 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[0]~7760 at LC_X51_Y4_N4
--operation mode is arithmetic
KB1L58 = CARRY(!KB1_internal_counter[0]);
--KB1_internal_counter[1] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[1] at LC_X51_Y4_N5
--operation mode is arithmetic
KB1_internal_counter[1]_carry_eqn = KB1L58;
KB1_internal_counter[1]_lut_out = KB1_internal_counter[1] $ !KB1_internal_counter[1]_carry_eqn;
KB1_internal_counter[1] = DFFEAS(KB1_internal_counter[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[1], , , KB1L181);
--KB1L60 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[1]~7761 at LC_X51_Y4_N5
--operation mode is arithmetic
KB1L60_cout_0 = KB1_internal_counter[1] & !KB1L58;
KB1L60 = CARRY(KB1L60_cout_0);
--KB1L61 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[1]~7761COUT1_7914 at LC_X51_Y4_N5
--operation mode is arithmetic
KB1L61_cout_1 = KB1_internal_counter[1] & !KB1L58;
KB1L61 = CARRY(KB1L61_cout_1);
--KB1_internal_counter[2] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[2] at LC_X51_Y4_N6
--operation mode is arithmetic
KB1_internal_counter[2]_carry_eqn = (!KB1L58 & KB1L60) # (KB1L58 & KB1L61);
KB1_internal_counter[2]_lut_out = KB1_internal_counter[2] $ KB1_internal_counter[2]_carry_eqn;
KB1_internal_counter[2] = DFFEAS(KB1_internal_counter[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[2], , , KB1L181);
--KB1L63 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[2]~7762 at LC_X51_Y4_N6
--operation mode is arithmetic
KB1L63_cout_0 = !KB1L60 # !KB1_internal_counter[2];
KB1L63 = CARRY(KB1L63_cout_0);
--KB1L64 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[2]~7762COUT1_7916 at LC_X51_Y4_N6
--operation mode is arithmetic
KB1L64_cout_1 = !KB1L61 # !KB1_internal_counter[2];
KB1L64 = CARRY(KB1L64_cout_1);
--KB1_internal_counter[3] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[3] at LC_X51_Y4_N7
--operation mode is arithmetic
KB1_internal_counter[3]_carry_eqn = (!KB1L58 & KB1L63) # (KB1L58 & KB1L64);
KB1_internal_counter[3]_lut_out = KB1_internal_counter[3] $ (!KB1_internal_counter[3]_carry_eqn);
KB1_internal_counter[3] = DFFEAS(KB1_internal_counter[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[3], , , KB1L181);
--KB1L66 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[3]~7763 at LC_X51_Y4_N7
--operation mode is arithmetic
KB1L66_cout_0 = KB1_internal_counter[3] & (!KB1L63);
KB1L66 = CARRY(KB1L66_cout_0);
--KB1L67 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[3]~7763COUT1_7918 at LC_X51_Y4_N7
--operation mode is arithmetic
KB1L67_cout_1 = KB1_internal_counter[3] & (!KB1L64);
KB1L67 = CARRY(KB1L67_cout_1);
--KB1L45 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~364 at LC_X52_Y2_N6
--operation mode is normal
KB1L45 = KB1_internal_counter[0] & KB1_internal_counter[2] & KB1_internal_counter[1] & KB1_internal_counter[3];
--KB1_internal_counter[4] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[4] at LC_X51_Y4_N8
--operation mode is arithmetic
KB1_internal_counter[4]_carry_eqn = (!KB1L58 & KB1L66) # (KB1L58 & KB1L67);
KB1_internal_counter[4]_lut_out = KB1_internal_counter[4] $ (KB1_internal_counter[4]_carry_eqn);
KB1_internal_counter[4] = DFFEAS(KB1_internal_counter[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[4], , , KB1L181);
--KB1L69 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[4]~7764 at LC_X51_Y4_N8
--operation mode is arithmetic
KB1L69_cout_0 = !KB1L66 # !KB1_internal_counter[4];
KB1L69 = CARRY(KB1L69_cout_0);
--KB1L70 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[4]~7764COUT1_7920 at LC_X51_Y4_N8
--operation mode is arithmetic
KB1L70_cout_1 = !KB1L67 # !KB1_internal_counter[4];
KB1L70 = CARRY(KB1L70_cout_1);
--KB1_internal_counter[5] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[5] at LC_X51_Y4_N9
--operation mode is arithmetic
KB1_internal_counter[5]_carry_eqn = (!KB1L58 & KB1L69) # (KB1L58 & KB1L70);
KB1_internal_counter[5]_lut_out = KB1_internal_counter[5] $ !KB1_internal_counter[5]_carry_eqn;
KB1_internal_counter[5] = DFFEAS(KB1_internal_counter[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[5], , , KB1L181);
--KB1L72 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[5]~7765 at LC_X51_Y4_N9
--operation mode is arithmetic
KB1L72 = CARRY(!KB1_internal_counter[5] & !KB1L70);
--KB1_internal_counter[6] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[6] at LC_X51_Y3_N0
--operation mode is arithmetic
KB1_internal_counter[6]_carry_eqn = KB1L72;
KB1_internal_counter[6]_lut_out = KB1_internal_counter[6] $ KB1_internal_counter[6]_carry_eqn;
KB1_internal_counter[6] = DFFEAS(KB1_internal_counter[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[6], , , KB1L181);
--KB1L74 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[6]~7766 at LC_X51_Y3_N0
--operation mode is arithmetic
KB1L74_cout_0 = KB1_internal_counter[6] # !KB1L72;
KB1L74 = CARRY(KB1L74_cout_0);
--KB1L75 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[6]~7766COUT1_7922 at LC_X51_Y3_N0
--operation mode is arithmetic
KB1L75_cout_1 = KB1_internal_counter[6] # !KB1L72;
KB1L75 = CARRY(KB1L75_cout_1);
--KB1_internal_counter[7] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[7] at LC_X51_Y3_N1
--operation mode is arithmetic
KB1_internal_counter[7]_carry_eqn = (!KB1L72 & KB1L74) # (KB1L72 & KB1L75);
KB1_internal_counter[7]_lut_out = KB1_internal_counter[7] $ !KB1_internal_counter[7]_carry_eqn;
KB1_internal_counter[7] = DFFEAS(KB1_internal_counter[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[7], , , KB1L181);
--KB1L77 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[7]~7767 at LC_X51_Y3_N1
--operation mode is arithmetic
KB1L77_cout_0 = !KB1_internal_counter[7] & !KB1L74;
KB1L77 = CARRY(KB1L77_cout_0);
--KB1L78 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[7]~7767COUT1_7924 at LC_X51_Y3_N1
--operation mode is arithmetic
KB1L78_cout_1 = !KB1_internal_counter[7] & !KB1L75;
KB1L78 = CARRY(KB1L78_cout_1);
--KB1L46 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~365 at LC_X52_Y3_N7
--operation mode is normal
KB1L46 = !KB1_internal_counter[6] & KB1_internal_counter[4] & !KB1_internal_counter[5] & !KB1_internal_counter[7];
--KB1_internal_counter[8] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[8] at LC_X51_Y3_N2
--operation mode is arithmetic
KB1_internal_counter[8]_carry_eqn = (!KB1L72 & KB1L77) # (KB1L72 & KB1L78);
KB1_internal_counter[8]_lut_out = KB1_internal_counter[8] $ (KB1_internal_counter[8]_carry_eqn);
KB1_internal_counter[8] = DFFEAS(KB1_internal_counter[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[8], , , KB1L181);
--KB1L80 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[8]~7768 at LC_X51_Y3_N2
--operation mode is arithmetic
KB1L80_cout_0 = !KB1L77 # !KB1_internal_counter[8];
KB1L80 = CARRY(KB1L80_cout_0);
--KB1L81 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[8]~7768COUT1_7926 at LC_X51_Y3_N2
--operation mode is arithmetic
KB1L81_cout_1 = !KB1L78 # !KB1_internal_counter[8];
KB1L81 = CARRY(KB1L81_cout_1);
--KB1_internal_counter[9] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[9] at LC_X51_Y3_N3
--operation mode is arithmetic
KB1_internal_counter[9]_carry_eqn = (!KB1L72 & KB1L80) # (KB1L72 & KB1L81);
KB1_internal_counter[9]_lut_out = KB1_internal_counter[9] $ (!KB1_internal_counter[9]_carry_eqn);
KB1_internal_counter[9] = DFFEAS(KB1_internal_counter[9]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[9], , , KB1L181);
--KB1L83 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[9]~7769 at LC_X51_Y3_N3
--operation mode is arithmetic
KB1L83_cout_0 = !KB1_internal_counter[9] & (!KB1L80);
KB1L83 = CARRY(KB1L83_cout_0);
--KB1L84 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[9]~7769COUT1_7928 at LC_X51_Y3_N3
--operation mode is arithmetic
KB1L84_cout_1 = !KB1_internal_counter[9] & (!KB1L81);
KB1L84 = CARRY(KB1L84_cout_1);
--KB1_internal_counter[10] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[10] at LC_X51_Y3_N4
--operation mode is arithmetic
KB1_internal_counter[10]_carry_eqn = (!KB1L72 & KB1L83) # (KB1L72 & KB1L84);
KB1_internal_counter[10]_lut_out = KB1_internal_counter[10] $ (KB1_internal_counter[10]_carry_eqn);
KB1_internal_counter[10] = DFFEAS(KB1_internal_counter[10]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[10], , , KB1L181);
--KB1L86 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[10]~7770 at LC_X51_Y3_N4
--operation mode is arithmetic
KB1L86 = CARRY(KB1_internal_counter[10] # !KB1L84);
--KB1_internal_counter[11] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[11] at LC_X51_Y3_N5
--operation mode is arithmetic
KB1_internal_counter[11]_carry_eqn = KB1L86;
KB1_internal_counter[11]_lut_out = KB1_internal_counter[11] $ !KB1_internal_counter[11]_carry_eqn;
KB1_internal_counter[11] = DFFEAS(KB1_internal_counter[11]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[11], , , KB1L181);
--KB1L88 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[11]~7771 at LC_X51_Y3_N5
--operation mode is arithmetic
KB1L88_cout_0 = !KB1_internal_counter[11] & !KB1L86;
KB1L88 = CARRY(KB1L88_cout_0);
--KB1L89 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[11]~7771COUT1_7930 at LC_X51_Y3_N5
--operation mode is arithmetic
KB1L89_cout_1 = !KB1_internal_counter[11] & !KB1L86;
KB1L89 = CARRY(KB1L89_cout_1);
--KB1L47 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~366 at LC_X50_Y3_N2
--operation mode is normal
KB1L47 = !KB1_internal_counter[9] & KB1_internal_counter[8] & !KB1_internal_counter[10] & !KB1_internal_counter[11];
--KB1_internal_counter[13] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[13] at LC_X51_Y3_N7
--operation mode is arithmetic
KB1_internal_counter[13]_carry_eqn = (!KB1L86 & KB1L91) # (KB1L86 & KB1L92);
KB1_internal_counter[13]_lut_out = KB1_internal_counter[13] $ (!KB1_internal_counter[13]_carry_eqn);
KB1_internal_counter[13] = DFFEAS(KB1_internal_counter[13]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[13], , , KB1L181);
--KB1L94 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[13]~7772 at LC_X51_Y3_N7
--operation mode is arithmetic
KB1L94_cout_0 = KB1_internal_counter[13] & (!KB1L91);
KB1L94 = CARRY(KB1L94_cout_0);
--KB1L95 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[13]~7772COUT1_7934 at LC_X51_Y3_N7
--operation mode is arithmetic
KB1L95_cout_1 = KB1_internal_counter[13] & (!KB1L92);
KB1L95 = CARRY(KB1L95_cout_1);
--KB1_internal_counter[15] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[15] at LC_X51_Y3_N9
--operation mode is arithmetic
KB1_internal_counter[15]_carry_eqn = (!KB1L86 & KB1L97) # (KB1L86 & KB1L98);
KB1_internal_counter[15]_lut_out = KB1_internal_counter[15] $ !KB1_internal_counter[15]_carry_eqn;
KB1_internal_counter[15] = DFFEAS(KB1_internal_counter[15]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[15], , , KB1L181);
--KB1L100 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[15]~7773 at LC_X51_Y3_N9
--operation mode is arithmetic
KB1L100 = CARRY(KB1_internal_counter[15] & !KB1L98);
--KB1_internal_counter[12] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[12] at LC_X51_Y3_N6
--operation mode is arithmetic
KB1_internal_counter[12]_carry_eqn = (!KB1L86 & KB1L88) # (KB1L86 & KB1L89);
KB1_internal_counter[12]_lut_out = KB1_internal_counter[12] $ KB1_internal_counter[12]_carry_eqn;
KB1_internal_counter[12] = DFFEAS(KB1_internal_counter[12]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[12], , , KB1L181);
--KB1L91 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[12]~7774 at LC_X51_Y3_N6
--operation mode is arithmetic
KB1L91_cout_0 = KB1_internal_counter[12] # !KB1L88;
KB1L91 = CARRY(KB1L91_cout_0);
--KB1L92 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[12]~7774COUT1_7932 at LC_X51_Y3_N6
--operation mode is arithmetic
KB1L92_cout_1 = KB1_internal_counter[12] # !KB1L89;
KB1L92 = CARRY(KB1L92_cout_1);
--KB1_internal_counter[14] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[14] at LC_X51_Y3_N8
--operation mode is arithmetic
KB1_internal_counter[14]_carry_eqn = (!KB1L86 & KB1L94) # (KB1L86 & KB1L95);
KB1_internal_counter[14]_lut_out = KB1_internal_counter[14] $ (KB1_internal_counter[14]_carry_eqn);
KB1_internal_counter[14] = DFFEAS(KB1_internal_counter[14]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_l_register[14], , , KB1L181);
--KB1L97 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[14]~7775 at LC_X51_Y3_N8
--operation mode is arithmetic
KB1L97_cout_0 = KB1_internal_counter[14] # !KB1L94;
KB1L97 = CARRY(KB1L97_cout_0);
--KB1L98 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[14]~7775COUT1_7936 at LC_X51_Y3_N8
--operation mode is arithmetic
KB1L98_cout_1 = KB1_internal_counter[14] # !KB1L95;
KB1L98 = CARRY(KB1L98_cout_1);
--KB1L48 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~367 at LC_X50_Y3_N6
--operation mode is normal
KB1L48 = KB1_internal_counter[13] & !KB1_internal_counter[12] & !KB1_internal_counter[14] & KB1_internal_counter[15];
--KB1L49 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~368 at LC_X50_Y3_N9
--operation mode is normal
KB1L49 = KB1L47 & KB1L46 & KB1L45 & KB1L48;
--KB1_internal_counter[16] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[16] at LC_X51_Y2_N0
--operation mode is arithmetic
KB1_internal_counter[16]_carry_eqn = KB1L100;
KB1_internal_counter[16]_lut_out = KB1_internal_counter[16] $ KB1_internal_counter[16]_carry_eqn;
KB1_internal_counter[16] = DFFEAS(KB1_internal_counter[16]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[0], , , KB1L181);
--KB1L102 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[16]~7776 at LC_X51_Y2_N0
--operation mode is arithmetic
KB1L102_cout_0 = !KB1L100 # !KB1_internal_counter[16];
KB1L102 = CARRY(KB1L102_cout_0);
--KB1L103 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[16]~7776COUT1_7938 at LC_X51_Y2_N0
--operation mode is arithmetic
KB1L103_cout_1 = !KB1L100 # !KB1_internal_counter[16];
KB1L103 = CARRY(KB1L103_cout_1);
--KB1_internal_counter[17] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[17] at LC_X51_Y2_N1
--operation mode is arithmetic
KB1_internal_counter[17]_carry_eqn = (!KB1L100 & KB1L102) # (KB1L100 & KB1L103);
KB1_internal_counter[17]_lut_out = KB1_internal_counter[17] $ !KB1_internal_counter[17]_carry_eqn;
KB1_internal_counter[17] = DFFEAS(KB1_internal_counter[17]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[1], , , KB1L181);
--KB1L105 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[17]~7777 at LC_X51_Y2_N1
--operation mode is arithmetic
KB1L105_cout_0 = KB1_internal_counter[17] & !KB1L102;
KB1L105 = CARRY(KB1L105_cout_0);
--KB1L106 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[17]~7777COUT1_7940 at LC_X51_Y2_N1
--operation mode is arithmetic
KB1L106_cout_1 = KB1_internal_counter[17] & !KB1L103;
KB1L106 = CARRY(KB1L106_cout_1);
--KB1_internal_counter[18] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[18] at LC_X51_Y2_N2
--operation mode is arithmetic
KB1_internal_counter[18]_carry_eqn = (!KB1L100 & KB1L105) # (KB1L100 & KB1L106);
KB1_internal_counter[18]_lut_out = KB1_internal_counter[18] $ (KB1_internal_counter[18]_carry_eqn);
KB1_internal_counter[18] = DFFEAS(KB1_internal_counter[18]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[2], , , KB1L181);
--KB1L108 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[18]~7778 at LC_X51_Y2_N2
--operation mode is arithmetic
KB1L108_cout_0 = !KB1L105 # !KB1_internal_counter[18];
KB1L108 = CARRY(KB1L108_cout_0);
--KB1L109 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[18]~7778COUT1_7942 at LC_X51_Y2_N2
--operation mode is arithmetic
KB1L109_cout_1 = !KB1L106 # !KB1_internal_counter[18];
KB1L109 = CARRY(KB1L109_cout_1);
--KB1_internal_counter[19] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[19] at LC_X51_Y2_N3
--operation mode is arithmetic
KB1_internal_counter[19]_carry_eqn = (!KB1L100 & KB1L108) # (KB1L100 & KB1L109);
KB1_internal_counter[19]_lut_out = KB1_internal_counter[19] $ (!KB1_internal_counter[19]_carry_eqn);
KB1_internal_counter[19] = DFFEAS(KB1_internal_counter[19]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[3], , , KB1L181);
--KB1L111 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[19]~7779 at LC_X51_Y2_N3
--operation mode is arithmetic
KB1L111_cout_0 = !KB1_internal_counter[19] & (!KB1L108);
KB1L111 = CARRY(KB1L111_cout_0);
--KB1L112 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[19]~7779COUT1_7944 at LC_X51_Y2_N3
--operation mode is arithmetic
KB1L112_cout_1 = !KB1_internal_counter[19] & (!KB1L109);
KB1L112 = CARRY(KB1L112_cout_1);
--KB1L50 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~369 at LC_X50_Y2_N9
--operation mode is normal
KB1L50 = KB1_internal_counter[17] & KB1_internal_counter[18] & KB1_internal_counter[16] & !KB1_internal_counter[19];
--KB1_internal_counter[20] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[20] at LC_X51_Y2_N4
--operation mode is arithmetic
KB1_internal_counter[20]_carry_eqn = (!KB1L100 & KB1L111) # (KB1L100 & KB1L112);
KB1_internal_counter[20]_lut_out = KB1_internal_counter[20] $ (KB1_internal_counter[20]_carry_eqn);
KB1_internal_counter[20] = DFFEAS(KB1_internal_counter[20]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[4], , , KB1L181);
--KB1L114 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[20]~7780 at LC_X51_Y2_N4
--operation mode is arithmetic
KB1L114 = CARRY(KB1_internal_counter[20] # !KB1L112);
--KB1_internal_counter[21] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[21] at LC_X51_Y2_N5
--operation mode is arithmetic
KB1_internal_counter[21]_carry_eqn = KB1L114;
KB1_internal_counter[21]_lut_out = KB1_internal_counter[21] $ !KB1_internal_counter[21]_carry_eqn;
KB1_internal_counter[21] = DFFEAS(KB1_internal_counter[21]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[5], , , KB1L181);
--KB1L116 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[21]~7781 at LC_X51_Y2_N5
--operation mode is arithmetic
KB1L116_cout_0 = !KB1_internal_counter[21] & !KB1L114;
KB1L116 = CARRY(KB1L116_cout_0);
--KB1L117 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[21]~7781COUT1_7946 at LC_X51_Y2_N5
--operation mode is arithmetic
KB1L117_cout_1 = !KB1_internal_counter[21] & !KB1L114;
KB1L117 = CARRY(KB1L117_cout_1);
--KB1_internal_counter[22] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[22] at LC_X51_Y2_N6
--operation mode is arithmetic
KB1_internal_counter[22]_carry_eqn = (!KB1L114 & KB1L116) # (KB1L114 & KB1L117);
KB1_internal_counter[22]_lut_out = KB1_internal_counter[22] $ KB1_internal_counter[22]_carry_eqn;
KB1_internal_counter[22] = DFFEAS(KB1_internal_counter[22]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[6], , , KB1L181);
--KB1L119 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[22]~7782 at LC_X51_Y2_N6
--operation mode is arithmetic
KB1L119_cout_0 = KB1_internal_counter[22] # !KB1L116;
KB1L119 = CARRY(KB1L119_cout_0);
--KB1L120 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[22]~7782COUT1_7948 at LC_X51_Y2_N6
--operation mode is arithmetic
KB1L120_cout_1 = KB1_internal_counter[22] # !KB1L117;
KB1L120 = CARRY(KB1L120_cout_1);
--KB1_internal_counter[23] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[23] at LC_X51_Y2_N7
--operation mode is arithmetic
KB1_internal_counter[23]_carry_eqn = (!KB1L114 & KB1L119) # (KB1L114 & KB1L120);
KB1_internal_counter[23]_lut_out = KB1_internal_counter[23] $ (!KB1_internal_counter[23]_carry_eqn);
KB1_internal_counter[23] = DFFEAS(KB1_internal_counter[23]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[7], , , KB1L181);
--KB1L122 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[23]~7783 at LC_X51_Y2_N7
--operation mode is arithmetic
KB1L122_cout_0 = !KB1_internal_counter[23] & (!KB1L119);
KB1L122 = CARRY(KB1L122_cout_0);
--KB1L123 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[23]~7783COUT1_7950 at LC_X51_Y2_N7
--operation mode is arithmetic
KB1L123_cout_1 = !KB1_internal_counter[23] & (!KB1L120);
KB1L123 = CARRY(KB1L123_cout_1);
--KB1L51 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~370 at LC_X52_Y2_N5
--operation mode is normal
KB1L51 = !KB1_internal_counter[23] & !KB1_internal_counter[20] & !KB1_internal_counter[22] & !KB1_internal_counter[21];
--KB1_internal_counter[24] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[24] at LC_X51_Y2_N8
--operation mode is arithmetic
KB1_internal_counter[24]_carry_eqn = (!KB1L114 & KB1L122) # (KB1L114 & KB1L123);
KB1_internal_counter[24]_lut_out = KB1_internal_counter[24] $ (KB1_internal_counter[24]_carry_eqn);
KB1_internal_counter[24] = DFFEAS(KB1_internal_counter[24]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[8], , , KB1L181);
--KB1L125 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[24]~7784 at LC_X51_Y2_N8
--operation mode is arithmetic
KB1L125_cout_0 = KB1_internal_counter[24] # !KB1L122;
KB1L125 = CARRY(KB1L125_cout_0);
--KB1L126 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[24]~7784COUT1_7952 at LC_X51_Y2_N8
--operation mode is arithmetic
KB1L126_cout_1 = KB1_internal_counter[24] # !KB1L123;
KB1L126 = CARRY(KB1L126_cout_1);
--KB1_internal_counter[25] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[25] at LC_X51_Y2_N9
--operation mode is arithmetic
KB1_internal_counter[25]_carry_eqn = (!KB1L114 & KB1L125) # (KB1L114 & KB1L126);
KB1_internal_counter[25]_lut_out = KB1_internal_counter[25] $ !KB1_internal_counter[25]_carry_eqn;
KB1_internal_counter[25] = DFFEAS(KB1_internal_counter[25]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[9], , , KB1L181);
--KB1L128 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[25]~7785 at LC_X51_Y2_N9
--operation mode is arithmetic
KB1L128 = CARRY(!KB1_internal_counter[25] & !KB1L126);
--KB1_internal_counter[26] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[26] at LC_X51_Y1_N0
--operation mode is arithmetic
KB1_internal_counter[26]_carry_eqn = KB1L128;
KB1_internal_counter[26]_lut_out = KB1_internal_counter[26] $ KB1_internal_counter[26]_carry_eqn;
KB1_internal_counter[26] = DFFEAS(KB1_internal_counter[26]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[10], , , KB1L181);
--KB1L130 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[26]~7786 at LC_X51_Y1_N0
--operation mode is arithmetic
KB1L130_cout_0 = KB1_internal_counter[26] # !KB1L128;
KB1L130 = CARRY(KB1L130_cout_0);
--KB1L131 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[26]~7786COUT1_7954 at LC_X51_Y1_N0
--operation mode is arithmetic
KB1L131_cout_1 = KB1_internal_counter[26] # !KB1L128;
KB1L131 = CARRY(KB1L131_cout_1);
--KB1_internal_counter[27] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[27] at LC_X51_Y1_N1
--operation mode is arithmetic
KB1_internal_counter[27]_carry_eqn = (!KB1L128 & KB1L130) # (KB1L128 & KB1L131);
KB1_internal_counter[27]_lut_out = KB1_internal_counter[27] $ !KB1_internal_counter[27]_carry_eqn;
KB1_internal_counter[27] = DFFEAS(KB1_internal_counter[27]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[11], , , KB1L181);
--KB1L133 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[27]~7787 at LC_X51_Y1_N1
--operation mode is arithmetic
KB1L133_cout_0 = !KB1_internal_counter[27] & !KB1L130;
KB1L133 = CARRY(KB1L133_cout_0);
--KB1L134 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[27]~7787COUT1_7956 at LC_X51_Y1_N1
--operation mode is arithmetic
KB1L134_cout_1 = !KB1_internal_counter[27] & !KB1L131;
KB1L134 = CARRY(KB1L134_cout_1);
--KB1L52 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~371 at LC_X50_Y2_N0
--operation mode is normal
KB1L52 = !KB1_internal_counter[26] & !KB1_internal_counter[27] & !KB1_internal_counter[24] & !KB1_internal_counter[25];
--KB1_internal_counter[28] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[28] at LC_X51_Y1_N2
--operation mode is arithmetic
KB1_internal_counter[28]_carry_eqn = (!KB1L128 & KB1L133) # (KB1L128 & KB1L134);
KB1_internal_counter[28]_lut_out = KB1_internal_counter[28] $ (KB1_internal_counter[28]_carry_eqn);
KB1_internal_counter[28] = DFFEAS(KB1_internal_counter[28]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[12], , , KB1L181);
--KB1L136 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[28]~7788 at LC_X51_Y1_N2
--operation mode is arithmetic
KB1L136_cout_0 = KB1_internal_counter[28] # !KB1L133;
KB1L136 = CARRY(KB1L136_cout_0);
--KB1L137 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[28]~7788COUT1_7958 at LC_X51_Y1_N2
--operation mode is arithmetic
KB1L137_cout_1 = KB1_internal_counter[28] # !KB1L134;
KB1L137 = CARRY(KB1L137_cout_1);
--KB1_internal_counter[29] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[29] at LC_X51_Y1_N3
--operation mode is arithmetic
KB1_internal_counter[29]_carry_eqn = (!KB1L128 & KB1L136) # (KB1L128 & KB1L137);
KB1_internal_counter[29]_lut_out = KB1_internal_counter[29] $ (!KB1_internal_counter[29]_carry_eqn);
KB1_internal_counter[29] = DFFEAS(KB1_internal_counter[29]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[13], , , KB1L181);
--KB1L139 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[29]~7789 at LC_X51_Y1_N3
--operation mode is arithmetic
KB1L139_cout_0 = !KB1_internal_counter[29] & (!KB1L136);
KB1L139 = CARRY(KB1L139_cout_0);
--KB1L140 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[29]~7789COUT1_7960 at LC_X51_Y1_N3
--operation mode is arithmetic
KB1L140_cout_1 = !KB1_internal_counter[29] & (!KB1L137);
KB1L140 = CARRY(KB1L140_cout_1);
--KB1_internal_counter[30] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[30] at LC_X51_Y1_N4
--operation mode is arithmetic
KB1_internal_counter[30]_carry_eqn = (!KB1L128 & KB1L139) # (KB1L128 & KB1L140);
KB1_internal_counter[30]_lut_out = KB1_internal_counter[30] $ (KB1_internal_counter[30]_carry_eqn);
KB1_internal_counter[30] = DFFEAS(KB1_internal_counter[30]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[14], , , KB1L181);
--KB1L142 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[30]~7790 at LC_X51_Y1_N4
--operation mode is arithmetic
KB1L142 = CARRY(KB1_internal_counter[30] # !KB1L140);
--KB1_internal_counter[31] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|internal_counter[31] at LC_X51_Y1_N5
--operation mode is normal
KB1_internal_counter[31]_carry_eqn = KB1L142;
KB1_internal_counter[31]_lut_out = KB1_internal_counter[31] $ !KB1_internal_counter[31]_carry_eqn;
KB1_internal_counter[31] = DFFEAS(KB1_internal_counter[31]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L180, KB1_period_h_register[15], , , KB1L181);
--KB1L53 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~372 at LC_X50_Y2_N7
--operation mode is normal
KB1L53 = !KB1_internal_counter[31] & !KB1_internal_counter[30] & !KB1_internal_counter[29] & !KB1_internal_counter[28];
--KB1L54 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|Equal0~373 at LC_X50_Y2_N8
--operation mode is normal
KB1L54 = KB1L51 & KB1L52 & KB1L53 & KB1L50;
--KB1_delayed_unxcounter_is_zeroxx0 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|delayed_unxcounter_is_zeroxx0 at LC_X50_Y6_N3
--operation mode is normal
KB1_delayed_unxcounter_is_zeroxx0_lut_out = KB1L49 & (KB1L54);
KB1_delayed_unxcounter_is_zeroxx0 = DFFEAS(KB1_delayed_unxcounter_is_zeroxx0_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--KB1L235 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|timeout_occurred~37 at LC_X50_Y6_N4
--operation mode is normal
KB1L235 = KB1_timeout_occurred # KB1L54 & !KB1_delayed_unxcounter_is_zeroxx0 & KB1L49;
--N1L28 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[7]~1868 at LC_X45_Y12_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[7]_qfbk = N1_dbs_latent_8_reg_segment_0[7];
N1L28 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_0[7]_qfbk & (BE1_q_a[7] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[7] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_0[7] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[7] at LC_X45_Y12_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[7] = DFFEAS(N1L28, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L154, Q1_internal_incoming_ext_ram_bus_data[7], , , VCC);
--N1L29 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[7]~1869 at LC_X45_Y19_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]_qfbk = Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
N1L29 = Q1_internal_incoming_ext_ram_bus_data[7] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]_qfbk & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] at LC_X45_Y19_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] = DFFEAS(N1L29, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[0], , , VCC);
--N1L30 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[7]~1870 at LC_X48_Y18_N9
--operation mode is normal
N1L30 = N1L29 & N1L28 & (FB1_za_data[7] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L25 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[6]~1872 at LC_X45_Y12_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[6]_qfbk = N1_dbs_latent_8_reg_segment_0[6];
N1L25 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_0[6]_qfbk & (BE1_q_a[6] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[6] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_0[6] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[6] at LC_X45_Y12_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[6] = DFFEAS(N1L25, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L154, Q1_internal_incoming_ext_ram_bus_data[6], , , VCC);
--N1L26 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[6]~1873 at LC_X47_Y11_N3
--operation mode is normal
N1L26 = Q1_internal_incoming_ext_ram_bus_data[6] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L27 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[6]~1874 at LC_X47_Y11_N6
--operation mode is normal
N1L27 = N1L26 & N1L25 & (FB1_za_data[6] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L19 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[4]~1876 at LC_X45_Y12_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[4]_qfbk = N1_dbs_latent_8_reg_segment_0[4];
N1L19 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_0[4]_qfbk & (BE1_q_a[4] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[4] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_0[4] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[4] at LC_X45_Y12_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[4] = DFFEAS(N1L19, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L154, Q1_internal_incoming_ext_ram_bus_data[4], , , VCC);
--N1L20 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[4]~1877 at LC_X47_Y18_N8
--operation mode is normal
N1L20 = Q1_internal_incoming_ext_ram_bus_data[4] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L21 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[4]~1878 at LC_X47_Y18_N2
--operation mode is normal
N1L21 = N1L20 & N1L19 & (FB1_za_data[4] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L52 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~1880 at LC_X45_Y12_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[7]_qfbk = N1_dbs_latent_8_reg_segment_1[7];
N1L52 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_1[7]_qfbk & (BE1_q_a[15] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[15] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_1[7] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[7] at LC_X45_Y12_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[7] = DFFEAS(N1L52, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L155, Q1_internal_incoming_ext_ram_bus_data[7], , , VCC);
--N1L53 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~1881 at LC_X45_Y13_N7
--operation mode is normal
N1L53 = Q1_internal_incoming_ext_ram_bus_data[15] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L54 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[15]~1882 at LC_X45_Y13_N8
--operation mode is normal
N1L54 = N1L53 & N1L52 & (FB1_za_data[15] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L22 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[5]~1884 at LC_X45_Y12_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[5]_qfbk = N1_dbs_latent_8_reg_segment_0[5];
N1L22 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_0[5]_qfbk & (BE1_q_a[5] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[5] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_0[5] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[5] at LC_X45_Y12_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[5] = DFFEAS(N1L22, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L154, Q1_internal_incoming_ext_ram_bus_data[5], , , VCC);
--N1L23 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[5]~1885 at LC_X46_Y17_N2
--operation mode is normal
N1L23 = Q1_internal_incoming_ext_ram_bus_data[5] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L24 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[5]~1886 at LC_X48_Y15_N8
--operation mode is normal
N1L24 = N1L23 & N1L22 & (FB1_za_data[5] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L7 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[0]~1888 at LC_X46_Y15_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[0]_qfbk = N1_dbs_latent_8_reg_segment_0[0];
N1L7 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_0[0]_qfbk & (BE1_q_a[0] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[0] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_0[0] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[0] at LC_X46_Y15_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[0] = DFFEAS(N1L7, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L154, Q1_internal_incoming_ext_ram_bus_data[0], , , VCC);
--N1L8 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[0]~1889 at LC_X41_Y19_N7
--operation mode is normal
N1L8 = Q1_internal_incoming_ext_ram_bus_data[0] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L9 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[0]~1890 at LC_X40_Y20_N4
--operation mode is normal
N1L9 = N1L7 & N1L8 & (FB1_za_data[0] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L10 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[1]~1892 at LC_X45_Y15_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[1]_qfbk = N1_dbs_latent_8_reg_segment_0[1];
N1L10 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_0[1]_qfbk & (BE1_q_a[1] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[1] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_0[1] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[1] at LC_X45_Y15_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[1] = DFFEAS(N1L10, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L154, Q1_internal_incoming_ext_ram_bus_data[1], , , VCC);
--N1L11 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[1]~1893 at LC_X45_Y20_N8
--operation mode is normal
N1L11 = Q1_internal_incoming_ext_ram_bus_data[1] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L12 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[1]~1894 at LC_X45_Y20_N3
--operation mode is normal
N1L12 = N1L11 & N1L10 & (FB1_za_data[1] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L13 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[2]~1896 at LC_X46_Y12_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[2]_qfbk = N1_dbs_latent_8_reg_segment_0[2];
N1L13 = AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & BE1_q_a[2] & (N1_dbs_latent_8_reg_segment_0[2]_qfbk # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_0[2]_qfbk # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1_dbs_latent_8_reg_segment_0[2] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[2] at LC_X46_Y12_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[2] = DFFEAS(N1L13, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L154, Q1_internal_incoming_ext_ram_bus_data[2], , , VCC);
--N1L14 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[2]~1897 at LC_X41_Y20_N5
--operation mode is normal
N1L14 = Q1_internal_incoming_ext_ram_bus_data[2] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L15 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[2]~1898 at LC_X46_Y12_N4
--operation mode is normal
N1L15 = N1L14 & N1L13 & (FB1_za_data[2] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L16 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[3]~1900 at LC_X45_Y15_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[3]_qfbk = N1_dbs_latent_8_reg_segment_0[3];
N1L16 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_0[3]_qfbk & (BE1_q_a[3] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[3] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_0[3] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_0[3] at LC_X45_Y15_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_0[3] = DFFEAS(N1L16, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L154, Q1_internal_incoming_ext_ram_bus_data[3], , , VCC);
--N1L17 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[3]~1901 at LC_X41_Y14_N4
--operation mode is normal
N1L17 = Q1_internal_incoming_ext_ram_bus_data[3] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L18 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[3]~1902 at LC_X45_Y15_N1
--operation mode is normal
N1L18 = N1L16 & N1L17 & (FB1_za_data[3] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L88 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[27]~1904 at LC_X41_Y14_N9
--operation mode is normal
N1L88 = Q1_internal_incoming_ext_ram_bus_data[3] & (BE1_q_a[27] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_internal_incoming_ext_ram_bus_data[3] & !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[27] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1L89 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[27]~1905 at LC_X41_Y14_N2
--operation mode is normal
N1L89 = Q1_internal_incoming_ext_ram_bus_data[27] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L90 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[27]~1906 at LC_X41_Y14_N6
--operation mode is normal
N1L90 = N1L89 & N1L88 & (FB1_za_data[27] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L91 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[28]~1908 at LC_X44_Y20_N6
--operation mode is normal
N1L91 = AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & BE1_q_a[28] & (Q1_internal_incoming_ext_ram_bus_data[4] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (Q1_internal_incoming_ext_ram_bus_data[4] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1L92 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[28]~1909 at LC_X44_Y18_N4
--operation mode is normal
N1L92 = Q1_internal_incoming_ext_ram_bus_data[28] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L93 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[28]~1910 at LC_X44_Y18_N2
--operation mode is normal
N1L93 = N1L92 & N1L91 & (FB1_za_data[28] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L94 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[29]~1912 at LC_X44_Y13_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]_qfbk = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1];
N1L94 = BE1_q_a[29] & (Q1_internal_incoming_ext_ram_bus_data[5] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]_qfbk) # !BE1_q_a[29] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (Q1_internal_incoming_ext_ram_bus_data[5] # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]_qfbk);
--Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] at LC_X44_Y13_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] = DFFEAS(N1L94, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[0], , , VCC);
--N1L95 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[29]~1913 at LC_X44_Y13_N5
--operation mode is normal
N1L95 = Q1_internal_incoming_ext_ram_bus_data[29] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L96 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[29]~1914 at LC_X44_Y13_N2
--operation mode is normal
N1L96 = N1L95 & N1L94 & (FB1_za_data[29] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L97 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[30]~1916 at LC_X44_Y13_N6
--operation mode is normal
N1L97 = Q1_internal_incoming_ext_ram_bus_data[6] & (BE1_q_a[30] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_internal_incoming_ext_ram_bus_data[6] & !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[30] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1L98 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[30]~1917 at LC_X48_Y18_N1
--operation mode is normal
N1L98 = Q1_internal_incoming_ext_ram_bus_data[30] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L99 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[30]~1918 at LC_X48_Y18_N2
--operation mode is normal
N1L99 = N1L98 & N1L97 & (FB1_za_data[30] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L100 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[31]~1920 at LC_X45_Y12_N3
--operation mode is normal
N1L100 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & Q1_internal_incoming_ext_ram_bus_data[7] & (BE1_q_a[31] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[31] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1L101 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[31]~1921 at LC_X44_Y16_N1
--operation mode is normal
N1L101 = Q1_internal_incoming_ext_ram_bus_data[31] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L102 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[31]~1922 at LC_X44_Y19_N2
--operation mode is normal
N1L102 = N1L101 & N1L100 & (FB1_za_data[31] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--L1L1279 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[26]~1371 at LC_X13_Y14_N7
--operation mode is normal
L1L1279 = AMPP_FUNCTION(QC1_result[58], QC1_result[26]);
--HC1_result[26] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[26] at LC_X18_Y10_N6
--operation mode is arithmetic
HC1_result[26] = AMPP_FUNCTION(L1L695, L1L629, HC1L71, HC1L73, HC1L74, L1_E_ctrl_alu_subtract);
--HC1L76 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[26]~COUT at LC_X18_Y10_N6
--operation mode is arithmetic
HC1L76 = AMPP_FUNCTION(L1L695, L1L629, HC1L73, L1_E_ctrl_alu_subtract);
--HC1L77 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[26]~COUTCOUT1_189 at LC_X18_Y10_N6
--operation mode is arithmetic
HC1L77 = AMPP_FUNCTION(L1L695, L1L629, HC1L74, L1_E_ctrl_alu_subtract);
--L1L74 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12955 at LC_X19_Y13_N8
--operation mode is normal
L1L74 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[26]);
--L1L558 is std_1s10:inst|cpu:the_cpu|E_logic_result[26]~16137 at LC_X14_Y10_N8
--operation mode is normal
L1L558 = AMPP_FUNCTION(L1_E_logic_op[0], L1_E_logic_op[1], L1L629, L1L695);
--L1L1280 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[27]~1372 at LC_X12_Y15_N7
--operation mode is normal
L1L1280 = AMPP_FUNCTION(QC1_result[59], QC1_result[27]);
--HC1_result[27] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[27] at LC_X18_Y10_N7
--operation mode is arithmetic
HC1_result[27] = AMPP_FUNCTION(L1L696, L1L630, HC1L71, HC1L76, HC1L77, L1_E_ctrl_alu_subtract);
--HC1L79 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[27]~COUT at LC_X18_Y10_N7
--operation mode is arithmetic
HC1L79 = AMPP_FUNCTION(L1L696, L1L630, HC1L76, L1_E_ctrl_alu_subtract);
--HC1L80 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[27]~COUTCOUT1_191 at LC_X18_Y10_N7
--operation mode is arithmetic
HC1L80 = AMPP_FUNCTION(L1L696, L1L630, HC1L77, L1_E_ctrl_alu_subtract);
--L1L75 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12956 at LC_X18_Y7_N7
--operation mode is normal
L1L75 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[27]);
--L1L559 is std_1s10:inst|cpu:the_cpu|E_logic_result[27]~16138 at LC_X14_Y10_N9
--operation mode is normal
L1L559 = AMPP_FUNCTION(L1L696, L1_E_logic_op[1], L1L630, L1_E_logic_op[0]);
--L1L1281 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[28]~1373 at LC_X12_Y13_N1
--operation mode is normal
L1L1281 = AMPP_FUNCTION(QC1_result[28], QC1_result[60]);
--HC1_result[28] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[28] at LC_X18_Y10_N8
--operation mode is arithmetic
HC1_result[28] = AMPP_FUNCTION(L1L697, L1L631, HC1L71, HC1L79, HC1L80, L1_E_ctrl_alu_subtract);
--HC1L82 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[28]~COUT at LC_X18_Y10_N8
--operation mode is arithmetic
HC1L82 = AMPP_FUNCTION(L1L697, L1L631, HC1L79, L1_E_ctrl_alu_subtract);
--HC1L83 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[28]~COUTCOUT1_193 at LC_X18_Y10_N8
--operation mode is arithmetic
HC1L83 = AMPP_FUNCTION(L1L697, L1L631, HC1L80, L1_E_ctrl_alu_subtract);
--L1L76 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12957 at LC_X19_Y13_N9
--operation mode is normal
L1L76 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[28]);
--L1L560 is std_1s10:inst|cpu:the_cpu|E_logic_result[28]~16139 at LC_X14_Y10_N7
--operation mode is normal
L1L560 = AMPP_FUNCTION(L1L697, L1_E_logic_op[1], L1_E_logic_op[0], L1L631);
--L1L1282 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[29]~1374 at LC_X12_Y13_N5
--operation mode is normal
L1L1282 = AMPP_FUNCTION(QC1_result[29], QC1_result[61]);
--HC1_result[29] is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|result[29] at LC_X18_Y10_N9
--operation mode is arithmetic
HC1_result[29] = AMPP_FUNCTION(L1L698, L1L632, HC1L71, HC1L82, HC1L83, L1_E_ctrl_alu_subtract);
--HC1L85 is std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder|add_sub_cell[29]~COUT at LC_X18_Y10_N9
--operation mode is arithmetic
HC1L85 = AMPP_FUNCTION(L1L698, L1L632, HC1L71, HC1L82, HC1L83, L1_E_ctrl_alu_subtract);
--L1L77 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12958 at LC_X19_Y14_N8
--operation mode is normal
L1L77 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[29]);
--L1L561 is std_1s10:inst|cpu:the_cpu|E_logic_result[29]~16140 at LC_X19_Y14_N6
--operation mode is normal
L1L561 = AMPP_FUNCTION(L1L632, L1L698, L1_E_logic_op[1], L1_E_logic_op[0]);
--L1L1283 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[30]~1375 at LC_X12_Y13_N3
--operation mode is normal
L1L1283 = AMPP_FUNCTION(QC1_result[62], QC1_result[30]);
--L1L78 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12959 at LC_X18_Y9_N3
--operation mode is normal
L1L78 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[30]);
--L1L562 is std_1s10:inst|cpu:the_cpu|E_logic_result[30]~16141 at LC_X18_Y13_N1
--operation mode is normal
L1L562 = AMPP_FUNCTION(L1_E_logic_op[1], L1L699, L1_E_logic_op[0], L1L633);
--L1L1285 is std_1s10:inst|cpu:the_cpu|M_mul_shift_rot_result_nxt[31]~1376 at LC_X12_Y13_N4
--operation mode is normal
L1L1285 = AMPP_FUNCTION(QC1_result[31], QC1_result[63]);
--L1L79 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogicVector~12960 at LC_X18_Y9_N8
--operation mode is normal
L1L79 = AMPP_FUNCTION(L1_E_ctrl_dst_data_sel_pc_plus_one, HC1_result[31]);
--L1L563 is std_1s10:inst|cpu:the_cpu|E_logic_result[31]~16142 at LC_X17_Y13_N4
--operation mode is normal
L1L563 = AMPP_FUNCTION(L1L634, L1L700, L1_E_logic_op[0], L1_E_logic_op[1]);
--L1L239 is std_1s10:inst|cpu:the_cpu|D_ctrl_mul_cell_src1_signed~102 at LC_X17_Y13_N0
--operation mode is normal
L1L239 = AMPP_FUNCTION(L1_D_iw[14], L1_D_iw[16], L1_D_iw[13], L1_D_iw[11]);
--L1L414 is std_1s10:inst|cpu:the_cpu|D_src2_imm[26]~2263 at LC_X17_Y7_N5
--operation mode is normal
L1L414 = AMPP_FUNCTION(L1_D_iw[21], L1L236, L1_D_iw[16]);
--L1L415 is std_1s10:inst|cpu:the_cpu|D_src2_imm[27]~2265 at LC_X27_Y20_N0
--operation mode is normal
L1L415 = AMPP_FUNCTION(L1_D_iw[17], L1_D_iw[21], L1L236);
--L1L416 is std_1s10:inst|cpu:the_cpu|D_src2_imm[28]~2267 at LC_X27_Y20_N5
--operation mode is normal
L1L416 = AMPP_FUNCTION(L1_D_iw[21], L1_D_iw[18], L1L236);
--L1L417 is std_1s10:inst|cpu:the_cpu|D_src2_imm[29]~2269 at LC_X19_Y16_N7
--operation mode is normal
L1L417 = AMPP_FUNCTION(L1L236, L1_D_iw[21], L1_D_iw[19]);
--L1L418 is std_1s10:inst|cpu:the_cpu|D_src2_imm[30]~2271 at LC_X28_Y20_N9
--operation mode is normal
L1L418 = AMPP_FUNCTION(L1_D_iw[21], L1L236, L1_D_iw[20]);
--T1L76 is std_1s10:inst|jtag_uart:the_jtag_uart|rvalid~18 at LC_X51_Y15_N7
--operation mode is normal
T1L76 = T1L58 & WD2_b_non_empty;
--QD1_wdata[2] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[2] at LC_X36_Y23_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_wdata[2] = AMPP_FUNCTION(!A1L6, QD1_td_shift[6], !C1_CLR_SIGNAL, GND, QD1L74);
--YD4_safe_q[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[0] at LC_X52_Y15_N1
--operation mode is arithmetic
YD4_safe_q[0]_lut_out = T1_wr_rfifo $ YD4_safe_q[0];
YD4_safe_q[0] = DFFEAS(YD4_safe_q[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD4L2 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella0~COUT at LC_X52_Y15_N1
--operation mode is arithmetic
YD4L2 = CARRY(YD4L2_cout_0);
--YD4L3 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella0~COUTCOUT1_9 at LC_X52_Y15_N1
--operation mode is arithmetic
YD4L3 = CARRY(YD4L3_cout_1);
--YD4_safe_q[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[1] at LC_X52_Y15_N2
--operation mode is arithmetic
YD4_safe_q[1]_lut_out = YD4_safe_q[1] $ (T1_wr_rfifo & YD4L2);
YD4_safe_q[1] = DFFEAS(YD4_safe_q[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD4L5 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella1~COUT at LC_X52_Y15_N2
--operation mode is arithmetic
YD4L5_cout_0 = !YD4L2 # !YD4_safe_q[1];
YD4L5 = CARRY(YD4L5_cout_0);
--YD4L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella1~COUTCOUT1_8 at LC_X52_Y15_N2
--operation mode is arithmetic
YD4L6_cout_1 = !YD4L3 # !YD4_safe_q[1];
YD4L6 = CARRY(YD4L6_cout_1);
--YD4_safe_q[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[2] at LC_X52_Y15_N3
--operation mode is arithmetic
YD4_safe_q[2]_lut_out = YD4_safe_q[2] $ (T1_wr_rfifo & !YD4L5);
YD4_safe_q[2] = DFFEAS(YD4_safe_q[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD4L8 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella2~COUT at LC_X52_Y15_N3
--operation mode is arithmetic
YD4L8_cout_0 = YD4_safe_q[2] & (!YD4L5);
YD4L8 = CARRY(YD4L8_cout_0);
--YD4L9 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella2~COUTCOUT1_6 at LC_X52_Y15_N3
--operation mode is arithmetic
YD4L9_cout_1 = YD4_safe_q[2] & (!YD4L6);
YD4L9 = CARRY(YD4L9_cout_1);
--YD4_safe_q[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[3] at LC_X52_Y15_N4
--operation mode is arithmetic
YD4_safe_q[3]_lut_out = YD4_safe_q[3] $ (T1_wr_rfifo & YD4L8);
YD4_safe_q[3] = DFFEAS(YD4_safe_q[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD4L11 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella3~COUT at LC_X52_Y15_N4
--operation mode is arithmetic
--YD4_safe_q[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[4] at LC_X52_Y15_N5
--operation mode is arithmetic
YD4_safe_q[4]_carry_eqn = (!YD4L11 & GND) # (YD4L11 & VCC);
YD4_safe_q[4]_lut_out = YD4_safe_q[4] $ (T1_wr_rfifo & !YD4_safe_q[4]_carry_eqn);
YD4_safe_q[4] = DFFEAS(YD4_safe_q[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD4L15 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella4~COUT at LC_X52_Y15_N5
--operation mode is arithmetic
YD4L15_cout_0 = YD4_safe_q[4] & !YD4L11;
YD4L15 = CARRY(YD4L15_cout_0);
--YD4L16 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella4~COUTCOUT1_8 at LC_X52_Y15_N5
--operation mode is arithmetic
YD4L16_cout_1 = YD4_safe_q[4] & !YD4L11;
YD4L16 = CARRY(YD4L16_cout_1);
--YD4_safe_q[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[5] at LC_X52_Y15_N6
--operation mode is normal
YD4_safe_q[5]_carry_eqn = (!YD4L11 & YD4L15) # (YD4L11 & YD4L16);
YD4_safe_q[5]_lut_out = YD4_safe_q[5] $ (T1_wr_rfifo & YD4_safe_q[5]_carry_eqn);
YD4_safe_q[5] = DFFEAS(YD4_safe_q[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD3_safe_q[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[0] at LC_X51_Y18_N1
--operation mode is arithmetic
YD3_safe_q[0]_lut_out = YD3_safe_q[0] $ T1L76;
YD3_safe_q[0] = DFFEAS(YD3_safe_q[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD3L2 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella0~COUT at LC_X51_Y18_N1
--operation mode is arithmetic
YD3L2 = CARRY(YD3L2_cout_0);
--YD3L3 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella0~COUTCOUT1_9 at LC_X51_Y18_N1
--operation mode is arithmetic
YD3L3 = CARRY(YD3L3_cout_1);
--YD3_safe_q[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[1] at LC_X51_Y18_N2
--operation mode is arithmetic
YD3_safe_q[1]_lut_out = YD3_safe_q[1] $ (T1L76 & YD3L2);
YD3_safe_q[1] = DFFEAS(YD3_safe_q[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD3L5 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella1~COUT at LC_X51_Y18_N2
--operation mode is arithmetic
YD3L5_cout_0 = !YD3L2 # !YD3_safe_q[1];
YD3L5 = CARRY(YD3L5_cout_0);
--YD3L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella1~COUTCOUT1_8 at LC_X51_Y18_N2
--operation mode is arithmetic
YD3L6_cout_1 = !YD3L3 # !YD3_safe_q[1];
YD3L6 = CARRY(YD3L6_cout_1);
--YD3_safe_q[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[2] at LC_X51_Y18_N3
--operation mode is arithmetic
YD3_safe_q[2]_lut_out = YD3_safe_q[2] $ (T1L76 & !YD3L5);
YD3_safe_q[2] = DFFEAS(YD3_safe_q[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD3L8 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella2~COUT at LC_X51_Y18_N3
--operation mode is arithmetic
YD3L8_cout_0 = YD3_safe_q[2] & (!YD3L5);
YD3L8 = CARRY(YD3L8_cout_0);
--YD3L9 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella2~COUTCOUT1_6 at LC_X51_Y18_N3
--operation mode is arithmetic
YD3L9_cout_1 = YD3_safe_q[2] & (!YD3L6);
YD3L9 = CARRY(YD3L9_cout_1);
--YD3_safe_q[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[3] at LC_X51_Y18_N4
--operation mode is arithmetic
YD3_safe_q[3]_lut_out = YD3_safe_q[3] $ (T1L76 & YD3L8);
YD3_safe_q[3] = DFFEAS(YD3_safe_q[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD3L11 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella3~COUT at LC_X51_Y18_N4
--operation mode is arithmetic
--YD3_safe_q[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[4] at LC_X51_Y18_N5
--operation mode is arithmetic
YD3_safe_q[4]_carry_eqn = (!YD3L11 & GND) # (YD3L11 & VCC);
YD3_safe_q[4]_lut_out = YD3_safe_q[4] $ (T1L76 & !YD3_safe_q[4]_carry_eqn);
YD3_safe_q[4] = DFFEAS(YD3_safe_q[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD3L15 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella4~COUT at LC_X51_Y18_N5
--operation mode is arithmetic
YD3L15_cout_0 = YD3_safe_q[4] & (!YD3L11);
YD3L15 = CARRY(YD3L15_cout_0);
--YD3L16 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella4~COUTCOUT1_8 at LC_X51_Y18_N5
--operation mode is arithmetic
YD3L16_cout_1 = YD3_safe_q[4] & (!YD3L11);
YD3L16 = CARRY(YD3L16_cout_1);
--YD3_safe_q[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[5] at LC_X51_Y18_N6
--operation mode is normal
YD3_safe_q[5]_carry_eqn = (!YD3L11 & YD3L15) # (YD3L11 & YD3L16);
YD3_safe_q[5]_lut_out = YD3_safe_q[5] $ (T1L76 & YD3_safe_q[5]_carry_eqn);
YD3_safe_q[5] = DFFEAS(YD3_safe_q[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--H1_slave_readdata_p1[2] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[2] at LC_X47_Y18_N4
--operation mode is normal
H1_slave_readdata_p1[2]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[2];
H1_slave_readdata_p1[2] = DFFEAS(H1_slave_readdata_p1[2]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--HE1L22 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|Equal1~106 at LC_X46_Y9_N4
--operation mode is normal
HE1L22 = !L1_M_alu_result[3] & L1_M_alu_result[4];
--KB1L233 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|snap_strobe~22 at LC_X46_Y9_N8
--operation mode is normal
KB1L233 = HE1L22 & LB1L3 & KB1L7 & LB1L2;
--KB1_period_h_wr_strobe is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_wr_strobe at LC_X48_Y9_N5
--operation mode is normal
KB1_period_h_wr_strobe = KB1L7 & HE1L15 & LB1L3 & LB1L2;
--KB1_period_l_wr_strobe is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_wr_strobe at LC_X48_Y9_N9
--operation mode is normal
KB1_period_l_wr_strobe = KB1L7 & HE1L20 & LB1L3 & LB1L2;
--R1L232 is std_1s10:inst|high_res_timer:the_high_res_timer|snap_strobe~16 at LC_X46_Y9_N1
--operation mode is normal
R1L232 = HE1L22 & KB1L7 & S1L2 & LB1L2;
--R1_period_h_wr_strobe is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_wr_strobe at LC_X46_Y9_N7
--operation mode is normal
R1_period_h_wr_strobe = HE1L15 & KB1L7 & S1L2 & LB1L2;
--R1_period_l_wr_strobe is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_wr_strobe at LC_X46_Y9_N0
--operation mode is normal
R1_period_l_wr_strobe = S1L2 & HE1L20 & KB1L7 & LB1L2;
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] at LC_X51_Y11_N5
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]_lut_out = JE1_do_start_rx # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1];
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1L71, , , , );
--JE1_got_new_char is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|got_new_char at LC_X48_Y10_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_delayed_unxrx_in_processxx3_qfbk = JE1_delayed_unxrx_in_processxx3;
JE1_got_new_char = JE1_delayed_unxrx_in_processxx3_qfbk & !JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0];
--JE1_delayed_unxrx_in_processxx3 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|delayed_unxrx_in_processxx3 at LC_X48_Y10_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_delayed_unxrx_in_processxx3 = DFFEAS(JE1_got_new_char, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0], , , VCC);
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] at LC_X51_Y11_N4
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1]_lut_out = JE1_do_start_rx # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2];
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1L71, , , , );
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] at LC_X51_Y11_N1
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8]_lut_out = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] # JE1_do_start_rx;
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1L71, , , , );
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] at LC_X51_Y11_N9
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]_lut_out = JE1_do_start_rx # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4];
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1L71, , , , );
--JE1L78 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|WideOr0~60 at LC_X51_Y9_N1
--operation mode is normal
JE1L78 = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3];
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] at LC_X51_Y11_N6
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2]_lut_out = JE1_do_start_rx # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3];
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1L71, , , , );
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] at LC_X51_Y11_N0
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4]_lut_out = JE1_do_start_rx # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5];
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1L71, , , , );
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] at LC_X51_Y11_N2
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5]_lut_out = JE1_do_start_rx # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6];
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1L71, , , , );
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] at LC_X51_Y11_N3
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]_lut_out = JE1_do_start_rx # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7];
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1L71, , , , );
--JE1L79 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|WideOr0~61 at LC_X51_Y11_N8
--operation mode is normal
JE1L79 = JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4];
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] at LC_X51_Y11_N7
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]_lut_out = JE1_do_start_rx # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8];
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1L71, , , , );
--JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] at LC_X41_Y29_N4
--operation mode is normal
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]_lut_out = JE1_do_start_rx # JE1L1 & (JE1_sync_rxd) # !JE1L1 & JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9];
JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] = DFFEAS(JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--JE1L80 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|WideOr0~62 at LC_X51_Y9_N7
--operation mode is normal
JE1L80 = JE1L79 # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] # JE1L78 # JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7];
--HE1L63 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|status_wr_strobe~11 at LC_X48_Y9_N8
--operation mode is normal
HE1L63 = QB1L2 & HE1L20 & L1_internal_d_write & LB1L2;
--DD1L191 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_b~22 at LC_X33_Y28_N7
--operation mode is normal
DD1L191 = AMPP_FUNCTION(DD1_ir[1], DD1_jxdr, DD1_internal_jdo1[35], DD1_ir[0]);
--DD1_internal_jdo1[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[3] at LC_X33_Y29_N2
--operation mode is normal
DD1_internal_jdo1[3] = AMPP_FUNCTION(!A1L9, DD1_sr[3], VCC, DD1L144);
--CD1_MonAReg[10] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[10] at LC_X34_Y27_N8
--operation mode is normal
CD1_MonAReg[10] = AMPP_FUNCTION(DE1__clk0, CD1L90, DD1L190, CD1L27, DD1_internal_jdo1[17], !C1_CLR_SIGNAL, DD1L192);
--CD1L37 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7316 at LC_X36_Y24_N7
--operation mode is normal
CD1L37 = AMPP_FUNCTION(CD1_MonAReg[10], PD1_q_b[0]);
--CD1L38 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7318 at LC_X36_Y24_N1
--operation mode is normal
CD1L38 = AMPP_FUNCTION(DD1L191, DD1L189, CD1_MonRd1);
--CD1L28 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~88 at LC_X36_Y26_N7
--operation mode is normal
CD1L28 = AMPP_FUNCTION(CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4]);
--DD1_internal_jdo1[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[4] at LC_X33_Y29_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[4] = AMPP_FUNCTION(!A1L9, DD1_sr[4], VCC, GND, DD1L144);
--CD1L39 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7319 at LC_X36_Y24_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
CD1L39 = AMPP_FUNCTION(DD1L191);
--CD1_MonRd1 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonRd1 at LC_X36_Y24_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
CD1_MonRd1 = AMPP_FUNCTION(DE1__clk0, CD1_MonRd, !C1_CLR_SIGNAL, GND);
--CD1L29 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~89 at LC_X36_Y26_N0
--operation mode is normal
CD1L29 = AMPP_FUNCTION(CD1_MonAReg[2], CD1_MonAReg[3], CD1_MonAReg[4]);
--DD1_internal_jdo1[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[5] at LC_X33_Y29_N8
--operation mode is normal
DD1_internal_jdo1[5] = AMPP_FUNCTION(!A1L9, DD1_sr[5], VCC, DD1L144);
--CD1L1 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|A_WE_StdLogicVector~138 at LC_X35_Y27_N9
--operation mode is normal
CD1L1 = AMPP_FUNCTION(CD1_MonAReg[3], CD1_MonAReg[4], CD1_MonAReg[2]);
--DD1_internal_jdo1[6] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[6] at LC_X35_Y29_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[6] = AMPP_FUNCTION(!A1L9, DD1_sr[6], VCC, GND, DD1L144);
--DD1_internal_jdo1[7] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[7] at LC_X35_Y29_N1
--operation mode is normal
DD1_internal_jdo1[7] = AMPP_FUNCTION(!A1L9, DD1_sr[7], VCC, DD1L144);
--CD1L30 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~90 at LC_X39_Y25_N4
--operation mode is normal
CD1L30 = AMPP_FUNCTION(CD1_MonAReg[3], CD1_MonAReg[2], CD1_MonAReg[4]);
--DD1_internal_jdo1[8] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[8] at LC_X35_Y29_N4
--operation mode is normal
DD1_internal_jdo1[8] = AMPP_FUNCTION(!A1L9, DD1_sr[8], VCC, DD1L144);
--DD1_internal_jdo1[9] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[9] at LC_X35_Y29_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[9] = AMPP_FUNCTION(!A1L9, DD1_sr[9], VCC, GND, DD1L144);
--DD1_internal_jdo1[10] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[10] at LC_X35_Y29_N7
--operation mode is normal
DD1_internal_jdo1[10] = AMPP_FUNCTION(!A1L9, DD1_sr[10], VCC, DD1L144);
--DD1_internal_jdo1[26] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[26] at LC_X35_Y29_N8
--operation mode is normal
DD1_internal_jdo1[26] = AMPP_FUNCTION(!A1L9, DD1_sr[26], VCC, DD1L144);
--CD1L2 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~132 at LC_X35_Y27_N0
--operation mode is arithmetic
CD1L2 = AMPP_FUNCTION(CD1_MonAReg[2]);
--CD1L3 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~133 at LC_X35_Y27_N0
--operation mode is arithmetic
CD1L3 = AMPP_FUNCTION(CD1_MonAReg[2]);
--CD1L4 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~133COUT1_185 at LC_X35_Y27_N0
--operation mode is arithmetic
CD1L4 = AMPP_FUNCTION(CD1_MonAReg[2]);
--CD1L82 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1144 at LC_X35_Y26_N1
--operation mode is normal
CD1L82 = AMPP_FUNCTION(CD1_MonAReg[2], CD1L2, DD1L191);
--DD1L192 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_no_action_ocimem_a~16 at LC_X34_Y25_N6
--operation mode is normal
DD1L192 = AMPP_FUNCTION(DD1L189, DD1_internal_jdo1[34]);
--DD1_internal_jdo1[27] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[27] at LC_X35_Y29_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[27] = AMPP_FUNCTION(!A1L9, DD1_sr[27], VCC, GND, DD1L144);
--CD1L5 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~134 at LC_X35_Y27_N1
--operation mode is arithmetic
CD1L5 = AMPP_FUNCTION(CD1_MonAReg[3], CD1L3, CD1L4);
--CD1L6 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~135 at LC_X35_Y27_N1
--operation mode is arithmetic
CD1L6 = AMPP_FUNCTION(CD1_MonAReg[3], CD1L3);
--CD1L7 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~135COUT1_187 at LC_X35_Y27_N1
--operation mode is arithmetic
CD1L7 = AMPP_FUNCTION(CD1_MonAReg[3], CD1L4);
--CD1L83 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1145 at LC_X35_Y26_N4
--operation mode is normal
CD1L83 = AMPP_FUNCTION(CD1_MonAReg[3], DD1L191, CD1L5);
--DD1_internal_jdo1[28] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[28] at LC_X35_Y29_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[28] = AMPP_FUNCTION(!A1L9, DD1_sr[28], VCC, GND, DD1L144);
--CD1L8 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~136 at LC_X35_Y27_N2
--operation mode is arithmetic
CD1L8 = AMPP_FUNCTION(CD1_MonAReg[4], CD1L6, CD1L7);
--CD1L9 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~137 at LC_X35_Y27_N2
--operation mode is arithmetic
CD1L9 = AMPP_FUNCTION(CD1_MonAReg[4], CD1L6);
--CD1L10 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~137COUT1_189 at LC_X35_Y27_N2
--operation mode is arithmetic
CD1L10 = AMPP_FUNCTION(CD1_MonAReg[4], CD1L7);
--CD1L84 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1146 at LC_X35_Y26_N7
--operation mode is normal
CD1L84 = AMPP_FUNCTION(CD1_MonAReg[4], CD1L8, DD1L191);
--DD1_internal_jdo1[29] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[29] at LC_X34_Y28_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[29] = AMPP_FUNCTION(!A1L9, DD1_sr[29], VCC, GND, DD1L144);
--CD1L11 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~138 at LC_X35_Y27_N3
--operation mode is arithmetic
CD1L11 = AMPP_FUNCTION(CD1_MonAReg[5], CD1L9, CD1L10);
--CD1L12 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~139 at LC_X35_Y27_N3
--operation mode is arithmetic
CD1L12 = AMPP_FUNCTION(CD1_MonAReg[5], CD1L9);
--CD1L13 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~139COUT1_191 at LC_X35_Y27_N3
--operation mode is arithmetic
CD1L13 = AMPP_FUNCTION(CD1_MonAReg[5], CD1L10);
--CD1L85 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1147 at LC_X35_Y26_N9
--operation mode is normal
CD1L85 = AMPP_FUNCTION(DD1L191, CD1_MonAReg[5], CD1L11);
--DD1_internal_jdo1[30] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[30] at LC_X34_Y27_N9
--operation mode is normal
DD1_internal_jdo1[30] = AMPP_FUNCTION(!A1L9, DD1_sr[30], VCC, DD1L144);
--CD1L14 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~140 at LC_X35_Y27_N4
--operation mode is arithmetic
CD1L14 = AMPP_FUNCTION(CD1_MonAReg[6], CD1L12, CD1L13);
--CD1L15 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~141 at LC_X35_Y27_N4
--operation mode is arithmetic
CD1L15 = AMPP_FUNCTION(CD1_MonAReg[6], CD1L12, CD1L13);
--CD1L86 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1148 at LC_X34_Y27_N1
--operation mode is normal
CD1L86 = AMPP_FUNCTION(DD1L191, CD1L14, CD1_MonAReg[6]);
--DD1_internal_jdo1[31] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[31] at LC_X34_Y28_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[31] = AMPP_FUNCTION(!A1L9, DD1_sr[31], VCC, GND, DD1L144);
--CD1L18 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~142 at LC_X35_Y27_N5
--operation mode is arithmetic
CD1L18 = AMPP_FUNCTION(CD1_MonAReg[7], CD1L15);
--CD1L19 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~143 at LC_X35_Y27_N5
--operation mode is arithmetic
CD1L19 = AMPP_FUNCTION(CD1_MonAReg[7]);
--CD1L20 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~143COUT1_193 at LC_X35_Y27_N5
--operation mode is arithmetic
CD1L20 = AMPP_FUNCTION(CD1_MonAReg[7]);
--CD1L87 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1149 at LC_X35_Y26_N5
--operation mode is normal
CD1L87 = AMPP_FUNCTION(DD1L191, CD1L18, CD1_MonAReg[7]);
--DD1_internal_jdo1[32] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[32] at LC_X34_Y27_N0
--operation mode is normal
DD1_internal_jdo1[32] = AMPP_FUNCTION(!A1L9, DD1_sr[32], VCC, DD1L144);
--CD1L21 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~144 at LC_X35_Y27_N6
--operation mode is arithmetic
CD1L21 = AMPP_FUNCTION(CD1_MonAReg[8], CD1L15, CD1L19, CD1L20);
--CD1L22 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~145 at LC_X35_Y27_N6
--operation mode is arithmetic
CD1L22 = AMPP_FUNCTION(CD1_MonAReg[8], CD1L19);
--CD1L23 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~145COUT1_195 at LC_X35_Y27_N6
--operation mode is arithmetic
CD1L23 = AMPP_FUNCTION(CD1_MonAReg[8], CD1L20);
--CD1L88 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1150 at LC_X34_Y27_N7
--operation mode is normal
CD1L88 = AMPP_FUNCTION(CD1_MonAReg[8], DD1L191, CD1L21);
--DD1_internal_jdo1[33] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[33] at LC_X34_Y28_N7
--operation mode is normal
DD1_internal_jdo1[33] = AMPP_FUNCTION(!A1L9, DD1_sr[33], VCC, DD1L144);
--CD1L24 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~146 at LC_X35_Y27_N7
--operation mode is arithmetic
CD1L24 = AMPP_FUNCTION(CD1_MonAReg[9], CD1L15, CD1L22, CD1L23);
--CD1L25 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~147 at LC_X35_Y27_N7
--operation mode is arithmetic
CD1L25 = AMPP_FUNCTION(CD1_MonAReg[9], CD1L22);
--CD1L26 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~147COUT1_197 at LC_X35_Y27_N7
--operation mode is arithmetic
CD1L26 = AMPP_FUNCTION(CD1_MonAReg[9], CD1L23);
--CD1L89 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1151 at LC_X34_Y27_N4
--operation mode is normal
CD1L89 = AMPP_FUNCTION(CD1_MonAReg[9], DD1L191, CD1L24);
--CD1L31 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Equal0~91 at LC_X39_Y25_N2
--operation mode is normal
CD1L31 = AMPP_FUNCTION(CD1_MonAReg[3], CD1_MonAReg[2], CD1_MonAReg[4]);
--DD1_internal_jdo1[24] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[24] at LC_X34_Y28_N2
--operation mode is normal
DD1_internal_jdo1[24] = AMPP_FUNCTION(!A1L9, DD1_sr[24], VCC, DD1L144);
--N1L43 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[12]~1924 at LC_X45_Y12_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[4]_qfbk = N1_dbs_latent_8_reg_segment_1[4];
N1L43 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_1[4]_qfbk & (BE1_q_a[12] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[12] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_1[4] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[4] at LC_X45_Y12_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[4] = DFFEAS(N1L43, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L155, Q1_internal_incoming_ext_ram_bus_data[4], , , VCC);
--N1L44 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[12]~1925 at LC_X45_Y11_N4
--operation mode is normal
N1L44 = Q1_internal_incoming_ext_ram_bus_data[12] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L45 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[12]~1926 at LC_X45_Y11_N3
--operation mode is normal
N1L45 = N1L43 & N1L44 & (FB1_za_data[12] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L40 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[11]~1928 at LC_X45_Y15_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[3]_qfbk = N1_dbs_latent_8_reg_segment_1[3];
N1L40 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_1[3]_qfbk & (BE1_q_a[11] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[11] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_1[3] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[3] at LC_X45_Y15_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[3] = DFFEAS(N1L40, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L155, Q1_internal_incoming_ext_ram_bus_data[3], , , VCC);
--N1L41 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[11]~1929 at LC_X45_Y15_N9
--operation mode is normal
N1L41 = Q1_internal_incoming_ext_ram_bus_data[11] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L42 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[11]~1930 at LC_X45_Y15_N0
--operation mode is normal
N1L42 = N1L40 & N1L41 & (FB1_za_data[11] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L55 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[16]~1932 at LC_X41_Y19_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[0]_qfbk = N1_dbs_latent_8_reg_segment_2[0];
N1L55 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_2[0]_qfbk & (BE1_q_a[16] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[16] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_2[0] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[0] at LC_X41_Y19_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[0] = DFFEAS(N1L55, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L156, Q1_internal_incoming_ext_ram_bus_data[0], , , VCC);
--N1L56 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[16]~1933 at LC_X41_Y19_N8
--operation mode is normal
N1L56 = Q1_internal_incoming_ext_ram_bus_data[16] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L57 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[16]~1934 at LC_X41_Y19_N1
--operation mode is normal
N1L57 = N1L55 & N1L56 & (FB1_za_data[16] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L49 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[14]~1936 at LC_X45_Y12_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[6]_qfbk = N1_dbs_latent_8_reg_segment_1[6];
N1L49 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_1[6]_qfbk & (BE1_q_a[14] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[14] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_1[6] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[6] at LC_X45_Y12_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[6] = DFFEAS(N1L49, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L155, Q1_internal_incoming_ext_ram_bus_data[6], , , VCC);
--N1L50 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[14]~1937 at LC_X44_Y12_N2
--operation mode is normal
N1L50 = Q1_internal_incoming_ext_ram_bus_data[14] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L51 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[14]~1938 at LC_X44_Y12_N4
--operation mode is normal
N1L51 = N1L49 & N1L50 & (FB1_za_data[14] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L46 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[13]~1940 at LC_X45_Y15_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[5]_qfbk = N1_dbs_latent_8_reg_segment_1[5];
N1L46 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_1[5]_qfbk & (BE1_q_a[13] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[13] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_1[5] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[5] at LC_X45_Y15_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[5] = DFFEAS(N1L46, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L155, Q1_internal_incoming_ext_ram_bus_data[5], , , VCC);
--N1L47 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[13]~1941 at LC_X48_Y17_N0
--operation mode is normal
N1L47 = Q1_internal_incoming_ext_ram_bus_data[13] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L48 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[13]~1942 at LC_X48_Y17_N8
--operation mode is normal
N1L48 = N1L46 & N1L47 & (FB1_za_data[13] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L70 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[21]~1944 at LC_X46_Y17_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[5]_qfbk = N1_dbs_latent_8_reg_segment_2[5];
N1L70 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_2[5]_qfbk & (BE1_q_a[21] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[21] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_2[5] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[5] at LC_X46_Y17_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[5] = DFFEAS(N1L70, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L156, Q1_internal_incoming_ext_ram_bus_data[5], , , VCC);
--N1L71 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[21]~1945 at LC_X46_Y19_N1
--operation mode is normal
N1L71 = Q1_internal_incoming_ext_ram_bus_data[21] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L72 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[21]~1946 at LC_X46_Y19_N7
--operation mode is normal
N1L72 = N1L70 & N1L71 & (FB1_za_data[21] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--QB1_d1_reasons_to_wait is std_1s10:inst|uart1_s1_arbitrator:the_uart1_s1|d1_reasons_to_wait at LC_X47_Y13_N9
--operation mode is normal
QB1_d1_reasons_to_wait_lut_out = !QB1_d1_reasons_to_wait & L1_M_alu_result[6] & LB1L2 & !L1_M_alu_result[5];
QB1_d1_reasons_to_wait = DFFEAS(QB1_d1_reasons_to_wait_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--JE1L62 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_rd_strobe_onset~25 at LC_X48_Y10_N6
--operation mode is normal
JE1L62 = !L1_M_alu_result[5] & L1_M_alu_result[6] & !QB1_d1_reasons_to_wait;
--JE1L63 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_rd_strobe_onset~26 at LC_X48_Y10_N2
--operation mode is normal
JE1L63 = NB1L2 & JE1L62 & P1L7 & !L1_M_alu_result[7];
--KE1L41 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|tx_wr_strobe_onset~16 at LC_X48_Y10_N3
--operation mode is normal
KE1L41 = L1_internal_d_write & HE1L19 & (JE1L63);
--JE1L48 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|framing_error~94 at LC_X51_Y9_N3
--operation mode is normal
JE1L48 = JE1_framing_error # JE1_got_new_char & JE1L80 & !JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9];
--KE1L33 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|internal_tx_ready~34 at LC_X52_Y7_N2
--operation mode is normal
KE1L33 = KE1_do_load_shifter # !KE1_internal_tx_ready;
--JE1L51 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|internal_rx_char_ready~30 at LC_X48_Y10_N9
--operation mode is normal
JE1L51 = JE1_internal_rx_char_ready # !JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] & (JE1_delayed_unxrx_in_processxx3);
--QD1_wdata[3] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[3] at LC_X36_Y23_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_wdata[3] = AMPP_FUNCTION(!A1L6, QD1_td_shift[7], !C1_CLR_SIGNAL, GND, QD1L74);
--H1_slave_readdata_p1[3] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[3] at LC_X50_Y19_N3
--operation mode is normal
H1_slave_readdata_p1[3]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[3];
H1_slave_readdata_p1[3] = DFFEAS(H1_slave_readdata_p1[3]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--N1L34 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~1948 at LC_X45_Y15_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[1]_qfbk = N1_dbs_latent_8_reg_segment_1[1];
N1L34 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_1[1]_qfbk & (BE1_q_a[9] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[9] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_1[1] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[1] at LC_X45_Y15_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[1] = DFFEAS(N1L34, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L155, Q1_internal_incoming_ext_ram_bus_data[1], , , VCC);
--N1L35 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~1949 at LC_X45_Y14_N1
--operation mode is normal
N1L35 = Q1_internal_incoming_ext_ram_bus_data[9] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L36 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[9]~1950 at LC_X45_Y14_N7
--operation mode is normal
N1L36 = N1L35 & N1L34 & (FB1_za_data[9] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--QD1_wdata[7] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[7] at LC_X36_Y23_N3
--operation mode is normal
QD1_wdata[7] = AMPP_FUNCTION(!A1L6, altera_internal_jtag, !C1_CLR_SIGNAL, QD1L74);
--H1_slave_readdata_p1[7] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[7] at LC_X48_Y18_N3
--operation mode is normal
H1_slave_readdata_p1[7]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[7];
H1_slave_readdata_p1[7] = DFFEAS(H1_slave_readdata_p1[7]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--GC1L8 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~565 at LC_X14_Y10_N3
--operation mode is arithmetic
GC1L8 = AMPP_FUNCTION(L1L698, L1L632, GC1L11);
--GC1L9 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~565COUT1_797 at LC_X14_Y10_N3
--operation mode is arithmetic
GC1L9 = AMPP_FUNCTION(L1L698, L1L632, GC1L12);
--L1L209 is std_1s10:inst|cpu:the_cpu|D_ctrl_alu_signed_cmp~319 at LC_X21_Y6_N9
--operation mode is normal
L1L209 = AMPP_FUNCTION(L1_D_iw[5], L1_D_iw[4], L1L208, L1L213);
--TC1_break_readreg[18] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[18] at LC_X32_Y26_N4
--operation mode is normal
TC1_break_readreg[18] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[18], DD1L188, DD1_internal_jdo1[36], DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L23 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19912 at LC_X32_Y25_N7
--operation mode is normal
DD1L23 = AMPP_FUNCTION(TC1_break_readreg[18], CD1_internal_MonDReg[18], DD1_ir[1]);
--DD1L24 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19913 at LC_X32_Y25_N9
--operation mode is normal
DD1L24 = AMPP_FUNCTION(DD1_ir[1], DD1_ir[0], DD1L23, DD1L143);
--TC1_break_readreg[17] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[17] at LC_X32_Y26_N9
--operation mode is normal
TC1_break_readreg[17] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[37], DD1L188, DD1_internal_jdo1[36], DD1_internal_jdo1[17], !C1_CLR_SIGNAL, DD1L188);
--DD1L25 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19915 at LC_X33_Y25_N7
--operation mode is normal
DD1L25 = AMPP_FUNCTION(DD1_ir[1], CD1_internal_MonDReg[17], TC1_break_readreg[17]);
--DD1L26 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19916 at LC_X33_Y25_N0
--operation mode is normal
DD1L26 = AMPP_FUNCTION(DD1L25, DD1_ir[0], DD1L142, DD1L144);
--DD1L27 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19917 at LC_X33_Y25_N8
--operation mode is normal
DD1L27 = AMPP_FUNCTION(A1L5, DD1_ir[0], DD1L144, DD1L25);
--DD1_internal_jdo1[37] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[37] at LC_X32_Y28_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[37] = AMPP_FUNCTION(!A1L9, DD1_sr[37], VCC, GND, DD1L144);
--DD1_internal_jdo1[36] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[36] at LC_X32_Y28_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[36] = AMPP_FUNCTION(!A1L9, DD1_sr[36], VCC, GND, DD1L144);
--DD1L188 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_break_c~45 at LC_X33_Y28_N4
--operation mode is normal
DD1L188 = AMPP_FUNCTION(DD1_jxdr, DD1_ir[1], DD1_ir[0]);
--RE1_state[14] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[14] at LC_X28_Y4_N5
--operation mode is normal
RE1_state[14] = AMPP_FUNCTION(!A1L6, A1L8, RE1_state[13], VCC);
--VC1L3 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_monitor_error~106 at LC_X34_Y25_N0
--operation mode is normal
VC1L3 = AMPP_FUNCTION(DD1_internal_jdo1[25], VC1_internal_monitor_error, DD1_internal_jdo1[34], DD1L189);
--DD1_sr[37] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[37] at LC_X32_Y28_N1
--operation mode is normal
DD1_sr[37] = AMPP_FUNCTION(!A1L6, altera_internal_jtag, A1L5, DD1L28, DD1L144, !C1_CLR_SIGNAL, DD1L30);
--DD1L28 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19919 at LC_X32_Y27_N7
--operation mode is normal
DD1L28 = AMPP_FUNCTION(DD1_ir[1], DD1_ir[0]);
--DD1L29 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19921 at LC_X32_Y25_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1L29 = AMPP_FUNCTION(DD1_ir[0]);
--DD1_ir[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[1] at LC_X32_Y25_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_ir[1] = AMPP_FUNCTION(!A1L6, ME5_Q[1], VCC, GND, DD1L116);
--DD1L30 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19922 at LC_X32_Y28_N7
--operation mode is normal
DD1L30 = AMPP_FUNCTION(DD1_st_updateir, DD1L141, DD1L29, DD1L143);
--C1L8 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~1 at LC_X29_Y27_N5
--operation mode is normal
C1L8 = AMPP_FUNCTION(RE1_state[5], ME8_Q[0], C1_OK_TO_UPDATE_IR_Q);
--R1_period_l_register[0] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[0] at LC_X52_Y6_N8
--operation mode is normal
R1_period_l_register[0]_lut_out = !L1_M_st_data[0];
R1_period_l_register[0] = DFFEAS(R1_period_l_register[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, , , , );
--R1_force_reload is std_1s10:inst|high_res_timer:the_high_res_timer|force_reload at LC_X47_Y9_N4
--operation mode is normal
R1_force_reload_lut_out = KB1L7 & NB1L3 & LB1L2 & S1L2;
R1_force_reload = DFFEAS(R1_force_reload_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--R1L180 is std_1s10:inst|high_res_timer:the_high_res_timer|process0~1 at LC_X48_Y7_N7
--operation mode is normal
R1L180 = R1_force_reload # R1L53 & R1L48;
--R1_counter_is_running is std_1s10:inst|high_res_timer:the_high_res_timer|counter_is_running at LC_X48_Y7_N5
--operation mode is normal
R1_counter_is_running_lut_out = R1_control_wr_strobe & (L1_M_st_data[2] # R1L9 & !L1_M_st_data[3]) # !R1_control_wr_strobe & R1L9;
R1_counter_is_running = DFFEAS(R1_counter_is_running_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--R1L179 is std_1s10:inst|high_res_timer:the_high_res_timer|process0~0 at LC_X48_Y7_N1
--operation mode is normal
R1L179 = R1_counter_is_running # R1_force_reload;
--R1_period_l_register[1] is std_1s10:inst|high_res_timer:the_high_res_timer|period_l_register[1] at LC_X52_Y6_N6
--operation mode is normal
R1_period_l_register[1]_lut_out = !L1_M_st_data[1];
R1_period_l_register[1] = DFFEAS(R1_period_l_register[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_l_wr_strobe, , , , );
--R1_period_h_register[0] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[0] at LC_X48_Y6_N7
--operation mode is normal
R1_period_h_register[0]_lut_out = L1_M_st_data[0];
R1_period_h_register[0] = DFFEAS(R1_period_h_register[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, , , , );
--R1_period_h_register[1] is std_1s10:inst|high_res_timer:the_high_res_timer|period_h_register[1] at LC_X48_Y6_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_period_h_register[1]_lut_out = GND;
R1_period_h_register[1] = DFFEAS(R1_period_h_register[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_period_h_wr_strobe, L1_M_st_data[1], , , VCC);
--QD1_wdata[4] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[4] at LC_X36_Y23_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_wdata[4] = AMPP_FUNCTION(!A1L6, QD1_td_shift[8], !C1_CLR_SIGNAL, GND, QD1L74);
--H1_slave_readdata_p1[4] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[4] at LC_X47_Y18_N3
--operation mode is normal
H1_slave_readdata_p1[4]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[4];
H1_slave_readdata_p1[4] = DFFEAS(H1_slave_readdata_p1[4]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--N1L37 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~1952 at LC_X44_Y13_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[2]_qfbk = N1_dbs_latent_8_reg_segment_1[2];
N1L37 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_1[2]_qfbk & (BE1_q_a[10] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[10] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_1[2] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_1[2] at LC_X44_Y13_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_1[2] = DFFEAS(N1L37, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L155, Q1_internal_incoming_ext_ram_bus_data[2], , , VCC);
--N1L38 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~1953 at LC_X44_Y11_N3
--operation mode is normal
N1L38 = Q1_internal_incoming_ext_ram_bus_data[10] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L39 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[10]~1954 at LC_X44_Y11_N8
--operation mode is normal
N1L39 = N1L38 & N1L37 & (FB1_za_data[10] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--WD2L5 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_full~86 at LC_X51_Y15_N4
--operation mode is normal
WD2L5 = ZD2_safe_q[4] & ZD2_safe_q[1] & QD1L37Q & ZD2_safe_q[5];
--WD2L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_full~87 at LC_X51_Y15_N5
--operation mode is normal
WD2L6 = ZD2_safe_q[0] & ZD2_safe_q[3] & ZD2_safe_q[2] & WD2L5;
--H1_slave_readdata_p1[15] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[15] at LC_X50_Y19_N8
--operation mode is normal
H1_slave_readdata_p1[15]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[15];
H1_slave_readdata_p1[15] = DFFEAS(H1_slave_readdata_p1[15]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--DD1_internal_jdo1[11] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[11] at LC_X34_Y28_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[11] = AMPP_FUNCTION(!A1L9, DD1_sr[11], VCC, GND, DD1L144);
--DD1_internal_jdo1[12] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[12] at LC_X34_Y28_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[12] = AMPP_FUNCTION(!A1L9, DD1_sr[12], VCC, GND, DD1L144);
--DD1_internal_jdo1[13] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[13] at LC_X34_Y28_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[13] = AMPP_FUNCTION(!A1L9, DD1_sr[13], VCC, GND, DD1L144);
--DD1_internal_jdo1[14] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[14] at LC_X35_Y29_N0
--operation mode is normal
DD1_internal_jdo1[14] = AMPP_FUNCTION(!A1L9, DD1_sr[14], VCC, DD1L144);
--DD1_internal_jdo1[15] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[15] at LC_X34_Y28_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[15] = AMPP_FUNCTION(!A1L9, DD1_sr[15], VCC, GND, DD1L144);
--DD1_internal_jdo1[16] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[16] at LC_X35_Y25_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[16] = AMPP_FUNCTION(!A1L9, DD1_sr[16], VCC, GND, DD1L144);
--DD1_internal_jdo1[17] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[17] at LC_X34_Y28_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
DD1_internal_jdo1[17] = AMPP_FUNCTION(!A1L9, DD1_sr[17], VCC, GND, DD1L144);
--N1L73 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[22]~1956 at LC_X46_Y17_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[6]_qfbk = N1_dbs_latent_8_reg_segment_2[6];
N1L73 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_dbs_latent_8_reg_segment_2[6]_qfbk & (BE1_q_a[22] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[22] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1_dbs_latent_8_reg_segment_2[6] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[6] at LC_X46_Y17_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[6] = DFFEAS(N1L73, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L156, Q1_internal_incoming_ext_ram_bus_data[6], , , VCC);
--N1L74 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[22]~1957 at LC_X46_Y17_N3
--operation mode is normal
N1L74 = Q1_internal_incoming_ext_ram_bus_data[22] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L75 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[22]~1958 at LC_X46_Y17_N9
--operation mode is normal
N1L75 = N1L74 & N1L73 & (FB1_za_data[22] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L76 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[23]~1960 at LC_X45_Y19_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[7]_qfbk = N1_dbs_latent_8_reg_segment_2[7];
N1L76 = AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & BE1_q_a[23] & (N1_dbs_latent_8_reg_segment_2[7]_qfbk # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_2[7]_qfbk # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1_dbs_latent_8_reg_segment_2[7] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[7] at LC_X45_Y19_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[7] = DFFEAS(N1L76, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L156, Q1_internal_incoming_ext_ram_bus_data[7], , , VCC);
--N1L77 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[23]~1961 at LC_X45_Y19_N6
--operation mode is normal
N1L77 = Q1_internal_incoming_ext_ram_bus_data[23] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L78 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[23]~1962 at LC_X45_Y19_N1
--operation mode is normal
N1L78 = N1L77 & N1L76 & (FB1_za_data[23] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L79 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[24]~1964 at LC_X46_Y15_N6
--operation mode is normal
N1L79 = Q1_internal_incoming_ext_ram_bus_data[0] & (BE1_q_a[24] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_internal_incoming_ext_ram_bus_data[0] & !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[24] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1L80 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[24]~1965 at LC_X44_Y16_N4
--operation mode is normal
N1L80 = Q1_internal_incoming_ext_ram_bus_data[24] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L81 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[24]~1966 at LC_X44_Y15_N2
--operation mode is normal
N1L81 = N1L80 & N1L79 & (FB1_za_data[24] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L82 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[25]~1968 at LC_X44_Y17_N9
--operation mode is normal
N1L82 = Q1_internal_incoming_ext_ram_bus_data[1] & (BE1_q_a[25] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_internal_incoming_ext_ram_bus_data[1] & !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[25] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1L83 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[25]~1969 at LC_X44_Y16_N6
--operation mode is normal
N1L83 = Q1_internal_incoming_ext_ram_bus_data[25] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L84 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[25]~1970 at LC_X44_Y16_N3
--operation mode is normal
N1L84 = N1L83 & N1L82 & (FB1_za_data[25] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--N1L85 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[26]~1972 at LC_X41_Y20_N8
--operation mode is normal
N1L85 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & Q1_internal_incoming_ext_ram_bus_data[2] & (BE1_q_a[26] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register) # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & (BE1_q_a[26] # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register);
--N1L86 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[26]~1973 at LC_X41_Y20_N3
--operation mode is normal
N1L86 = Q1_internal_incoming_ext_ram_bus_data[26] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L87 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[26]~1974 at LC_X41_Y20_N9
--operation mode is normal
N1L87 = N1L86 & N1L85 & (FB1_za_data[26] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--T1L51 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~316 at LC_X51_Y17_N0
--operation mode is arithmetic
T1L51_cout_0 = !ZD1_safe_q[0];
T1L51 = CARRY(T1L51_cout_0);
--T1L52 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~316COUT1_349 at LC_X51_Y17_N0
--operation mode is arithmetic
T1L52_cout_1 = !ZD1_safe_q[0];
T1L52 = CARRY(T1L52_cout_1);
--N1L67 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[20]~1976 at LC_X45_Y17_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[4]_qfbk = N1_dbs_latent_8_reg_segment_2[4];
N1L67 = AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & BE1_q_a[20] & (N1_dbs_latent_8_reg_segment_2[4]_qfbk # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_2[4]_qfbk # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1_dbs_latent_8_reg_segment_2[4] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[4] at LC_X45_Y17_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[4] = DFFEAS(N1L67, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L156, Q1_internal_incoming_ext_ram_bus_data[4], , , VCC);
--N1L68 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[20]~1977 at LC_X44_Y16_N9
--operation mode is normal
N1L68 = Q1_internal_incoming_ext_ram_bus_data[20] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L69 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[20]~1978 at LC_X45_Y18_N8
--operation mode is normal
N1L69 = N1L67 & N1L68 & (FB1_za_data[20] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--H1_slave_readdata_p1[14] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[14] at LC_X50_Y19_N2
--operation mode is normal
H1_slave_readdata_p1[14]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[14];
H1_slave_readdata_p1[14] = DFFEAS(H1_slave_readdata_p1[14]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--N1L64 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[19]~1980 at LC_X46_Y19_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[3]_qfbk = N1_dbs_latent_8_reg_segment_2[3];
N1L64 = AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & BE1_q_a[19] & (N1_dbs_latent_8_reg_segment_2[3]_qfbk # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_2[3]_qfbk # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1_dbs_latent_8_reg_segment_2[3] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[3] at LC_X46_Y19_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[3] = DFFEAS(N1L64, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L156, Q1_internal_incoming_ext_ram_bus_data[3], , , VCC);
--N1L65 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[19]~1981 at LC_X46_Y19_N4
--operation mode is normal
N1L65 = Q1_internal_incoming_ext_ram_bus_data[19] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & (!Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1]);
--N1L66 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[19]~1982 at LC_X46_Y19_N3
--operation mode is normal
N1L66 = N1L65 & N1L64 & (FB1_za_data[19] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--H1_slave_readdata_p1[13] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[13] at LC_X48_Y17_N1
--operation mode is normal
H1_slave_readdata_p1[13]_lut_out = BB1_control_reg_out[13] & (H1_master_nativeaddress[0]);
H1_slave_readdata_p1[13] = DFFEAS(H1_slave_readdata_p1[13]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--N1L61 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[18]~1984 at LC_X45_Y17_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[2]_qfbk = N1_dbs_latent_8_reg_segment_2[2];
N1L61 = AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & BE1_q_a[18] & (N1_dbs_latent_8_reg_segment_2[2]_qfbk # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_2[2]_qfbk # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1_dbs_latent_8_reg_segment_2[2] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[2] at LC_X45_Y17_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[2] = DFFEAS(N1L61, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L156, Q1_internal_incoming_ext_ram_bus_data[2], , , VCC);
--N1L62 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[18]~1985 at LC_X44_Y16_N2
--operation mode is normal
N1L62 = Q1_internal_incoming_ext_ram_bus_data[18] # !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1];
--N1L63 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[18]~1986 at LC_X45_Y16_N3
--operation mode is normal
N1L63 = N1L62 & N1L61 & (FB1_za_data[18] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--H1_slave_readdata_p1[12] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[12] at LC_X50_Y19_N7
--operation mode is normal
H1_slave_readdata_p1[12]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[12];
H1_slave_readdata_p1[12] = DFFEAS(H1_slave_readdata_p1[12]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--N1L58 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[17]~1988 at LC_X45_Y17_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[1]_qfbk = N1_dbs_latent_8_reg_segment_2[1];
N1L58 = BE1_q_a[17] & (N1_dbs_latent_8_reg_segment_2[1]_qfbk # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]) # !BE1_q_a[17] & !AB1_cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register & (N1_dbs_latent_8_reg_segment_2[1]_qfbk # !Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1]);
--N1_dbs_latent_8_reg_segment_2[1] is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|dbs_latent_8_reg_segment_2[1] at LC_X45_Y17_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
N1_dbs_latent_8_reg_segment_2[1] = DFFEAS(N1L58, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , N1L156, Q1_internal_incoming_ext_ram_bus_data[1], , , VCC);
--N1L59 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[17]~1989 at LC_X44_Y16_N0
--operation mode is normal
N1L59 = Q1_internal_incoming_ext_ram_bus_data[17] # !Q1_cpu_instruction_master_read_data_valid_lan91c111_s1_shift_register[1] & !Q1_cpu_instruction_master_read_data_valid_ext_ram_s1_shift_register[1];
--N1L60 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|cpu_instruction_master_readdata[17]~1990 at LC_X46_Y16_N0
--operation mode is normal
N1L60 = N1L59 & N1L58 & (FB1_za_data[17] # !GB1_cpu_instruction_master_read_data_valid_sdram_s1);
--H1_slave_readdata_p1[11] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[11] at LC_X48_Y16_N3
--operation mode is normal
H1_slave_readdata_p1[11]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[11];
H1_slave_readdata_p1[11] = DFFEAS(H1_slave_readdata_p1[11]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--T1L2 is std_1s10:inst|jtag_uart:the_jtag_uart|ac~73 at LC_X48_Y16_N8
--operation mode is normal
--H1_slave_readdata_p1[10] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[10] at LC_X48_Y16_N1
--operation mode is normal
H1_slave_readdata_p1[10]_lut_out = BB1_control_reg_out[10] & (H1_master_nativeaddress[0]);
H1_slave_readdata_p1[10] = DFFEAS(H1_slave_readdata_p1[10]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--H1_slave_readdata_p1[9] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[9] at LC_X50_Y19_N0
--operation mode is normal
H1_slave_readdata_p1[9]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[9];
H1_slave_readdata_p1[9] = DFFEAS(H1_slave_readdata_p1[9]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--H1_slave_readdata_p1[8] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[8] at LC_X50_Y19_N5
--operation mode is normal
H1_slave_readdata_p1[8]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[8];
H1_slave_readdata_p1[8] = DFFEAS(H1_slave_readdata_p1[8]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--QD1_wdata[5] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[5] at LC_X36_Y23_N9
--operation mode is normal
QD1_wdata[5] = AMPP_FUNCTION(!A1L6, QD1_td_shift[9], !C1_CLR_SIGNAL, QD1L74);
--H1_slave_readdata_p1[5] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[5] at LC_X48_Y15_N3
--operation mode is normal
H1_slave_readdata_p1[5]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[5];
H1_slave_readdata_p1[5] = DFFEAS(H1_slave_readdata_p1[5]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--QD1_wdata[6] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[6] at LC_X36_Y23_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_wdata[6] = AMPP_FUNCTION(!A1L6, QD1_td_shift[10], !C1_CLR_SIGNAL, GND, QD1L74);
--H1_slave_readdata_p1[6] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[6] at LC_X50_Y19_N4
--operation mode is normal
H1_slave_readdata_p1[6]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[6];
H1_slave_readdata_p1[6] = DFFEAS(H1_slave_readdata_p1[6]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--F1L24 is std_1s10:inst|button_pio:the_button_pio|read_mux_out[0]~380 at LC_X50_Y10_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
F1_irq_mask[0]_qfbk = F1_irq_mask[0];
F1L24 = L1_M_alu_result[2] & F1_edge_capture[0] # !L1_M_alu_result[2] & (F1_irq_mask[0]_qfbk);
--F1_irq_mask[0] is std_1s10:inst|button_pio:the_button_pio|irq_mask[0] at LC_X50_Y10_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
F1_irq_mask[0] = DFFEAS(F1L24, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , F1L23, L1_M_st_data[0], , , VCC);
--M1L266 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[0]~2136 at LC_X50_Y16_N2
--operation mode is normal
M1L266 = T1_read_0 & AE2_q_b[0] # !T1_read_0 & (T1_ien_AF);
--M1L267 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[0]~2137 at LC_X50_Y16_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[0]_qfbk = H1_slave_readdata[0];
M1L267 = GB1L24 & (J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[0]_qfbk # !FB1_za_data[0]) # !GB1L24 & J1_cpu_data_master_requests_clock_0_in & !H1_slave_readdata[0]_qfbk;
--H1_slave_readdata[0] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[0] at LC_X50_Y16_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[0] = DFFEAS(M1L267, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[0], , , VCC);
--HE1_control_reg[0] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_reg[0] at LC_X52_Y4_N2
--operation mode is normal
HE1_control_reg[0]_lut_out = L1_M_st_data[0];
HE1_control_reg[0] = DFFEAS(HE1_control_reg[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L13, , , , );
--HE1L48 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[0]~693 at LC_X51_Y9_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[0]_qfbk = JE1_rx_data[0];
HE1L48 = !L1_M_alu_result[3] & (L1_M_alu_result[2] & (HE1_internal_tx_data[0]) # !L1_M_alu_result[2] & JE1_rx_data[0]_qfbk);
--JE1_rx_data[0] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[0] at LC_X51_Y9_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[0] = DFFEAS(HE1L48, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1_got_new_char, JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1], , , VCC);
--R1L181 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[0]~1289 at LC_X48_Y6_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[16]_qfbk = R1_counter_snapshot[16];
R1L181 = R1_period_h_register[0] & (HE1L15 # HE1L18 & R1_counter_snapshot[16]_qfbk) # !R1_period_h_register[0] & HE1L18 & R1_counter_snapshot[16]_qfbk;
--R1_counter_snapshot[16] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[16] at LC_X48_Y6_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[16] = DFFEAS(R1L181, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[16], , , VCC);
--R1L182 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[0]~1290 at LC_X48_Y7_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_control_register[0]_qfbk = R1_control_register[0];
R1L182 = R1_timeout_occurred & (HE1L21 # HE1L19 & R1_control_register[0]_qfbk) # !R1_timeout_occurred & HE1L19 & R1_control_register[0]_qfbk;
--R1_control_register[0] is std_1s10:inst|high_res_timer:the_high_res_timer|control_register[0] at LC_X48_Y7_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_control_register[0] = DFFEAS(R1L182, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_control_wr_strobe, L1_M_st_data[0], , , VCC);
--R1_counter_snapshot[0] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[0] at LC_X47_Y4_N2
--operation mode is normal
R1_counter_snapshot[0]_lut_out = !R1_internal_counter[0];
R1_counter_snapshot[0] = DFFEAS(R1_counter_snapshot[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, , , , );
--R1L183 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[0]~1291 at LC_X50_Y7_N0
--operation mode is normal
R1L183 = HE1L17 & (R1_counter_snapshot[0] # HE1L20 & !R1_period_l_register[0]) # !HE1L17 & HE1L20 & (!R1_period_l_register[0]);
--KB1_counter_snapshot[16] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[16] at LC_X50_Y2_N4
--operation mode is normal
KB1_counter_snapshot[16]_lut_out = !KB1_internal_counter[16];
KB1_counter_snapshot[16] = DFFEAS(KB1_counter_snapshot[16]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--KB1_period_h_register[0] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[0] at LC_X52_Y5_N1
--operation mode is normal
KB1_period_h_register[0]_lut_out = !L1_M_st_data[0];
KB1_period_h_register[0] = DFFEAS(KB1_period_h_register[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, , , , );
--KB1L182 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[0]~1278 at LC_X50_Y7_N3
--operation mode is normal
KB1L182 = KB1_counter_snapshot[16] & (HE1L18 # HE1L15 & !KB1_period_h_register[0]) # !KB1_counter_snapshot[16] & HE1L15 & !KB1_period_h_register[0];
--KB1L183 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[0]~1279 at LC_X50_Y7_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_control_register[0]_qfbk = KB1_control_register[0];
KB1L183 = HE1L19 & (KB1_control_register[0]_qfbk # HE1L21 & KB1_timeout_occurred) # !HE1L19 & HE1L21 & (KB1_timeout_occurred);
--KB1_control_register[0] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|control_register[0] at LC_X50_Y7_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_control_register[0] = DFFEAS(KB1L183, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_control_wr_strobe, L1_M_st_data[0], , , VCC);
--KB1_counter_snapshot[0] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[0] at LC_X52_Y2_N7
--operation mode is normal
KB1_counter_snapshot[0]_lut_out = !KB1_internal_counter[0];
KB1_counter_snapshot[0] = DFFEAS(KB1_counter_snapshot[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--KB1_period_l_register[0] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[0] at LC_X52_Y5_N7
--operation mode is normal
KB1_period_l_register[0]_lut_out = !L1_M_st_data[0];
KB1_period_l_register[0] = DFFEAS(KB1_period_l_register[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, , , , );
--KB1L184 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[0]~1280 at LC_X50_Y7_N2
--operation mode is normal
KB1L184 = KB1_counter_snapshot[0] & (HE1L17 # HE1L20 & !KB1_period_l_register[0]) # !KB1_counter_snapshot[0] & HE1L20 & !KB1_period_l_register[0];
--F1L25 is std_1s10:inst|button_pio:the_button_pio|read_mux_out[1]~382 at LC_X50_Y12_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
F1_irq_mask[1]_qfbk = F1_irq_mask[1];
F1L25 = L1_M_alu_result[2] & (F1_edge_capture[1]) # !L1_M_alu_result[2] & F1_irq_mask[1]_qfbk;
--F1_irq_mask[1] is std_1s10:inst|button_pio:the_button_pio|irq_mask[1] at LC_X50_Y12_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
F1_irq_mask[1] = DFFEAS(F1L25, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , F1L23, L1_M_st_data[1], , , VCC);
--M1L268 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[1]~2139 at LC_X50_Y17_N6
--operation mode is normal
M1L268 = T1_read_0 & AE2_q_b[1] # !T1_read_0 & (T1_ien_AE);
--M1L269 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|p1_registered_cpu_data_master_readdata[1]~2140 at LC_X50_Y17_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[1]_qfbk = H1_slave_readdata[1];
M1L269 = J1_cpu_data_master_requests_clock_0_in & (GB1L24 & !FB1_za_data[1] # !H1_slave_readdata[1]_qfbk) # !J1_cpu_data_master_requests_clock_0_in & GB1L24 & (!FB1_za_data[1]);
--H1_slave_readdata[1] is std_1s10:inst|clock_0:the_clock_0|slave_readdata[1] at LC_X50_Y17_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_readdata[1] = DFFEAS(M1L269, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , H1_slave_readdata_p1[1], , , VCC);
--HE1L49 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[1]~695 at LC_X48_Y9_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_internal_tx_data[1]_qfbk = HE1_internal_tx_data[1];
HE1L49 = L1_M_alu_result[3] & (HE1_control_reg[1]) # !L1_M_alu_result[3] & (HE1_internal_tx_data[1]_qfbk);
--HE1_internal_tx_data[1] is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|internal_tx_data[1] at LC_X48_Y9_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
HE1_internal_tx_data[1] = DFFEAS(HE1L49, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , HE1L64, L1_M_st_data[1], , , VCC);
--HE1L50 is std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|selected_read_data[1]~696 at LC_X51_Y10_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[1]_qfbk = JE1_rx_data[1];
HE1L50 = L1_M_alu_result[3] & JE1_framing_error # !L1_M_alu_result[3] & (JE1_rx_data[1]_qfbk);
--JE1_rx_data[1] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rx_data[1] at LC_X51_Y10_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_rx_data[1] = DFFEAS(HE1L50, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , JE1_got_new_char, JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2], , , VCC);
--KB1_counter_snapshot[17] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[17] at LC_X50_Y2_N3
--operation mode is normal
KB1_counter_snapshot[17]_lut_out = !KB1_internal_counter[17];
KB1_counter_snapshot[17] = DFFEAS(KB1_counter_snapshot[17]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--KB1_period_h_register[1] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_register[1] at LC_X51_Y5_N2
--operation mode is normal
KB1_period_h_register[1]_lut_out = !L1_M_st_data[1];
KB1_period_h_register[1] = DFFEAS(KB1_period_h_register[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_h_wr_strobe, , , , );
--KB1L185 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[1]~1281 at LC_X50_Y5_N7
--operation mode is normal
KB1L185 = HE1L15 & (HE1L18 & KB1_counter_snapshot[17] # !KB1_period_h_register[1]) # !HE1L15 & HE1L18 & KB1_counter_snapshot[17];
--KB1_counter_is_running is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_is_running at LC_X50_Y5_N9
--operation mode is normal
KB1_counter_is_running_lut_out = KB1_control_wr_strobe & (L1_M_st_data[2] # !L1_M_st_data[3] & KB1L10) # !KB1_control_wr_strobe & (KB1L10);
KB1_counter_is_running = DFFEAS(KB1_counter_is_running_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--KB1L186 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[1]~1282 at LC_X50_Y5_N1
--operation mode is normal
KB1L186 = HE1L19 & (KB1_control_register[1] # KB1_counter_is_running & HE1L21) # !HE1L19 & KB1_counter_is_running & HE1L21;
--KB1_counter_snapshot[1] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_snapshot[1] at LC_X52_Y2_N4
--operation mode is normal
KB1_counter_snapshot[1]_lut_out = !KB1_internal_counter[1];
KB1_counter_snapshot[1] = DFFEAS(KB1_counter_snapshot[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1L233, , , , );
--KB1_period_l_register[1] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_register[1] at LC_X52_Y6_N0
--operation mode is normal
KB1_period_l_register[1]_lut_out = !L1_M_st_data[1];
KB1_period_l_register[1] = DFFEAS(KB1_period_l_register[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_period_l_wr_strobe, , , , );
--KB1L187 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|read_mux_out[1]~1283 at LC_X50_Y5_N3
--operation mode is normal
KB1L187 = HE1L17 & (KB1_counter_snapshot[1] # HE1L20 & !KB1_period_l_register[1]) # !HE1L17 & (HE1L20 & !KB1_period_l_register[1]);
--R1L184 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[1]~1292 at LC_X48_Y6_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[17]_qfbk = R1_counter_snapshot[17];
R1L184 = R1_period_h_register[1] & (HE1L15 # HE1L18 & R1_counter_snapshot[17]_qfbk) # !R1_period_h_register[1] & HE1L18 & R1_counter_snapshot[17]_qfbk;
--R1_counter_snapshot[17] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[17] at LC_X48_Y6_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_counter_snapshot[17] = DFFEAS(R1L184, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, R1_internal_counter[17], , , VCC);
--R1L185 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[1]~1293 at LC_X48_Y7_N8
--operation mode is normal
R1L185 = R1_control_register[1] & (HE1L19 # HE1L21 & R1_counter_is_running) # !R1_control_register[1] & HE1L21 & (R1_counter_is_running);
--R1_counter_snapshot[1] is std_1s10:inst|high_res_timer:the_high_res_timer|counter_snapshot[1] at LC_X47_Y4_N0
--operation mode is normal
R1_counter_snapshot[1]_lut_out = !R1_internal_counter[1];
R1_counter_snapshot[1] = DFFEAS(R1_counter_snapshot[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1L232, , , , );
--R1L186 is std_1s10:inst|high_res_timer:the_high_res_timer|read_mux_out[1]~1294 at LC_X47_Y4_N5
--operation mode is normal
R1L186 = HE1L17 & (R1_counter_snapshot[1] # HE1L20 & !R1_period_l_register[1]) # !HE1L17 & HE1L20 & !R1_period_l_register[1];
--KE1L38 is std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|process4~0 at LC_X52_Y7_N7
--operation mode is normal
KE1L38 = KE1_do_load_shifter # !KE1_baud_rate_counter[8] & KE1L31 & KE1L30;
--NE1L16 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux1~63 at LC_X27_Y27_N7
--operation mode is normal
NE1L16 = AMPP_FUNCTION(NE1_word_counter[3], NE1_word_counter[0], NE1_word_counter[1], NE1_word_counter[4]);
--NE1L17 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux1~64 at LC_X27_Y27_N4
--operation mode is normal
NE1L17 = AMPP_FUNCTION(NE1_word_counter[3], NE1_word_counter[0], NE1_word_counter[1], NE1_word_counter[4]);
--NE1_WORD_SR[3] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3] at LC_X28_Y28_N7
--operation mode is normal
NE1_WORD_SR[3] = AMPP_FUNCTION(!A1L6, altera_internal_jtag, NE1L18, NE1_clear_signal, RE1_state[4], VCC, NE1L24);
--QD1L19 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena~1 at LC_X34_Y23_N3
--operation mode is normal
QD1L19 = AMPP_FUNCTION(QD1_rvalid0, T1_r_val, QD1_r_ena1);
--QD1_read_req is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_req at LC_X34_Y23_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_read_req = AMPP_FUNCTION(!A1L6, QD1_td_shift[9], !C1_CLR_SIGNAL, GND, QD1L72);
--QD1L72 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[0]~7 at LC_X34_Y23_N5
--operation mode is normal
QD1L72 = AMPP_FUNCTION(QD1L69, QD1_count[1]);
--QD1_td_shift[3] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[3] at LC_X35_Y24_N4
--operation mode is normal
QD1_td_shift[3] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1L57, ME4_Q[0], QD1L62, !C1_CLR_SIGNAL, QD1L52);
--QD1L56 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3503 at LC_X35_Y24_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1L56 = AMPP_FUNCTION(QD1_count[9], QD1_td_shift[3]);
--QD1_rdata[0] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[0] at LC_X35_Y24_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_rdata[0] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[0], E1_data_out, GND, QD1L18);
--QD1_count[7] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[7] at LC_X31_Y26_N5
--operation mode is normal
QD1_count[7] = AMPP_FUNCTION(!A1L6, QD1_count[6], RE1_state[4], !C1_CLR_SIGNAL, QD1L52);
--AE1_q_b[7] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[7] at M512_X49_Y24
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 64, Port A Width: 8, Port B Depth: 64, Port B Width: 8
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
AE1_q_b[7]_PORT_A_data_in = BUS(L1_M_st_data[7], L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[2], L1_M_st_data[3]);
AE1_q_b[7]_PORT_A_data_in_reg = DFFE(AE1_q_b[7]_PORT_A_data_in, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[7]_PORT_A_address_reg = DFFE(AE1_q_b[7]_PORT_A_address, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[7]_PORT_B_address_reg = DFFE(AE1_q_b[7]_PORT_B_address, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_PORT_A_write_enable = VCC;
AE1_q_b[7]_PORT_A_write_enable_reg = DFFE(AE1_q_b[7]_PORT_A_write_enable, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_read_enable = VCC;
AE1_q_b[7]_PORT_B_read_enable_reg = DFFE(AE1_q_b[7]_PORT_B_read_enable, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_clock_0 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_1 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[7]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[7]_PORT_B_data_out = MEMORY(AE1_q_b[7]_PORT_A_data_in_reg, , AE1_q_b[7]_PORT_A_address_reg, AE1_q_b[7]_PORT_B_address_reg, AE1_q_b[7]_PORT_A_write_enable_reg, AE1_q_b[7]_PORT_B_read_enable_reg, , , AE1_q_b[7]_clock_0, AE1_q_b[7]_clock_1, AE1_q_b[7]_clock_enable_0, AE1_q_b[7]_clock_enable_1, , );
AE1_q_b[7] = AE1_q_b[7]_PORT_B_data_out[0];
--AE1_q_b[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[3] at M512_X49_Y24
AE1_q_b[7]_PORT_A_data_in = BUS(L1_M_st_data[7], L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[2], L1_M_st_data[3]);
AE1_q_b[7]_PORT_A_data_in_reg = DFFE(AE1_q_b[7]_PORT_A_data_in, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[7]_PORT_A_address_reg = DFFE(AE1_q_b[7]_PORT_A_address, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[7]_PORT_B_address_reg = DFFE(AE1_q_b[7]_PORT_B_address, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_PORT_A_write_enable = VCC;
AE1_q_b[7]_PORT_A_write_enable_reg = DFFE(AE1_q_b[7]_PORT_A_write_enable, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_read_enable = VCC;
AE1_q_b[7]_PORT_B_read_enable_reg = DFFE(AE1_q_b[7]_PORT_B_read_enable, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_clock_0 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_1 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[7]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[7]_PORT_B_data_out = MEMORY(AE1_q_b[7]_PORT_A_data_in_reg, , AE1_q_b[7]_PORT_A_address_reg, AE1_q_b[7]_PORT_B_address_reg, AE1_q_b[7]_PORT_A_write_enable_reg, AE1_q_b[7]_PORT_B_read_enable_reg, , , AE1_q_b[7]_clock_0, AE1_q_b[7]_clock_1, AE1_q_b[7]_clock_enable_0, AE1_q_b[7]_clock_enable_1, , );
AE1_q_b[3] = AE1_q_b[7]_PORT_B_data_out[7];
--AE1_q_b[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[2] at M512_X49_Y24
AE1_q_b[7]_PORT_A_data_in = BUS(L1_M_st_data[7], L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[2], L1_M_st_data[3]);
AE1_q_b[7]_PORT_A_data_in_reg = DFFE(AE1_q_b[7]_PORT_A_data_in, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[7]_PORT_A_address_reg = DFFE(AE1_q_b[7]_PORT_A_address, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[7]_PORT_B_address_reg = DFFE(AE1_q_b[7]_PORT_B_address, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_PORT_A_write_enable = VCC;
AE1_q_b[7]_PORT_A_write_enable_reg = DFFE(AE1_q_b[7]_PORT_A_write_enable, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_read_enable = VCC;
AE1_q_b[7]_PORT_B_read_enable_reg = DFFE(AE1_q_b[7]_PORT_B_read_enable, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_clock_0 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_1 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[7]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[7]_PORT_B_data_out = MEMORY(AE1_q_b[7]_PORT_A_data_in_reg, , AE1_q_b[7]_PORT_A_address_reg, AE1_q_b[7]_PORT_B_address_reg, AE1_q_b[7]_PORT_A_write_enable_reg, AE1_q_b[7]_PORT_B_read_enable_reg, , , AE1_q_b[7]_clock_0, AE1_q_b[7]_clock_1, AE1_q_b[7]_clock_enable_0, AE1_q_b[7]_clock_enable_1, , );
AE1_q_b[2] = AE1_q_b[7]_PORT_B_data_out[6];
--AE1_q_b[6] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[6] at M512_X49_Y24
AE1_q_b[7]_PORT_A_data_in = BUS(L1_M_st_data[7], L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[2], L1_M_st_data[3]);
AE1_q_b[7]_PORT_A_data_in_reg = DFFE(AE1_q_b[7]_PORT_A_data_in, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[7]_PORT_A_address_reg = DFFE(AE1_q_b[7]_PORT_A_address, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[7]_PORT_B_address_reg = DFFE(AE1_q_b[7]_PORT_B_address, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_PORT_A_write_enable = VCC;
AE1_q_b[7]_PORT_A_write_enable_reg = DFFE(AE1_q_b[7]_PORT_A_write_enable, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_read_enable = VCC;
AE1_q_b[7]_PORT_B_read_enable_reg = DFFE(AE1_q_b[7]_PORT_B_read_enable, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_clock_0 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_1 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[7]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[7]_PORT_B_data_out = MEMORY(AE1_q_b[7]_PORT_A_data_in_reg, , AE1_q_b[7]_PORT_A_address_reg, AE1_q_b[7]_PORT_B_address_reg, AE1_q_b[7]_PORT_A_write_enable_reg, AE1_q_b[7]_PORT_B_read_enable_reg, , , AE1_q_b[7]_clock_0, AE1_q_b[7]_clock_1, AE1_q_b[7]_clock_enable_0, AE1_q_b[7]_clock_enable_1, , );
AE1_q_b[6] = AE1_q_b[7]_PORT_B_data_out[5];
--AE1_q_b[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[5] at M512_X49_Y24
AE1_q_b[7]_PORT_A_data_in = BUS(L1_M_st_data[7], L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[2], L1_M_st_data[3]);
AE1_q_b[7]_PORT_A_data_in_reg = DFFE(AE1_q_b[7]_PORT_A_data_in, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[7]_PORT_A_address_reg = DFFE(AE1_q_b[7]_PORT_A_address, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[7]_PORT_B_address_reg = DFFE(AE1_q_b[7]_PORT_B_address, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_PORT_A_write_enable = VCC;
AE1_q_b[7]_PORT_A_write_enable_reg = DFFE(AE1_q_b[7]_PORT_A_write_enable, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_read_enable = VCC;
AE1_q_b[7]_PORT_B_read_enable_reg = DFFE(AE1_q_b[7]_PORT_B_read_enable, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_clock_0 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_1 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[7]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[7]_PORT_B_data_out = MEMORY(AE1_q_b[7]_PORT_A_data_in_reg, , AE1_q_b[7]_PORT_A_address_reg, AE1_q_b[7]_PORT_B_address_reg, AE1_q_b[7]_PORT_A_write_enable_reg, AE1_q_b[7]_PORT_B_read_enable_reg, , , AE1_q_b[7]_clock_0, AE1_q_b[7]_clock_1, AE1_q_b[7]_clock_enable_0, AE1_q_b[7]_clock_enable_1, , );
AE1_q_b[5] = AE1_q_b[7]_PORT_B_data_out[4];
--AE1_q_b[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[4] at M512_X49_Y24
AE1_q_b[7]_PORT_A_data_in = BUS(L1_M_st_data[7], L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[2], L1_M_st_data[3]);
AE1_q_b[7]_PORT_A_data_in_reg = DFFE(AE1_q_b[7]_PORT_A_data_in, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[7]_PORT_A_address_reg = DFFE(AE1_q_b[7]_PORT_A_address, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[7]_PORT_B_address_reg = DFFE(AE1_q_b[7]_PORT_B_address, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_PORT_A_write_enable = VCC;
AE1_q_b[7]_PORT_A_write_enable_reg = DFFE(AE1_q_b[7]_PORT_A_write_enable, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_read_enable = VCC;
AE1_q_b[7]_PORT_B_read_enable_reg = DFFE(AE1_q_b[7]_PORT_B_read_enable, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_clock_0 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_1 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[7]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[7]_PORT_B_data_out = MEMORY(AE1_q_b[7]_PORT_A_data_in_reg, , AE1_q_b[7]_PORT_A_address_reg, AE1_q_b[7]_PORT_B_address_reg, AE1_q_b[7]_PORT_A_write_enable_reg, AE1_q_b[7]_PORT_B_read_enable_reg, , , AE1_q_b[7]_clock_0, AE1_q_b[7]_clock_1, AE1_q_b[7]_clock_enable_0, AE1_q_b[7]_clock_enable_1, , );
AE1_q_b[4] = AE1_q_b[7]_PORT_B_data_out[3];
--AE1_q_b[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[1] at M512_X49_Y24
AE1_q_b[7]_PORT_A_data_in = BUS(L1_M_st_data[7], L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[2], L1_M_st_data[3]);
AE1_q_b[7]_PORT_A_data_in_reg = DFFE(AE1_q_b[7]_PORT_A_data_in, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[7]_PORT_A_address_reg = DFFE(AE1_q_b[7]_PORT_A_address, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[7]_PORT_B_address_reg = DFFE(AE1_q_b[7]_PORT_B_address, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_PORT_A_write_enable = VCC;
AE1_q_b[7]_PORT_A_write_enable_reg = DFFE(AE1_q_b[7]_PORT_A_write_enable, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_read_enable = VCC;
AE1_q_b[7]_PORT_B_read_enable_reg = DFFE(AE1_q_b[7]_PORT_B_read_enable, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_clock_0 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_1 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[7]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[7]_PORT_B_data_out = MEMORY(AE1_q_b[7]_PORT_A_data_in_reg, , AE1_q_b[7]_PORT_A_address_reg, AE1_q_b[7]_PORT_B_address_reg, AE1_q_b[7]_PORT_A_write_enable_reg, AE1_q_b[7]_PORT_B_read_enable_reg, , , AE1_q_b[7]_clock_0, AE1_q_b[7]_clock_1, AE1_q_b[7]_clock_enable_0, AE1_q_b[7]_clock_enable_1, , );
AE1_q_b[1] = AE1_q_b[7]_PORT_B_data_out[2];
--AE1_q_b[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|q_b[0] at M512_X49_Y24
AE1_q_b[7]_PORT_A_data_in = BUS(L1_M_st_data[7], L1_M_st_data[0], L1_M_st_data[1], L1_M_st_data[4], L1_M_st_data[5], L1_M_st_data[6], L1_M_st_data[2], L1_M_st_data[3]);
AE1_q_b[7]_PORT_A_data_in_reg = DFFE(AE1_q_b[7]_PORT_A_data_in, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_A_address = BUS(YD2_safe_q[0], YD2_safe_q[1], YD2_safe_q[2], YD2_safe_q[3], YD2_safe_q[4], YD2_safe_q[5]);
AE1_q_b[7]_PORT_A_address_reg = DFFE(AE1_q_b[7]_PORT_A_address, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_address = BUS(YD1_safe_q[0], YD1_safe_q[1], YD1_safe_q[2], YD1_safe_q[3], YD1_safe_q[4], YD1_safe_q[5]);
AE1_q_b[7]_PORT_B_address_reg = DFFE(AE1_q_b[7]_PORT_B_address, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_PORT_A_write_enable = VCC;
AE1_q_b[7]_PORT_A_write_enable_reg = DFFE(AE1_q_b[7]_PORT_A_write_enable, AE1_q_b[7]_clock_0, , , AE1_q_b[7]_clock_enable_0);
AE1_q_b[7]_PORT_B_read_enable = VCC;
AE1_q_b[7]_PORT_B_read_enable_reg = DFFE(AE1_q_b[7]_PORT_B_read_enable, AE1_q_b[7]_clock_1, , , AE1_q_b[7]_clock_enable_1);
AE1_q_b[7]_clock_0 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_1 = GLOBAL(DE1__clk0);
AE1_q_b[7]_clock_enable_0 = T1_fifo_wr;
AE1_q_b[7]_clock_enable_1 = T1_rd_wfifo;
AE1_q_b[7]_PORT_B_data_out = MEMORY(AE1_q_b[7]_PORT_A_data_in_reg, , AE1_q_b[7]_PORT_A_address_reg, AE1_q_b[7]_PORT_B_address_reg, AE1_q_b[7]_PORT_A_write_enable_reg, AE1_q_b[7]_PORT_B_read_enable_reg, , , AE1_q_b[7]_clock_0, AE1_q_b[7]_clock_1, AE1_q_b[7]_clock_enable_0, AE1_q_b[7]_clock_enable_1, , );
AE1_q_b[0] = AE1_q_b[7]_PORT_B_data_out[1];
--QD1L18 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena~0 at LC_X34_Y23_N8
--operation mode is normal
QD1L18 = AMPP_FUNCTION(QD1_r_ena1, T1_r_val);
--DD1_internal_jdo1[0] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[0] at LC_X34_Y28_N8
--operation mode is normal
DD1_internal_jdo1[0] = AMPP_FUNCTION(!A1L9, DD1_sr[0], VCC, DD1L144);
--TC1_break_readreg[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[1] at LC_X32_Y26_N0
--operation mode is normal
TC1_break_readreg[1] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[1], DD1L188, DD1_internal_jdo1[36], DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L129 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux38~14 at LC_X32_Y25_N0
--operation mode is normal
DD1L129 = AMPP_FUNCTION(CD1_internal_MonDReg[1], DD1_ir[0], TC1_break_readreg[1], DD1_ir[1]);
--DD1_sr[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[3] at LC_X33_Y29_N0
--operation mode is normal
DD1_sr[3] = AMPP_FUNCTION(!A1L6, DD1L141, DD1L128, DD1_sr[4], DD1L143, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[25] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[25] at LC_X32_Y27_N9
--operation mode is normal
DD1_sr[25] = AMPP_FUNCTION(!A1L6, DD1L70, DD1L34, DD1L35, DD1_sr[26], !C1_CLR_SIGNAL, DD1L12);
--L1L237 is std_1s10:inst|cpu:the_cpu|D_ctrl_jmp_indirect~36 at LC_X33_Y10_N5
--operation mode is normal
L1L237 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[11]);
--GE1_stage_4 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_4 at LC_X41_Y9_N7
--operation mode is normal
GE1_stage_4_lut_out = GE1_full_5 & GE1_stage_5 # !GE1_full_5 & (GB1L25);
GE1_stage_4 = DFFEAS(GE1_stage_4_lut_out, GLOBAL(DE1__clk0), VCC, , GE1L22, , , , );
--GE1_full_4 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_4 at LC_X45_Y9_N5
--operation mode is normal
GE1_full_4_lut_out = GB1L34 & (GE1_full_3) # !GB1L34 & (FB1_za_valid & (GE1_full_5) # !FB1_za_valid & GE1_full_3);
GE1_full_4 = DFFEAS(GE1_full_4_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FE1L13, , , , );
--GE1L23 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process6~1 at LC_X44_Y10_N4
--operation mode is normal
GE1L23 = FB1_za_valid # GB1L34 & !GE1_full_3;
--FE1_stage_4 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_4 at LC_X41_Y9_N5
--operation mode is normal
FE1_stage_4_lut_out = GE1_full_5 & FE1_stage_5 # !GE1_full_5 & (GB1L20);
FE1_stage_4 = DFFEAS(FE1_stage_4_lut_out, GLOBAL(DE1__clk0), VCC, , GE1L22, , , , );
--WB1L10 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux1~124 at LC_X48_Y21_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
XB3_data_in_d1_qfbk = XB3_data_in_d1;
WB1L10 = !WB1_master_state[1] & !WB1_master_state[0] & (TB1_data_out $ XB3_data_in_d1_qfbk);
--XB3_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_request_edge_to_pulse|data_in_d1 at LC_X48_Y21_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
XB3_data_in_d1 = DFFEAS(WB1L10, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , TB1_data_out, , , VCC);
--UB1_data_out is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_out at LC_X48_Y20_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
UB1_data_out_lut_out = GND;
UB1_data_out = DFFEAS(UB1_data_out_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , UB1_data_in_d1, , , VCC);
--WB1L9 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux0~176 at LC_X48_Y21_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
TB1_data_out_qfbk = TB1_data_out;
WB1L9 = WB1_master_state[2] # WB1_master_state[1] # TB1_data_out_qfbk $ XB3_data_in_d1;
--TB1_data_out is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_out at LC_X48_Y21_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
TB1_data_out = DFFEAS(WB1L9, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , TB1_data_in_d1, , , VCC);
--WB1L11 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux2~236 at LC_X48_Y21_N4
--operation mode is normal
WB1L11 = WB1_master_state[2] # WB1_master_state[1] & (CB1_d1_reasons_to_wait # !WB1_master_state[0]);
--WB1L12 is std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|Mux2~237 at LC_X48_Y21_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
XB4_data_in_d1_qfbk = XB4_data_in_d1;
WB1L12 = TB1_data_out & XB3_data_in_d1 & (UB1_data_out $ !XB4_data_in_d1_qfbk) # !TB1_data_out & !XB3_data_in_d1 & (UB1_data_out $ !XB4_data_in_d1_qfbk);
--XB4_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_request_edge_to_pulse|data_in_d1 at LC_X48_Y21_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
XB4_data_in_d1 = DFFEAS(WB1L12, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , UB1_data_out, , , VCC);
--D1_data_in_d1 is std_1s10:inst|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch|data_in_d1 at LC_X27_Y1_N4
--operation mode is normal
D1_data_in_d1_lut_out = VCC;
D1_data_in_d1 = DFFEAS(D1_data_in_d1_lut_out, GLOBAL(PLD_CLOCKINPUT), !GLOBAL(B1L1), , , , , , );
--TC1_break_readreg[22] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[22] at LC_X32_Y26_N5
--operation mode is normal
TC1_break_readreg[22] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[22], DD1_internal_jdo1[36], DD1L188, DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L31 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19924 at LC_X31_Y28_N3
--operation mode is normal
DD1L31 = AMPP_FUNCTION(DD1_ir[1], CD1_internal_MonDReg[22], TC1_break_readreg[22]);
--DD1L32 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19925 at LC_X31_Y28_N4
--operation mode is normal
DD1L32 = AMPP_FUNCTION(DD1L31, DD1_ir[0], DD1L144, DD1L142);
--DD1_sr[24] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[24] at LC_X32_Y27_N5
--operation mode is normal
DD1_sr[24] = AMPP_FUNCTION(!A1L6, DD1L37, DD1L9, DD1L38, DD1_sr[25], !C1_CLR_SIGNAL, DD1L12);
--DD1L33 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19926 at LC_X31_Y28_N6
--operation mode is normal
DD1L33 = AMPP_FUNCTION(DD1L31, DD1_ir[0], DD1L144, A1L5);
--WD1L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~141 at LC_X50_Y17_N2
--operation mode is normal
WD1L6 = ZD1_safe_q[1] # ZD1_safe_q[2] # ZD1_safe_q[4] # ZD1_safe_q[5];
--WD1L7 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~142 at LC_X50_Y17_N9
--operation mode is normal
WD1L7 = ZD1_safe_q[3] # WD1L6 # !T1_rd_wfifo # !ZD1_safe_q[0];
--QD1_read_write is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write at LC_X36_Y23_N0
--operation mode is normal
QD1_read_write = AMPP_FUNCTION(!A1L6, QD1_read_write, !C1_CLR_SIGNAL, QD1L74);
--QD1_jupdate is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate at LC_X30_Y26_N6
--operation mode is normal
QD1_jupdate = AMPP_FUNCTION(A1L6, RE1_state[8], QD1_jupdate, QD1L1, ME4_Q[0], !C1_CLR_SIGNAL);
--N1L155 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process3~0 at LC_X45_Y15_N2
--operation mode is normal
N1L155 = N1_cpu_instruction_master_dbs_rdv_counter[0] & Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !N1_cpu_instruction_master_dbs_rdv_counter[1];
--KB1_force_reload is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|force_reload at LC_X48_Y11_N2
--operation mode is normal
KB1_force_reload_lut_out = LB1L2 & NB1L3 & LB1L3 & KB1L7;
KB1_force_reload = DFFEAS(KB1_force_reload_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--KB1L181 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|process0~1 at LC_X50_Y6_N8
--operation mode is normal
KB1L181 = KB1_force_reload # KB1L49 & KB1L54;
--KB1L180 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|process0~0 at LC_X50_Y5_N0
--operation mode is normal
KB1L180 = KB1_force_reload # KB1_counter_is_running;
--N1L154 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process2~0 at LC_X46_Y12_N0
--operation mode is normal
N1L154 = Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & !N1_cpu_instruction_master_dbs_rdv_counter[0] & !N1_cpu_instruction_master_dbs_rdv_counter[1];
--QD1_td_shift[6] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[6] at LC_X35_Y24_N9
--operation mode is normal
QD1_td_shift[6] = AMPP_FUNCTION(!A1L6, QD1L63, QD1L58, QD1L53, !C1_CLR_SIGNAL, QD1L52);
--QD1L74 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[1]~6 at LC_X33_Y23_N4
--operation mode is normal
QD1L74 = AMPP_FUNCTION(QD1L69, QD1_count[8]);
--H1_master_nativeaddress[0] is std_1s10:inst|clock_0:the_clock_0|master_nativeaddress[0] at LC_X50_Y20_N6
--operation mode is normal
H1_master_nativeaddress[0]_lut_out = H1_slave_nativeaddress_d1[0];
H1_master_nativeaddress[0] = DFFEAS(H1_master_nativeaddress[0]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--BB1_control_reg_out[2] is std_1s10:inst|pll:the_pll|control_reg_out[2] at LC_X50_Y20_N5
--operation mode is normal
BB1_control_reg_out[2]_lut_out = H1_master_writedata[2];
BB1_control_reg_out[2] = DFFEAS(BB1_control_reg_out[2]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, , , , );
--H1L22 is std_1s10:inst|clock_0:the_clock_0|process0~9 at LC_X47_Y18_N1
--operation mode is normal
H1L22 = WB1_master_state[1] & CB1_d1_reasons_to_wait;
--JE1_do_start_rx is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|do_start_rx at LC_X41_Y29_N6
--operation mode is normal
JE1_do_start_rx_lut_out = JE1_delayed_unxsync_rxdxx2 & (!JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] & !JE1_sync_rxd);
JE1_do_start_rx = DFFEAS(JE1_do_start_rx_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--JE1_baud_clk_en is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_clk_en at LC_X41_Y27_N2
--operation mode is normal
JE1_baud_clk_en_lut_out = !JE1_baud_rate_counter[8] & JE1L44 & JE1L45 & !JE1_rxd_edge;
JE1_baud_clk_en = DFFEAS(JE1_baud_clk_en_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--JE1L71 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]~7381 at LC_X41_Y29_N8
--operation mode is normal
JE1L71 = JE1_do_start_rx # JE1_baud_clk_en & JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0];
--JE1L1 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|A_WE_StdLogicVector~22 at LC_X41_Y29_N5
--operation mode is normal
JE1L1 = JE1_baud_clk_en & JE1_unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0];
--CD1L27 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|Add0~148 at LC_X35_Y27_N8
--operation mode is normal
CD1L27 = AMPP_FUNCTION(CD1_MonAReg[10], CD1L15, CD1L25, CD1L26);
--CD1L90 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg~1152 at LC_X34_Y27_N2
--operation mode is normal
CD1L90 = AMPP_FUNCTION(DD1L191, CD1L27, CD1_MonAReg[10]);
--CD1_MonRd is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonRd at LC_X36_Y24_N9
--operation mode is normal
CD1_MonRd = AMPP_FUNCTION(DE1__clk0, DD1L191, CD1L93, DD1L189, CD1_MonRd, !C1_CLR_SIGNAL);
--DD1_sr[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[4] at LC_X33_Y29_N1
--operation mode is normal
DD1_sr[4] = AMPP_FUNCTION(!A1L6, DD1L141, DD1_sr[5], DD1L127, DD1L143, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[5] at LC_X33_Y29_N9
--operation mode is normal
DD1_sr[5] = AMPP_FUNCTION(!A1L6, DD1L141, DD1_sr[6], DD1L126, DD1L143, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[6] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[6] at LC_X34_Y29_N3
--operation mode is normal
DD1_sr[6] = AMPP_FUNCTION(!A1L6, DD1L141, DD1L143, DD1L125, DD1_sr[7], !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[7] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[7] at LC_X34_Y29_N0
--operation mode is normal
DD1_sr[7] = AMPP_FUNCTION(!A1L6, DD1L138, DD1_sr[8], DD1L124, altera_internal_jtag, !C1_CLR_SIGNAL, DD1L143, DD1L6);
--DD1_sr[8] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[8] at LC_X34_Y29_N1
--operation mode is normal
DD1_sr[8] = AMPP_FUNCTION(!A1L6, DD1L141, DD1L143, DD1L123, DD1_sr[9], !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[9] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[9] at LC_X34_Y29_N9
--operation mode is normal
DD1_sr[9] = AMPP_FUNCTION(!A1L6, DD1L141, DD1L143, DD1L39, DD1_sr[10], !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[10] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[10] at LC_X34_Y29_N2
--operation mode is normal
DD1_sr[10] = AMPP_FUNCTION(!A1L6, DD1L141, DD1L143, DD1_sr[11], DD1L40, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[26] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[26] at LC_X32_Y27_N6
--operation mode is normal
DD1_sr[26] = AMPP_FUNCTION(!A1L6, DD1L43, DD1_sr[27], DD1L42, DD1L9, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[27] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[27] at LC_X32_Y27_N4
--operation mode is normal
DD1_sr[27] = AMPP_FUNCTION(!A1L6, DD1L45, DD1_sr[28], DD1L46, DD1L9, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[28] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[28] at LC_X33_Y27_N8
--operation mode is normal
DD1_sr[28] = AMPP_FUNCTION(!A1L6, DD1L47, DD1L70, DD1_sr[29], DD1L48, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[29] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[29] at LC_X33_Y27_N5
--operation mode is normal
DD1_sr[29] = AMPP_FUNCTION(!A1L6, DD1L9, DD1_sr[30], DD1L51, DD1L50, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[30] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[30] at LC_X33_Y27_N6
--operation mode is normal
DD1_sr[30] = AMPP_FUNCTION(!A1L6, DD1_sr[31], DD1L70, DD1L53, DD1L52, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[31] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[31] at LC_X33_Y27_N0
--operation mode is normal
DD1_sr[31] = AMPP_FUNCTION(!A1L6, DD1_ir[1], DD1L136, DD1L71, DD1L54, !C1_CLR_SIGNAL, !DD1_ir[0], DD1L12);
--DD1_sr[32] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[32] at LC_X33_Y24_N8
--operation mode is normal
DD1_sr[32] = AMPP_FUNCTION(!A1L6, DD1L9, DD1L57, DD1_sr[33], DD1L58, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[33] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[33] at LC_X33_Y24_N7
--operation mode is normal
DD1_sr[33] = AMPP_FUNCTION(!A1L6, DD1L17, DD1L141, DD1_sr[34], DD1L59, !C1_CLR_SIGNAL, DD1L12);
--N1L156 is std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process4~0 at LC_X45_Y17_N2
--operation mode is normal
N1L156 = !N1_cpu_instruction_master_dbs_rdv_counter[0] & Q1_cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] & N1_cpu_instruction_master_dbs_rdv_counter[1];
--QD1_td_shift[7] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[7] at LC_X34_Y24_N6
--operation mode is normal
QD1_td_shift[7] = AMPP_FUNCTION(!A1L6, QD1L59, ME4_Q[0], RE1_state[4], QD1L62, !C1_CLR_SIGNAL, QD1L52);
--BB1_control_reg_out[3] is std_1s10:inst|pll:the_pll|control_reg_out[3] at LC_X50_Y20_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
BB1_control_reg_out[3]_lut_out = GND;
BB1_control_reg_out[3] = DFFEAS(BB1_control_reg_out[3]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, H1_master_writedata[3], , , VCC);
--BB1_control_reg_out[7] is std_1s10:inst|pll:the_pll|control_reg_out[7] at LC_X50_Y20_N4
--operation mode is normal
BB1_control_reg_out[7]_lut_out = H1_master_writedata[7];
BB1_control_reg_out[7] = DFFEAS(BB1_control_reg_out[7]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, , , , );
--GC1L11 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~567 at LC_X14_Y10_N2
--operation mode is arithmetic
GC1L11 = AMPP_FUNCTION(L1L631, L1L697, GC1L14);
--GC1L12 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~567COUT1_795 at LC_X14_Y10_N2
--operation mode is arithmetic
GC1L12 = AMPP_FUNCTION(L1L631, L1L697, GC1L15);
--RE1_state[13] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[13] at LC_X28_Y4_N9
--operation mode is normal
RE1_state[13] = AMPP_FUNCTION(!A1L6, RE1_state[12], RE1_state[13], VCC, !A1L8);
--R1L8 is std_1s10:inst|high_res_timer:the_high_res_timer|counter_is_running~91 at LC_X48_Y7_N3
--operation mode is normal
R1L8 = R1_counter_is_running & !R1_force_reload;
--R1L9 is std_1s10:inst|high_res_timer:the_high_res_timer|counter_is_running~92 at LC_X48_Y7_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_control_register[1]_qfbk = R1_control_register[1];
R1L9 = R1L8 & (R1_control_register[1]_qfbk # !R1L53 # !R1L48);
--R1_control_register[1] is std_1s10:inst|high_res_timer:the_high_res_timer|control_register[1] at LC_X48_Y7_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
R1_control_register[1] = DFFEAS(R1L9, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , R1_control_wr_strobe, L1_M_st_data[1], , , VCC);
--QD1_td_shift[8] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[8] at LC_X35_Y23_N9
--operation mode is normal
QD1_td_shift[8] = AMPP_FUNCTION(!A1L6, QD1_rdata[6], QD1_count[9], QD1_td_shift[9], !C1_CLR_SIGNAL, !RE1_state[4], QD1L52);
--BB1_control_reg_out[4] is std_1s10:inst|pll:the_pll|control_reg_out[4] at LC_X50_Y20_N7
--operation mode is normal
BB1_control_reg_out[4]_lut_out = H1_master_writedata[4];
BB1_control_reg_out[4] = DFFEAS(BB1_control_reg_out[4]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, , , , );
--BB1_control_reg_out[15] is std_1s10:inst|pll:the_pll|control_reg_out[15] at LC_X50_Y20_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
BB1_control_reg_out[15]_lut_out = GND;
BB1_control_reg_out[15] = DFFEAS(BB1_control_reg_out[15]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, H1_master_writedata[15], , , VCC);
--DD1_sr[11] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[11] at LC_X34_Y29_N5
--operation mode is normal
DD1_sr[11] = AMPP_FUNCTION(!A1L6, DD1L141, DD1L143, DD1L60, DD1_sr[12], !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[12] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[12] at LC_X34_Y29_N8
--operation mode is normal
DD1_sr[12] = AMPP_FUNCTION(!A1L6, DD1L141, DD1L143, DD1L61, DD1_sr[13], !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[13] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[13] at LC_X34_Y29_N6
--operation mode is normal
DD1_sr[13] = AMPP_FUNCTION(!A1L6, DD1L141, DD1L143, DD1L62, DD1_sr[14], !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[14] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[14] at LC_X34_Y29_N4
--operation mode is normal
DD1_sr[14] = AMPP_FUNCTION(!A1L6, DD1L141, DD1L143, DD1_sr[15], DD1L63, !C1_CLR_SIGNAL, DD1L6);
--DD1_sr[15] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[15] at LC_X34_Y29_N7
--operation mode is normal
DD1_sr[15] = AMPP_FUNCTION(!A1L6, DD1L137, altera_internal_jtag, DD1L122, DD1_sr[16], !C1_CLR_SIGNAL, DD1L143, DD1L6);
--DD1_sr[16] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[16] at LC_X33_Y25_N1
--operation mode is normal
DD1_sr[16] = AMPP_FUNCTION(!A1L6, DD1L66, DD1L65, DD1_sr[17], DD1L9, !C1_CLR_SIGNAL, DD1L12);
--DD1_sr[17] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[17] at LC_X33_Y25_N5
--operation mode is normal
DD1_sr[17] = AMPP_FUNCTION(!A1L6, DD1L69, DD1L9, DD1_sr[18], DD1L68, !C1_CLR_SIGNAL, DD1L12);
--BB1_control_reg_out[14] is std_1s10:inst|pll:the_pll|control_reg_out[14] at LC_X50_Y20_N2
--operation mode is normal
BB1_control_reg_out[14]_lut_out = H1_master_writedata[14];
BB1_control_reg_out[14] = DFFEAS(BB1_control_reg_out[14]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, , , , );
--BB1_control_reg_out[13] is std_1s10:inst|pll:the_pll|control_reg_out[13] at LC_X51_Y19_N4
--operation mode is normal
BB1_control_reg_out[13]_lut_out = H1_master_writedata[13];
BB1_control_reg_out[13] = DFFEAS(BB1_control_reg_out[13]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, , , , );
--BB1_control_reg_out[12] is std_1s10:inst|pll:the_pll|control_reg_out[12] at LC_X51_Y19_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
BB1_control_reg_out[12]_lut_out = GND;
BB1_control_reg_out[12] = DFFEAS(BB1_control_reg_out[12]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, H1_master_writedata[12], , , VCC);
--BB1_control_reg_out[11] is std_1s10:inst|pll:the_pll|control_reg_out[11] at LC_X51_Y19_N7
--operation mode is normal
BB1_control_reg_out[11]_lut_out = H1_master_writedata[11];
BB1_control_reg_out[11] = DFFEAS(BB1_control_reg_out[11]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, , , , );
--BB1_control_reg_out[10] is std_1s10:inst|pll:the_pll|control_reg_out[10] at LC_X51_Y19_N5
--operation mode is normal
BB1_control_reg_out[10]_lut_out = H1_master_writedata[10];
BB1_control_reg_out[10] = DFFEAS(BB1_control_reg_out[10]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, , , , );
--BB1_control_reg_out[9] is std_1s10:inst|pll:the_pll|control_reg_out[9] at LC_X51_Y19_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
BB1_control_reg_out[9]_lut_out = GND;
BB1_control_reg_out[9] = DFFEAS(BB1_control_reg_out[9]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, H1_master_writedata[9], , , VCC);
--BB1_control_reg_out[8] is std_1s10:inst|pll:the_pll|control_reg_out[8] at LC_X51_Y20_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
BB1_control_reg_out[8]_lut_out = GND;
BB1_control_reg_out[8] = DFFEAS(BB1_control_reg_out[8]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, H1_master_writedata[8], , , VCC);
--BB1_control_reg_out[5] is std_1s10:inst|pll:the_pll|control_reg_out[5] at LC_X51_Y20_N5
--operation mode is normal
BB1_control_reg_out[5]_lut_out = H1_master_writedata[5];
BB1_control_reg_out[5] = DFFEAS(BB1_control_reg_out[5]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, , , , );
--BB1_control_reg_out[6] is std_1s10:inst|pll:the_pll|control_reg_out[6] at LC_X51_Y20_N4
--operation mode is normal
BB1_control_reg_out[6]_lut_out = H1_master_writedata[6];
BB1_control_reg_out[6] = DFFEAS(BB1_control_reg_out[6]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, , , , );
--QD1_wdata[0] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[0] at LC_X33_Y23_N2
--operation mode is normal
QD1_wdata[0] = AMPP_FUNCTION(!A1L6, altera_internal_jtag, !C1_CLR_SIGNAL, QD1L72);
--H1_slave_readdata_p1[0] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[0] at LC_X50_Y19_N1
--operation mode is normal
H1_slave_readdata_p1[0]_lut_out = H1_master_nativeaddress[0] & BB1_control_reg_out[0];
H1_slave_readdata_p1[0] = DFFEAS(H1_slave_readdata_p1[0]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--QD1_wdata[1] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[1] at LC_X36_Y23_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_wdata[1] = AMPP_FUNCTION(!A1L6, QD1_td_shift[5], !C1_CLR_SIGNAL, GND, QD1L74);
--H1_slave_readdata_p1[1] is std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[1] at LC_X50_Y18_N2
--operation mode is normal
H1_slave_readdata_p1[1]_lut_out = H1_master_nativeaddress[0] & (!BB1_control_reg_out[1]);
H1_slave_readdata_p1[1] = DFFEAS(H1_slave_readdata_p1[1]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , H1L22, , , , );
--KB1L9 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_is_running~91 at LC_X50_Y5_N5
--operation mode is normal
KB1L9 = !KB1_force_reload & KB1_counter_is_running;
--KB1L10 is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|counter_is_running~92 at LC_X50_Y5_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_control_register[1]_qfbk = KB1_control_register[1];
KB1L10 = KB1L9 & (KB1_control_register[1]_qfbk # !KB1L54 # !KB1L49);
--KB1_control_register[1] is std_1s10:inst|sys_clk_timer:the_sys_clk_timer|control_register[1] at LC_X50_Y5_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
KB1_control_register[1] = DFFEAS(KB1L10, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , KB1_control_wr_strobe, L1_M_st_data[1], , , VCC);
--NE1L18 is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|Mux1~65 at LC_X27_Y27_N5
--operation mode is normal
NE1L18 = AMPP_FUNCTION(NE1_word_counter[3], NE1_word_counter[0], NE1_word_counter[1]);
--QD1_td_shift[4] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[4] at LC_X35_Y24_N8
--operation mode is normal
QD1_td_shift[4] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1L60, ME4_Q[0], QD1L62, !C1_CLR_SIGNAL, QD1L52);
--QD1L57 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3507 at LC_X35_Y24_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1L57 = AMPP_FUNCTION(QD1_count[9], QD1_td_shift[4]);
--QD1_rdata[1] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[1] at LC_X35_Y24_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_rdata[1] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[1], E1_data_out, GND, QD1L18);
--QD1_count[6] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[6] at LC_X31_Y26_N7
--operation mode is normal
QD1_count[6] = AMPP_FUNCTION(!A1L6, QD1_count[5], RE1_state[4], !C1_CLR_SIGNAL, QD1L52);
--YD2_safe_q[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[0] at LC_X51_Y23_N1
--operation mode is arithmetic
YD2_safe_q[0]_lut_out = T1_fifo_wr $ YD2_safe_q[0];
YD2_safe_q[0] = DFFEAS(YD2_safe_q[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD2L2 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella0~COUT at LC_X51_Y23_N1
--operation mode is arithmetic
YD2L2 = CARRY(YD2L2_cout_0);
--YD2L3 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella0~COUTCOUT1_9 at LC_X51_Y23_N1
--operation mode is arithmetic
YD2L3 = CARRY(YD2L3_cout_1);
--YD2_safe_q[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[1] at LC_X51_Y23_N2
--operation mode is arithmetic
YD2_safe_q[1]_lut_out = YD2_safe_q[1] $ (T1_fifo_wr & YD2L2);
YD2_safe_q[1] = DFFEAS(YD2_safe_q[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD2L5 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella1~COUT at LC_X51_Y23_N2
--operation mode is arithmetic
YD2L5_cout_0 = !YD2L2 # !YD2_safe_q[1];
YD2L5 = CARRY(YD2L5_cout_0);
--YD2L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella1~COUTCOUT1_8 at LC_X51_Y23_N2
--operation mode is arithmetic
YD2L6_cout_1 = !YD2L3 # !YD2_safe_q[1];
YD2L6 = CARRY(YD2L6_cout_1);
--YD2_safe_q[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[2] at LC_X51_Y23_N3
--operation mode is arithmetic
YD2_safe_q[2]_lut_out = YD2_safe_q[2] $ (T1_fifo_wr & !YD2L5);
YD2_safe_q[2] = DFFEAS(YD2_safe_q[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD2L8 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella2~COUT at LC_X51_Y23_N3
--operation mode is arithmetic
YD2L8_cout_0 = YD2_safe_q[2] & (!YD2L5);
YD2L8 = CARRY(YD2L8_cout_0);
--YD2L9 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella2~COUTCOUT1_6 at LC_X51_Y23_N3
--operation mode is arithmetic
YD2L9_cout_1 = YD2_safe_q[2] & (!YD2L6);
YD2L9 = CARRY(YD2L9_cout_1);
--YD2_safe_q[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[3] at LC_X51_Y23_N4
--operation mode is arithmetic
YD2_safe_q[3]_lut_out = YD2_safe_q[3] $ (T1_fifo_wr & YD2L8);
YD2_safe_q[3] = DFFEAS(YD2_safe_q[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD2L11 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella3~COUT at LC_X51_Y23_N4
--operation mode is arithmetic
--YD2_safe_q[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[4] at LC_X51_Y23_N5
--operation mode is arithmetic
YD2_safe_q[4]_carry_eqn = (!YD2L11 & GND) # (YD2L11 & VCC);
YD2_safe_q[4]_lut_out = YD2_safe_q[4] $ (T1_fifo_wr & !YD2_safe_q[4]_carry_eqn);
YD2_safe_q[4] = DFFEAS(YD2_safe_q[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD2L15 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella4~COUT at LC_X51_Y23_N5
--operation mode is arithmetic
YD2L15_cout_0 = YD2_safe_q[4] & (!YD2L11);
YD2L15 = CARRY(YD2L15_cout_0);
--YD2L16 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|counter_cella4~COUTCOUT1_8 at LC_X51_Y23_N5
--operation mode is arithmetic
YD2L16_cout_1 = YD2_safe_q[4] & (!YD2L11);
YD2L16 = CARRY(YD2L16_cout_1);
--YD2_safe_q[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr|safe_q[5] at LC_X51_Y23_N6
--operation mode is normal
YD2_safe_q[5]_carry_eqn = (!YD2L11 & YD2L15) # (YD2L11 & YD2L16);
YD2_safe_q[5]_lut_out = YD2_safe_q[5] $ (T1_fifo_wr & YD2_safe_q[5]_carry_eqn);
YD2_safe_q[5] = DFFEAS(YD2_safe_q[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD1_safe_q[0] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[0] at LC_X50_Y24_N1
--operation mode is arithmetic
YD1_safe_q[0]_lut_out = T1_rd_wfifo $ YD1_safe_q[0];
YD1_safe_q[0] = DFFEAS(YD1_safe_q[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD1L2 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella0~COUT at LC_X50_Y24_N1
--operation mode is arithmetic
YD1L2 = CARRY(YD1L2_cout_0);
--YD1L3 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella0~COUTCOUT1_9 at LC_X50_Y24_N1
--operation mode is arithmetic
YD1L3 = CARRY(YD1L3_cout_1);
--YD1_safe_q[1] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[1] at LC_X50_Y24_N2
--operation mode is arithmetic
YD1_safe_q[1]_lut_out = YD1_safe_q[1] $ (T1_rd_wfifo & YD1L2);
YD1_safe_q[1] = DFFEAS(YD1_safe_q[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD1L5 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella1~COUT at LC_X50_Y24_N2
--operation mode is arithmetic
YD1L5_cout_0 = !YD1L2 # !YD1_safe_q[1];
YD1L5 = CARRY(YD1L5_cout_0);
--YD1L6 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella1~COUTCOUT1_8 at LC_X50_Y24_N2
--operation mode is arithmetic
YD1L6_cout_1 = !YD1L3 # !YD1_safe_q[1];
YD1L6 = CARRY(YD1L6_cout_1);
--YD1_safe_q[2] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[2] at LC_X50_Y24_N3
--operation mode is arithmetic
YD1_safe_q[2]_lut_out = YD1_safe_q[2] $ (T1_rd_wfifo & !YD1L5);
YD1_safe_q[2] = DFFEAS(YD1_safe_q[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD1L8 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella2~COUT at LC_X50_Y24_N3
--operation mode is arithmetic
YD1L8_cout_0 = YD1_safe_q[2] & (!YD1L5);
YD1L8 = CARRY(YD1L8_cout_0);
--YD1L9 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella2~COUTCOUT1_6 at LC_X50_Y24_N3
--operation mode is arithmetic
YD1L9_cout_1 = YD1_safe_q[2] & (!YD1L6);
YD1L9 = CARRY(YD1L9_cout_1);
--YD1_safe_q[3] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[3] at LC_X50_Y24_N4
--operation mode is arithmetic
YD1_safe_q[3]_lut_out = YD1_safe_q[3] $ (T1_rd_wfifo & YD1L8);
YD1_safe_q[3] = DFFEAS(YD1_safe_q[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD1L11 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella3~COUT at LC_X50_Y24_N4
--operation mode is arithmetic
--YD1_safe_q[4] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[4] at LC_X50_Y24_N5
--operation mode is arithmetic
YD1_safe_q[4]_carry_eqn = (!YD1L11 & GND) # (YD1L11 & VCC);
YD1_safe_q[4]_lut_out = YD1_safe_q[4] $ (T1_rd_wfifo & !YD1_safe_q[4]_carry_eqn);
YD1_safe_q[4] = DFFEAS(YD1_safe_q[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YD1L15 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella4~COUT at LC_X50_Y24_N5
--operation mode is arithmetic
YD1L15_cout_0 = YD1_safe_q[4] & (!YD1L11);
YD1L15 = CARRY(YD1L15_cout_0);
--YD1L16 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|counter_cella4~COUTCOUT1_8 at LC_X50_Y24_N5
--operation mode is arithmetic
YD1L16_cout_1 = YD1_safe_q[4] & (!YD1L11);
YD1L16 = CARRY(YD1L16_cout_1);
--YD1_safe_q[5] is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count|safe_q[5] at LC_X50_Y24_N6
--operation mode is normal
YD1_safe_q[5]_carry_eqn = (!YD1L11 & YD1L15) # (YD1L11 & YD1L16);
YD1_safe_q[5]_lut_out = YD1_safe_q[5] $ (T1_rd_wfifo & YD1_safe_q[5]_carry_eqn);
YD1_safe_q[5] = DFFEAS(YD1_safe_q[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--DD1_internal_jdo1[1] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[1] at LC_X30_Y27_N2
--operation mode is normal
DD1_internal_jdo1[1] = AMPP_FUNCTION(!A1L9, DD1_sr[1], VCC, DD1L144);
--TC1_break_readreg[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[2] at LC_X32_Y26_N6
--operation mode is normal
TC1_break_readreg[2] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[2], DD1_internal_jdo1[36], DD1L188, DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L128 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux37~14 at LC_X33_Y26_N4
--operation mode is normal
DD1L128 = AMPP_FUNCTION(DD1_ir[0], TC1_break_readreg[2], CD1_internal_MonDReg[2], DD1_ir[1]);
--TC1_break_readreg[24] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[24] at LC_X36_Y29_N6
--operation mode is normal
TC1_break_readreg[24] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[24], DD1_internal_jdo1[36], DD1_internal_jdo1[37], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L34 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19930 at LC_X36_Y28_N2
--operation mode is normal
DD1L34 = AMPP_FUNCTION(CD1_internal_MonDReg[24], TC1_break_readreg[24], DD1_ir[1]);
--DD1L35 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19931 at LC_X32_Y27_N3
--operation mode is normal
DD1L35 = AMPP_FUNCTION(DD1L143, DD1L34, DD1_ir[1], DD1_ir[0]);
--GE1_stage_5 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|stage_5 at LC_X39_Y9_N2
--operation mode is normal
GE1_stage_5_lut_out = GE1_full_6 & GE1_stage_6 # !GE1_full_6 & (GB1L25);
GE1_stage_5 = DFFEAS(GE1_stage_5_lut_out, GLOBAL(DE1__clk0), VCC, , GE1L21, , , , );
--GE1_full_5 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_5 at LC_X45_Y9_N6
--operation mode is normal
GE1_full_5_lut_out = GB1L34 & (GE1_full_4) # !GB1L34 & (FB1_za_valid & (GE1_full_6) # !FB1_za_valid & GE1_full_4);
GE1_full_5 = DFFEAS(GE1_full_5_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FE1L13, , , , );
--GE1L22 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process4~1 at LC_X44_Y9_N2
--operation mode is normal
GE1L22 = FB1_za_valid # !GE1_full_4 & (GB1L34);
--FE1_stage_5 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|stage_5 at LC_X39_Y9_N4
--operation mode is normal
FE1_stage_5_lut_out = GE1_full_6 & (FE1_stage_6) # !GE1_full_6 & (GB1L20);
FE1_stage_5 = DFFEAS(FE1_stage_5_lut_out, GLOBAL(DE1__clk0), VCC, , GE1L21, , , , );
--TB1_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_in_d1 at LC_X48_Y24_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
TB1_data_in_d1_lut_out = GND;
TB1_data_in_d1 = DFFEAS(TB1_data_in_d1_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , YB1_internal_slave_read_request, , , VCC);
--UB1_data_in_d1 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_in_d1 at LC_X48_Y20_N3
--operation mode is normal
UB1_data_in_d1_lut_out = YB1_internal_slave_write_request;
UB1_data_in_d1 = DFFEAS(UB1_data_in_d1_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--TC1_break_readreg[23] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[23] at LC_X36_Y29_N4
--operation mode is normal
TC1_break_readreg[23] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[23], DD1_internal_jdo1[36], DD1_internal_jdo1[37], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L36 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19933 at LC_X31_Y28_N7
--operation mode is normal
DD1L36 = AMPP_FUNCTION(DD1_ir[1], CD1_internal_MonDReg[23], TC1_break_readreg[23]);
--DD1L37 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19934 at LC_X31_Y28_N5
--operation mode is normal
DD1L37 = AMPP_FUNCTION(DD1L144, DD1_ir[0], DD1L36, DD1L142);
--DD1L38 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19935 at LC_X31_Y28_N8
--operation mode is normal
DD1L38 = AMPP_FUNCTION(DD1L36, DD1_ir[0], DD1L144, A1L5);
--QD1L58 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3510 at LC_X35_Y24_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1L58 = AMPP_FUNCTION(QD1_count[9], QD1_td_shift[7]);
--QD1_rdata[4] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[4] at LC_X35_Y24_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_rdata[4] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[4], E1_data_out, GND, QD1L18);
--H1_slave_nativeaddress_d1[0] is std_1s10:inst|clock_0:the_clock_0|slave_nativeaddress_d1[0] at LC_X47_Y19_N4
--operation mode is normal
H1_slave_nativeaddress_d1[0]_lut_out = L1_M_alu_result[2];
H1_slave_nativeaddress_d1[0] = DFFEAS(H1_slave_nativeaddress_d1[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--H1_master_writedata[2] is std_1s10:inst|clock_0:the_clock_0|master_writedata[2] at LC_X51_Y22_N2
--operation mode is normal
H1_master_writedata[2]_lut_out = H1_slave_writedata_d1[2];
H1_master_writedata[2] = DFFEAS(H1_master_writedata[2]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--H1_master_nativeaddress[2] is std_1s10:inst|clock_0:the_clock_0|master_nativeaddress[2] at LC_X50_Y20_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_master_nativeaddress[2]_lut_out = GND;
H1_master_nativeaddress[2] = DFFEAS(H1_master_nativeaddress[2]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , H1_slave_nativeaddress_d1[2], , , VCC);
--BB1L1 is std_1s10:inst|pll:the_pll|control_reg_en~18 at LC_X50_Y20_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_master_nativeaddress[1]_qfbk = H1_master_nativeaddress[1];
BB1L1 = WB1_master_state[2] & H1_master_nativeaddress[0] & !H1_master_nativeaddress[1]_qfbk & !H1_master_nativeaddress[2];
--H1_master_nativeaddress[1] is std_1s10:inst|clock_0:the_clock_0|master_nativeaddress[1] at LC_X50_Y20_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_master_nativeaddress[1] = DFFEAS(BB1L1, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , H1_slave_nativeaddress_d1[1], , , VCC);
--JE1_delayed_unxsync_rxdxx2 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|delayed_unxsync_rxdxx2 at LC_X41_Y29_N7
--operation mode is normal
JE1_delayed_unxsync_rxdxx2_lut_out = JE1_sync_rxd;
JE1_delayed_unxsync_rxdxx2 = DFFEAS(JE1_delayed_unxsync_rxdxx2_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--JE1_baud_rate_counter[0] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[0] at LC_X41_Y27_N0
--operation mode is normal
JE1_baud_rate_counter[0]_lut_out = JE1_baud_rate_counter[0] & (JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2) # !JE1_baud_rate_counter[0] & (JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2 # !JE1L46);
JE1_baud_rate_counter[0] = DFFEAS(JE1_baud_rate_counter[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--JE1_baud_rate_counter[1] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[1] at LC_X41_Y27_N8
--operation mode is normal
JE1_baud_rate_counter[1]_lut_out = JE1L46 & (JE1_delayed_unxsync_rxdxx2 $ !JE1_sync_rxd) # !JE1L46 & JE1L2 & (JE1_delayed_unxsync_rxdxx2 $ !JE1_sync_rxd);
JE1_baud_rate_counter[1] = DFFEAS(JE1_baud_rate_counter[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--JE1_baud_rate_counter[2] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[2] at LC_X41_Y27_N6
--operation mode is normal
JE1_baud_rate_counter[2]_lut_out = JE1L5 & !JE1L46 & (JE1_sync_rxd $ !JE1_delayed_unxsync_rxdxx2);
JE1_baud_rate_counter[2] = DFFEAS(JE1_baud_rate_counter[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--JE1_baud_rate_counter[3] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[3] at LC_X41_Y27_N3
--operation mode is normal
JE1_baud_rate_counter[3]_lut_out = JE1L8 & (JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2 # !JE1L46) # !JE1L8 & (JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2);
JE1_baud_rate_counter[3] = DFFEAS(JE1_baud_rate_counter[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--JE1L44 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Equal0~166 at LC_X41_Y27_N4
--operation mode is normal
JE1L44 = !JE1_baud_rate_counter[0] & !JE1_baud_rate_counter[2] & !JE1_baud_rate_counter[3] & !JE1_baud_rate_counter[1];
--JE1_baud_rate_counter[4] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[4] at LC_X41_Y27_N7
--operation mode is normal
JE1_baud_rate_counter[4]_lut_out = JE1L46 # JE1L11 # JE1_delayed_unxsync_rxdxx2 $ JE1_sync_rxd;
JE1_baud_rate_counter[4] = DFFEAS(JE1_baud_rate_counter[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--JE1_baud_rate_counter[5] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[5] at LC_X41_Y28_N9
--operation mode is normal
JE1_baud_rate_counter[5]_lut_out = JE1L15 & (JE1_delayed_unxsync_rxdxx2 $ (!JE1_sync_rxd)) # !JE1L15 & JE1L46 & (JE1_delayed_unxsync_rxdxx2 $ !JE1_sync_rxd);
JE1_baud_rate_counter[5] = DFFEAS(JE1_baud_rate_counter[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--JE1_baud_rate_counter[6] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[6] at LC_X41_Y29_N3
--operation mode is normal
JE1_baud_rate_counter[6]_lut_out = JE1L46 & (JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2) # !JE1L46 & (JE1L18 # JE1_sync_rxd $ JE1_delayed_unxsync_rxdxx2);
JE1_baud_rate_counter[6] = DFFEAS(JE1_baud_rate_counter[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--JE1_baud_rate_counter[7] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[7] at LC_X41_Y29_N2
--operation mode is normal
JE1_baud_rate_counter[7]_lut_out = JE1L21 # JE1L46 # JE1_delayed_unxsync_rxdxx2 $ JE1_sync_rxd;
JE1_baud_rate_counter[7] = DFFEAS(JE1_baud_rate_counter[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--JE1L45 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Equal0~167 at LC_X41_Y29_N9
--operation mode is normal
JE1L45 = !JE1_baud_rate_counter[6] & !JE1_baud_rate_counter[4] & !JE1_baud_rate_counter[5] & !JE1_baud_rate_counter[7];
--JE1_rxd_edge is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|rxd_edge at LC_X41_Y27_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_sync_rxd_qfbk = JE1_sync_rxd;
JE1_rxd_edge = JE1_sync_rxd_qfbk $ JE1_delayed_unxsync_rxdxx2;
--JE1_sync_rxd is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|sync_rxd at LC_X41_Y27_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_sync_rxd = DFFEAS(JE1_rxd_edge, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , JE1_d1_source_rxd, , , VCC);
--JE1_baud_rate_counter[8] is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|baud_rate_counter[8] at LC_X41_Y27_N9
--operation mode is normal
JE1_baud_rate_counter[8]_lut_out = JE1L46 & (JE1_delayed_unxsync_rxdxx2 $ !JE1_sync_rxd) # !JE1L46 & JE1L24 & (JE1_delayed_unxsync_rxdxx2 $ !JE1_sync_rxd);
JE1_baud_rate_counter[8] = DFFEAS(JE1_baud_rate_counter[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--JE1_d1_source_rxd is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|d1_source_rxd at LC_X41_Y22_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
JE1_d1_source_rxd_lut_out = GND;
JE1_d1_source_rxd = DFFEAS(JE1_d1_source_rxd_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , rxd_to_the_uart1, , , VCC);
--CD1L93 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonRd~104 at LC_X32_Y24_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
CD1L93 = AMPP_FUNCTION(P1L30);
--VC1_resetrequest is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|resetrequest at LC_X32_Y24_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
VC1_resetrequest = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[22], !C1_CLR_SIGNAL, GND, DD1L190);
--TC1_break_readreg[3] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[3] at LC_X36_Y29_N1
--operation mode is normal
TC1_break_readreg[3] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[3], DD1_internal_jdo1[37], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L127 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux36~14 at LC_X36_Y28_N7
--operation mode is normal
DD1L127 = AMPP_FUNCTION(CD1_internal_MonDReg[3], DD1_ir[0], TC1_break_readreg[3], DD1_ir[1]);
--TC1_break_readreg[4] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[4] at LC_X36_Y29_N0
--operation mode is normal
TC1_break_readreg[4] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[37], DD1_internal_jdo1[4], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L126 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux35~14 at LC_X36_Y28_N0
--operation mode is normal
DD1L126 = AMPP_FUNCTION(DD1_ir[1], DD1_ir[0], TC1_break_readreg[4], CD1_internal_MonDReg[4]);
--TC1_break_readreg[5] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[5] at LC_X36_Y29_N8
--operation mode is normal
TC1_break_readreg[5] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[5], DD1_internal_jdo1[36], DD1_internal_jdo1[37], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L125 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux34~14 at LC_X36_Y28_N9
--operation mode is normal
DD1L125 = AMPP_FUNCTION(CD1_internal_MonDReg[5], DD1_ir[0], TC1_break_readreg[5], DD1_ir[1]);
--TC1_break_readreg[6] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[6] at LC_X32_Y26_N3
--operation mode is normal
TC1_break_readreg[6] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[37], DD1L188, DD1_internal_jdo1[36], DD1_internal_jdo1[6], !C1_CLR_SIGNAL, DD1L188);
--DD1L124 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux33~12 at LC_X36_Y28_N6
--operation mode is normal
DD1L124 = AMPP_FUNCTION(DD1_ir[1], DD1_ir[0], TC1_break_readreg[6], CD1_internal_MonDReg[6]);
--DD1L138 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux44~41 at LC_X32_Y29_N2
--operation mode is normal
DD1L138 = AMPP_FUNCTION(DD1_DRsize[1], DD1_DRsize[0], DD1_DRsize[2]);
--TC1_break_readreg[7] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[7] at LC_X36_Y29_N3
--operation mode is normal
TC1_break_readreg[7] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[7], DD1_internal_jdo1[36], DD1_internal_jdo1[37], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L123 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux32~14 at LC_X36_Y28_N1
--operation mode is normal
DD1L123 = AMPP_FUNCTION(CD1_internal_MonDReg[7], DD1_ir[0], TC1_break_readreg[7], DD1_ir[1]);
--TC1_break_readreg[8] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[8] at LC_X36_Y29_N2
--operation mode is normal
TC1_break_readreg[8] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[37], DD1_internal_jdo1[8], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L39 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19941 at LC_X36_Y28_N3
--operation mode is normal
DD1L39 = AMPP_FUNCTION(DD1_ir[1], DD1_ir[0], CD1_internal_MonDReg[8], TC1_break_readreg[8]);
--TC1_break_readreg[9] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[9] at LC_X36_Y29_N5
--operation mode is normal
TC1_break_readreg[9] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[37], DD1_internal_jdo1[9], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L40 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19943 at LC_X36_Y28_N4
--operation mode is normal
DD1L40 = AMPP_FUNCTION(DD1_ir[1], DD1_ir[0], CD1_internal_MonDReg[9], TC1_break_readreg[9]);
--TC1_break_readreg[25] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[25] at LC_X36_Y29_N7
--operation mode is normal
TC1_break_readreg[25] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[25], DD1_internal_jdo1[36], DD1_internal_jdo1[37], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L41 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19945 at LC_X33_Y26_N5
--operation mode is normal
DD1L41 = AMPP_FUNCTION(CD1_internal_MonDReg[25], TC1_break_readreg[25], DD1_ir[1]);
--DD1L42 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19946 at LC_X31_Y28_N2
--operation mode is normal
DD1L42 = AMPP_FUNCTION(DD1L41, DD1_ir[0], DD1L144, DD1L142);
--DD1L43 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19947 at LC_X33_Y26_N1
--operation mode is normal
DD1L43 = AMPP_FUNCTION(A1L5, DD1L41, DD1L144, DD1_ir[0]);
--TC1_break_readreg[26] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[26] at LC_X36_Y29_N9
--operation mode is normal
TC1_break_readreg[26] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[37], DD1_internal_jdo1[26], DD1_internal_jdo1[36], DD1L188, !C1_CLR_SIGNAL, DD1L188);
--DD1L44 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19949 at LC_X33_Y26_N2
--operation mode is normal
DD1L44 = AMPP_FUNCTION(CD1_internal_MonDReg[26], TC1_break_readreg[26], DD1_ir[1]);
--DD1L45 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19950 at LC_X33_Y26_N6
--operation mode is normal
DD1L45 = AMPP_FUNCTION(DD1_ir[0], DD1L142, DD1L144, DD1L44);
--DD1L46 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19951 at LC_X33_Y26_N0
--operation mode is normal
DD1L46 = AMPP_FUNCTION(DD1_ir[0], DD1L44, DD1L144, A1L5);
--TC1_break_readreg[27] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[27] at LC_X35_Y28_N1
--operation mode is normal
TC1_break_readreg[27] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[36], DD1_internal_jdo1[27], DD1L188, DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L47 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19953 at LC_X33_Y27_N3
--operation mode is normal
DD1L47 = AMPP_FUNCTION(CD1_internal_MonDReg[27], TC1_break_readreg[27], DD1_ir[1]);
--DD1L48 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19954 at LC_X33_Y27_N4
--operation mode is normal
DD1L48 = AMPP_FUNCTION(DD1_ir[0], DD1L143, DD1_ir[1], DD1L47);
--TC1_break_readreg[28] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[28] at LC_X35_Y28_N4
--operation mode is normal
TC1_break_readreg[28] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[36], DD1_internal_jdo1[28], DD1L188, DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L49 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19956 at LC_X36_Y27_N2
--operation mode is normal
DD1L49 = AMPP_FUNCTION(DD1_ir[1], TC1_break_readreg[28], CD1_internal_MonDReg[28]);
--DD1L50 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19957 at LC_X33_Y27_N9
--operation mode is normal
DD1L50 = AMPP_FUNCTION(DD1_ir[0], DD1L49, DD1L144, DD1L142);
--DD1L51 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19958 at LC_X33_Y27_N7
--operation mode is normal
DD1L51 = AMPP_FUNCTION(A1L5, DD1L49, DD1L144, DD1_ir[0]);
--TC1_break_readreg[29] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[29] at LC_X35_Y28_N5
--operation mode is normal
TC1_break_readreg[29] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[36], DD1_internal_jdo1[29], DD1L188, DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L52 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19960 at LC_X33_Y27_N2
--operation mode is normal
DD1L52 = AMPP_FUNCTION(CD1_internal_MonDReg[29], TC1_break_readreg[29], DD1_ir[1]);
--DD1L53 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19961 at LC_X33_Y27_N1
--operation mode is normal
DD1L53 = AMPP_FUNCTION(DD1_ir[0], DD1L143, DD1_ir[1], DD1L52);
--DD1L134 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux42~95 at LC_X34_Y26_N2
--operation mode is normal
DD1L134 = AMPP_FUNCTION(altera_internal_jtag, DD1_DRsize[0], DD1_DRsize[1], DD1_DRsize[2]);
--DD1L135 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux42~96 at LC_X34_Y26_N7
--operation mode is normal
DD1L135 = AMPP_FUNCTION(DD1_sr[32], DD1_DRsize[0], DD1_DRsize[1], DD1_DRsize[2]);
--DD1L54 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19963 at LC_X34_Y26_N9
--operation mode is normal
DD1L54 = AMPP_FUNCTION(A1L5, DD1L144, DD1L135, DD1L134);
--DD1L136 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux42~97 at LC_X34_Y26_N3
--operation mode is normal
DD1L136 = AMPP_FUNCTION(DD1L135, DD1L134);
--TC1_break_readreg[30] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[30] at LC_X34_Y26_N0
--operation mode is normal
TC1_break_readreg[30] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[30], DD1_internal_jdo1[37], DD1L188, DD1_internal_jdo1[36], !C1_CLR_SIGNAL, DD1L188);
--DD1L55 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19964 at LC_X34_Y26_N1
--operation mode is normal
DD1L55 = AMPP_FUNCTION(CD1_internal_MonDReg[30], DD1_ir[1], TC1_break_readreg[30]);
--TC1_break_readreg[31] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[31] at LC_X35_Y28_N9
--operation mode is normal
TC1_break_readreg[31] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[36], DD1_internal_jdo1[31], DD1L188, DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L56 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19965 at LC_X34_Y26_N5
--operation mode is normal
DD1L56 = AMPP_FUNCTION(CD1_internal_MonDReg[31], DD1_ir[1], TC1_break_readreg[31]);
--DD1L57 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19966 at LC_X33_Y26_N3
--operation mode is normal
DD1L57 = AMPP_FUNCTION(DD1L56, DD1L142, DD1L144, DD1_ir[0]);
--DD1L58 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19967 at LC_X33_Y24_N6
--operation mode is normal
DD1L58 = AMPP_FUNCTION(A1L5, DD1L144, DD1_ir[0], DD1L56);
--VC1_internal_resetlatch is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_resetlatch at LC_X33_Y24_N2
--operation mode is normal
VC1_internal_resetlatch = AMPP_FUNCTION(DE1__clk0, DD1L190, VC1L9, DD1_internal_jdo1[24], VC1_internal_resetlatch, VCC);
--DD1L59 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19969 at LC_X33_Y24_N0
--operation mode is normal
DD1L59 = AMPP_FUNCTION(DD1_ir[0], DD1_ir[1], VC1_internal_resetlatch);
--QD1L59 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3512 at LC_X34_Y24_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1L59 = AMPP_FUNCTION(QD1_td_shift[8], QD1_count[9]);
--QD1_rdata[5] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[5] at LC_X34_Y24_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_rdata[5] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[5], E1_data_out, GND, QD1L18);
--H1_master_writedata[3] is std_1s10:inst|clock_0:the_clock_0|master_writedata[3] at LC_X45_Y8_N2
--operation mode is normal
H1_master_writedata[3]_lut_out = H1_slave_writedata_d1[3];
H1_master_writedata[3] = DFFEAS(H1_master_writedata[3]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--H1_master_writedata[7] is std_1s10:inst|clock_0:the_clock_0|master_writedata[7] at LC_X50_Y21_N2
--operation mode is normal
H1_master_writedata[7]_lut_out = H1_slave_writedata_d1[7];
H1_master_writedata[7] = DFFEAS(H1_master_writedata[7]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--GC1L14 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~569 at LC_X14_Y10_N1
--operation mode is arithmetic
GC1L14 = AMPP_FUNCTION(L1L696, L1L630, GC1L17);
--GC1L15 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~569COUT1_793 at LC_X14_Y10_N1
--operation mode is arithmetic
GC1L15 = AMPP_FUNCTION(L1L696, L1L630, GC1L18);
--QD1_rdata[6] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[6] at LC_X35_Y23_N5
--operation mode is normal
QD1_rdata[6] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[6], E1_data_out, QD1L18);
--H1_master_writedata[4] is std_1s10:inst|clock_0:the_clock_0|master_writedata[4] at LC_X50_Y25_N2
--operation mode is normal
H1_master_writedata[4]_lut_out = H1_slave_writedata_d1[4];
H1_master_writedata[4] = DFFEAS(H1_master_writedata[4]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--H1_master_writedata[15] is std_1s10:inst|clock_0:the_clock_0|master_writedata[15] at LC_X50_Y11_N4
--operation mode is normal
H1_master_writedata[15]_lut_out = H1_slave_writedata_d1[15];
H1_master_writedata[15] = DFFEAS(H1_master_writedata[15]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--TC1_break_readreg[10] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[10] at LC_X35_Y28_N6
--operation mode is normal
TC1_break_readreg[10] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[10], DD1L188, DD1_internal_jdo1[36], DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L60 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19971 at LC_X36_Y28_N5
--operation mode is normal
DD1L60 = AMPP_FUNCTION(DD1_ir[1], DD1_ir[0], CD1_internal_MonDReg[10], TC1_break_readreg[10]);
--TC1_break_readreg[11] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[11] at LC_X35_Y28_N0
--operation mode is normal
TC1_break_readreg[11] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[11], DD1L188, DD1_internal_jdo1[36], DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L61 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19973 at LC_X36_Y28_N8
--operation mode is normal
DD1L61 = AMPP_FUNCTION(DD1_ir[1], DD1_ir[0], CD1_internal_MonDReg[11], TC1_break_readreg[11]);
--TC1_break_readreg[12] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[12] at LC_X35_Y28_N7
--operation mode is normal
TC1_break_readreg[12] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[36], DD1_internal_jdo1[12], DD1L188, DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L62 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19975 at LC_X36_Y27_N6
--operation mode is normal
DD1L62 = AMPP_FUNCTION(DD1_ir[1], DD1_ir[0], TC1_break_readreg[12], CD1_internal_MonDReg[12]);
--TC1_break_readreg[13] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[13] at LC_X35_Y28_N8
--operation mode is normal
TC1_break_readreg[13] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[36], DD1_internal_jdo1[13], DD1L188, DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L63 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19977 at LC_X36_Y27_N4
--operation mode is normal
DD1L63 = AMPP_FUNCTION(DD1_ir[1], DD1_ir[0], CD1_internal_MonDReg[13], TC1_break_readreg[13]);
--TC1_break_readreg[14] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[14] at LC_X35_Y28_N3
--operation mode is normal
TC1_break_readreg[14] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[14], DD1L188, DD1_internal_jdo1[36], DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L122 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux25~50 at LC_X36_Y27_N5
--operation mode is normal
DD1L122 = AMPP_FUNCTION(DD1_ir[1], DD1_ir[0], CD1_internal_MonDReg[14], TC1_break_readreg[14]);
--DD1L137 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|Mux43~41 at LC_X32_Y29_N6
--operation mode is normal
DD1L137 = AMPP_FUNCTION(DD1_DRsize[1], DD1_DRsize[0], DD1_DRsize[2]);
--TC1_break_readreg[15] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[15] at LC_X35_Y28_N2
--operation mode is normal
TC1_break_readreg[15] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[15], DD1L188, DD1_internal_jdo1[36], DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L64 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19979 at LC_X33_Y26_N8
--operation mode is normal
DD1L64 = AMPP_FUNCTION(CD1_internal_MonDReg[15], TC1_break_readreg[15], DD1_ir[1]);
--DD1L65 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19980 at LC_X33_Y26_N7
--operation mode is normal
DD1L65 = AMPP_FUNCTION(DD1_ir[0], DD1L142, DD1L144, DD1L64);
--DD1L66 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19981 at LC_X33_Y26_N9
--operation mode is normal
DD1L66 = AMPP_FUNCTION(DD1_ir[0], DD1L64, DD1L144, A1L5);
--TC1_break_readreg[16] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break|break_readreg[16] at LC_X33_Y25_N2
--operation mode is normal
TC1_break_readreg[16] = AMPP_FUNCTION(DE1__clk0, DD1_internal_jdo1[16], DD1_internal_jdo1[36], DD1L188, DD1_internal_jdo1[37], !C1_CLR_SIGNAL, DD1L188);
--DD1L67 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19983 at LC_X33_Y25_N9
--operation mode is normal
DD1L67 = AMPP_FUNCTION(DD1_ir[1], CD1_internal_MonDReg[16], TC1_break_readreg[16]);
--DD1L68 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19984 at LC_X33_Y25_N6
--operation mode is normal
DD1L68 = AMPP_FUNCTION(DD1L144, DD1_ir[0], DD1L142, DD1L67);
--DD1L69 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19985 at LC_X33_Y25_N4
--operation mode is normal
DD1L69 = AMPP_FUNCTION(A1L5, DD1_ir[0], DD1L144, DD1L67);
--H1_master_writedata[14] is std_1s10:inst|clock_0:the_clock_0|master_writedata[14] at LC_X50_Y23_N2
--operation mode is normal
H1_master_writedata[14]_lut_out = H1_slave_writedata_d1[14];
H1_master_writedata[14] = DFFEAS(H1_master_writedata[14]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--H1_master_writedata[13] is std_1s10:inst|clock_0:the_clock_0|master_writedata[13] at LC_X51_Y19_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_master_writedata[13]_lut_out = GND;
H1_master_writedata[13] = DFFEAS(H1_master_writedata[13]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , H1_slave_writedata_d1[13], , , VCC);
--H1_master_writedata[12] is std_1s10:inst|clock_0:the_clock_0|master_writedata[12] at LC_X51_Y19_N3
--operation mode is normal
H1_master_writedata[12]_lut_out = H1_slave_writedata_d1[12];
H1_master_writedata[12] = DFFEAS(H1_master_writedata[12]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--H1_master_writedata[11] is std_1s10:inst|clock_0:the_clock_0|master_writedata[11] at LC_X51_Y19_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_master_writedata[11]_lut_out = GND;
H1_master_writedata[11] = DFFEAS(H1_master_writedata[11]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , H1_slave_writedata_d1[11], , , VCC);
--H1_master_writedata[10] is std_1s10:inst|clock_0:the_clock_0|master_writedata[10] at LC_X51_Y19_N9
--operation mode is normal
H1_master_writedata[10]_lut_out = H1_slave_writedata_d1[10];
H1_master_writedata[10] = DFFEAS(H1_master_writedata[10]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--H1_master_writedata[9] is std_1s10:inst|clock_0:the_clock_0|master_writedata[9] at LC_X51_Y19_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_master_writedata[9]_lut_out = GND;
H1_master_writedata[9] = DFFEAS(H1_master_writedata[9]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , H1_slave_writedata_d1[9], , , VCC);
--H1_master_writedata[8] is std_1s10:inst|clock_0:the_clock_0|master_writedata[8] at LC_X51_Y20_N3
--operation mode is normal
H1_master_writedata[8]_lut_out = H1_slave_writedata_d1[8];
H1_master_writedata[8] = DFFEAS(H1_master_writedata[8]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--H1_master_writedata[5] is std_1s10:inst|clock_0:the_clock_0|master_writedata[5] at LC_X51_Y20_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_master_writedata[5]_lut_out = GND;
H1_master_writedata[5] = DFFEAS(H1_master_writedata[5]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , H1_slave_writedata_d1[5], , , VCC);
--H1_master_writedata[6] is std_1s10:inst|clock_0:the_clock_0|master_writedata[6] at LC_X51_Y20_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_master_writedata[6]_lut_out = GND;
H1_master_writedata[6] = DFFEAS(H1_master_writedata[6]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , H1_slave_writedata_d1[6], , , VCC);
--BB1_control_reg_out[0] is std_1s10:inst|pll:the_pll|control_reg_out[0] at LC_X51_Y20_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
BB1_control_reg_out[0]_lut_out = GND;
BB1_control_reg_out[0] = DFFEAS(BB1_control_reg_out[0]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, H1_master_writedata[0], , , VCC);
--QD1_td_shift[5] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[5] at LC_X35_Y24_N0
--operation mode is normal
QD1_td_shift[5] = AMPP_FUNCTION(!A1L6, QD1L63, QD1L61, QD1L53, !C1_CLR_SIGNAL, QD1L52);
--BB1_control_reg_out[1] is std_1s10:inst|pll:the_pll|control_reg_out[1] at LC_X51_Y20_N2
--operation mode is normal
BB1_control_reg_out[1]_lut_out = !H1_master_writedata[1];
BB1_control_reg_out[1] = DFFEAS(BB1_control_reg_out[1]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , BB1L1, , , , );
--QD1L60 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3514 at LC_X35_Y24_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1L60 = AMPP_FUNCTION(QD1_count[9], QD1_td_shift[5]);
--QD1_rdata[2] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[2] at LC_X35_Y24_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_rdata[2] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[2], E1_data_out, GND, QD1L18);
--QD1_count[5] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[5] at LC_X35_Y23_N4
--operation mode is normal
QD1_count[5] = AMPP_FUNCTION(!A1L6, QD1_count[4], RE1_state[4], !C1_CLR_SIGNAL, QD1L52);
--DD1_internal_jdo1[2] is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|internal_jdo1[2] at LC_X33_Y29_N7
--operation mode is normal
DD1_internal_jdo1[2] = AMPP_FUNCTION(!A1L9, DD1_sr[2], VCC, DD1L144);
--GE1_full_6 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|full_6 at LC_X45_Y9_N0
--operation mode is normal
GE1_full_6_lut_out = GE1_full_5 & (GB1L34 # !FB1_za_valid);
GE1_full_6 = DFFEAS(GE1_full_6_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , FE1L13, , , , );
--GE1L21 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process2~1 at LC_X45_Y9_N7
--operation mode is normal
GE1L21 = FB1_za_valid # GB1L34 & !GE1_full_5;
--YB1_internal_slave_read_request is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_read_request at LC_X48_Y20_N7
--operation mode is normal
YB1_internal_slave_read_request_lut_out = YB1_internal_slave_read_request $ (YB1L2 & J1L1);
YB1_internal_slave_read_request = DFFEAS(YB1_internal_slave_read_request_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--YB1_internal_slave_write_request is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_write_request at LC_X48_Y20_N9
--operation mode is normal
YB1_internal_slave_write_request_lut_out = YB1_internal_slave_write_request $ (YB1L2 & YB1L4);
YB1_internal_slave_write_request = DFFEAS(YB1_internal_slave_write_request_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--H1_slave_writedata_d1[2] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[2] at LC_X51_Y22_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_writedata_d1[2]_lut_out = GND;
H1_slave_writedata_d1[2] = DFFEAS(H1_slave_writedata_d1[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , L1_M_st_data[2], , , VCC);
--H1_slave_nativeaddress_d1[1] is std_1s10:inst|clock_0:the_clock_0|slave_nativeaddress_d1[1] at LC_X50_Y10_N4
--operation mode is normal
H1_slave_nativeaddress_d1[1]_lut_out = L1_M_alu_result[3];
H1_slave_nativeaddress_d1[1] = DFFEAS(H1_slave_nativeaddress_d1[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--H1_slave_nativeaddress_d1[2] is std_1s10:inst|clock_0:the_clock_0|slave_nativeaddress_d1[2] at LC_X50_Y10_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_nativeaddress_d1[2]_lut_out = GND;
H1_slave_nativeaddress_d1[2] = DFFEAS(H1_slave_nativeaddress_d1[2]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , L1_M_alu_result[4], , , VCC);
--JE1L46 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Equal0~168 at LC_X41_Y27_N5
--operation mode is normal
JE1L46 = !JE1_baud_rate_counter[8] & (JE1L45 & JE1L44);
--JE1L2 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~164 at LC_X41_Y28_N1
--operation mode is arithmetic
JE1L2 = JE1_baud_rate_counter[1] $ (!JE1L26);
--JE1L3 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~165 at LC_X41_Y28_N1
--operation mode is arithmetic
JE1L3_cout_0 = !JE1_baud_rate_counter[1] & (!JE1L26);
JE1L3 = CARRY(JE1L3_cout_0);
--JE1L4 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~165COUT1_219 at LC_X41_Y28_N1
--operation mode is arithmetic
JE1L4_cout_1 = !JE1_baud_rate_counter[1] & (!JE1L27);
JE1L4 = CARRY(JE1L4_cout_1);
--JE1L5 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~166 at LC_X41_Y28_N2
--operation mode is arithmetic
JE1L5 = JE1_baud_rate_counter[2] $ (JE1L3);
--JE1L6 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~167 at LC_X41_Y28_N2
--operation mode is arithmetic
JE1L6_cout_0 = JE1_baud_rate_counter[2] # !JE1L3;
JE1L6 = CARRY(JE1L6_cout_0);
--JE1L7 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~167COUT1_221 at LC_X41_Y28_N2
--operation mode is arithmetic
JE1L7_cout_1 = JE1_baud_rate_counter[2] # !JE1L4;
JE1L7 = CARRY(JE1L7_cout_1);
--JE1L8 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~168 at LC_X41_Y28_N3
--operation mode is arithmetic
JE1L8 = JE1_baud_rate_counter[3] $ !JE1L6;
--JE1L9 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~169 at LC_X41_Y28_N3
--operation mode is arithmetic
JE1L9_cout_0 = !JE1_baud_rate_counter[3] & !JE1L6;
JE1L9 = CARRY(JE1L9_cout_0);
--JE1L10 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~169COUT1_223 at LC_X41_Y28_N3
--operation mode is arithmetic
JE1L10_cout_1 = !JE1_baud_rate_counter[3] & !JE1L7;
JE1L10 = CARRY(JE1L10_cout_1);
--JE1L11 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~170 at LC_X41_Y28_N4
--operation mode is arithmetic
JE1L11 = JE1_baud_rate_counter[4] $ JE1L9;
--JE1L12 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~171 at LC_X41_Y28_N4
--operation mode is arithmetic
--JE1L15 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~172 at LC_X41_Y28_N5
--operation mode is arithmetic
JE1L15_carry_eqn = (!JE1L12 & GND) # (JE1L12 & VCC);
JE1L15 = JE1_baud_rate_counter[5] $ !JE1L15_carry_eqn;
--JE1L16 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~173 at LC_X41_Y28_N5
--operation mode is arithmetic
JE1L16_cout_0 = !JE1_baud_rate_counter[5] & !JE1L12;
JE1L16 = CARRY(JE1L16_cout_0);
--JE1L17 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~173COUT1_225 at LC_X41_Y28_N5
--operation mode is arithmetic
JE1L17_cout_1 = !JE1_baud_rate_counter[5] & !JE1L12;
JE1L17 = CARRY(JE1L17_cout_1);
--JE1L18 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~174 at LC_X41_Y28_N6
--operation mode is arithmetic
JE1L18_carry_eqn = (!JE1L12 & JE1L16) # (JE1L12 & JE1L17);
JE1L18 = JE1_baud_rate_counter[6] $ (JE1L18_carry_eqn);
--JE1L19 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~175 at LC_X41_Y28_N6
--operation mode is arithmetic
JE1L19_cout_0 = JE1_baud_rate_counter[6] # !JE1L16;
JE1L19 = CARRY(JE1L19_cout_0);
--JE1L20 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~175COUT1_227 at LC_X41_Y28_N6
--operation mode is arithmetic
JE1L20_cout_1 = JE1_baud_rate_counter[6] # !JE1L17;
JE1L20 = CARRY(JE1L20_cout_1);
--JE1L21 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~176 at LC_X41_Y28_N7
--operation mode is arithmetic
JE1L21_carry_eqn = (!JE1L12 & JE1L19) # (JE1L12 & JE1L20);
JE1L21 = JE1_baud_rate_counter[7] $ !JE1L21_carry_eqn;
--JE1L22 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~177 at LC_X41_Y28_N7
--operation mode is arithmetic
JE1L22_cout_0 = !JE1_baud_rate_counter[7] & !JE1L19;
JE1L22 = CARRY(JE1L22_cout_0);
--JE1L23 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~177COUT1_229 at LC_X41_Y28_N7
--operation mode is arithmetic
JE1L23_cout_1 = !JE1_baud_rate_counter[7] & !JE1L20;
JE1L23 = CARRY(JE1L23_cout_1);
--JE1L24 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~178 at LC_X41_Y28_N8
--operation mode is normal
JE1L24_carry_eqn = (!JE1L12 & JE1L22) # (JE1L12 & JE1L23);
JE1L24 = JE1_baud_rate_counter[8] $ JE1L24_carry_eqn;
--VC1L9 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_resetlatch~185 at LC_X33_Y24_N9
--operation mode is normal
VC1L9 = AMPP_FUNCTION(VC1_internal_resetlatch, E1_data_out, C1_CLR_SIGNAL);
--H1_slave_writedata_d1[3] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[3] at LC_X45_Y8_N4
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_writedata_d1[3]_lut_out = GND;
H1_slave_writedata_d1[3] = DFFEAS(H1_slave_writedata_d1[3]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , L1_M_st_data[3], , , VCC);
--H1_slave_writedata_d1[7] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[7] at LC_X50_Y21_N4
--operation mode is normal
H1_slave_writedata_d1[7]_lut_out = L1_M_st_data[7];
H1_slave_writedata_d1[7] = DFFEAS(H1_slave_writedata_d1[7]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--GC1L17 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~571 at LC_X14_Y10_N0
--operation mode is arithmetic
GC1L17 = AMPP_FUNCTION(L1L629, L1L695);
--GC1L18 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~571COUT1_791 at LC_X14_Y10_N0
--operation mode is arithmetic
GC1L18 = AMPP_FUNCTION(L1L629, L1L695);
--H1_slave_writedata_d1[4] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[4] at LC_X50_Y25_N4
--operation mode is normal
H1_slave_writedata_d1[4]_lut_out = L1_M_st_data[4];
H1_slave_writedata_d1[4] = DFFEAS(H1_slave_writedata_d1[4]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--H1_slave_writedata_d1[15] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[15] at LC_X50_Y11_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_writedata_d1[15]_lut_out = GND;
H1_slave_writedata_d1[15] = DFFEAS(H1_slave_writedata_d1[15]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , L1_M_st_data[15], , , VCC);
--H1_slave_writedata_d1[14] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[14] at LC_X50_Y23_N4
--operation mode is normal
H1_slave_writedata_d1[14]_lut_out = L1_M_st_data[14];
H1_slave_writedata_d1[14] = DFFEAS(H1_slave_writedata_d1[14]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--H1_slave_writedata_d1[13] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[13] at LC_X50_Y22_N2
--operation mode is normal
H1_slave_writedata_d1[13]_lut_out = L1_M_st_data[13];
H1_slave_writedata_d1[13] = DFFEAS(H1_slave_writedata_d1[13]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--H1_slave_writedata_d1[12] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[12] at LC_X52_Y20_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_writedata_d1[12]_lut_out = GND;
H1_slave_writedata_d1[12] = DFFEAS(H1_slave_writedata_d1[12]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , L1_M_st_data[12], , , VCC);
--H1_slave_writedata_d1[11] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[11] at LC_X51_Y14_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_writedata_d1[11]_lut_out = GND;
H1_slave_writedata_d1[11] = DFFEAS(H1_slave_writedata_d1[11]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , L1_M_st_data[11], , , VCC);
--H1_slave_writedata_d1[10] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[10] at LC_X52_Y18_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_writedata_d1[10]_lut_out = GND;
H1_slave_writedata_d1[10] = DFFEAS(H1_slave_writedata_d1[10]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , L1_M_st_data[10], , , VCC);
--H1_slave_writedata_d1[9] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[9] at LC_X52_Y19_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_writedata_d1[9]_lut_out = GND;
H1_slave_writedata_d1[9] = DFFEAS(H1_slave_writedata_d1[9]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , L1_M_st_data[9], , , VCC);
--H1_slave_writedata_d1[8] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[8] at LC_X52_Y21_N2
--operation mode is normal
H1_slave_writedata_d1[8]_lut_out = L1_M_st_data[8];
H1_slave_writedata_d1[8] = DFFEAS(H1_slave_writedata_d1[8]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--H1_slave_writedata_d1[5] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[5] at LC_X51_Y21_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_writedata_d1[5]_lut_out = GND;
H1_slave_writedata_d1[5] = DFFEAS(H1_slave_writedata_d1[5]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , L1_M_st_data[5], , , VCC);
--H1_slave_writedata_d1[6] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[6] at LC_X51_Y5_N4
--operation mode is normal
H1_slave_writedata_d1[6]_lut_out = L1_M_st_data[6];
H1_slave_writedata_d1[6] = DFFEAS(H1_slave_writedata_d1[6]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--H1_master_writedata[0] is std_1s10:inst|clock_0:the_clock_0|master_writedata[0] at LC_X51_Y20_N7
--operation mode is normal
H1_master_writedata[0]_lut_out = H1_slave_writedata_d1[0];
H1_master_writedata[0] = DFFEAS(H1_master_writedata[0]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--QD1L61 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3517 at LC_X35_Y24_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1L61 = AMPP_FUNCTION(QD1_count[9], QD1_td_shift[6]);
--QD1_rdata[3] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[3] at LC_X35_Y24_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
QD1_rdata[3] = AMPP_FUNCTION(DE1__clk0, AE1_q_b[3], E1_data_out, GND, QD1L18);
--H1_master_writedata[1] is std_1s10:inst|clock_0:the_clock_0|master_writedata[1] at LC_X51_Y20_N0
--operation mode is normal
H1_master_writedata[1]_lut_out = H1_slave_writedata_d1[1];
H1_master_writedata[1] = DFFEAS(H1_master_writedata[1]_lut_out, GLOBAL(PLD_CLOCKINPUT), GLOBAL(D1_data_out), , , , , , );
--QD1_count[4] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[4] at LC_X35_Y23_N1
--operation mode is normal
QD1_count[4] = AMPP_FUNCTION(!A1L6, QD1_count[3], RE1_state[4], !C1_CLR_SIGNAL, QD1L52);
--GE1L20 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process0~1 at LC_X44_Y9_N6
--operation mode is normal
GE1L20 = FB1_za_valid # !GE1_full_6 & (GB1L34);
--YB1L2 is std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_read_request~29 at LC_X48_Y19_N5
--operation mode is normal
YB1L2 = !YB1_slave_state[2] & !YB1_slave_state[0] & !YB1_slave_state[1];
--JE1L26 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~181 at LC_X41_Y28_N0
--operation mode is arithmetic
JE1L26_cout_0 = JE1_baud_rate_counter[0];
JE1L26 = CARRY(JE1L26_cout_0);
--JE1L27 is std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|Add0~181COUT1_217 at LC_X41_Y28_N0
--operation mode is arithmetic
JE1L27_cout_1 = JE1_baud_rate_counter[0];
JE1L27 = CARRY(JE1L27_cout_1);
--GC1L20 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~573 at LC_X14_Y11_N9
--operation mode is arithmetic
GC1L20 = AMPP_FUNCTION(L1L628, L1L694, GC1L34, GC1L22, GC1L23);
--H1_slave_writedata_d1[0] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[0] at LC_X50_Y7_N7
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
H1_slave_writedata_d1[0]_lut_out = GND;
H1_slave_writedata_d1[0] = DFFEAS(H1_slave_writedata_d1[0]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , L1_M_st_data[0], , , VCC);
--H1_slave_writedata_d1[1] is std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[1] at LC_X52_Y22_N2
--operation mode is normal
H1_slave_writedata_d1[1]_lut_out = L1_M_st_data[1];
H1_slave_writedata_d1[1] = DFFEAS(H1_slave_writedata_d1[1]_lut_out, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--QD1_count[3] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[3] at LC_X35_Y23_N7
--operation mode is normal
QD1_count[3] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1_count[2], !C1_CLR_SIGNAL, QD1L52);
--GC1L22 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~575 at LC_X14_Y11_N8
--operation mode is arithmetic
GC1L22 = AMPP_FUNCTION(L1L693, L1L627, GC1L25);
--GC1L23 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~575COUT1_789 at LC_X14_Y11_N8
--operation mode is arithmetic
GC1L23 = AMPP_FUNCTION(L1L693, L1L627, GC1L26);
--QD1_count[2] is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|count[2] at LC_X35_Y23_N6
--operation mode is normal
QD1_count[2] = AMPP_FUNCTION(!A1L6, RE1_state[4], QD1_count[1], !C1_CLR_SIGNAL, QD1L52);
--GC1L25 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~577 at LC_X14_Y11_N7
--operation mode is arithmetic
GC1L25 = AMPP_FUNCTION(L1L692, L1L626, GC1L28);
--GC1L26 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~577COUT1_787 at LC_X14_Y11_N7
--operation mode is arithmetic
GC1L26 = AMPP_FUNCTION(L1L692, L1L626, GC1L29);
--GC1L28 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~579 at LC_X14_Y11_N6
--operation mode is arithmetic
GC1L28 = AMPP_FUNCTION(L1L625, L1L691, GC1L31);
--GC1L29 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~579COUT1_785 at LC_X14_Y11_N6
--operation mode is arithmetic
GC1L29 = AMPP_FUNCTION(L1L625, L1L691, GC1L32);
--GC1L31 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~581 at LC_X14_Y11_N5
--operation mode is arithmetic
GC1L31 = AMPP_FUNCTION(L1L624, L1L690);
--GC1L32 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~581COUT1_783 at LC_X14_Y11_N5
--operation mode is arithmetic
GC1L32 = AMPP_FUNCTION(L1L624, L1L690);
--GC1L34 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~583 at LC_X14_Y11_N4
--operation mode is arithmetic
GC1L34 = AMPP_FUNCTION(L1L623, L1L689, GC1L48, GC1L36, GC1L37);
--GC1L36 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~585 at LC_X14_Y11_N3
--operation mode is arithmetic
GC1L36 = AMPP_FUNCTION(L1L622, L1L688, GC1L39);
--GC1L37 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~585COUT1_781 at LC_X14_Y11_N3
--operation mode is arithmetic
GC1L37 = AMPP_FUNCTION(L1L622, L1L688, GC1L40);
--GC1L39 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~587 at LC_X14_Y11_N2
--operation mode is arithmetic
GC1L39 = AMPP_FUNCTION(L1L621, L1L687, GC1L42);
--GC1L40 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~587COUT1_779 at LC_X14_Y11_N2
--operation mode is arithmetic
GC1L40 = AMPP_FUNCTION(L1L621, L1L687, GC1L43);
--GC1L42 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~589 at LC_X14_Y11_N1
--operation mode is arithmetic
GC1L42 = AMPP_FUNCTION(L1L686, L1L620, GC1L45);
--GC1L43 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~589COUT1_777 at LC_X14_Y11_N1
--operation mode is arithmetic
GC1L43 = AMPP_FUNCTION(L1L686, L1L620, GC1L46);
--GC1L45 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~591 at LC_X14_Y11_N0
--operation mode is arithmetic
GC1L45 = AMPP_FUNCTION(L1L685, L1L619);
--GC1L46 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~591COUT1_775 at LC_X14_Y11_N0
--operation mode is arithmetic
GC1L46 = AMPP_FUNCTION(L1L685, L1L619);
--GC1L48 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~593 at LC_X14_Y12_N9
--operation mode is arithmetic
GC1L48 = AMPP_FUNCTION(L1L684, L1L618, GC1L62, GC1L50, GC1L51);
--GC1L50 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~595 at LC_X14_Y12_N8
--operation mode is arithmetic
GC1L50 = AMPP_FUNCTION(L1L617, L1L683, GC1L53);
--GC1L51 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~595COUT1_773 at LC_X14_Y12_N8
--operation mode is arithmetic
GC1L51 = AMPP_FUNCTION(L1L617, L1L683, GC1L54);
--GC1L53 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~597 at LC_X14_Y12_N7
--operation mode is arithmetic
GC1L53 = AMPP_FUNCTION(L1L616, L1L682, GC1L56);
--GC1L54 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~597COUT1_771 at LC_X14_Y12_N7
--operation mode is arithmetic
GC1L54 = AMPP_FUNCTION(L1L616, L1L682, GC1L57);
--GC1L56 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~599 at LC_X14_Y12_N6
--operation mode is arithmetic
GC1L56 = AMPP_FUNCTION(L1L681, L1L615, GC1L59);
--GC1L57 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~599COUT1_769 at LC_X14_Y12_N6
--operation mode is arithmetic
GC1L57 = AMPP_FUNCTION(L1L681, L1L615, GC1L60);
--GC1L59 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~601 at LC_X14_Y12_N5
--operation mode is arithmetic
GC1L59 = AMPP_FUNCTION(L1L680, L1L614);
--GC1L60 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~601COUT1_767 at LC_X14_Y12_N5
--operation mode is arithmetic
GC1L60 = AMPP_FUNCTION(L1L680, L1L614);
--GC1L62 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~603 at LC_X14_Y12_N4
--operation mode is arithmetic
GC1L62 = AMPP_FUNCTION(L1L679, L1L613, GC1L76, GC1L64, GC1L65);
--GC1L64 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~605 at LC_X14_Y12_N3
--operation mode is arithmetic
GC1L64 = AMPP_FUNCTION(L1L612, L1L678, GC1L67);
--GC1L65 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~605COUT1_765 at LC_X14_Y12_N3
--operation mode is arithmetic
GC1L65 = AMPP_FUNCTION(L1L612, L1L678, GC1L68);
--GC1L67 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~607 at LC_X14_Y12_N2
--operation mode is arithmetic
GC1L67 = AMPP_FUNCTION(L1L611, L1L677, GC1L70);
--GC1L68 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~607COUT1_763 at LC_X14_Y12_N2
--operation mode is arithmetic
GC1L68 = AMPP_FUNCTION(L1L611, L1L677, GC1L71);
--GC1L70 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~609 at LC_X14_Y12_N1
--operation mode is arithmetic
GC1L70 = AMPP_FUNCTION(L1L610, L1L676, GC1L73);
--GC1L71 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~609COUT1_761 at LC_X14_Y12_N1
--operation mode is arithmetic
GC1L71 = AMPP_FUNCTION(L1L610, L1L676, GC1L74);
--GC1L73 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~611 at LC_X14_Y12_N0
--operation mode is arithmetic
GC1L73 = AMPP_FUNCTION(L1L609, L1L675);
--GC1L74 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~611COUT1_759 at LC_X14_Y12_N0
--operation mode is arithmetic
GC1L74 = AMPP_FUNCTION(L1L609, L1L675);
--GC1L76 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~613 at LC_X14_Y13_N9
--operation mode is arithmetic
GC1L76 = AMPP_FUNCTION(L1L608, L1L674, GC1L90, GC1L78, GC1L79);
--GC1L78 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~615 at LC_X14_Y13_N8
--operation mode is arithmetic
GC1L78 = AMPP_FUNCTION(L1L673, L1L607, GC1L81);
--GC1L79 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~615COUT1_757 at LC_X14_Y13_N8
--operation mode is arithmetic
GC1L79 = AMPP_FUNCTION(L1L673, L1L607, GC1L82);
--GC1L81 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~617 at LC_X14_Y13_N7
--operation mode is arithmetic
GC1L81 = AMPP_FUNCTION(L1L672, L1L606, GC1L84);
--GC1L82 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~617COUT1_755 at LC_X14_Y13_N7
--operation mode is arithmetic
GC1L82 = AMPP_FUNCTION(L1L672, L1L606, GC1L85);
--GC1L84 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~619 at LC_X14_Y13_N6
--operation mode is arithmetic
GC1L84 = AMPP_FUNCTION(L1L605, L1L671, GC1L87);
--GC1L85 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~619COUT1_753 at LC_X14_Y13_N6
--operation mode is arithmetic
GC1L85 = AMPP_FUNCTION(L1L605, L1L671, GC1L88);
--GC1L87 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~621 at LC_X14_Y13_N5
--operation mode is arithmetic
GC1L87 = AMPP_FUNCTION(L1L604, L1L670);
--GC1L88 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~621COUT1_751 at LC_X14_Y13_N5
--operation mode is arithmetic
GC1L88 = AMPP_FUNCTION(L1L604, L1L670);
--GC1L90 is std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench|Add0~623 at LC_X14_Y13_N4
--operation mode is arithmetic
GC1L90 = AMPP_FUNCTION(L1L669, L1L603);
--EB1L4 is std_1s10:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1~46 at LC_X40_Y12_N5
--operation mode is normal
EB1L4 = !L1_M_alu_result[6] & L1_M_alu_result[5] & (L1_internal_d_write # L1_internal_d_read);
--W1L36 is std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave|LessThan0~90 at LC_X39_Y18_N6
--operation mode is normal
W1L36 = !W1_lcd_display_control_slave_wait_counter[5] & (!W1_lcd_display_control_slave_wait_counter[4] & W1L34);
--V1L5 is std_1s10:inst|lcd_display:the_lcd_display|LCD_E~445 at LC_X39_Y18_N8
--operation mode is normal
V1L5 = W1_lcd_display_control_slave_wait_counter[4] & (W1_lcd_display_control_slave_wait_counter[3] & V1L2) # !W1_lcd_display_control_slave_wait_counter[4] & !W1_lcd_display_control_slave_wait_counter[5] & (!V1L2 # !W1_lcd_display_control_slave_wait_counter[3]);
--Q1L95 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_flash_s1~274 at LC_X34_Y13_N9
--operation mode is normal
Q1L95 = !L1_M_alu_result[23] & !L1_M_alu_result[24] & (L1_internal_d_write # L1_internal_d_read);
--AB1L9 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_requests_onchip_ram_64_kbytes_s1~300 at LC_X36_Y13_N5
--operation mode is normal
AB1L9 = !L1_M_alu_result[16] & (L1_internal_d_write # L1_internal_d_read);
--Q1_cpu_instruction_master_arbiterlock is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_arbiterlock at LC_X40_Y15_N3
--operation mode is normal
Q1_cpu_instruction_master_arbiterlock = Q1_ext_ram_bus_avalon_slave_slavearbiterlockenable & (Q1L103 # Q1_last_cycle_cpu_instruction_master_granted_slave_ext_flash_s1 & Q1L118);
--Q1L72 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_lan91c111_s1~119 at LC_X39_Y17_N4
--operation mode is normal
Q1L72 = !Q1_cpu_instruction_master_arbiterlock & Q1L81 & (Q1L12 # Q1L9);
--Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_saved_chosen_master_vector[1] at LC_X39_Y17_N4
--operation mode is normal
Q1_ext_ram_bus_avalon_slave_saved_chosen_master_vector[1] = DFFEAS(Q1L72, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , Q1L342, , , , );
--Q1L445 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_read_n_to_the_ext_ram~39 at LC_X36_Y14_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[9]_qfbk = L1_ic_fill_tag[9];
Q1L445 = AB1L13 & !L1_ic_fill_tag[8] & !L1_ic_fill_tag[9]_qfbk & !L1_ic_fill_tag[10];
--L1_ic_fill_tag[9] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[9] at LC_X36_Y14_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[9] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[19], E1_data_out, GND, L1_D_ic_fill_starting);
--FB1L233 is std_1s10:inst|sdram:the_sdram|m_cmd~50 at LC_X36_Y4_N3
--operation mode is normal
FB1L233 = FB1_f_pop & (FB1L724 # !EE1_entries[0] & !EE1_entries[1]);
--FB1L436 is std_1s10:inst|sdram:the_sdram|Mux19~1739 at LC_X35_Y2_N5
--operation mode is normal
FB1L436 = !FB1_m_state[4] & !FB1_m_state[3] & !FB1_init_done & FB1_i_cmd[1];
--L1_W_stall is std_1s10:inst|cpu:the_cpu|W_stall at LC_X22_Y21_N6
--operation mode is normal
L1_W_stall = AMPP_FUNCTION(L1_internal_d_write, L1L1480, M1_internal_cpu_data_master_waitrequest);
--X1L13 is std_1s10:inst|led_pio:the_led_pio|process0~53 at LC_X40_Y12_N3
--operation mode is normal
X1L13 = NB1L2 & L1_M_alu_result[7] & P1L7 & !L1_M_alu_result[5];
--FB1_f_select is std_1s10:inst|sdram:the_sdram|f_select at LC_X36_Y4_N8
--operation mode is normal
FB1_f_select = FB1_f_pop & !FB1L724 & (EE1_entries[0] # EE1_entries[1]);
--FB1L625 is std_1s10:inst|sdram:the_sdram|Mux108~1489 at LC_X33_Y6_N7
--operation mode is normal
FB1L625 = FB1L621 # FB1L189Q & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L632 is std_1s10:inst|sdram:the_sdram|Mux109~1355 at LC_X34_Y6_N0
--operation mode is normal
FB1L632 = FB1L629 # FB1L185Q & (FB1_m_state[3] $ !FB1_m_state[4]);
--FB1L639 is std_1s10:inst|sdram:the_sdram|Mux110~1395 at LC_X34_Y3_N5
--operation mode is normal
FB1L639 = FB1L636 # FB1L181Q & (FB1_m_state[3] $ !FB1_m_state[4]);
--FB1L646 is std_1s10:inst|sdram:the_sdram|Mux111~1322 at LC_X34_Y5_N7
--operation mode is normal
FB1L646 = FB1L643 # FB1L177Q & (FB1_m_state[3] $ !FB1_m_state[4]);
--FB1L653 is std_1s10:inst|sdram:the_sdram|Mux112~1354 at LC_X34_Y8_N7
--operation mode is normal
FB1L653 = FB1L650 # FB1L173Q & (FB1_m_state[3] $ !FB1_m_state[4]);
--FB1L660 is std_1s10:inst|sdram:the_sdram|Mux113~1354 at LC_X33_Y5_N8
--operation mode is normal
FB1L660 = FB1L657 # FB1L169Q & (FB1_m_state[4] $ !FB1_m_state[3]);
--FB1L667 is std_1s10:inst|sdram:the_sdram|Mux114~1354 at LC_X35_Y5_N7
--operation mode is normal
FB1L667 = FB1L664 # FB1L165Q & (FB1_m_state[3] $ !FB1_m_state[4]);
--FB1L674 is std_1s10:inst|sdram:the_sdram|Mux115~1354 at LC_X36_Y5_N6
--operation mode is normal
FB1L674 = FB1L671 # FB1L161Q & (FB1_m_state[3] $ !FB1_m_state[4]);
--FB1L681 is std_1s10:inst|sdram:the_sdram|Mux118~1215 at LC_X35_Y3_N6
--operation mode is normal
FB1L681 = FB1L448 & !FB1_m_state[8] & !FB1_m_state[5] & !FB1_m_state[6];
--GB1L24 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_requests_sdram_s1~431 at LC_X39_Y13_N2
--operation mode is normal
GB1L24 = !L1_M_alu_result[25] & L1_M_alu_result[24] & (L1_internal_d_write # L1_internal_d_read);
--P1L8 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~308 at LC_X36_Y12_N0
--operation mode is normal
P1L8 = !L1_M_alu_result[11] & (L1_internal_d_write # L1_internal_d_read);
--P1L14 is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_requests_cpu_jtag_debug_module~63 at LC_X36_Y12_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[0]_qfbk = L1_ic_fill_tag[0];
P1L14 = !L1_ic_fill_tag[1] & P1L12 & !L1_ic_fill_tag[0]_qfbk & !L1_ic_fill_line[6];
--L1_ic_fill_tag[0] is std_1s10:inst|cpu:the_cpu|ic_fill_tag[0] at LC_X36_Y12_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_ic_fill_tag[0] = AMPP_FUNCTION(DE1__clk0, L1_D_pc[10], E1_data_out, GND, L1_D_ic_fill_starting);
--L1_D_ic_fill_starting is std_1s10:inst|cpu:the_cpu|D_ic_fill_starting at LC_X35_Y21_N4
--operation mode is normal
L1_D_ic_fill_starting = AMPP_FUNCTION(L1_M_pipe_flush, L1_ic_fill_active, L1L259);
--L1_D_ic_fill_starting_d1 is std_1s10:inst|cpu:the_cpu|D_ic_fill_starting_d1 at LC_X35_Y21_N4
--operation mode is normal
L1_D_ic_fill_starting_d1 = AMPP_FUNCTION(DE1__clk0, L1_M_pipe_flush, L1_ic_fill_active, L1L259, E1_data_out);
--Q1_ext_flash_s1_in_a_read_cycle is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_flash_s1_in_a_read_cycle at LC_X39_Y16_N6
--operation mode is normal
Q1_ext_flash_s1_in_a_read_cycle = Q1L87 # N1L146 & (Q1L24 # Q1L21);
--GE1L36 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|updated_one_count~65 at LC_X39_Y10_N8
--operation mode is normal
GE1L36 = GB1L25 & (EE1_entries[0] # !EE1_entries[1]);
--GE1L5 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1203 at LC_X40_Y10_N4
--operation mode is normal
GE1L5 = GE1_how_many_ones[0] & GE1_how_many_ones[1] & (!FB1_za_valid # !GE1_stage_0) # !GE1_how_many_ones[0] & GE1_stage_0 & FB1_za_valid & !GE1_how_many_ones[1];
--GE1L6 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|A_WE_StdLogicVector~1204 at LC_X40_Y10_N9
--operation mode is normal
GE1_how_many_ones[0]_qfbk = GE1_how_many_ones[0];
GE1L6 = GE1L36 $ GE1_how_many_ones[0]_qfbk $ (FB1_za_valid & GE1_stage_0);
--GE1_how_many_ones[0] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|how_many_ones[0] at LC_X40_Y10_N9
--operation mode is normal
GE1_how_many_ones[0] = DFFEAS(GE1L6, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GE1L27, , , , );
--M1L18 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|A_WE_StdLogicVector~1060 at LC_X36_Y15_N3
--operation mode is normal
M1L18 = GB1L23 & (EE1_entries[1] & !EE1_entries[0] # !GB1L21);
--Q1L36 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~377 at LC_X39_Y13_N7
--operation mode is normal
Q1L36 = Q1L95 & !Q1_cpu_data_master_read_data_valid_ext_ram_s1_shift_register[0] & !Q1L80 & Q1L97;
--P1_cpu_data_master_requests_cpu_jtag_debug_module is std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module at LC_X39_Y12_N1
--operation mode is normal
P1_cpu_data_master_requests_cpu_jtag_debug_module = !L1_M_alu_result[11] & P1L7 & (L1_internal_d_write # L1_internal_d_read);
--AB1L1 is std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|Add2~231 at LC_X34_Y11_N4
--operation mode is normal
AB1L1 = AB1L11 & !AB1_onchip_ram_64_kbytes_s1_arb_addend[1] & AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1 & AB1L2 # !AB1L11 & (!AB1L2 # !AB1_cpu_data_master_requests_onchip_ram_64_kbytes_s1);
--T1L71 is std_1s10:inst|jtag_uart:the_jtag_uart|process2~44 at LC_X39_Y12_N4
--operation mode is normal
T1L71 = EB1L2 & !L1_M_alu_result[3] & T1L69 & !L1_M_alu_result[7];
--J1L3 is std_1s10:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in~363 at LC_X48_Y10_N1
--operation mode is normal
J1L3 = L1_M_alu_result[6] & (L1_internal_d_write # L1_internal_d_read);
--Q1L401 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|lan91c111_s1_counter_load_value~104 at LC_X40_Y16_N9
--operation mode is normal
Q1L401 = !Q1L345 & L1_internal_d_write & Q1L72 & !Q1_d1_ext_ram_bus_avalon_slave_end_xfer;
--FB1L453 is std_1s10:inst|sdram:the_sdram|Mux24~1464 at LC_X32_Y2_N5
--operation mode is normal
FB1L453 = FB1L451 & !FB1_m_count[2] & !FB1_m_count[1] & FB1L452;
--FB1L445 is std_1s10:inst|sdram:the_sdram|Mux22~1320 at LC_X31_Y2_N7
--operation mode is normal
FB1L445 = FB1_m_state[0] & (!FB1_m_state[2] & !FB1L744 # !FB1_m_state[8]);
--FB1L446 is std_1s10:inst|sdram:the_sdram|Mux22~1321 at LC_X32_Y2_N3
--operation mode is normal
FB1L446 = FB1_m_next[1] & !FB1_m_count[1] & !FB1_m_count[2] & FB1_m_state[2];
--FB1L479 is std_1s10:inst|sdram:the_sdram|Mux28~1612 at LC_X34_Y4_N2
--operation mode is normal
FB1L479 = FB1_m_next[1] # FB1_m_count[2] # FB1_m_count[1] # !FB1L549;
--FB1L464 is std_1s10:inst|sdram:the_sdram|Mux26~1227 at LC_X36_Y4_N4
--operation mode is normal
FB1L464 = !FB1_refresh_request & !FB1L724 & (EE1_entries[0] # EE1_entries[1]);
--FB1L468 is std_1s10:inst|sdram:the_sdram|Mux27~1230 at LC_X34_Y4_N3
--operation mode is normal
FB1L468 = FB1_m_state[0] & !FB1_m_state[8] & !FB1_m_state[2] & FB1L717;
--EE1L62 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56]~56 at LC_X36_Y4_N9
--operation mode is normal
EE1L62 = !EE1_wr_address & FB1L407 & (EE1_entries[0] # !EE1_entries[1]);
--EE1L123 is std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[56]~56 at LC_X36_Y4_N6
--operation mode is normal
EE1L123 = EE1_wr_address & FB1L407 & (EE1_entries[0] # !EE1_entries[1]);
--FB1L391 is std_1s10:inst|sdram:the_sdram|m_next~830 at LC_X36_Y4_N1
--operation mode is normal
FB1L391 = FB1_refresh_request & !FB1L724 & (EE1_entries[0] # EE1_entries[1]);
--FB1L392 is std_1s10:inst|sdram:the_sdram|m_next~831 at LC_X36_Y4_N5
--operation mode is normal
FB1L392 = FB1_refresh_request # FB1L724 & (EE1_entries[0] # EE1_entries[1]);
--FB1L505 is std_1s10:inst|sdram:the_sdram|Mux36~1270 at LC_X31_Y4_N7
--operation mode is normal
FB1L505 = FB1_m_next[3] & (FB1_m_state[3] $ !FB1_m_state[4] # !FB1L391);
--FB1L498 is std_1s10:inst|sdram:the_sdram|Mux35~1200 at LC_X31_Y4_N8
--operation mode is normal
FB1L498 = FB1_m_next[4] & (FB1_m_state[3] $ !FB1_m_state[4] # !FB1L391);
--L1L1383 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[2]~3709 at LC_X18_Y21_N0
--operation mode is normal
L1L1383 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[2], L1L1382);
--L1_W_wr_data[2] is std_1s10:inst|cpu:the_cpu|W_wr_data[2] at LC_X18_Y21_N0
--operation mode is normal
L1_W_wr_data[2] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[2], L1L1382, E1_data_out, L1_W_stall);
--L1_D_ctrl_b_not_src is std_1s10:inst|cpu:the_cpu|D_ctrl_b_not_src at LC_X19_Y18_N8
--operation mode is normal
L1_D_ctrl_b_not_src = AMPP_FUNCTION(L1L216, L1_D_iw[4], L1_D_iw[5], L1L828);
--L1L238 is std_1s10:inst|cpu:the_cpu|D_ctrl_jmp_indirect~38 at LC_X19_Y8_N4
--operation mode is normal
L1L238 = AMPP_FUNCTION(L1L827, L1_D_iw[12], L1_D_iw[4], L1_D_iw[5]);
--L1L1386 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[3]~3710 at LC_X19_Y21_N4
--operation mode is normal
L1L1386 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[3], L1_M_ctrl_mul_shift_rot, L1L1385);
--L1_W_wr_data[3] is std_1s10:inst|cpu:the_cpu|W_wr_data[3] at LC_X19_Y21_N4
--operation mode is normal
L1_W_wr_data[3] = AMPP_FUNCTION(DE1__clk0, L1_M_mul_shift_rot_result[3], L1_M_ctrl_mul_shift_rot, L1L1385, E1_data_out, L1_W_stall);
--L1L1398 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[7]~3711 at LC_X13_Y17_N9
--operation mode is normal
L1L1398 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[7], L1L1397);
--L1_W_wr_data[7] is std_1s10:inst|cpu:the_cpu|W_wr_data[7] at LC_X13_Y17_N9
--operation mode is normal
L1_W_wr_data[7] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[7], L1L1397, E1_data_out, L1_W_stall);
--L1_E_hbreak_req is std_1s10:inst|cpu:the_cpu|E_hbreak_req at LC_X27_Y22_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_hbreak_req = AMPP_FUNCTION(L1L502, L1_E_iw[13], L1L1005);
--L1_E_iw[14] is std_1s10:inst|cpu:the_cpu|E_iw[14] at LC_X27_Y22_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_E_iw[14] = AMPP_FUNCTION(DE1__clk0, L1_D_iw[14], E1_data_out, GND, L1_W_stall);
--L1L80 is std_1s10:inst|cpu:the_cpu|A_WE_StdLogic~268 at LC_X22_Y21_N1
--operation mode is normal
L1L80 = AMPP_FUNCTION(L1L1480, L1_internal_d_write, L1L818, M1_internal_cpu_data_master_waitrequest);
--L1L1389 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[4]~3712 at LC_X14_Y19_N6
--operation mode is normal
L1L1389 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[4], L1L1388);
--L1_W_wr_data[4] is std_1s10:inst|cpu:the_cpu|W_wr_data[4] at LC_X14_Y19_N6
--operation mode is normal
L1_W_wr_data[4] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[4], L1L1388, E1_data_out, L1_W_stall);
--L1L1443 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[22]~3713 at LC_X19_Y15_N5
--operation mode is normal
L1L1443 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[22], L1L1442);
--L1_W_wr_data[22] is std_1s10:inst|cpu:the_cpu|W_wr_data[22] at LC_X19_Y15_N5
--operation mode is normal
L1_W_wr_data[22] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[22], L1L1442, E1_data_out, L1_W_stall);
--L1L1440 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[21]~3714 at LC_X17_Y21_N3
--operation mode is normal
L1L1440 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[21], L1_M_ctrl_mul_shift_rot, L1L1439);
--L1_W_wr_data[21] is std_1s10:inst|cpu:the_cpu|W_wr_data[21] at LC_X17_Y21_N3
--operation mode is normal
L1_W_wr_data[21] = AMPP_FUNCTION(DE1__clk0, L1_M_mul_shift_rot_result[21], L1_M_ctrl_mul_shift_rot, L1L1439, E1_data_out, L1_W_stall);
--L1L1449 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[24]~3715 at LC_X19_Y21_N6
--operation mode is normal
L1L1449 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1L1448, L1_M_mul_shift_rot_result[24]);
--L1_W_wr_data[24] is std_1s10:inst|cpu:the_cpu|W_wr_data[24] at LC_X19_Y21_N6
--operation mode is normal
L1_W_wr_data[24] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1L1448, L1_M_mul_shift_rot_result[24], E1_data_out, L1_W_stall);
--L1L1434 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[19]~3716 at LC_X18_Y16_N7
--operation mode is normal
L1L1434 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[19], L1L1433);
--L1_W_wr_data[19] is std_1s10:inst|cpu:the_cpu|W_wr_data[19] at LC_X18_Y16_N7
--operation mode is normal
L1_W_wr_data[19] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[19], L1L1433, E1_data_out, L1_W_stall);
--L1L1431 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[18]~3717 at LC_X18_Y14_N0
--operation mode is normal
L1L1431 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1L1430, L1_M_mul_shift_rot_result[18]);
--L1_W_wr_data[18] is std_1s10:inst|cpu:the_cpu|W_wr_data[18] at LC_X18_Y14_N0
--operation mode is normal
L1_W_wr_data[18] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1L1430, L1_M_mul_shift_rot_result[18], E1_data_out, L1_W_stall);
--L1L1428 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[17]~3718 at LC_X17_Y14_N0
--operation mode is normal
L1L1428 = AMPP_FUNCTION(L1L1427, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[17]);
--L1_W_wr_data[17] is std_1s10:inst|cpu:the_cpu|W_wr_data[17] at LC_X17_Y14_N0
--operation mode is normal
L1_W_wr_data[17] = AMPP_FUNCTION(DE1__clk0, L1L1427, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[17], E1_data_out, L1_W_stall);
--L1L1425 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[16]~3719 at LC_X18_Y16_N2
--operation mode is normal
L1L1425 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[16], L1L1424);
--L1_W_wr_data[16] is std_1s10:inst|cpu:the_cpu|W_wr_data[16] at LC_X18_Y16_N2
--operation mode is normal
L1_W_wr_data[16] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[16], L1L1424, E1_data_out, L1_W_stall);
--L1L1446 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[23]~3720 at LC_X17_Y14_N2
--operation mode is normal
L1L1446 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[23], L1_M_ctrl_mul_shift_rot, L1L1445);
--L1_W_wr_data[23] is std_1s10:inst|cpu:the_cpu|W_wr_data[23] at LC_X17_Y14_N2
--operation mode is normal
L1_W_wr_data[23] = AMPP_FUNCTION(DE1__clk0, L1_M_mul_shift_rot_result[23], L1_M_ctrl_mul_shift_rot, L1L1445, E1_data_out, L1_W_stall);
--L1L1452 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[25]~3721 at LC_X14_Y19_N3
--operation mode is normal
L1L1452 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[25], L1L1451, L1_M_ctrl_mul_shift_rot);
--L1_W_wr_data[25] is std_1s10:inst|cpu:the_cpu|W_wr_data[25] at LC_X14_Y19_N3
--operation mode is normal
L1_W_wr_data[25] = AMPP_FUNCTION(DE1__clk0, L1_M_mul_shift_rot_result[25], L1L1451, L1_M_ctrl_mul_shift_rot, E1_data_out, L1_W_stall);
--L1L1437 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[20]~3722 at LC_X18_Y14_N9
--operation mode is normal
L1L1437 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[20], L1L1436);
--L1_W_wr_data[20] is std_1s10:inst|cpu:the_cpu|W_wr_data[20] at LC_X18_Y14_N9
--operation mode is normal
L1_W_wr_data[20] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[20], L1L1436, E1_data_out, L1_W_stall);
--L1L1422 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[15]~3723 at LC_X17_Y17_N7
--operation mode is normal
L1L1422 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1L1421, L1_M_mul_shift_rot_result[15]);
--L1_W_wr_data[15] is std_1s10:inst|cpu:the_cpu|W_wr_data[15] at LC_X17_Y17_N7
--operation mode is normal
L1_W_wr_data[15] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1L1421, L1_M_mul_shift_rot_result[15], E1_data_out, L1_W_stall);
--L1L1419 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[14]~3724 at LC_X14_Y18_N0
--operation mode is normal
L1L1419 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1L1418, L1_M_mul_shift_rot_result[14]);
--L1_W_wr_data[14] is std_1s10:inst|cpu:the_cpu|W_wr_data[14] at LC_X14_Y18_N0
--operation mode is normal
L1_W_wr_data[14] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1L1418, L1_M_mul_shift_rot_result[14], E1_data_out, L1_W_stall);
--L1L1416 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[13]~3725 at LC_X18_Y17_N7
--operation mode is normal
L1L1416 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[13], L1_M_ctrl_mul_shift_rot, L1L1415);
--L1_W_wr_data[13] is std_1s10:inst|cpu:the_cpu|W_wr_data[13] at LC_X18_Y17_N7
--operation mode is normal
L1_W_wr_data[13] = AMPP_FUNCTION(DE1__clk0, L1_M_mul_shift_rot_result[13], L1_M_ctrl_mul_shift_rot, L1L1415, E1_data_out, L1_W_stall);
--L1L1413 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[12]~3726 at LC_X14_Y16_N0
--operation mode is normal
L1L1413 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1L1412, L1_M_mul_shift_rot_result[12]);
--L1_W_wr_data[12] is std_1s10:inst|cpu:the_cpu|W_wr_data[12] at LC_X14_Y16_N0
--operation mode is normal
L1_W_wr_data[12] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1L1412, L1_M_mul_shift_rot_result[12], E1_data_out, L1_W_stall);
--L1L1410 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[11]~3727 at LC_X14_Y18_N5
--operation mode is normal
L1L1410 = AMPP_FUNCTION(L1L1409, L1_M_mul_shift_rot_result[11], L1_M_ctrl_mul_shift_rot);
--L1_W_wr_data[11] is std_1s10:inst|cpu:the_cpu|W_wr_data[11] at LC_X14_Y18_N5
--operation mode is normal
L1_W_wr_data[11] = AMPP_FUNCTION(DE1__clk0, L1L1409, L1_M_mul_shift_rot_result[11], L1_M_ctrl_mul_shift_rot, E1_data_out, L1_W_stall);
--L1L1407 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[10]~3728 at LC_X19_Y17_N9
--operation mode is normal
L1L1407 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[10], L1_M_ctrl_mul_shift_rot, L1L1406);
--L1_W_wr_data[10] is std_1s10:inst|cpu:the_cpu|W_wr_data[10] at LC_X19_Y17_N9
--operation mode is normal
L1_W_wr_data[10] = AMPP_FUNCTION(DE1__clk0, L1_M_mul_shift_rot_result[10], L1_M_ctrl_mul_shift_rot, L1L1406, E1_data_out, L1_W_stall);
--L1L1404 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[9]~3729 at LC_X14_Y14_N2
--operation mode is normal
L1L1404 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1L1403, L1_M_mul_shift_rot_result[9]);
--L1_W_wr_data[9] is std_1s10:inst|cpu:the_cpu|W_wr_data[9] at LC_X14_Y14_N2
--operation mode is normal
L1_W_wr_data[9] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1L1403, L1_M_mul_shift_rot_result[9], E1_data_out, L1_W_stall);
--L1L1401 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[8]~3730 at LC_X14_Y16_N1
--operation mode is normal
L1L1401 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[8], L1L1400, L1_M_ctrl_mul_shift_rot);
--L1_W_wr_data[8] is std_1s10:inst|cpu:the_cpu|W_wr_data[8] at LC_X14_Y16_N1
--operation mode is normal
L1_W_wr_data[8] = AMPP_FUNCTION(DE1__clk0, L1_M_mul_shift_rot_result[8], L1L1400, L1_M_ctrl_mul_shift_rot, E1_data_out, L1_W_stall);
--L1L1392 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[5]~3731 at LC_X19_Y15_N9
--operation mode is normal
L1L1392 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1L1391, L1_M_mul_shift_rot_result[5]);
--L1_W_wr_data[5] is std_1s10:inst|cpu:the_cpu|W_wr_data[5] at LC_X19_Y15_N9
--operation mode is normal
L1_W_wr_data[5] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1L1391, L1_M_mul_shift_rot_result[5], E1_data_out, L1_W_stall);
--L1L1395 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[6]~3732 at LC_X17_Y21_N8
--operation mode is normal
L1L1395 = AMPP_FUNCTION(L1L1394, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[6]);
--L1_W_wr_data[6] is std_1s10:inst|cpu:the_cpu|W_wr_data[6] at LC_X17_Y21_N8
--operation mode is normal
L1_W_wr_data[6] = AMPP_FUNCTION(DE1__clk0, L1L1394, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[6], E1_data_out, L1_W_stall);
--L1L1380 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[1]~3733 at LC_X13_Y17_N7
--operation mode is normal
L1L1380 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1L1379, L1_M_mul_shift_rot_result[1]);
--L1_W_wr_data[1] is std_1s10:inst|cpu:the_cpu|W_wr_data[1] at LC_X13_Y17_N7
--operation mode is normal
L1_W_wr_data[1] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1L1379, L1_M_mul_shift_rot_result[1], E1_data_out, L1_W_stall);
--L1L1377 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[0]~3734 at LC_X18_Y21_N2
--operation mode is normal
L1L1377 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1L1376, L1_M_mul_shift_rot_result[0]);
--L1_W_wr_data[0] is std_1s10:inst|cpu:the_cpu|W_wr_data[0] at LC_X18_Y21_N2
--operation mode is normal
L1_W_wr_data[0] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1L1376, L1_M_mul_shift_rot_result[0], E1_data_out, L1_W_stall);
--FE1L5 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1196 at LC_X44_Y10_N8
--operation mode is normal
FE1L5 = FE1_how_many_ones[0] & FE1_how_many_ones[1] & (!FE1_stage_0 # !FB1_za_valid) # !FE1_how_many_ones[0] & FB1_za_valid & FE1_stage_0 & !FE1_how_many_ones[1];
--FE1L6 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|A_WE_StdLogicVector~1197 at LC_X40_Y10_N7
--operation mode is normal
FE1_how_many_ones[0]_qfbk = FE1_how_many_ones[0];
FE1L6 = FE1L21 $ FE1_how_many_ones[0]_qfbk $ (FB1_za_valid & FE1_stage_0);
--FE1_how_many_ones[0] is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|how_many_ones[0] at LC_X40_Y10_N7
--operation mode is normal
FE1_how_many_ones[0] = DFFEAS(FE1L6, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , GE1L27, , , , );
--GB1L81 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_end_xfer~18 at LC_X39_Y11_N6
--operation mode is normal
GB1L81 = !EE1_entries[0] & (EE1_entries[1] & FB1L407);
--GB1_d1_reasons_to_wait is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|d1_reasons_to_wait at LC_X39_Y11_N6
--operation mode is normal
GB1_d1_reasons_to_wait = DFFEAS(GB1L81, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , , , , , );
--FB1L534 is std_1s10:inst|sdram:the_sdram|Mux40~1452 at LC_X32_Y1_N6
--operation mode is normal
FB1L534 = !FB1_m_state[4] & !FB1_m_state[3] & FB1L520;
--FB1L547 is std_1s10:inst|sdram:the_sdram|Mux41~1461 at LC_X32_Y1_N2
--operation mode is normal
FB1L547 = FB1_m_state[0] & !FB1_m_state[3] & FB1L520;
--FB1L548 is std_1s10:inst|sdram:the_sdram|Mux41~1462 at LC_X32_Y1_N9
--operation mode is normal
FB1L548 = FB1_m_count[1] & (!FB1_refresh_request # !FB1_init_done # !FB1L520);
--L1L248 is std_1s10:inst|cpu:the_cpu|D_ctrl_wrctl_inst~24 at LC_X22_Y6_N5
--operation mode is normal
L1L248 = AMPP_FUNCTION(L1L827, L1_D_iw[5], L1_D_iw[12], L1_D_iw[4]);
--U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave is std_1s10:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave|cpu_data_master_requests_jtag_uart_avalon_jtag_slave at LC_X48_Y13_N9
--operation mode is normal
U1_cpu_data_master_requests_jtag_uart_avalon_jtag_slave = !L1_M_alu_result[3] & EB1L2 & !L1_M_alu_result[7];
--S1_cpu_data_master_requests_high_res_timer_s1 is std_1s10:inst|high_res_timer_s1_arbitrator:the_high_res_timer_s1|cpu_data_master_requests_high_res_timer_s1 at LC_X46_Y12_N9
--operation mode is normal
S1_cpu_data_master_requests_high_res_timer_s1 = L1_M_alu_result[6] & L1_M_alu_result[5] & (LB1L2);
--M1L45 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~5018 at LC_X47_Y12_N5
--operation mode is normal
M1L45 = M1L42 & (Q1_internal_incoming_ext_ram_bus_data[2] # !Q1L97 # !Q1L95);
--QB1_cpu_data_master_granted_uart1_s1 is std_1s10:inst|uart1_s1_arbitrator:the_uart1_s1|cpu_data_master_granted_uart1_s1 at LC_X48_Y12_N3
--operation mode is normal
QB1_cpu_data_master_granted_uart1_s1 = !L1_M_alu_result[5] & L1_M_alu_result[6] & LB1L2;
--LB1_cpu_data_master_requests_sys_clk_timer_s1 is std_1s10:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1|cpu_data_master_requests_sys_clk_timer_s1 at LC_X46_Y8_N1
--operation mode is normal
LB1_cpu_data_master_requests_sys_clk_timer_s1 = !L1_M_alu_result[5] & LB1L2 & !L1_M_alu_result[6];
--M1L226 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~327 at LC_X46_Y8_N5
--operation mode is normal
M1L226 = R1_readdata[3] # !LB1L2 # !L1_M_alu_result[5] # !L1_M_alu_result[6];
--M1L54 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~5019 at LC_X47_Y12_N6
--operation mode is normal
M1L54 = M1L51 & (Q1_internal_incoming_ext_ram_bus_data[3] # !Q1L97 # !Q1L95);
--M1L88 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~5020 at LC_X47_Y12_N4
--operation mode is normal
M1L88 = M1L84 & (Q1_internal_incoming_ext_ram_bus_data[7] # !Q1L95 # !Q1L97);
--L1L233 is std_1s10:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~734 at LC_X22_Y6_N4
--operation mode is normal
L1L233 = AMPP_FUNCTION(L1_D_iw[4], L1L834, L1_D_iw[5], L1L831);
--L1L836 is std_1s10:inst|cpu:the_cpu|Equal53~790 at LC_X22_Y6_N6
--operation mode is normal
L1L836 = AMPP_FUNCTION(L1_D_iw[4], L1L827, L1_D_iw[5]);
--M1L62 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~5021 at LC_X47_Y12_N8
--operation mode is normal
M1L62 = M1L58 & (Q1_internal_incoming_ext_ram_bus_data[4] # !Q1L97 # !Q1L95);
--M1L180 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[22]~5022 at LC_X46_Y17_N8
--operation mode is normal
M1L180 = M1L178 & (Q1_internal_incoming_ext_ram_bus_data[22] # !Q1L97 # !Q1L95);
--M1L112 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[10]~5023 at LC_X48_Y14_N7
--operation mode is normal
M1L112 = !QB1_cpu_data_master_granted_uart1_s1 & (!L1_M_alu_result[7] & !L1_M_alu_result[4] # !EB1L3);
--M1L230 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~339 at LC_X46_Y8_N8
--operation mode is normal
M1L230 = R1_readdata[15] # !L1_M_alu_result[6] # !L1_M_alu_result[5] # !LB1L2;
--M1L175 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[21]~5024 at LC_X47_Y19_N3
--operation mode is normal
M1L175 = M1L145 & M1L174 & (!NB1_cpu_data_master_granted_sysid_control_slave # !L1_M_alu_result[2]);
--M1L150 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[16]~5025 at LC_X47_Y19_N8
--operation mode is normal
M1L150 = M1L145 & M1L149 & (!NB1_cpu_data_master_granted_sysid_control_slave # !L1_M_alu_result[2]);
--M1L138 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[14]~5026 at LC_X47_Y10_N3
--operation mode is normal
M1L138 = M1L135 & (Q1_internal_incoming_ext_ram_bus_data[14] # !Q1L95 # !Q1L97);
--M1L220 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[30]~5027 at LC_X47_Y13_N7
--operation mode is normal
M1L220 = M1L218 & (Q1_internal_incoming_ext_ram_bus_data[30] # !Q1L97 # !Q1L95);
--M1L229 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~337 at LC_X46_Y8_N6
--operation mode is normal
M1L229 = R1_readdata[13] # !L1_M_alu_result[6] # !L1_M_alu_result[5] # !LB1L2;
--M1L215 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[29]~5028 at LC_X44_Y14_N5
--operation mode is normal
M1L215 = M1L145 & M1L214 & (!L1_M_alu_result[2] # !NB1_cpu_data_master_granted_sysid_control_slave);
--M1L228 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~335 at LC_X46_Y5_N4
--operation mode is normal
M1L228 = R1_readdata[11] # !LB1L2 # !L1_M_alu_result[6] # !L1_M_alu_result[5];
--M1L205 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[27]~5029 at LC_X44_Y14_N8
--operation mode is normal
M1L205 = M1L145 & M1L204 & (!L1_M_alu_result[2] # !NB1_cpu_data_master_granted_sysid_control_slave);
--M1L227 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~333 at LC_X47_Y10_N7
--operation mode is normal
M1L227 = R1_readdata[9] # !L1_M_alu_result[5] # !L1_M_alu_result[6] # !LB1L2;
--M1L104 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[9]~5030 at LC_X47_Y10_N8
--operation mode is normal
M1L104 = M1L101 & (Q1_internal_incoming_ext_ram_bus_data[9] # !Q1L97 # !Q1L95);
--M1L95 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5031 at LC_X48_Y11_N7
--operation mode is normal
M1L95 = M1L92 & (Q1_internal_incoming_ext_ram_bus_data[8] # !Q1L95 # !Q1L97);
--M1L96 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[8]~5032 at LC_X48_Y14_N4
--operation mode is normal
M1L96 = L1_M_alu_result[7] & !G1L1 & (HE1_readdata[8] # !QB1_cpu_data_master_granted_uart1_s1) # !L1_M_alu_result[7] & (HE1_readdata[8] # !QB1_cpu_data_master_granted_uart1_s1);
--M1L231 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata~642 at LC_X48_Y12_N1
--operation mode is normal
M1L231 = L1_M_alu_result[5] # KB1_readdata[5] # L1_M_alu_result[6] # !LB1L2;
--M1L71 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~5033 at LC_X47_Y12_N1
--operation mode is normal
M1L71 = M1L69 & (Q1_internal_incoming_ext_ram_bus_data[5] # !Q1L95 # !Q1L97);
--M1L79 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~5034 at LC_X47_Y14_N7
--operation mode is normal
M1L79 = M1L75 & (Q1_internal_incoming_ext_ram_bus_data[6] # !Q1L97 # !Q1L95);
--C1L5 is sld_hub:sld_hub_inst|comb~97 at LC_X28_Y26_N4
--operation mode is normal
C1L5 = AMPP_FUNCTION(A1L8, altera_internal_jtag, C1L4, ME3_Q[6]);
--QD1L62 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3523 at LC_X34_Y24_N8
--operation mode is normal
QD1L62 = AMPP_FUNCTION(QD1_state, QD1_user_saw_rvalid, QD1_td_shift[9], QD1_count[1]);
--DD1L141 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process2~2 at LC_X32_Y28_N4
--operation mode is normal
DD1L141 = AMPP_FUNCTION(DD1_in_between_shiftdr_and_updatedr, A1L5, DD1L144);
--DB1L3 is std_1s10:inst|reconfig_request_pio:the_reconfig_request_pio|process2~24 at LC_X41_Y15_N9
--operation mode is normal
DB1L3 = EB1L2 & !M1_internal_cpu_data_master_waitrequest & L1_internal_d_write & L1_M_alu_result[7];
--GB1L79 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_winner~0 at LC_X41_Y11_N1
--operation mode is normal
GB1L79 = GB1_WideOr1 & (!GB1L76 & !GB1L19 # !GB1_sdram_s1_slavearbiterlockenable);
--GB1L64 is std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_counter_enable~43 at LC_X39_Y10_N9
--operation mode is normal
GB1L64 = GB1L63 & (EE1_entries[0] # !EE1_entries[1] # !FB1L407);
--L1L884 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[0]~4256 at LC_X35_Y18_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L884 = AMPP_FUNCTION(L1_D_inst_ram_hit, L1_D_kill, L1L882);
--L1_D_pc[3] is std_1s10:inst|cpu:the_cpu|D_pc[3] at LC_X35_Y18_N5
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_D_pc[3] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[3], E1_data_out, GND, L1_W_stall);
--L1L887 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[1]~4257 at LC_X35_Y20_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L887 = AMPP_FUNCTION(L1_D_inst_ram_hit, L1_D_kill, L1L885);
--L1_D_pc[4] is std_1s10:inst|cpu:the_cpu|D_pc[4] at LC_X35_Y20_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_D_pc[4] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[4], E1_data_out, GND, L1_W_stall);
--L1L890 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[2]~4258 at LC_X35_Y18_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L890 = AMPP_FUNCTION(L1_D_inst_ram_hit, L1_D_kill, L1L888);
--L1_D_pc[5] is std_1s10:inst|cpu:the_cpu|D_pc[5] at LC_X35_Y18_N3
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_D_pc[5] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[5], E1_data_out, GND, L1_W_stall);
--L1L893 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[3]~4259 at LC_X35_Y18_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L893 = AMPP_FUNCTION(L1_D_inst_ram_hit, L1_D_kill, L1L891);
--L1_D_pc[6] is std_1s10:inst|cpu:the_cpu|D_pc[6] at LC_X35_Y18_N6
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_D_pc[6] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[6], E1_data_out, GND, L1_W_stall);
--L1L896 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[4]~4260 at LC_X35_Y18_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L896 = AMPP_FUNCTION(L1_D_inst_ram_hit, L1_D_kill, L1L894);
--L1_D_pc[7] is std_1s10:inst|cpu:the_cpu|D_pc[7] at LC_X35_Y18_N9
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_D_pc[7] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[7], E1_data_out, GND, L1_W_stall);
--L1L899 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[5]~4261 at LC_X35_Y18_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L899 = AMPP_FUNCTION(L1_D_inst_ram_hit, L1_D_kill, L1L897);
--L1_D_pc[8] is std_1s10:inst|cpu:the_cpu|D_pc[8] at LC_X35_Y18_N0
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_D_pc[8] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[8], E1_data_out, GND, L1_W_stall);
--L1L902 is std_1s10:inst|cpu:the_cpu|F_ic_tag_rd_addr_nxt[6]~4262 at LC_X30_Y20_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L902 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1L900);
--L1_D_pc[9] is std_1s10:inst|cpu:the_cpu|D_pc[9] at LC_X30_Y20_N1
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_D_pc[9] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[9], E1_data_out, GND, L1_W_stall);
--L1L858 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[2]~1824 at LC_X35_Y17_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L858 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1L856);
--L1_D_pc[2] is std_1s10:inst|cpu:the_cpu|D_pc[2] at LC_X35_Y17_N8
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_D_pc[2] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[2], E1_data_out, GND, L1_W_stall);
--L1L855 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[1]~1825 at LC_X35_Y17_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L855 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1L853);
--L1_D_pc[1] is std_1s10:inst|cpu:the_cpu|D_pc[1] at LC_X35_Y17_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_D_pc[1] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[1], E1_data_out, GND, L1_W_stall);
--L1L852 is std_1s10:inst|cpu:the_cpu|F_ic_data_rd_addr_nxt[0]~1826 at LC_X35_Y16_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1L852 = AMPP_FUNCTION(L1_D_kill, L1_D_inst_ram_hit, L1L850);
--L1_D_pc[0] is std_1s10:inst|cpu:the_cpu|D_pc[0] at LC_X35_Y16_N2
--operation mode is normal --sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.
L1_D_pc[0] = AMPP_FUNCTION(DE1__clk0, L1_F_pc[0], E1_data_out, GND, L1_W_stall);
--L1L1370 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie~155 at LC_X28_Y22_N8
--operation mode is normal
L1L1370 = AMPP_FUNCTION(L1_E_ctrl_exception, L1_E_ctrl_break, L1L567, L1_E_wrctl_status);
--L1L1371 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie~156 at LC_X28_Y22_N6
--operation mode is normal
L1L1371 = AMPP_FUNCTION(L1_E_ctrl_exception, L1L819, L1_W_stall, L1_E_ctrl_break);
--M1L308 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|process3~0 at LC_X41_Y16_N9
--operation mode is normal
M1L308 = !M1_internal_cpu_data_master_dbs_address[1] & (!M1_internal_cpu_data_master_dbs_address[0] & M1L307);
--CD1L71 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|module_input6~23 at LC_X35_Y15_N5
--operation mode is normal
CD1L71 = AMPP_FUNCTION(L1_hbreak_enabled, P1L3, L1_M_alu_result[10], L1_internal_d_write);
--T1L53 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~317 at LC_X50_Y15_N8
--operation mode is normal
T1L53 = T1L48 # L1_M_alu_result[7] # L1_M_alu_result[3] # !EB1L2;
--T1L54 is std_1s10:inst|jtag_uart:the_jtag_uart|Add1~318 at LC_X48_Y13_N7
--operation mode is normal
T1L54 = T1L49 # L1_M_alu_result[7] # L1_M_alu_result[3] # !EB1L2;
--M1L27 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5035 at LC_X46_Y15_N1
--operation mode is normal
M1L27 = M1L22 & (Q1_internal_incoming_ext_ram_bus_data[0] # !Q1L97 # !Q1L95);
--M1L36 is std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5036 at LC_X47_Y14_N9
--operation mode is normal
M1L36 = M1L31 & (Q1_internal_incoming_ext_ram_bus_data[1] # !Q1L97 # !Q1L95);
--L1L1372 is std_1s10:inst|cpu:the_cpu|M_status_reg_pie~157 at LC_X28_Y22_N4
--operation mode is normal
L1L1372 = AMPP_FUNCTION(L1_internal_d_write, L1L819, M1_internal_cpu_data_master_waitrequest, L1L1480);
--WD2L1 is std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|_~28 at LC_X51_Y15_N3
--operation mode is normal
WD2L1 = QD1L37Q & (WD2_b_full $ (!WD2_b_non_empty # !T1L58)) # !QD1L37Q & (T1L58 & WD2_b_non_empty);
--L1L1455 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[26]~3735 at LC_X14_Y14_N0
--operation mode is normal
L1L1455 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[26], L1L1454, L1_M_ctrl_mul_shift_rot);
--L1_W_wr_data[26] is std_1s10:inst|cpu:the_cpu|W_wr_data[26] at LC_X14_Y14_N0
--operation mode is normal
L1_W_wr_data[26] = AMPP_FUNCTION(DE1__clk0, L1_M_mul_shift_rot_result[26], L1L1454, L1_M_ctrl_mul_shift_rot, E1_data_out, L1_W_stall);
--L1L1458 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[27]~3736 at LC_X19_Y16_N8
--operation mode is normal
L1L1458 = AMPP_FUNCTION(L1L1457, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[27]);
--L1_W_wr_data[27] is std_1s10:inst|cpu:the_cpu|W_wr_data[27] at LC_X19_Y16_N8
--operation mode is normal
L1_W_wr_data[27] = AMPP_FUNCTION(DE1__clk0, L1L1457, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[27], E1_data_out, L1_W_stall);
--L1L1461 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[28]~3737 at LC_X18_Y15_N8
--operation mode is normal
L1L1461 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[28], L1_M_ctrl_mul_shift_rot, L1L1460);
--L1_W_wr_data[28] is std_1s10:inst|cpu:the_cpu|W_wr_data[28] at LC_X18_Y15_N8
--operation mode is normal
L1_W_wr_data[28] = AMPP_FUNCTION(DE1__clk0, L1_M_mul_shift_rot_result[28], L1_M_ctrl_mul_shift_rot, L1L1460, E1_data_out, L1_W_stall);
--L1L1464 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[29]~3738 at LC_X19_Y14_N0
--operation mode is normal
L1L1464 = AMPP_FUNCTION(L1_M_mul_shift_rot_result[29], L1_M_ctrl_mul_shift_rot, L1L1463);
--L1_W_wr_data[29] is std_1s10:inst|cpu:the_cpu|W_wr_data[29] at LC_X19_Y14_N0
--operation mode is normal
L1_W_wr_data[29] = AMPP_FUNCTION(DE1__clk0, L1_M_mul_shift_rot_result[29], L1_M_ctrl_mul_shift_rot, L1L1463, E1_data_out, L1_W_stall);
--L1L1467 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[30]~3739 at LC_X18_Y15_N6
--operation mode is normal
L1L1467 = AMPP_FUNCTION(L1_M_ctrl_mul_shift_rot, L1L1466, L1_M_mul_shift_rot_result[30]);
--L1_W_wr_data[30] is std_1s10:inst|cpu:the_cpu|W_wr_data[30] at LC_X18_Y15_N6
--operation mode is normal
L1_W_wr_data[30] = AMPP_FUNCTION(DE1__clk0, L1_M_ctrl_mul_shift_rot, L1L1466, L1_M_mul_shift_rot_result[30], E1_data_out, L1_W_stall);
--L1L1470 is std_1s10:inst|cpu:the_cpu|M_wr_data_unfiltered[31]~3740 at LC_X17_Y13_N6
--operation mode is normal
L1L1470 = AMPP_FUNCTION(L1L1469, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[31]);
--L1_W_wr_data[31] is std_1s10:inst|cpu:the_cpu|W_wr_data[31] at LC_X17_Y13_N6
--operation mode is normal
L1_W_wr_data[31] = AMPP_FUNCTION(DE1__clk0, L1L1469, L1_M_ctrl_mul_shift_rot, L1_M_mul_shift_rot_result[31], E1_data_out, L1_W_stall);
--DD1L70 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19987 at LC_X32_Y28_N6
--operation mode is normal
DD1L70 = AMPP_FUNCTION(DD1_in_between_shiftdr_and_updatedr, DD1L144, DD1_ir[0], A1L5);
--DD1L71 is std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19988 at LC_X34_Y26_N4
--operation mode is normal
DD1L71 = AMPP_FUNCTION(DD1L135, DD1L55, DD1L143, DD1L134);
--L1L212 is std_1s10:inst|cpu:the_cpu|D_ctrl_alu_subtract~411 at LC_X18_Y9_N6
--operation mode is normal
L1L212 = AMPP_FUNCTION(L1_D_iw[15], L1_D_iw[13], L1_D_iw[14]);
--L1L225 is std_1s10:inst|cpu:the_cpu|D_ctrl_dst_data_sel_cmp~275 at LC_X22_Y21_N3
--operation mode is normal
L1L225 = AMPP_FUNCTION(L1_D_iw[15], L1_D_iw[13], L1_D_iw[14]);
--L1L234 is std_1s10:inst|cpu:the_cpu|D_ctrl_flush_pipe_always~735 at LC_X18_Y7_N8
--operation mode is normal
L1L234 = AMPP_FUNCTION(L1_D_iw[11], L1_D_iw[16]);
--L1L227 is std_1s10:inst|cpu:the_cpu|D_ctrl_dst_data_sel_pc_plus_one~92 at LC_X18_Y7_N5
--operation mode is normal
L1L227 = AMPP_FUNCTION(L1_D_iw[16], L1_D_iw[13]);
--L1L241 is std_1s10:inst|cpu:the_cpu|D_ctrl_mul_shift_rot~229 at LC_X19_Y10_N9
--operation mode is normal
L1L241 = AMPP_FUNCTION(L1_D_iw[11], L1_D_iw[13]);
--L1L213 is std_1s10:inst|cpu:the_cpu|D_ctrl_alu_subtract~412 at LC_X21_Y6_N0
--operation mode is normal
L1L213 = AMPP_FUNCTION(L1_D_iw[3], L1_D_iw[2], L1_D_iw[0], L1_D_iw[1]);
--QD1L63 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3524 at LC_X34_Y24_N5
--operation mode is normal
QD1L63 = AMPP_FUNCTION(RE1_state[4], ME4_Q[0], QD1L51, QD1_state);
--QD1L51 is std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3485 at LC_X34_Y23_N9
--operation mode is normal
QD1L51 = AMPP_FUNCTION(QD1_td_shift[9], QD1_user_saw_rvalid, QD1_count[1]);
--L1L837 is std_1s10:inst|cpu:the_cpu|Equal53~791 at LC_X21_Y6_N4
--operation mode is normal
L1L837 = AMPP_FUNCTION(L1_D_iw[3], L1_D_iw[2], L1_D_iw[0], L1_D_iw[1]);
--L1L221 is std_1s10:inst|cpu:the_cpu|D_ctrl_br~19 at LC_X23_Y6_N7
--operation mode is normal
L1L221 = AMPP_FUNCTION(L1_D_iw[2], L1_D_iw[0], L1_D_iw[1]);
--L1L419 is std_1s10:inst|cpu:the_cpu|D_wr_dst_reg~83 at LC_X21_Y6_N3
--operation mode is normal
L1L419 = AMPP_FUNCTION(L1_D_iw[0], L1_D_iw[2], L1_D_iw[1]);
--L1L420 is std_1s10:inst|cpu:the_cpu|D_wr_dst_reg~88 at LC_X19_Y10_N3
--operation mode is normal
L1L420 = AMPP_FUNCTION(L1_D_issue, L1_M_pipe_flush, L1L419);
--L1L421 is std_1s10:inst|cpu:the_cpu|D_wr_dst_reg~89 at LC_X19_Y8_N2
--operation mode is normal
L1L421 = AMPP_FUNCTION(L1_D_iw[0], L1_D_iw[1]);
--L1L245 is std_1s10:inst|cpu:the_cpu|D_ctrl_unsigned_lo_imm~281 at LC_X19_Y18_N7
--operation mode is normal
L1L245 = AMPP_FUNCTION(L1_D_iw[4], L1_D_iw[5], L1_D_iw[3], L1_D_iw[2]);
--L1L246 is std_1s10:inst|cpu:the_cpu|D_ctrl_unsigned_lo_imm~284 at LC_X19_Y16_N1
--operation mode is normal
L1L246 = AMPP_FUNCTION(L1_D_iw[0], L1_D_iw[1], L1L245);
--FB1L559 is std_1s10:inst|sdram:the_sdram|Mux42~1477 at LC_X34_Y1_N6
--operation mode is normal
FB1L559 = FB1_m_state[3] & FB1_m_count[0] & (FB1_m_state[4] # !FB1L553) # !FB1_m_state[3] & (FB1L553 # FB1_m_count[0] # !FB1_m_state[4]);
--FB1L560 is std_1s10:inst|sdram:the_sdram|Mux42~1478 at LC_X34_Y1_N8
--operation mode is normal
FB1L560 = FB1L559 & (FB1L557 # FB1_m_state[3] # FB1_m_state[4]);
--A1L275 is ~GND at LC_X52_Y12_N5
--operation mode is normal
A1L275 = GND;
--PLD_CLOCKINPUT is PLD_CLOCKINPUT at PIN_K17
--operation mode is input
PLD_CLOCKINPUT = INPUT();
--PLD_CLEAR_N is PLD_CLEAR_N at PIN_AC9
--operation mode is input
PLD_CLEAR_N = INPUT();
--in_port_to_the_button_pio[2] is in_port_to_the_button_pio[2] at PIN_AB2
--operation mode is input
in_port_to_the_button_pio[2] = INPUT();
--in_port_to_the_button_pio[3] is in_port_to_the_button_pio[3] at PIN_AB1
--operation mode is input
in_port_to_the_button_pio[3] = INPUT();
--irq_from_the_lan91c111 is irq_from_the_lan91c111 at PIN_V27
--operation mode is input
irq_from_the_lan91c111 = INPUT();
--in_port_to_the_button_pio[1] is in_port_to_the_button_pio[1] at PIN_W6
--operation mode is input
in_port_to_the_button_pio[1] = INPUT();
--in_port_to_the_button_pio[0] is in_port_to_the_button_pio[0] at PIN_W5
--operation mode is input
in_port_to_the_button_pio[0] = INPUT();
--rxd_to_the_uart1 is rxd_to_the_uart1 at PIN_Y28
--operation mode is input
rxd_to_the_uart1 = INPUT();
--ENET_ADS_N is ENET_ADS_N at PIN_V25
--operation mode is output
ENET_ADS_N = OUTPUT(A1L275);
--ENET_AEN is ENET_AEN at PIN_V28
--operation mode is output
--ior_n_to_the_lan91c111 is ior_n_to_the_lan91c111 at PIN_T23
--operation mode is output --output register power-up is high
ior_n_to_the_lan91c111 = OUTPUT(Q1_ior_n_to_the_lan91c111);
--Q1_ior_n_to_the_lan91c111 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ior_n_to_the_lan91c111 at PIN_T23
--operation mode is output --output register power-up is high
Q1_ior_n_to_the_lan91c111 = DFFE(!Q1L396, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--write_n_to_the_ext_flash is write_n_to_the_ext_flash at PIN_G19
--operation mode is output --output register power-up is high
write_n_to_the_ext_flash = OUTPUT(Q1_write_n_to_the_ext_flash);
--Q1_write_n_to_the_ext_flash is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_flash at PIN_G19
--operation mode is output --output register power-up is high
Q1_write_n_to_the_ext_flash = DFFE(!Q1L465, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--iow_n_to_the_lan91c111 is iow_n_to_the_lan91c111 at PIN_T24
--operation mode is output --output register power-up is high
iow_n_to_the_lan91c111 = OUTPUT(Q1_iow_n_to_the_lan91c111);
--Q1_iow_n_to_the_lan91c111 is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|iow_n_to_the_lan91c111 at PIN_T24
--operation mode is output --output register power-up is high
Q1_iow_n_to_the_lan91c111 = DFFE(!Q1L399, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--read_n_to_the_ext_flash is read_n_to_the_ext_flash at PIN_F19
--operation mode is output --output register power-up is high
read_n_to_the_ext_flash = OUTPUT(Q1_read_n_to_the_ext_flash);
--Q1_read_n_to_the_ext_flash is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_flash at PIN_F19
--operation mode is output --output register power-up is high
Q1_read_n_to_the_ext_flash = DFFE(!Q1L453, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--read_n_to_the_ext_ram is read_n_to_the_ext_ram at PIN_B26
--operation mode is output --output register power-up is high
read_n_to_the_ext_ram = OUTPUT(Q1_read_n_to_the_ext_ram);
--Q1_read_n_to_the_ext_ram is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram at PIN_B26
--operation mode is output --output register power-up is high
Q1_read_n_to_the_ext_ram = DFFE(!Q1L456, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--select_n_to_the_ext_ram is select_n_to_the_ext_ram at PIN_B24
--operation mode is output --output register power-up is high
select_n_to_the_ext_ram = OUTPUT(Q1_select_n_to_the_ext_ram);
--Q1_select_n_to_the_ext_ram is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram at PIN_B24
--operation mode is output --output register power-up is high
Q1_select_n_to_the_ext_ram = DFFE(!Q1L460, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--write_n_to_the_ext_ram is write_n_to_the_ext_ram at PIN_C24
--operation mode is output
write_n_to_the_ext_ram = OUTPUT(!Q1L468);
--zs_cas_n_from_the_sdram is zs_cas_n_from_the_sdram at PIN_AD18
--operation mode is output --output register power-up is high
zs_cas_n_from_the_sdram = OUTPUT(FB1_m_cmd[1]);
--FB1_m_cmd[1] is std_1s10:inst|sdram:the_sdram|m_cmd[1] at PIN_AD18
--operation mode is output --output register power-up is high
FB1_m_cmd[1] = DFFE(!FB1L224, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--zs_cke_from_the_sdram is zs_cke_from_the_sdram at PIN_AE18
--operation mode is output
zs_cke_from_the_sdram = OUTPUT(!A1L275);
--zs_cs_n_from_the_sdram is zs_cs_n_from_the_sdram at PIN_AG18
--operation mode is output --output register power-up is high
zs_cs_n_from_the_sdram = OUTPUT(FB1_m_cmd[3]);
--FB1_m_cmd[3] is std_1s10:inst|sdram:the_sdram|m_cmd[3] at PIN_AG18
--operation mode is output --output register power-up is high
FB1_m_cmd[3] = DFFE(!FB1L232, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--zs_ras_n_from_the_sdram is zs_ras_n_from_the_sdram at PIN_AH3
--operation mode is output --output register power-up is high
zs_ras_n_from_the_sdram = OUTPUT(FB1_m_cmd[2]);
--FB1_m_cmd[2] is std_1s10:inst|sdram:the_sdram|m_cmd[2] at PIN_AH3
--operation mode is output --output register power-up is high
FB1_m_cmd[2] = DFFE(!FB1L228, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--zs_we_n_from_the_sdram is zs_we_n_from_the_sdram at PIN_AH19
--operation mode is output --output register power-up is high
zs_we_n_from_the_sdram = OUTPUT(FB1_m_cmd[0]);
--FB1_m_cmd[0] is std_1s10:inst|sdram:the_sdram|m_cmd[0] at PIN_AH19
--operation mode is output --output register power-up is high
FB1_m_cmd[0] = DFFE(!FB1L220, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--LCD_RW_from_the_lcd_display is LCD_RW_from_the_lcd_display at PIN_M8
--operation mode is output
LCD_RW_from_the_lcd_display = OUTPUT(L1_M_alu_result[2]);
--LCD_RS_from_the_lcd_display is LCD_RS_from_the_lcd_display at PIN_M7
--operation mode is output
LCD_RS_from_the_lcd_display = OUTPUT(L1_M_alu_result[3]);
--LCD_E_from_the_lcd_display is LCD_E_from_the_lcd_display at PIN_K3
--operation mode is output
LCD_E_from_the_lcd_display = OUTPUT(V1L4);
--txd_from_the_uart1 is txd_from_the_uart1 at PIN_U21
--operation mode is output
txd_from_the_uart1 = OUTPUT(!KE1_txd);
--select_n_to_the_ext_flash is select_n_to_the_ext_flash at PIN_K19
--operation mode is output --output register power-up is high
select_n_to_the_ext_flash = OUTPUT(Q1_select_n_to_the_ext_flash);
--Q1_select_n_to_the_ext_flash is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_flash at PIN_K19
--operation mode is output --output register power-up is high
Q1_select_n_to_the_ext_flash = DFFE(!Q1L446, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--SDRAM_CLKOUT is SDRAM_CLKOUT at PIN_E15
--operation mode is output
SDRAM_CLKOUT = OUTPUT(DE1__extclk0);
--be_n_to_the_ext_ram[3] is be_n_to_the_ext_ram[3] at PIN_L17
--operation mode is output --output register power-up is high
be_n_to_the_ext_ram[3] = OUTPUT(Q1_be_n_to_the_ext_ram[3]);
--Q1_be_n_to_the_ext_ram[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[3] at PIN_L17
--operation mode is output --output register power-up is high
Q1_be_n_to_the_ext_ram[3] = DFFE(!Q1L52, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--be_n_to_the_ext_ram[2] is be_n_to_the_ext_ram[2] at PIN_J18
--operation mode is output --output register power-up is high
be_n_to_the_ext_ram[2] = OUTPUT(Q1_be_n_to_the_ext_ram[2]);
--Q1_be_n_to_the_ext_ram[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[2] at PIN_J18
--operation mode is output --output register power-up is high
Q1_be_n_to_the_ext_ram[2] = DFFE(!Q1L49, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--be_n_to_the_ext_ram[1] is be_n_to_the_ext_ram[1] at PIN_F17
--operation mode is output --output register power-up is high
be_n_to_the_ext_ram[1] = OUTPUT(Q1_be_n_to_the_ext_ram[1]);
--Q1_be_n_to_the_ext_ram[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[1] at PIN_F17
--operation mode is output --output register power-up is high
Q1_be_n_to_the_ext_ram[1] = DFFE(!Q1L46, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--be_n_to_the_ext_ram[0] is be_n_to_the_ext_ram[0] at PIN_M18
--operation mode is output --output register power-up is high
be_n_to_the_ext_ram[0] = OUTPUT(Q1_be_n_to_the_ext_ram[0]);
--Q1_be_n_to_the_ext_ram[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[0] at PIN_M18
--operation mode is output --output register power-up is high
Q1_be_n_to_the_ext_ram[0] = DFFE(!Q1L43, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--byteenablen_to_the_lan91c111[3] is byteenablen_to_the_lan91c111[3] at PIN_T19
--operation mode is output --output register power-up is high
byteenablen_to_the_lan91c111[3] = OUTPUT(Q1_byteenablen_to_the_lan91c111[3]);
--Q1_byteenablen_to_the_lan91c111[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[3] at PIN_T19
--operation mode is output --output register power-up is high
Q1_byteenablen_to_the_lan91c111[3] = DFFE(!Q1L65, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--byteenablen_to_the_lan91c111[2] is byteenablen_to_the_lan91c111[2] at PIN_U25
--operation mode is output --output register power-up is high
byteenablen_to_the_lan91c111[2] = OUTPUT(Q1_byteenablen_to_the_lan91c111[2]);
--Q1_byteenablen_to_the_lan91c111[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[2] at PIN_U25
--operation mode is output --output register power-up is high
Q1_byteenablen_to_the_lan91c111[2] = DFFE(!Q1L62, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--byteenablen_to_the_lan91c111[1] is byteenablen_to_the_lan91c111[1] at PIN_U26
--operation mode is output --output register power-up is high
byteenablen_to_the_lan91c111[1] = OUTPUT(Q1_byteenablen_to_the_lan91c111[1]);
--Q1_byteenablen_to_the_lan91c111[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[1] at PIN_U26
--operation mode is output --output register power-up is high
Q1_byteenablen_to_the_lan91c111[1] = DFFE(!Q1L59, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--byteenablen_to_the_lan91c111[0] is byteenablen_to_the_lan91c111[0] at PIN_T22
--operation mode is output --output register power-up is high
byteenablen_to_the_lan91c111[0] = OUTPUT(Q1_byteenablen_to_the_lan91c111[0]);
--Q1_byteenablen_to_the_lan91c111[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[0] at PIN_T22
--operation mode is output --output register power-up is high
Q1_byteenablen_to_the_lan91c111[0] = DFFE(!Q1L56, GLOBAL(DE1__clk0), , GLOBAL(E1_data_out), );
--ext_ram_bus_address[22] is ext_ram_bus_address[22] at PIN_B9
--operation mode is output --output register power-up is low
ext_ram_bus_address[22] = OUTPUT(Q1_ext_ram_bus_address[22]);
--Q1_ext_ram_bus_address[22] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22] at PIN_B9
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[22] = DFFE(Q1L323, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[21] is ext_ram_bus_address[21] at PIN_D9
--operation mode is output --output register power-up is low
ext_ram_bus_address[21] = OUTPUT(Q1_ext_ram_bus_address[21]);
--Q1_ext_ram_bus_address[21] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21] at PIN_D9
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[21] = DFFE(Q1L320, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[20] is ext_ram_bus_address[20] at PIN_E8
--operation mode is output --output register power-up is low
ext_ram_bus_address[20] = OUTPUT(Q1_ext_ram_bus_address[20]);
--Q1_ext_ram_bus_address[20] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20] at PIN_E8
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[20] = DFFE(Q1L317, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[19] is ext_ram_bus_address[19] at PIN_C8
--operation mode is output --output register power-up is low
ext_ram_bus_address[19] = OUTPUT(Q1_ext_ram_bus_address[19]);
--Q1_ext_ram_bus_address[19] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[19] at PIN_C8
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[19] = DFFE(Q1L314, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[18] is ext_ram_bus_address[18] at PIN_D8
--operation mode is output --output register power-up is low
ext_ram_bus_address[18] = OUTPUT(Q1_ext_ram_bus_address[18]);
--Q1_ext_ram_bus_address[18] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[18] at PIN_D8
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[18] = DFFE(Q1L312, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[17] is ext_ram_bus_address[17] at PIN_B6
--operation mode is output --output register power-up is low
ext_ram_bus_address[17] = OUTPUT(Q1_ext_ram_bus_address[17]);
--Q1_ext_ram_bus_address[17] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17] at PIN_B6
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[17] = DFFE(Q1L310, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[16] is ext_ram_bus_address[16] at PIN_C7
--operation mode is output --output register power-up is low
ext_ram_bus_address[16] = OUTPUT(Q1_ext_ram_bus_address[16]);
--Q1_ext_ram_bus_address[16] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[16] at PIN_C7
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[16] = DFFE(Q1L307, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[15] is ext_ram_bus_address[15] at PIN_C6
--operation mode is output --output register power-up is low
ext_ram_bus_address[15] = OUTPUT(Q1_ext_ram_bus_address[15]);
--Q1_ext_ram_bus_address[15] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[15] at PIN_C6
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[15] = DFFE(Q1L304, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[14] is ext_ram_bus_address[14] at PIN_D7
--operation mode is output --output register power-up is low
ext_ram_bus_address[14] = OUTPUT(Q1_ext_ram_bus_address[14]);
--Q1_ext_ram_bus_address[14] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[14] at PIN_D7
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[14] = DFFE(Q1L301, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[13] is ext_ram_bus_address[13] at PIN_A7
--operation mode is output --output register power-up is low
ext_ram_bus_address[13] = OUTPUT(Q1_ext_ram_bus_address[13]);
--Q1_ext_ram_bus_address[13] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[13] at PIN_A7
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[13] = DFFE(Q1L299, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[12] is ext_ram_bus_address[12] at PIN_D6
--operation mode is output --output register power-up is low
ext_ram_bus_address[12] = OUTPUT(Q1_ext_ram_bus_address[12]);
--Q1_ext_ram_bus_address[12] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[12] at PIN_D6
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[12] = DFFE(Q1L296, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[11] is ext_ram_bus_address[11] at PIN_B7
--operation mode is output --output register power-up is low
ext_ram_bus_address[11] = OUTPUT(Q1_ext_ram_bus_address[11]);
--Q1_ext_ram_bus_address[11] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[11] at PIN_B7
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[11] = DFFE(Q1L293, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[10] is ext_ram_bus_address[10] at PIN_A6
--operation mode is output --output register power-up is low
ext_ram_bus_address[10] = OUTPUT(Q1_ext_ram_bus_address[10]);
--Q1_ext_ram_bus_address[10] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[10] at PIN_A6
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[10] = DFFE(Q1L291, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[9] is ext_ram_bus_address[9] at PIN_E6
--operation mode is output --output register power-up is low
ext_ram_bus_address[9] = OUTPUT(Q1_ext_ram_bus_address[9]);
--Q1_ext_ram_bus_address[9] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[9] at PIN_E6
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[9] = DFFE(Q1L288, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[8] is ext_ram_bus_address[8] at PIN_D5
--operation mode is output --output register power-up is low
ext_ram_bus_address[8] = OUTPUT(Q1_ext_ram_bus_address[8]);
--Q1_ext_ram_bus_address[8] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[8] at PIN_D5
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[8] = DFFE(Q1L285, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[7] is ext_ram_bus_address[7] at PIN_C5
--operation mode is output --output register power-up is low
ext_ram_bus_address[7] = OUTPUT(Q1_ext_ram_bus_address[7]);
--Q1_ext_ram_bus_address[7] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[7] at PIN_C5
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[7] = DFFE(Q1L282, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[6] is ext_ram_bus_address[6] at PIN_A5
--operation mode is output --output register power-up is low
ext_ram_bus_address[6] = OUTPUT(Q1_ext_ram_bus_address[6]);
--Q1_ext_ram_bus_address[6] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[6] at PIN_A5
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[6] = DFFE(Q1L279, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[5] is ext_ram_bus_address[5] at PIN_C4
--operation mode is output --output register power-up is low
ext_ram_bus_address[5] = OUTPUT(Q1_ext_ram_bus_address[5]);
--Q1_ext_ram_bus_address[5] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[5] at PIN_C4
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[5] = DFFE(Q1L276, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[4] is ext_ram_bus_address[4] at PIN_B4
--operation mode is output --output register power-up is low
ext_ram_bus_address[4] = OUTPUT(Q1_ext_ram_bus_address[4]);
--Q1_ext_ram_bus_address[4] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[4] at PIN_B4
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[4] = DFFE(Q1L273, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[3] is ext_ram_bus_address[3] at PIN_B5
--operation mode is output --output register power-up is low
ext_ram_bus_address[3] = OUTPUT(Q1_ext_ram_bus_address[3]);
--Q1_ext_ram_bus_address[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[3] at PIN_B5
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[3] = DFFE(Q1L270, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[2] is ext_ram_bus_address[2] at PIN_B3
--operation mode is output --output register power-up is low
ext_ram_bus_address[2] = OUTPUT(Q1_ext_ram_bus_address[2]);
--Q1_ext_ram_bus_address[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[2] at PIN_B3
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[2] = DFFE(Q1L267, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[1] is ext_ram_bus_address[1] at PIN_A3
--operation mode is output --output register power-up is low
ext_ram_bus_address[1] = OUTPUT(Q1_ext_ram_bus_address[1]);
--Q1_ext_ram_bus_address[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[1] at PIN_A3
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[1] = DFFE(Q1L264, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_address[0] is ext_ram_bus_address[0] at PIN_A4
--operation mode is output --output register power-up is low
ext_ram_bus_address[0] = OUTPUT(Q1_ext_ram_bus_address[0]);
--Q1_ext_ram_bus_address[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[0] at PIN_A4
--operation mode is output --output register power-up is low
Q1_ext_ram_bus_address[0] = DFFE(Q1L261, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--out_port_from_the_led_pio[7] is out_port_from_the_led_pio[7] at PIN_L19
--operation mode is output
out_port_from_the_led_pio[7] = OUTPUT(X1_data_out[7]);
--out_port_from_the_led_pio[6] is out_port_from_the_led_pio[6] at PIN_L20
--operation mode is output
out_port_from_the_led_pio[6] = OUTPUT(X1_data_out[6]);
--out_port_from_the_led_pio[5] is out_port_from_the_led_pio[5] at PIN_J26
--operation mode is output
out_port_from_the_led_pio[5] = OUTPUT(X1_data_out[5]);
--out_port_from_the_led_pio[4] is out_port_from_the_led_pio[4] at PIN_J25
--operation mode is output
out_port_from_the_led_pio[4] = OUTPUT(X1_data_out[4]);
--out_port_from_the_led_pio[3] is out_port_from_the_led_pio[3] at PIN_L24
--operation mode is output
out_port_from_the_led_pio[3] = OUTPUT(X1_data_out[3]);
--out_port_from_the_led_pio[2] is out_port_from_the_led_pio[2] at PIN_L23
--operation mode is output
out_port_from_the_led_pio[2] = OUTPUT(X1_data_out[2]);
--out_port_from_the_led_pio[1] is out_port_from_the_led_pio[1] at PIN_H28
--operation mode is output
out_port_from_the_led_pio[1] = OUTPUT(X1_data_out[1]);
--out_port_from_the_led_pio[0] is out_port_from_the_led_pio[0] at PIN_H27
--operation mode is output
out_port_from_the_led_pio[0] = OUTPUT(X1_data_out[0]);
--out_port_from_the_seven_seg_pio[15] is out_port_from_the_seven_seg_pio[15] at PIN_D19
--operation mode is output
out_port_from_the_seven_seg_pio[15] = OUTPUT(HB1_data_out[15]);
--out_port_from_the_seven_seg_pio[14] is out_port_from_the_seven_seg_pio[14] at PIN_A18
--operation mode is output
out_port_from_the_seven_seg_pio[14] = OUTPUT(HB1_data_out[14]);
--out_port_from_the_seven_seg_pio[13] is out_port_from_the_seven_seg_pio[13] at PIN_C18
--operation mode is output
out_port_from_the_seven_seg_pio[13] = OUTPUT(HB1_data_out[13]);
--out_port_from_the_seven_seg_pio[12] is out_port_from_the_seven_seg_pio[12] at PIN_D18
--operation mode is output
out_port_from_the_seven_seg_pio[12] = OUTPUT(HB1_data_out[12]);
--out_port_from_the_seven_seg_pio[11] is out_port_from_the_seven_seg_pio[11] at PIN_A19
--operation mode is output
out_port_from_the_seven_seg_pio[11] = OUTPUT(HB1_data_out[11]);
--out_port_from_the_seven_seg_pio[10] is out_port_from_the_seven_seg_pio[10] at PIN_B19
--operation mode is output
out_port_from_the_seven_seg_pio[10] = OUTPUT(HB1_data_out[10]);
--out_port_from_the_seven_seg_pio[9] is out_port_from_the_seven_seg_pio[9] at PIN_C19
--operation mode is output
out_port_from_the_seven_seg_pio[9] = OUTPUT(HB1_data_out[9]);
--out_port_from_the_seven_seg_pio[8] is out_port_from_the_seven_seg_pio[8] at PIN_E19
--operation mode is output
out_port_from_the_seven_seg_pio[8] = OUTPUT(HB1_data_out[8]);
--out_port_from_the_seven_seg_pio[7] is out_port_from_the_seven_seg_pio[7] at PIN_D21
--operation mode is output
out_port_from_the_seven_seg_pio[7] = OUTPUT(HB1_data_out[7]);
--out_port_from_the_seven_seg_pio[6] is out_port_from_the_seven_seg_pio[6] at PIN_B18
--operation mode is output
out_port_from_the_seven_seg_pio[6] = OUTPUT(HB1_data_out[6]);
--out_port_from_the_seven_seg_pio[5] is out_port_from_the_seven_seg_pio[5] at PIN_B20
--operation mode is output
out_port_from_the_seven_seg_pio[5] = OUTPUT(HB1_data_out[5]);
--out_port_from_the_seven_seg_pio[4] is out_port_from_the_seven_seg_pio[4] at PIN_A20
--operation mode is output
out_port_from_the_seven_seg_pio[4] = OUTPUT(HB1_data_out[4]);
--out_port_from_the_seven_seg_pio[3] is out_port_from_the_seven_seg_pio[3] at PIN_C20
--operation mode is output
out_port_from_the_seven_seg_pio[3] = OUTPUT(HB1_data_out[3]);
--out_port_from_the_seven_seg_pio[2] is out_port_from_the_seven_seg_pio[2] at PIN_A21
--operation mode is output
out_port_from_the_seven_seg_pio[2] = OUTPUT(HB1_data_out[2]);
--out_port_from_the_seven_seg_pio[1] is out_port_from_the_seven_seg_pio[1] at PIN_B21
--operation mode is output
out_port_from_the_seven_seg_pio[1] = OUTPUT(HB1_data_out[1]);
--out_port_from_the_seven_seg_pio[0] is out_port_from_the_seven_seg_pio[0] at PIN_C21
--operation mode is output
out_port_from_the_seven_seg_pio[0] = OUTPUT(HB1_data_out[0]);
--zs_addr_from_the_sdram[11] is zs_addr_from_the_sdram[11] at PIN_AB7
--operation mode is output --output register power-up is low
zs_addr_from_the_sdram[11] = OUTPUT(FB1_m_addr[11]);
--FB1_m_addr[11] is std_1s10:inst|sdram:the_sdram|m_addr[11] at PIN_AB7
--operation mode is output --output register power-up is low
FB1_m_addr[11] = DFFE(FB1L206, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_addr_from_the_sdram[10] is zs_addr_from_the_sdram[10] at PIN_Y11
--operation mode is output --output register power-up is low
zs_addr_from_the_sdram[10] = OUTPUT(FB1_m_addr[10]);
--FB1_m_addr[10] is std_1s10:inst|sdram:the_sdram|m_addr[10] at PIN_Y11
--operation mode is output --output register power-up is low
FB1_m_addr[10] = DFFE(FB1L202, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_addr_from_the_sdram[9] is zs_addr_from_the_sdram[9] at PIN_V11
--operation mode is output --output register power-up is low
zs_addr_from_the_sdram[9] = OUTPUT(FB1_m_addr[9]);
--FB1_m_addr[9] is std_1s10:inst|sdram:the_sdram|m_addr[9] at PIN_V11
--operation mode is output --output register power-up is low
FB1_m_addr[9] = DFFE(FB1L198, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_addr_from_the_sdram[8] is zs_addr_from_the_sdram[8] at PIN_AB10
--operation mode is output --output register power-up is low
zs_addr_from_the_sdram[8] = OUTPUT(FB1_m_addr[8]);
--FB1_m_addr[8] is std_1s10:inst|sdram:the_sdram|m_addr[8] at PIN_AB10
--operation mode is output --output register power-up is low
FB1_m_addr[8] = DFFE(FB1L194, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_addr_from_the_sdram[7] is zs_addr_from_the_sdram[7] at PIN_AC8
--operation mode is output --output register power-up is low
zs_addr_from_the_sdram[7] = OUTPUT(FB1_m_addr[7]);
--FB1_m_addr[7] is std_1s10:inst|sdram:the_sdram|m_addr[7] at PIN_AC8
--operation mode is output --output register power-up is low
FB1_m_addr[7] = DFFE(FB1L190, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_addr_from_the_sdram[6] is zs_addr_from_the_sdram[6] at PIN_AB11
--operation mode is output --output register power-up is low
zs_addr_from_the_sdram[6] = OUTPUT(FB1_m_addr[6]);
--FB1_m_addr[6] is std_1s10:inst|sdram:the_sdram|m_addr[6] at PIN_AB11
--operation mode is output --output register power-up is low
FB1_m_addr[6] = DFFE(FB1L186, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_addr_from_the_sdram[5] is zs_addr_from_the_sdram[5] at PIN_AC10
--operation mode is output --output register power-up is low
zs_addr_from_the_sdram[5] = OUTPUT(FB1_m_addr[5]);
--FB1_m_addr[5] is std_1s10:inst|sdram:the_sdram|m_addr[5] at PIN_AC10
--operation mode is output --output register power-up is low
FB1_m_addr[5] = DFFE(FB1L182, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_addr_from_the_sdram[4] is zs_addr_from_the_sdram[4] at PIN_AA11
--operation mode is output --output register power-up is low
zs_addr_from_the_sdram[4] = OUTPUT(FB1_m_addr[4]);
--FB1_m_addr[4] is std_1s10:inst|sdram:the_sdram|m_addr[4] at PIN_AA11
--operation mode is output --output register power-up is low
FB1_m_addr[4] = DFFE(FB1L178, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_addr_from_the_sdram[3] is zs_addr_from_the_sdram[3] at PIN_W10
--operation mode is output --output register power-up is low
zs_addr_from_the_sdram[3] = OUTPUT(FB1_m_addr[3]);
--FB1_m_addr[3] is std_1s10:inst|sdram:the_sdram|m_addr[3] at PIN_W10
--operation mode is output --output register power-up is low
FB1_m_addr[3] = DFFE(FB1L174, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_addr_from_the_sdram[2] is zs_addr_from_the_sdram[2] at PIN_AC11
--operation mode is output --output register power-up is low
zs_addr_from_the_sdram[2] = OUTPUT(FB1_m_addr[2]);
--FB1_m_addr[2] is std_1s10:inst|sdram:the_sdram|m_addr[2] at PIN_AC11
--operation mode is output --output register power-up is low
FB1_m_addr[2] = DFFE(FB1L170, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_addr_from_the_sdram[1] is zs_addr_from_the_sdram[1] at PIN_W12
--operation mode is output --output register power-up is low
zs_addr_from_the_sdram[1] = OUTPUT(FB1_m_addr[1]);
--FB1_m_addr[1] is std_1s10:inst|sdram:the_sdram|m_addr[1] at PIN_W12
--operation mode is output --output register power-up is low
FB1_m_addr[1] = DFFE(FB1L166, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_addr_from_the_sdram[0] is zs_addr_from_the_sdram[0] at PIN_AE4
--operation mode is output --output register power-up is low
zs_addr_from_the_sdram[0] = OUTPUT(FB1_m_addr[0]);
--FB1_m_addr[0] is std_1s10:inst|sdram:the_sdram|m_addr[0] at PIN_AE4
--operation mode is output --output register power-up is low
FB1_m_addr[0] = DFFE(FB1L162, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_ba_from_the_sdram[1] is zs_ba_from_the_sdram[1] at PIN_AF19
--operation mode is output --output register power-up is low
zs_ba_from_the_sdram[1] = OUTPUT(FB1_m_bank[1]);
--FB1_m_bank[1] is std_1s10:inst|sdram:the_sdram|m_bank[1] at PIN_AF19
--operation mode is output --output register power-up is low
FB1_m_bank[1] = DFFE(FB1L215, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_ba_from_the_sdram[0] is zs_ba_from_the_sdram[0] at PIN_AG19
--operation mode is output --output register power-up is low
zs_ba_from_the_sdram[0] = OUTPUT(FB1_m_bank[0]);
--FB1_m_bank[0] is std_1s10:inst|sdram:the_sdram|m_bank[0] at PIN_AG19
--operation mode is output --output register power-up is low
FB1_m_bank[0] = DFFE(FB1L211, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dqm_from_the_sdram[3] is zs_dqm_from_the_sdram[3] at PIN_AG10
--operation mode is output --output register power-up is low
zs_dqm_from_the_sdram[3] = OUTPUT(FB1_m_dqm[3]);
--FB1_m_dqm[3] is std_1s10:inst|sdram:the_sdram|m_dqm[3] at PIN_AG10
--operation mode is output --output register power-up is low
FB1_m_dqm[3] = DFFE(FB1L383, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dqm_from_the_sdram[2] is zs_dqm_from_the_sdram[2] at PIN_AE7
--operation mode is output --output register power-up is low
zs_dqm_from_the_sdram[2] = OUTPUT(FB1_m_dqm[2]);
--FB1_m_dqm[2] is std_1s10:inst|sdram:the_sdram|m_dqm[2] at PIN_AE7
--operation mode is output --output register power-up is low
FB1_m_dqm[2] = DFFE(FB1L379, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dqm_from_the_sdram[1] is zs_dqm_from_the_sdram[1] at PIN_Y13
--operation mode is output --output register power-up is low
zs_dqm_from_the_sdram[1] = OUTPUT(FB1_m_dqm[1]);
--FB1_m_dqm[1] is std_1s10:inst|sdram:the_sdram|m_dqm[1] at PIN_Y13
--operation mode is output --output register power-up is low
FB1_m_dqm[1] = DFFE(FB1L375, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dqm_from_the_sdram[0] is zs_dqm_from_the_sdram[0] at PIN_AE14
--operation mode is output --output register power-up is low
zs_dqm_from_the_sdram[0] = OUTPUT(FB1_m_dqm[0]);
--FB1_m_dqm[0] is std_1s10:inst|sdram:the_sdram|m_dqm[0] at PIN_AE14
--operation mode is output --output register power-up is low
FB1_m_dqm[0] = DFFE(FB1L371, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--A1L22 is bidir_port_to_and_from_the_reconfig_request_pio~0 at PIN_U2
--operation mode is bidir
A1L22 = bidir_port_to_and_from_the_reconfig_request_pio;
--bidir_port_to_and_from_the_reconfig_request_pio is bidir_port_to_and_from_the_reconfig_request_pio at PIN_U2
--operation mode is bidir
bidir_port_to_and_from_the_reconfig_request_pio_tri_out = TRI(DB1_data_out, DB1_data_dir);
bidir_port_to_and_from_the_reconfig_request_pio = BIDIR(bidir_port_to_and_from_the_reconfig_request_pio_tri_out);
--Q1_internal_incoming_ext_ram_bus_data[31] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[31] at PIN_G7
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[31] = DFFE(ext_ram_bus_data[31], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[31] is ext_ram_bus_data[31] at PIN_G7
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[31]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[31], Q1L151Q);
ext_ram_bus_data[31] = BIDIR(ext_ram_bus_data[31]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[31] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[31] at PIN_G7
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[31] = DFFE(Q1L243, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L151Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_31 at PIN_G7
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L151Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[30] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[30] at PIN_L11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[30] = DFFE(ext_ram_bus_data[30], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[30] is ext_ram_bus_data[30] at PIN_L11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[30]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[30], Q1L150Q);
ext_ram_bus_data[30] = BIDIR(ext_ram_bus_data[30]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[30] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[30] at PIN_L11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[30] = DFFE(Q1L240, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L150Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_30 at PIN_L11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L150Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[29] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[29] at PIN_M11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[29] = DFFE(ext_ram_bus_data[29], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[29] is ext_ram_bus_data[29] at PIN_M11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[29]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[29], Q1L149Q);
ext_ram_bus_data[29] = BIDIR(ext_ram_bus_data[29]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[29] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[29] at PIN_M11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[29] = DFFE(Q1L237, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L149Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_29 at PIN_M11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L149Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[28] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[28] at PIN_L13
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[28] = DFFE(ext_ram_bus_data[28], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[28] is ext_ram_bus_data[28] at PIN_L13
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[28]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[28], Q1L148Q);
ext_ram_bus_data[28] = BIDIR(ext_ram_bus_data[28]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[28] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[28] at PIN_L13
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[28] = DFFE(Q1L234, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L148Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_28 at PIN_L13
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L148Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[27] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[27] at PIN_J13
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[27] = DFFE(ext_ram_bus_data[27], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[27] is ext_ram_bus_data[27] at PIN_J13
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[27]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[27], Q1L147Q);
ext_ram_bus_data[27] = BIDIR(ext_ram_bus_data[27]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[27] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[27] at PIN_J13
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[27] = DFFE(Q1L231, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L147Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_27 at PIN_J13
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L147Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[26] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[26] at PIN_J9
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[26] = DFFE(ext_ram_bus_data[26], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[26] is ext_ram_bus_data[26] at PIN_J9
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[26]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[26], Q1L146Q);
ext_ram_bus_data[26] = BIDIR(ext_ram_bus_data[26]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[26] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[26] at PIN_J9
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[26] = DFFE(Q1L228, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L146Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_26 at PIN_J9
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L146Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[25] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[25] at PIN_F8
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[25] = DFFE(ext_ram_bus_data[25], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[25] is ext_ram_bus_data[25] at PIN_F8
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[25]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[25], Q1L145Q);
ext_ram_bus_data[25] = BIDIR(ext_ram_bus_data[25]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[25] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[25] at PIN_F8
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[25] = DFFE(Q1L225, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L145Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_25 at PIN_F8
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L145Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[24] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[24] at PIN_G11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[24] = DFFE(ext_ram_bus_data[24], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[24] is ext_ram_bus_data[24] at PIN_G11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[24]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[24], Q1L144Q);
ext_ram_bus_data[24] = BIDIR(ext_ram_bus_data[24]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[24] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[24] at PIN_G11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[24] = DFFE(Q1L222, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L144Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_24 at PIN_G11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L144Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[23] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[23] at PIN_H11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[23] = DFFE(ext_ram_bus_data[23], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[23] is ext_ram_bus_data[23] at PIN_H11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[23]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[23], Q1L143Q);
ext_ram_bus_data[23] = BIDIR(ext_ram_bus_data[23]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[23] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[23] at PIN_H11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[23] = DFFE(Q1L219, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L143Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_23 at PIN_H11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L143Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[22] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[22] at PIN_F10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[22] = DFFE(ext_ram_bus_data[22], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[22] is ext_ram_bus_data[22] at PIN_F10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[22]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[22], Q1L142Q);
ext_ram_bus_data[22] = BIDIR(ext_ram_bus_data[22]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[22] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[22] at PIN_F10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[22] = DFFE(Q1L216, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L142Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_22 at PIN_F10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L142Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[21] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[21] at PIN_G10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[21] = DFFE(ext_ram_bus_data[21], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[21] is ext_ram_bus_data[21] at PIN_G10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[21]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[21], Q1L141Q);
ext_ram_bus_data[21] = BIDIR(ext_ram_bus_data[21]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[21] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[21] at PIN_G10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[21] = DFFE(Q1L213, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L141Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_21 at PIN_G10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L141Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[20] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[20] at PIN_D10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[20] = DFFE(ext_ram_bus_data[20], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[20] is ext_ram_bus_data[20] at PIN_D10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[20]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[20], Q1L140Q);
ext_ram_bus_data[20] = BIDIR(ext_ram_bus_data[20]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[20] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[20] at PIN_D10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[20] = DFFE(Q1L210, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L140Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_20 at PIN_D10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L140Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[19] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[19] at PIN_B11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[19] = DFFE(ext_ram_bus_data[19], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[19] is ext_ram_bus_data[19] at PIN_B11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[19]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[19], Q1L139Q);
ext_ram_bus_data[19] = BIDIR(ext_ram_bus_data[19]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[19] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[19] at PIN_B11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[19] = DFFE(Q1L207, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L139Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_19 at PIN_B11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L139Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[18] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[18] at PIN_D11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[18] = DFFE(ext_ram_bus_data[18], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[18] is ext_ram_bus_data[18] at PIN_D11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[18]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[18], Q1L138Q);
ext_ram_bus_data[18] = BIDIR(ext_ram_bus_data[18]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[18] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[18] at PIN_D11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[18] = DFFE(Q1L204, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L138Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_18 at PIN_D11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L138Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[17] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[17] at PIN_C11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[17] = DFFE(ext_ram_bus_data[17], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[17] is ext_ram_bus_data[17] at PIN_C11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[17]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[17], Q1L137Q);
ext_ram_bus_data[17] = BIDIR(ext_ram_bus_data[17]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[17] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[17] at PIN_C11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[17] = DFFE(Q1L201, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L137Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_17 at PIN_C11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L137Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[16] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[16] at PIN_A11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[16] = DFFE(ext_ram_bus_data[16], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[16] is ext_ram_bus_data[16] at PIN_A11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[16]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[16], Q1L136Q);
ext_ram_bus_data[16] = BIDIR(ext_ram_bus_data[16]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[16] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[16] at PIN_A11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[16] = DFFE(Q1L198, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L136Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_16 at PIN_A11
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L136Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[15] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[15] at PIN_B10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[15] = DFFE(ext_ram_bus_data[15], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[15] is ext_ram_bus_data[15] at PIN_B10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[15]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[15], Q1L135Q);
ext_ram_bus_data[15] = BIDIR(ext_ram_bus_data[15]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[15] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[15] at PIN_B10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[15] = DFFE(Q1L195, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L135Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_15 at PIN_B10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L135Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[14] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[14] at PIN_C10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[14] = DFFE(ext_ram_bus_data[14], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[14] is ext_ram_bus_data[14] at PIN_C10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[14]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[14], Q1L134Q);
ext_ram_bus_data[14] = BIDIR(ext_ram_bus_data[14]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[14] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[14] at PIN_C10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[14] = DFFE(Q1L192, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L134Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_14 at PIN_C10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L134Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[13] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[13] at PIN_A10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[13] = DFFE(ext_ram_bus_data[13], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[13] is ext_ram_bus_data[13] at PIN_A10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[13]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[13], Q1L133Q);
ext_ram_bus_data[13] = BIDIR(ext_ram_bus_data[13]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[13] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[13] at PIN_A10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[13] = DFFE(Q1L189, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L133Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_13 at PIN_A10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L133Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[12] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[12] at PIN_E10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[12] = DFFE(ext_ram_bus_data[12], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[12] is ext_ram_bus_data[12] at PIN_E10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[12]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[12], Q1L132Q);
ext_ram_bus_data[12] = BIDIR(ext_ram_bus_data[12]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[12] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[12] at PIN_E10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[12] = DFFE(Q1L186, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L132Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_12 at PIN_E10
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L132Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[11] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[11] at PIN_C9
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[11] = DFFE(ext_ram_bus_data[11], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[11] is ext_ram_bus_data[11] at PIN_C9
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[11]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[11], Q1L131Q);
ext_ram_bus_data[11] = BIDIR(ext_ram_bus_data[11]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[11] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[11] at PIN_C9
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[11] = DFFE(Q1L183, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L131Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_11 at PIN_C9
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L131Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[10] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[10] at PIN_A9
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[10] = DFFE(ext_ram_bus_data[10], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[10] is ext_ram_bus_data[10] at PIN_A9
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[10]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[10], Q1L130Q);
ext_ram_bus_data[10] = BIDIR(ext_ram_bus_data[10]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[10] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[10] at PIN_A9
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[10] = DFFE(Q1L180, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L130Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_10 at PIN_A9
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L130Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[9] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[9] at PIN_A8
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[9] = DFFE(ext_ram_bus_data[9], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[9] is ext_ram_bus_data[9] at PIN_A8
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[9]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[9], Q1L129Q);
ext_ram_bus_data[9] = BIDIR(ext_ram_bus_data[9]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[9] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[9] at PIN_A8
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[9] = DFFE(Q1L177, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L129Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_9 at PIN_A8
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L129Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[8] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[8] at PIN_B8
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[8] = DFFE(ext_ram_bus_data[8], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[8] is ext_ram_bus_data[8] at PIN_B8
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[8]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[8], Q1L128Q);
ext_ram_bus_data[8] = BIDIR(ext_ram_bus_data[8]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[8] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[8] at PIN_B8
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[8] = DFFE(Q1L174, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L128Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_8 at PIN_B8
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L128Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[7] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[7] at PIN_G18
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[7] = DFFE(ext_ram_bus_data[7], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[7] is ext_ram_bus_data[7] at PIN_G18
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[7]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[7], Q1L127Q);
ext_ram_bus_data[7] = BIDIR(ext_ram_bus_data[7]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[7] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7] at PIN_G18
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[7] = DFFE(Q1L171, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L127Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_7 at PIN_G18
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L127Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[6] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[6] at PIN_H18
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[6] = DFFE(ext_ram_bus_data[6], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[6] is ext_ram_bus_data[6] at PIN_H18
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[6]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[6], Q1L126Q);
ext_ram_bus_data[6] = BIDIR(ext_ram_bus_data[6]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[6] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6] at PIN_H18
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[6] = DFFE(Q1L169, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L126Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_6 at PIN_H18
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L126Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[5] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[5] at PIN_K18
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[5] = DFFE(ext_ram_bus_data[5], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[5] is ext_ram_bus_data[5] at PIN_K18
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[5]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[5], Q1L125Q);
ext_ram_bus_data[5] = BIDIR(ext_ram_bus_data[5]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[5] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5] at PIN_K18
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[5] = DFFE(Q1L167, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L125Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_5 at PIN_K18
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L125Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[4] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[4] at PIN_H17
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[4] = DFFE(ext_ram_bus_data[4], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[4] is ext_ram_bus_data[4] at PIN_H17
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[4]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[4], Q1L124Q);
ext_ram_bus_data[4] = BIDIR(ext_ram_bus_data[4]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[4] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[4] at PIN_H17
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[4] = DFFE(Q1L165, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L124Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_4 at PIN_H17
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L124Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[3] at PIN_M12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[3] = DFFE(ext_ram_bus_data[3], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[3] is ext_ram_bus_data[3] at PIN_M12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[3]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[3], Q1L123Q);
ext_ram_bus_data[3] = BIDIR(ext_ram_bus_data[3]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[3] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[3] at PIN_M12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[3] = DFFE(Q1L163, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L123Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_3 at PIN_M12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L123Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[2] at PIN_J12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[2] = DFFE(ext_ram_bus_data[2], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[2] is ext_ram_bus_data[2] at PIN_J12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[2]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[2], Q1L122Q);
ext_ram_bus_data[2] = BIDIR(ext_ram_bus_data[2]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[2] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[2] at PIN_J12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[2] = DFFE(Q1L161, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L122Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_2 at PIN_J12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L122Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[1] at PIN_F12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[1] = DFFE(ext_ram_bus_data[1], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[1] is ext_ram_bus_data[1] at PIN_F12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[1]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[1], Q1L121Q);
ext_ram_bus_data[1] = BIDIR(ext_ram_bus_data[1]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[1] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[1] at PIN_F12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[1] = DFFE(Q1L159, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1L121Q is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_1 at PIN_F12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1L121Q = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_internal_incoming_ext_ram_bus_data[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[0] at PIN_H12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_internal_incoming_ext_ram_bus_data[0] = DFFE(ext_ram_bus_data[0], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--ext_ram_bus_data[0] is ext_ram_bus_data[0] at PIN_H12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
ext_ram_bus_data[0]_tri_out = TRI(Q1_d1_outgoing_ext_ram_bus_data[0], Q1_d1_in_a_write_cycle);
ext_ram_bus_data[0] = BIDIR(ext_ram_bus_data[0]_tri_out);
--Q1_d1_outgoing_ext_ram_bus_data[0] is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[0] at PIN_H12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_outgoing_ext_ram_bus_data[0] = DFFE(Q1L157, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--Q1_d1_in_a_write_cycle is std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle at PIN_H12
--operation mode is bidir --input register power-up is low --output register power-up is low --oe register power-up is low
Q1_d1_in_a_write_cycle = DFFE(Q1L152, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--A1L136 is LCD_data_to_and_from_the_lcd_display~0 at PIN_J4
--operation mode is bidir
A1L136 = LCD_data_to_and_from_the_lcd_display[7];
--LCD_data_to_and_from_the_lcd_display[7] is LCD_data_to_and_from_the_lcd_display[7] at PIN_J4
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[7]_tri_out = TRI(L1_M_st_data[7], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[7] = BIDIR(LCD_data_to_and_from_the_lcd_display[7]_tri_out);
--A1L137 is LCD_data_to_and_from_the_lcd_display~1 at PIN_L5
--operation mode is bidir
A1L137 = LCD_data_to_and_from_the_lcd_display[6];
--LCD_data_to_and_from_the_lcd_display[6] is LCD_data_to_and_from_the_lcd_display[6] at PIN_L5
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[6]_tri_out = TRI(L1_M_st_data[6], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[6] = BIDIR(LCD_data_to_and_from_the_lcd_display[6]_tri_out);
--A1L138 is LCD_data_to_and_from_the_lcd_display~2 at PIN_L6
--operation mode is bidir
A1L138 = LCD_data_to_and_from_the_lcd_display[5];
--LCD_data_to_and_from_the_lcd_display[5] is LCD_data_to_and_from_the_lcd_display[5] at PIN_L6
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[5]_tri_out = TRI(L1_M_st_data[5], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[5] = BIDIR(LCD_data_to_and_from_the_lcd_display[5]_tri_out);
--A1L139 is LCD_data_to_and_from_the_lcd_display~3 at PIN_H1
--operation mode is bidir
A1L139 = LCD_data_to_and_from_the_lcd_display[4];
--LCD_data_to_and_from_the_lcd_display[4] is LCD_data_to_and_from_the_lcd_display[4] at PIN_H1
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[4]_tri_out = TRI(L1_M_st_data[4], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[4] = BIDIR(LCD_data_to_and_from_the_lcd_display[4]_tri_out);
--A1L140 is LCD_data_to_and_from_the_lcd_display~4 at PIN_H2
--operation mode is bidir
A1L140 = LCD_data_to_and_from_the_lcd_display[3];
--LCD_data_to_and_from_the_lcd_display[3] is LCD_data_to_and_from_the_lcd_display[3] at PIN_H2
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[3]_tri_out = TRI(L1_M_st_data[3], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[3] = BIDIR(LCD_data_to_and_from_the_lcd_display[3]_tri_out);
--A1L141 is LCD_data_to_and_from_the_lcd_display~5 at PIN_L8
--operation mode is bidir
A1L141 = LCD_data_to_and_from_the_lcd_display[2];
--LCD_data_to_and_from_the_lcd_display[2] is LCD_data_to_and_from_the_lcd_display[2] at PIN_L8
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[2]_tri_out = TRI(L1_M_st_data[2], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[2] = BIDIR(LCD_data_to_and_from_the_lcd_display[2]_tri_out);
--A1L142 is LCD_data_to_and_from_the_lcd_display~6 at PIN_L7
--operation mode is bidir
A1L142 = LCD_data_to_and_from_the_lcd_display[1];
--LCD_data_to_and_from_the_lcd_display[1] is LCD_data_to_and_from_the_lcd_display[1] at PIN_L7
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[1]_tri_out = TRI(L1_M_st_data[1], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[1] = BIDIR(LCD_data_to_and_from_the_lcd_display[1]_tri_out);
--A1L143 is LCD_data_to_and_from_the_lcd_display~7 at PIN_H3
--operation mode is bidir
A1L143 = LCD_data_to_and_from_the_lcd_display[0];
--LCD_data_to_and_from_the_lcd_display[0] is LCD_data_to_and_from_the_lcd_display[0] at PIN_H3
--operation mode is bidir
LCD_data_to_and_from_the_lcd_display[0]_tri_out = TRI(L1_M_st_data[0], !L1_M_alu_result[2]);
LCD_data_to_and_from_the_lcd_display[0] = BIDIR(LCD_data_to_and_from_the_lcd_display[0]_tri_out);
--FB1_za_data[31] is std_1s10:inst|sdram:the_sdram|za_data[31] at PIN_AG11
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[31] = DFFE(zs_dq_to_and_from_the_sdram[31], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[31] is zs_dq_to_and_from_the_sdram[31] at PIN_AG11
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[31]_tri_out = TRI(FB1_m_data[31], FB1_oe);
zs_dq_to_and_from_the_sdram[31] = BIDIR(zs_dq_to_and_from_the_sdram[31]_tri_out);
--FB1_m_data[31] is std_1s10:inst|sdram:the_sdram|m_data[31] at PIN_AG11
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[31] = DFFE(FB1L366, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[30] is std_1s10:inst|sdram:the_sdram|za_data[30] at PIN_AH11
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[30] = DFFE(zs_dq_to_and_from_the_sdram[30], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[30] is zs_dq_to_and_from_the_sdram[30] at PIN_AH11
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[30]_tri_out = TRI(FB1_m_data[30], FB1_oe);
zs_dq_to_and_from_the_sdram[30] = BIDIR(zs_dq_to_and_from_the_sdram[30]_tri_out);
--FB1_m_data[30] is std_1s10:inst|sdram:the_sdram|m_data[30] at PIN_AH11
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[30] = DFFE(FB1L362, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[29] is std_1s10:inst|sdram:the_sdram|za_data[29] at PIN_AE11
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[29] = DFFE(zs_dq_to_and_from_the_sdram[29], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[29] is zs_dq_to_and_from_the_sdram[29] at PIN_AE11
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[29]_tri_out = TRI(FB1_m_data[29], FB1_oe);
zs_dq_to_and_from_the_sdram[29] = BIDIR(zs_dq_to_and_from_the_sdram[29]_tri_out);
--FB1_m_data[29] is std_1s10:inst|sdram:the_sdram|m_data[29] at PIN_AE11
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[29] = DFFE(FB1L358, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[28] is std_1s10:inst|sdram:the_sdram|za_data[28] at PIN_AF11
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[28] = DFFE(zs_dq_to_and_from_the_sdram[28], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[28] is zs_dq_to_and_from_the_sdram[28] at PIN_AF11
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[28]_tri_out = TRI(FB1_m_data[28], FB1_oe);
zs_dq_to_and_from_the_sdram[28] = BIDIR(zs_dq_to_and_from_the_sdram[28]_tri_out);
--FB1_m_data[28] is std_1s10:inst|sdram:the_sdram|m_data[28] at PIN_AF11
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[28] = DFFE(FB1L354, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[27] is std_1s10:inst|sdram:the_sdram|za_data[27] at PIN_AE10
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[27] = DFFE(zs_dq_to_and_from_the_sdram[27], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[27] is zs_dq_to_and_from_the_sdram[27] at PIN_AE10
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[27]_tri_out = TRI(FB1_m_data[27], FB1_oe);
zs_dq_to_and_from_the_sdram[27] = BIDIR(zs_dq_to_and_from_the_sdram[27]_tri_out);
--FB1_m_data[27] is std_1s10:inst|sdram:the_sdram|m_data[27] at PIN_AE10
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[27] = DFFE(FB1L350, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[26] is std_1s10:inst|sdram:the_sdram|za_data[26] at PIN_AH10
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[26] = DFFE(zs_dq_to_and_from_the_sdram[26], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[26] is zs_dq_to_and_from_the_sdram[26] at PIN_AH10
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[26]_tri_out = TRI(FB1_m_data[26], FB1_oe);
zs_dq_to_and_from_the_sdram[26] = BIDIR(zs_dq_to_and_from_the_sdram[26]_tri_out);
--FB1_m_data[26] is std_1s10:inst|sdram:the_sdram|m_data[26] at PIN_AH10
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[26] = DFFE(FB1L346, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[25] is std_1s10:inst|sdram:the_sdram|za_data[25] at PIN_AF10
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[25] = DFFE(zs_dq_to_and_from_the_sdram[25], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[25] is zs_dq_to_and_from_the_sdram[25] at PIN_AF10
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[25]_tri_out = TRI(FB1_m_data[25], FB1_oe);
zs_dq_to_and_from_the_sdram[25] = BIDIR(zs_dq_to_and_from_the_sdram[25]_tri_out);
--FB1_m_data[25] is std_1s10:inst|sdram:the_sdram|m_data[25] at PIN_AF10
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[25] = DFFE(FB1L342, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[24] is std_1s10:inst|sdram:the_sdram|za_data[24] at PIN_AD10
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[24] = DFFE(zs_dq_to_and_from_the_sdram[24], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[24] is zs_dq_to_and_from_the_sdram[24] at PIN_AD10
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[24]_tri_out = TRI(FB1_m_data[24], FB1_oe);
zs_dq_to_and_from_the_sdram[24] = BIDIR(zs_dq_to_and_from_the_sdram[24]_tri_out);
--FB1_m_data[24] is std_1s10:inst|sdram:the_sdram|m_data[24] at PIN_AD10
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[24] = DFFE(FB1L338, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[23] is std_1s10:inst|sdram:the_sdram|za_data[23] at PIN_AG9
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[23] = DFFE(zs_dq_to_and_from_the_sdram[23], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[23] is zs_dq_to_and_from_the_sdram[23] at PIN_AG9
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[23]_tri_out = TRI(FB1_m_data[23], FB1_oe);
zs_dq_to_and_from_the_sdram[23] = BIDIR(zs_dq_to_and_from_the_sdram[23]_tri_out);
--FB1_m_data[23] is std_1s10:inst|sdram:the_sdram|m_data[23] at PIN_AG9
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[23] = DFFE(FB1L334, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[22] is std_1s10:inst|sdram:the_sdram|za_data[22] at PIN_AF9
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[22] = DFFE(zs_dq_to_and_from_the_sdram[22], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[22] is zs_dq_to_and_from_the_sdram[22] at PIN_AF9
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[22]_tri_out = TRI(FB1_m_data[22], FB1_oe);
zs_dq_to_and_from_the_sdram[22] = BIDIR(zs_dq_to_and_from_the_sdram[22]_tri_out);
--FB1_m_data[22] is std_1s10:inst|sdram:the_sdram|m_data[22] at PIN_AF9
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[22] = DFFE(FB1L330, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[21] is std_1s10:inst|sdram:the_sdram|za_data[21] at PIN_AE9
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[21] = DFFE(zs_dq_to_and_from_the_sdram[21], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[21] is zs_dq_to_and_from_the_sdram[21] at PIN_AE9
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[21]_tri_out = TRI(FB1_m_data[21], FB1_oe);
zs_dq_to_and_from_the_sdram[21] = BIDIR(zs_dq_to_and_from_the_sdram[21]_tri_out);
--FB1_m_data[21] is std_1s10:inst|sdram:the_sdram|m_data[21] at PIN_AE9
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[21] = DFFE(FB1L326, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[20] is std_1s10:inst|sdram:the_sdram|za_data[20] at PIN_AH8
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[20] = DFFE(zs_dq_to_and_from_the_sdram[20], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[20] is zs_dq_to_and_from_the_sdram[20] at PIN_AH8
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[20]_tri_out = TRI(FB1_m_data[20], FB1_oe);
zs_dq_to_and_from_the_sdram[20] = BIDIR(zs_dq_to_and_from_the_sdram[20]_tri_out);
--FB1_m_data[20] is std_1s10:inst|sdram:the_sdram|m_data[20] at PIN_AH8
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[20] = DFFE(FB1L322, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[19] is std_1s10:inst|sdram:the_sdram|za_data[19] at PIN_AH9
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[19] = DFFE(zs_dq_to_and_from_the_sdram[19], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[19] is zs_dq_to_and_from_the_sdram[19] at PIN_AH9
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[19]_tri_out = TRI(FB1_m_data[19], FB1_oe);
zs_dq_to_and_from_the_sdram[19] = BIDIR(zs_dq_to_and_from_the_sdram[19]_tri_out);
--FB1_m_data[19] is std_1s10:inst|sdram:the_sdram|m_data[19] at PIN_AH9
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[19] = DFFE(FB1L318, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[18] is std_1s10:inst|sdram:the_sdram|za_data[18] at PIN_AD8
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[18] = DFFE(zs_dq_to_and_from_the_sdram[18], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[18] is zs_dq_to_and_from_the_sdram[18] at PIN_AD8
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[18]_tri_out = TRI(FB1_m_data[18], FB1_oe);
zs_dq_to_and_from_the_sdram[18] = BIDIR(zs_dq_to_and_from_the_sdram[18]_tri_out);
--FB1_m_data[18] is std_1s10:inst|sdram:the_sdram|m_data[18] at PIN_AD8
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[18] = DFFE(FB1L314, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[17] is std_1s10:inst|sdram:the_sdram|za_data[17] at PIN_AF8
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[17] = DFFE(zs_dq_to_and_from_the_sdram[17], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[17] is zs_dq_to_and_from_the_sdram[17] at PIN_AF8
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[17]_tri_out = TRI(FB1_m_data[17], FB1_oe);
zs_dq_to_and_from_the_sdram[17] = BIDIR(zs_dq_to_and_from_the_sdram[17]_tri_out);
--FB1_m_data[17] is std_1s10:inst|sdram:the_sdram|m_data[17] at PIN_AF8
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[17] = DFFE(FB1L310, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[16] is std_1s10:inst|sdram:the_sdram|za_data[16] at PIN_AG8
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[16] = DFFE(zs_dq_to_and_from_the_sdram[16], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[16] is zs_dq_to_and_from_the_sdram[16] at PIN_AG8
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[16]_tri_out = TRI(FB1_m_data[16], FB1_oe);
zs_dq_to_and_from_the_sdram[16] = BIDIR(zs_dq_to_and_from_the_sdram[16]_tri_out);
--FB1_m_data[16] is std_1s10:inst|sdram:the_sdram|m_data[16] at PIN_AG8
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[16] = DFFE(FB1L306, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[15] is std_1s10:inst|sdram:the_sdram|za_data[15] at PIN_AF6
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[15] = DFFE(zs_dq_to_and_from_the_sdram[15], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[15] is zs_dq_to_and_from_the_sdram[15] at PIN_AF6
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[15]_tri_out = TRI(FB1_m_data[15], FB1_oe);
zs_dq_to_and_from_the_sdram[15] = BIDIR(zs_dq_to_and_from_the_sdram[15]_tri_out);
--FB1_m_data[15] is std_1s10:inst|sdram:the_sdram|m_data[15] at PIN_AF6
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[15] = DFFE(FB1L302, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[14] is std_1s10:inst|sdram:the_sdram|za_data[14] at PIN_AG7
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[14] = DFFE(zs_dq_to_and_from_the_sdram[14], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[14] is zs_dq_to_and_from_the_sdram[14] at PIN_AG7
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[14]_tri_out = TRI(FB1_m_data[14], FB1_oe);
zs_dq_to_and_from_the_sdram[14] = BIDIR(zs_dq_to_and_from_the_sdram[14]_tri_out);
--FB1_m_data[14] is std_1s10:inst|sdram:the_sdram|m_data[14] at PIN_AG7
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[14] = DFFE(FB1L298, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[13] is std_1s10:inst|sdram:the_sdram|za_data[13] at PIN_AH7
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[13] = DFFE(zs_dq_to_and_from_the_sdram[13], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[13] is zs_dq_to_and_from_the_sdram[13] at PIN_AH7
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[13]_tri_out = TRI(FB1_m_data[13], FB1_oe);
zs_dq_to_and_from_the_sdram[13] = BIDIR(zs_dq_to_and_from_the_sdram[13]_tri_out);
--FB1_m_data[13] is std_1s10:inst|sdram:the_sdram|m_data[13] at PIN_AH7
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[13] = DFFE(FB1L294, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[12] is std_1s10:inst|sdram:the_sdram|za_data[12] at PIN_AF7
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[12] = DFFE(zs_dq_to_and_from_the_sdram[12], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[12] is zs_dq_to_and_from_the_sdram[12] at PIN_AF7
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[12]_tri_out = TRI(FB1_m_data[12], FB1_oe);
zs_dq_to_and_from_the_sdram[12] = BIDIR(zs_dq_to_and_from_the_sdram[12]_tri_out);
--FB1_m_data[12] is std_1s10:inst|sdram:the_sdram|m_data[12] at PIN_AF7
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[12] = DFFE(FB1L290, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[11] is std_1s10:inst|sdram:the_sdram|za_data[11] at PIN_AD6
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[11] = DFFE(zs_dq_to_and_from_the_sdram[11], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[11] is zs_dq_to_and_from_the_sdram[11] at PIN_AD6
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[11]_tri_out = TRI(FB1_m_data[11], FB1_oe);
zs_dq_to_and_from_the_sdram[11] = BIDIR(zs_dq_to_and_from_the_sdram[11]_tri_out);
--FB1_m_data[11] is std_1s10:inst|sdram:the_sdram|m_data[11] at PIN_AD6
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[11] = DFFE(FB1L286, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[10] is std_1s10:inst|sdram:the_sdram|za_data[10] at PIN_AH6
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[10] = DFFE(zs_dq_to_and_from_the_sdram[10], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[10] is zs_dq_to_and_from_the_sdram[10] at PIN_AH6
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[10]_tri_out = TRI(FB1_m_data[10], FB1_oe);
zs_dq_to_and_from_the_sdram[10] = BIDIR(zs_dq_to_and_from_the_sdram[10]_tri_out);
--FB1_m_data[10] is std_1s10:inst|sdram:the_sdram|m_data[10] at PIN_AH6
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[10] = DFFE(FB1L282, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[9] is std_1s10:inst|sdram:the_sdram|za_data[9] at PIN_AG6
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[9] = DFFE(zs_dq_to_and_from_the_sdram[9], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[9] is zs_dq_to_and_from_the_sdram[9] at PIN_AG6
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[9]_tri_out = TRI(FB1_m_data[9], FB1_oe);
zs_dq_to_and_from_the_sdram[9] = BIDIR(zs_dq_to_and_from_the_sdram[9]_tri_out);
--FB1_m_data[9] is std_1s10:inst|sdram:the_sdram|m_data[9] at PIN_AG6
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[9] = DFFE(FB1L278, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[8] is std_1s10:inst|sdram:the_sdram|za_data[8] at PIN_AE6
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[8] = DFFE(zs_dq_to_and_from_the_sdram[8], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[8] is zs_dq_to_and_from_the_sdram[8] at PIN_AE6
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[8]_tri_out = TRI(FB1_m_data[8], FB1_oe);
zs_dq_to_and_from_the_sdram[8] = BIDIR(zs_dq_to_and_from_the_sdram[8]_tri_out);
--FB1_m_data[8] is std_1s10:inst|sdram:the_sdram|m_data[8] at PIN_AE6
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[8] = DFFE(FB1L274, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[7] is std_1s10:inst|sdram:the_sdram|za_data[7] at PIN_AF5
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[7] = DFFE(zs_dq_to_and_from_the_sdram[7], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[7] is zs_dq_to_and_from_the_sdram[7] at PIN_AF5
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[7]_tri_out = TRI(FB1_m_data[7], FB1_oe);
zs_dq_to_and_from_the_sdram[7] = BIDIR(zs_dq_to_and_from_the_sdram[7]_tri_out);
--FB1_m_data[7] is std_1s10:inst|sdram:the_sdram|m_data[7] at PIN_AF5
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[7] = DFFE(FB1L270, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[6] is std_1s10:inst|sdram:the_sdram|za_data[6] at PIN_AH5
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[6] = DFFE(zs_dq_to_and_from_the_sdram[6], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[6] is zs_dq_to_and_from_the_sdram[6] at PIN_AH5
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[6]_tri_out = TRI(FB1_m_data[6], FB1_oe);
zs_dq_to_and_from_the_sdram[6] = BIDIR(zs_dq_to_and_from_the_sdram[6]_tri_out);
--FB1_m_data[6] is std_1s10:inst|sdram:the_sdram|m_data[6] at PIN_AH5
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[6] = DFFE(FB1L266, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[5] is std_1s10:inst|sdram:the_sdram|za_data[5] at PIN_AF4
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[5] = DFFE(zs_dq_to_and_from_the_sdram[5], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[5] is zs_dq_to_and_from_the_sdram[5] at PIN_AF4
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[5]_tri_out = TRI(FB1_m_data[5], FB1_oe);
zs_dq_to_and_from_the_sdram[5] = BIDIR(zs_dq_to_and_from_the_sdram[5]_tri_out);
--FB1_m_data[5] is std_1s10:inst|sdram:the_sdram|m_data[5] at PIN_AF4
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[5] = DFFE(FB1L262, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[4] is std_1s10:inst|sdram:the_sdram|za_data[4] at PIN_AG4
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[4] = DFFE(zs_dq_to_and_from_the_sdram[4], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[4] is zs_dq_to_and_from_the_sdram[4] at PIN_AG4
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[4]_tri_out = TRI(FB1_m_data[4], FB1_oe);
zs_dq_to_and_from_the_sdram[4] = BIDIR(zs_dq_to_and_from_the_sdram[4]_tri_out);
--FB1_m_data[4] is std_1s10:inst|sdram:the_sdram|m_data[4] at PIN_AG4
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[4] = DFFE(FB1L258, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[3] is std_1s10:inst|sdram:the_sdram|za_data[3] at PIN_AG5
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[3] = DFFE(zs_dq_to_and_from_the_sdram[3], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[3] is zs_dq_to_and_from_the_sdram[3] at PIN_AG5
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[3]_tri_out = TRI(FB1_m_data[3], FB1_oe);
zs_dq_to_and_from_the_sdram[3] = BIDIR(zs_dq_to_and_from_the_sdram[3]_tri_out);
--FB1_m_data[3] is std_1s10:inst|sdram:the_sdram|m_data[3] at PIN_AG5
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[3] = DFFE(FB1L254, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[2] is std_1s10:inst|sdram:the_sdram|za_data[2] at PIN_AG3
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[2] = DFFE(zs_dq_to_and_from_the_sdram[2], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[2] is zs_dq_to_and_from_the_sdram[2] at PIN_AG3
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[2]_tri_out = TRI(FB1_m_data[2], FB1_oe);
zs_dq_to_and_from_the_sdram[2] = BIDIR(zs_dq_to_and_from_the_sdram[2]_tri_out);
--FB1_m_data[2] is std_1s10:inst|sdram:the_sdram|m_data[2] at PIN_AG3
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[2] = DFFE(FB1L250, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[1] is std_1s10:inst|sdram:the_sdram|za_data[1] at PIN_AE5
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[1] = DFFE(zs_dq_to_and_from_the_sdram[1], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[1] is zs_dq_to_and_from_the_sdram[1] at PIN_AE5
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[1]_tri_out = TRI(FB1_m_data[1], FB1_oe);
zs_dq_to_and_from_the_sdram[1] = BIDIR(zs_dq_to_and_from_the_sdram[1]_tri_out);
--FB1_m_data[1] is std_1s10:inst|sdram:the_sdram|m_data[1] at PIN_AE5
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[1] = DFFE(FB1L246, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--FB1_za_data[0] is std_1s10:inst|sdram:the_sdram|za_data[0] at PIN_AH4
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_za_data[0] = DFFE(zs_dq_to_and_from_the_sdram[0], GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--zs_dq_to_and_from_the_sdram[0] is zs_dq_to_and_from_the_sdram[0] at PIN_AH4
--operation mode is bidir --input register power-up is low --output register power-up is low
zs_dq_to_and_from_the_sdram[0]_tri_out = TRI(FB1_m_data[0], FB1_oe);
zs_dq_to_and_from_the_sdram[0] = BIDIR(zs_dq_to_and_from_the_sdram[0]_tri_out);
--FB1_m_data[0] is std_1s10:inst|sdram:the_sdram|m_data[0] at PIN_AH4
--operation mode is bidir --input register power-up is low --output register power-up is low
FB1_m_data[0] = DFFE(FB1L242, GLOBAL(DE1__clk0), GLOBAL(E1_data_out), , );
--A1L2 is altera_internal_jtag~$wirecell at LC_X29_Y29_N7
--operation mode is normal
--L1L1050 is std_1s10:inst|cpu:the_cpu|ic_fill_ap_offset[0]~$wirecell at LC_X36_Y9_N2
--operation mode is normal
L1L1050 = AMPP_FUNCTION(L1_ic_fill_ap_offset[0]);