Fitter report for standard

Fri Apr 21 03:03:25 2006
Version 6.0 Build 176 04/19/2006 SJ Full Version


Table of Contents

Top
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Netlist Optimizations
  5. Fitter Equations
  6. Pin-Out File
  7. Fitter Resource Usage Summary
  8. Input Pins
  9. Output Pins
  10. Bidir Pins
  11. I/O Bank Usage
  12. All Package Pins
  13. PLL Summary
  14. PLL Usage
  15. Output Pin Default Load For Reported TCO
  16. Fitter Resource Utilization by Entity
  17. Delay Chain Summary
  18. Pad To Core Delay Chain Fanout
  19. Control Signals
  20. Global & Other Fast Signals
  21. Non-Global High Fan-Out Signals
  22. Fitter RAM Summary
  23. Fitter DSP Block Usage Summary
  24. DSP Block Details
  25. Interconnect Usage Summary
  26. LAB Logic Elements
  27. LAB-wide Signals
  28. LAB Signals Sourced
  29. LAB Signals Sourced Out
  30. LAB Distinct Inputs
  31. Fitter Device Options
  32. Fitter Messages
  33. Fitter Suppressed Messages


Legal Notice

Top
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.


Fitter Summary

Top
Fitter Status Successful - Fri Apr 21 03:03:24 2006
Quartus II Version 6.0 Build 176 04/19/2006 SJ Full Version
Revision Name standard
Top-level Entity Name standard
Family Stratix
Device EP1S10F780C6
Timing Models Final
Total logic elements 4,013 / 10,570 ( 38 % )
Total pins 179 / 427 ( 42 % )
Total virtual pins 0
Total memory bits 571,136 / 920,448 ( 62 % )
DSP block 9-bit elements 8 / 48 ( 17 % )
Total PLLs 1 / 6 ( 17 % )
Total DLLs 0 / 2 ( 0 % )


Fitter Settings

Top
Option Setting Default Value
Device EP1S10F780C6  
Perform Register Duplication On Off
Use smart compilation Off Off
Router Timing Optimization Level Normal Normal
Placement Effort Multiplier 1.0 1.0
Router Effort Multiplier 1.0 1.0
Optimize Hold Timing IO Paths and Minimum TPD Paths IO Paths and Minimum TPD Paths
Optimize Fast-Corner Timing Off Off
Optimize Timing Normal compilation Normal compilation
Optimize IOC Register Placement for Timing On On
Limit to One Fitting Attempt Off Off
Final Placement Optimizations Automatically Automatically
Fitter Aggressive Routability Optimizations Automatically Automatically
Fitter Initial Placement Seed 1 1
Slow Slew Rate Off Off
PCI I/O Off Off
Weak Pull-Up Resistor Off Off
Enable Bus-Hold Circuitry Off Off
Auto Global Memory Control Signals Off Off
Auto Packed Registers -- Stratix/Stratix GX Auto Auto
Auto Delay Chains On On
Auto Merge PLLs On On
Perform Physical Synthesis for Combinational Logic Off Off
Perform Register Retiming Off Off
Perform Asynchronous Signal Pipelining Off Off
Fitter Effort Auto Fit Auto Fit
Physical Synthesis Effort Level Normal Normal
Logic Cell Insertion - Logic Duplication Auto Auto
Auto Register Duplication Auto Auto
Auto Global Clock On On
Auto Global Register Control Signals On On


Fitter Netlist Optimizations

Top
Node Action Operation Reason Node Port Destination Node Destination Port
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[0] Packed Register Register Packing Fast Output Register assignment REGOUT be_n_to_the_ext_ram[0] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[1] Packed Register Register Packing Fast Output Register assignment REGOUT be_n_to_the_ext_ram[1] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[2] Packed Register Register Packing Fast Output Register assignment REGOUT be_n_to_the_ext_ram[2] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|be_n_to_the_ext_ram[3] Packed Register Register Packing Fast Output Register assignment REGOUT be_n_to_the_ext_ram[3] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[0] Packed Register Register Packing Fast Output Register assignment REGOUT byteenablen_to_the_lan91c111[0] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[1] Packed Register Register Packing Fast Output Register assignment REGOUT byteenablen_to_the_lan91c111[1] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[2] Packed Register Register Packing Fast Output Register assignment REGOUT byteenablen_to_the_lan91c111[2] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|byteenablen_to_the_lan91c111[3] Packed Register Register Packing Fast Output Register assignment REGOUT byteenablen_to_the_lan91c111[3] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[0] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_1 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_1 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[1] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_1 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_2 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_2 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[2] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_2 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_3 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_3 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[3] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_3 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_4 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_4 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[4] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_4 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_5 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_5 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[5] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_5 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_6 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_6 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[6] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_6 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_7 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_7 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[7] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_7 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_8 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_8 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[8] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_8 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_9 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_9 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[9] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_9 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_10 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_10 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[10] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_10 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_11 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_11 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[11] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_11 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_12 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_12 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[12] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_12 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_13 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_13 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[13] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_13 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_14 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_14 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[14] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_14 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_15 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_15 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[15] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_15 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_16 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_16 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[16] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_16 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_17 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_17 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[17] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_17 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_18 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_18 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[18] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_18 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_19 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_19 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[19] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_19 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_20 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_20 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[20] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_20 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_21 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_21 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[21] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_21 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_22 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_22 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[22] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_22 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_23 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_23 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[23] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_23 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_24 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_24 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[24] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_24 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_25 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_25 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[25] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_25 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_26 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_26 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[26] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_26 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_27 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_27 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[27] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_27 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_28 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_28 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[28] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_28 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_29 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_29 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[29] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_29 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_30 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_30 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[30] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_30 Duplicated Register Packing Fast Output Enable Register assignment REGOUT std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_31 REGOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~_Duplicate_31 Packed Register Register Packing Fast Output Enable Register assignment REGOUT ext_ram_bus_data[31] OE
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[0] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[0] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[1] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[1] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[2] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[2] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[3] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[3] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[4] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[4] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[5] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[5] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[6] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[6] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[7] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[7] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[8] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[8] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[9] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[9] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[10] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[10] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[11] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[11] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[12] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[12] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[13] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[13] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[14] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[14] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[15] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[15] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[16] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[16] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[17] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[17] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[18] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[18] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[19] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[19] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[20] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[20] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[21] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[21] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[22] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[22] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[23] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[23] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[24] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[24] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[25] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[25] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[26] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[26] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[27] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[27] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[28] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[28] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[29] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[29] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[30] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[30] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_outgoing_ext_ram_bus_data[31] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_data[31] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[0] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[0] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[1] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[1] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[2] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[2] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[3] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[3] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[4] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[4] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[5] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[5] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[6] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[6] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[7] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[7] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[8] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[8] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[9] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[9] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[10] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[10] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[11] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[11] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[12] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[12] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[13] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[13] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[14] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[14] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[15] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[15] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[16] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[16] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[17] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[17] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[18] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[18] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[19] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[19] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[20] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[20] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[21] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[21] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[22] Packed Register Register Packing Fast Output Register assignment REGOUT ext_ram_bus_address[22] DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[0] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[0] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[1] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[1] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[2] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[2] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[3] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[3] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[4] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[4] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[5] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[5] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[6] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[6] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[7] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[7] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[8] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[8] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[9] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[9] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[10] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[10] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[11] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[11] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[12] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[12] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[13] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[13] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[14] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[14] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[15] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[15] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[16] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[16] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[17] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[17] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[18] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[18] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[19] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[19] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[20] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[20] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[21] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[21] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[22] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[22] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[23] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[23] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[24] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[24] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[25] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[25] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[26] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[26] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[27] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[27] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[28] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[28] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[29] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[29] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[30] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[30] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|internal_incoming_ext_ram_bus_data[31] Packed Register Register Packing Fast Input Register assignment REGOUT ext_ram_bus_data[31] COMBOUT
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ior_n_to_the_lan91c111 Packed Register Register Packing Fast Output Register assignment REGOUT ior_n_to_the_lan91c111 DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|iow_n_to_the_lan91c111 Packed Register Register Packing Fast Output Register assignment REGOUT iow_n_to_the_lan91c111 DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_flash Packed Register Register Packing Fast Output Register assignment REGOUT read_n_to_the_ext_flash DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|read_n_to_the_ext_ram Packed Register Register Packing Fast Output Register assignment REGOUT read_n_to_the_ext_ram DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_flash Packed Register Register Packing Fast Output Register assignment REGOUT select_n_to_the_ext_flash DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|select_n_to_the_ext_ram Packed Register Register Packing Fast Output Register assignment REGOUT select_n_to_the_ext_ram DATAIN
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|write_n_to_the_ext_flash Packed Register Register Packing Fast Output Register assignment REGOUT write_n_to_the_ext_flash DATAIN
std_1s10:inst|sdram:the_sdram|m_addr[0] Packed Register Register Packing Fast Output Register assignment REGOUT zs_addr_from_the_sdram[0] DATAIN
std_1s10:inst|sdram:the_sdram|m_addr[0] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_addr[0]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_addr[1] Packed Register Register Packing Fast Output Register assignment REGOUT zs_addr_from_the_sdram[1] DATAIN
std_1s10:inst|sdram:the_sdram|m_addr[1] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_addr[1]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_addr[2] Packed Register Register Packing Fast Output Register assignment REGOUT zs_addr_from_the_sdram[2] DATAIN
std_1s10:inst|sdram:the_sdram|m_addr[2] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_addr[2]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_addr[3] Packed Register Register Packing Fast Output Register assignment REGOUT zs_addr_from_the_sdram[3] DATAIN
std_1s10:inst|sdram:the_sdram|m_addr[3] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_addr[3]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_addr[4] Packed Register Register Packing Fast Output Register assignment REGOUT zs_addr_from_the_sdram[4] DATAIN
std_1s10:inst|sdram:the_sdram|m_addr[4] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_addr[4]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_addr[5] Packed Register Register Packing Fast Output Register assignment REGOUT zs_addr_from_the_sdram[5] DATAIN
std_1s10:inst|sdram:the_sdram|m_addr[5] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_addr[5]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_addr[6] Packed Register Register Packing Fast Output Register assignment REGOUT zs_addr_from_the_sdram[6] DATAIN
std_1s10:inst|sdram:the_sdram|m_addr[6] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_addr[6]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_addr[7] Packed Register Register Packing Fast Output Register assignment REGOUT zs_addr_from_the_sdram[7] DATAIN
std_1s10:inst|sdram:the_sdram|m_addr[7] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_addr[7]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_addr[8] Packed Register Register Packing Fast Output Register assignment REGOUT zs_addr_from_the_sdram[8] DATAIN
std_1s10:inst|sdram:the_sdram|m_addr[8] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_addr[8]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_addr[9] Packed Register Register Packing Fast Output Register assignment REGOUT zs_addr_from_the_sdram[9] DATAIN
std_1s10:inst|sdram:the_sdram|m_addr[9] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_addr[9]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_addr[10] Packed Register Register Packing Fast Output Register assignment REGOUT zs_addr_from_the_sdram[10] DATAIN
std_1s10:inst|sdram:the_sdram|m_addr[10] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_addr[10]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_addr[11] Packed Register Register Packing Fast Output Register assignment REGOUT zs_addr_from_the_sdram[11] DATAIN
std_1s10:inst|sdram:the_sdram|m_addr[11] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_addr[11]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_bank[0] Packed Register Register Packing Fast Output Register assignment REGOUT zs_ba_from_the_sdram[0] DATAIN
std_1s10:inst|sdram:the_sdram|m_bank[0] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_bank[0]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_bank[1] Packed Register Register Packing Fast Output Register assignment REGOUT zs_ba_from_the_sdram[1] DATAIN
std_1s10:inst|sdram:the_sdram|m_bank[1] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_bank[1]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_cmd[0] Packed Register Register Packing Fast Output Register assignment REGOUT zs_we_n_from_the_sdram DATAIN
std_1s10:inst|sdram:the_sdram|m_cmd[0] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_cmd[0]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_cmd[1] Packed Register Register Packing Fast Output Register assignment REGOUT zs_cas_n_from_the_sdram DATAIN
std_1s10:inst|sdram:the_sdram|m_cmd[1] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_cmd[1]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_cmd[2] Packed Register Register Packing Fast Output Register assignment REGOUT zs_ras_n_from_the_sdram DATAIN
std_1s10:inst|sdram:the_sdram|m_cmd[2] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_cmd[2]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_cmd[3] Packed Register Register Packing Fast Output Register assignment REGOUT zs_cs_n_from_the_sdram DATAIN
std_1s10:inst|sdram:the_sdram|m_data[0] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[0] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[0] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[0]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[1] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[1] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[1] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[1]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[2] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[2] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[2] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[2]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[3] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[3] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[3] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[3]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[4] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[4] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[4] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[4]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[5] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[5] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[5] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[5]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[6] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[6] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[6] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[6]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[7] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[7] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[7] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[7]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[8] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[8] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[8] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[8]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[9] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[9] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[9] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[9]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[10] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[10] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[10] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[10]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[11] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[11] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[11] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[11]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[12] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[12] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[12] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[12]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[13] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[13] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[13] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[13]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[14] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[14] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[14] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[14]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[15] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[15] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[15] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[15]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[16] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[16] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[16] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[16]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[17] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[17] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[17] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[17]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[18] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[18] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[18] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[18]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[19] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[19] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[19] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[19]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[20] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[20] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[20] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[20]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[21] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[21] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[21] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[21]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[22] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[22] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[22] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[22]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[23] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[23] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[23] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[23]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[24] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[24] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[24] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[24]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[25] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[25] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[25] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[25]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[26] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[26] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[26] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[26]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[27] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[27] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[27] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[27]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[28] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[28] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[28] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[28]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[29] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[29] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[29] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[29]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[30] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[30] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[30] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[30]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_data[31] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dq_to_and_from_the_sdram[31] DATAIN
std_1s10:inst|sdram:the_sdram|m_data[31] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_data[31]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_dqm[0] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dqm_from_the_sdram[0] DATAIN
std_1s10:inst|sdram:the_sdram|m_dqm[0] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_dqm[0]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_dqm[1] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dqm_from_the_sdram[1] DATAIN
std_1s10:inst|sdram:the_sdram|m_dqm[1] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_dqm[1]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_dqm[2] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dqm_from_the_sdram[2] DATAIN
std_1s10:inst|sdram:the_sdram|m_dqm[2] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_dqm[2]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|m_dqm[3] Packed Register Register Packing Fast Output Register assignment REGOUT zs_dqm_from_the_sdram[3] DATAIN
std_1s10:inst|sdram:the_sdram|m_dqm[3] Duplicated Register Packing Fast Output Register assignment REGOUT std_1s10:inst|sdram:the_sdram|m_dqm[3]~_Duplicate_1 REGOUT
std_1s10:inst|sdram:the_sdram|za_data[0] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[0] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[1] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[1] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[2] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[2] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[3] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[3] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[4] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[4] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[5] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[5] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[6] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[6] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[7] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[7] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[8] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[8] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[9] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[9] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[10] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[10] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[11] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[11] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[12] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[12] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[13] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[13] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[14] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[14] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[15] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[15] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[16] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[16] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[17] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[17] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[18] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[18] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[19] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[19] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[20] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[20] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[21] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[21] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[22] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[22] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[23] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[23] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[24] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[24] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[25] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[25] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[26] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[26] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[27] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[27] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[28] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[28] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[29] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[29] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[30] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[30] COMBOUT
std_1s10:inst|sdram:the_sdram|za_data[31] Packed Register Register Packing Fast Input Register assignment REGOUT zs_dq_to_and_from_the_sdram[31] COMBOUT


Fitter Equations

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Fitter Equations


Pin-Out File

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Pin-Out File


Fitter Resource Usage Summary

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Resource Usage
Total logic elements 4,013 / 10,570 ( 38 % )
    -- Combinational with no register 1971
    -- Register only 286
    -- Combinational with a register 1756
   
Logic element usage by number of LUT inputs  
    -- 4 input functions 2109
    -- 3 input functions 1056
    -- 2 input functions 469
    -- 1 input functions 256
    -- 0 input functions 123
   
Logic elements by mode  
    -- normal mode 3732
    -- arithmetic mode 281
    -- qfbk mode 356
    -- register cascade mode 0
    -- synchronous clear/load mode 793
    -- asynchronous clear/load mode 1767
   
Total LABs 466 / 1,057 ( 44 % )
Logic elements in carry chains 305
User inserted logic elements 0
Virtual pins 0
I/O pins 179 / 427 ( 42 % )
    -- Clock pins 1 / 16 ( 6 % )
Number of I/O registers 220
Global signals 10
M512s 2 / 94 ( 2 % )
M4Ks 13 / 60 ( 22 % )
M-RAMs 1 / 1 ( 100 % )
Total memory bits 571,136 / 920,448 ( 62 % )
Total RAM block bits 650,880 / 920,448 ( 71 % )
DSP block 9-bit elements 8 / 48 ( 17 % )
PLLs 1 / 6 ( 17 % )
Global clocks 10 / 16 ( 63 % )
Regional clocks 0 / 16 ( 0 % )
Fast regional clocks 0 / 8 ( 0 % )
SERDES transmitters 0 / 44 ( 0 % )
SERDES receivers 0 / 44 ( 0 % )
Maximum fan-out node std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0
Maximum fan-out 1924
Highest non-global fan-out signal std_1s10:inst|cpu:the_cpu|W_stall
Highest non-global fan-out 511
Total fan-out 19849
Average fan-out 4.71


Input Pins

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Name Pin # I/O Bank X coordinate Y coordinate Cell number Combinational Fan-Out Registered Fan-Out Global Input Register Power Up High PCI I/O Enabled Bus Hold Weak Pull Up I/O Standard Termination Location assigned by
PLD_CLEAR_N AC9 7 36 0 2 1 0 no no no no no Off LVTTL Off User
PLD_CLOCKINPUT K17 3 21 31 2 74 0 yes no no no no Off LVTTL Off User
in_port_to_the_button_pio[0] W5 6 53 1 1 2 0 no no no no no Off LVTTL Off User
in_port_to_the_button_pio[1] W6 6 53 1 0 2 0 no no no no no Off LVTTL Off User
in_port_to_the_button_pio[2] AB2 6 53 1 3 2 0 no no no no no Off LVTTL Off User
in_port_to_the_button_pio[3] AB1 6 53 1 2 2 0 no no no no no Off LVTTL Off User
irq_from_the_lan91c111 V27 1 0 9 2 1 0 no no no no no Off LVTTL Off User
rxd_to_the_uart1 Y28 1 0 5 2 1 0 no no no no no Off LVTTL Off User


Output Pins

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Name Pin # I/O Bank X coordinate Y coordinate Cell number Output Register Output Enable Register Power Up High Slow Slew Rate PCI I/O Enabled Open Drain TRI Primitive Bus Hold Weak Pull Up I/O Standard Current Strength Termination Location assigned by Load
ENET_ADS_N V25 1 0 8 3 no no no no no no no no Off LVTTL 24mA Off User 10 pF
ENET_AEN V28 1 0 9 3 no no no no no no no no Off LVTTL 24mA Off User 10 pF
LCD_E_from_the_lcd_display K3 5 53 25 2 no no no no no no no no Off LVTTL 24mA Off User 10 pF
LCD_RS_from_the_lcd_display M7 5 53 26 0 no no no no no no no no Off LVTTL 24mA Off User 10 pF
LCD_RW_from_the_lcd_display M8 5 53 26 1 no no no no no no no no Off LVTTL 24mA Off User 10 pF
SDRAM_CLKOUT E15 9 25 31 4 no no no no no no no no Off LVTTL 24mA Off User 10 pF
be_n_to_the_ext_ram[0] M18 3 3 31 5 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
be_n_to_the_ext_ram[1] F17 3 1 31 1 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
be_n_to_the_ext_ram[2] J18 3 19 31 3 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
be_n_to_the_ext_ram[3] L17 3 21 31 1 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
byteenablen_to_the_lan91c111[0] T22 1 0 11 1 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
byteenablen_to_the_lan91c111[1] U26 1 0 10 2 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
byteenablen_to_the_lan91c111[2] U25 1 0 10 3 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
byteenablen_to_the_lan91c111[3] T19 1 0 10 0 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[0] A4 4 52 31 5 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[10] A6 4 48 31 5 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[11] B7 4 48 31 2 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[12] D6 4 48 31 0 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[13] A7 4 48 31 1 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[14] D7 4 46 31 4 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[15] C6 4 46 31 2 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[16] C7 4 46 31 0 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[17] B6 4 48 31 3 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[18] D8 4 46 31 5 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[19] C8 4 46 31 3 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[1] A3 4 52 31 2 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[20] E8 4 46 31 1 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[21] D9 4 44 31 5 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[22] B9 4 44 31 2 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[2] B3 4 52 31 3 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[3] B5 4 52 31 1 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[4] B4 4 50 31 4 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[5] C4 4 50 31 5 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[6] A5 4 50 31 2 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[7] C5 4 50 31 3 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[8] D5 4 52 31 0 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_address[9] E6 4 48 31 4 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
ior_n_to_the_lan91c111 T23 1 0 9 0 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
iow_n_to_the_lan91c111 T24 1 0 9 1 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_led_pio[0] H27 2 0 28 2 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_led_pio[1] H28 2 0 28 3 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_led_pio[2] L23 2 0 28 0 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_led_pio[3] L24 2 0 28 1 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_led_pio[4] J25 2 0 27 2 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_led_pio[5] J26 2 0 27 3 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_led_pio[6] L20 2 0 27 0 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_led_pio[7] L19 2 0 27 1 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[0] C21 3 7 31 4 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[10] B19 3 12 31 2 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[11] A19 3 17 31 0 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[12] D18 3 17 31 2 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[13] C18 3 17 31 4 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[14] A18 3 19 31 1 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[15] D19 3 12 31 1 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[1] B21 3 9 31 1 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[2] A21 3 9 31 0 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[3] C20 3 9 31 2 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[4] A20 3 9 31 5 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[5] B20 3 9 31 4 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[6] B18 3 17 31 3 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[7] D21 3 7 31 2 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[8] E19 3 12 31 0 no no no no no no no no Off LVTTL 24mA Off User 10 pF
out_port_from_the_seven_seg_pio[9] C19 3 12 31 3 no no no no no no no no Off LVTTL 24mA Off User 10 pF
read_n_to_the_ext_flash F19 3 12 31 4 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
read_n_to_the_ext_ram B26 3 1 31 0 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
select_n_to_the_ext_flash K19 3 19 31 0 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
select_n_to_the_ext_ram B24 3 1 31 5 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
txd_from_the_uart1 U21 1 0 5 0 no no no no no no no no Off LVTTL 24mA Off User 10 pF
write_n_to_the_ext_flash G19 3 12 31 5 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
write_n_to_the_ext_ram C24 3 3 31 1 no no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_addr_from_the_sdram[0] AE4 7 31 0 0 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_addr_from_the_sdram[10] Y11 7 50 0 0 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_addr_from_the_sdram[11] AB7 7 52 0 4 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_addr_from_the_sdram[1] W12 7 31 0 3 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_addr_from_the_sdram[2] AC11 7 33 0 0 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_addr_from_the_sdram[3] W10 7 33 0 3 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_addr_from_the_sdram[4] AA11 7 33 0 2 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_addr_from_the_sdram[5] AC10 7 33 0 5 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_addr_from_the_sdram[6] AB11 7 33 0 4 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_addr_from_the_sdram[7] AC8 7 41 0 5 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_addr_from_the_sdram[8] AB10 7 41 0 4 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_addr_from_the_sdram[9] V11 7 50 0 1 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_ba_from_the_sdram[0] AG19 8 12 0 3 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_ba_from_the_sdram[1] AF19 8 12 0 0 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_cas_n_from_the_sdram AD18 8 17 0 3 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
zs_cke_from_the_sdram AE18 8 17 0 5 no no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_cs_n_from_the_sdram AG18 8 17 0 4 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
zs_dqm_from_the_sdram[0] AE14 7 29 0 2 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dqm_from_the_sdram[1] Y13 7 29 0 0 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dqm_from_the_sdram[2] AE7 7 48 0 3 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dqm_from_the_sdram[3] AG10 7 41 0 1 yes no no no no no no no Off LVTTL 24mA Off User 10 pF
zs_ras_n_from_the_sdram AH3 7 52 0 0 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF
zs_we_n_from_the_sdram AH19 8 17 0 1 yes no yes no no no no no Off LVTTL 24mA Off User 10 pF


Bidir Pins

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Name Pin # I/O Bank X coordinate Y coordinate Cell number Combinational Fan-Out Registered Fan-Out Global Input Register Output Register Output Enable Register Power Up High Slow Slew Rate PCI I/O Enabled Open Drain Bus Hold Weak Pull Up I/O Standard Current Strength Termination Location assigned by Load
LCD_data_to_and_from_the_lcd_display[0] H3 5 53 29 3 1 0 no no no no no no no no no Off LVTTL 24mA Off User 10 pF
LCD_data_to_and_from_the_lcd_display[1] L7 5 53 29 0 1 0 no no no no no no no no no Off LVTTL 24mA Off User 10 pF
LCD_data_to_and_from_the_lcd_display[2] L8 5 53 29 1 1 0 no no no no no no no no no Off LVTTL 24mA Off User 10 pF
LCD_data_to_and_from_the_lcd_display[3] H2 5 53 28 2 1 0 no no no no no no no no no Off LVTTL 24mA Off User 10 pF
LCD_data_to_and_from_the_lcd_display[4] H1 5 53 28 3 1 0 no no no no no no no no no Off LVTTL 24mA Off User 10 pF
LCD_data_to_and_from_the_lcd_display[5] L6 5 53 28 0 1 0 no no no no no no no no no Off LVTTL 24mA Off User 10 pF
LCD_data_to_and_from_the_lcd_display[6] L5 5 53 28 1 1 0 no no no no no no no no no Off LVTTL 24mA Off User 10 pF
LCD_data_to_and_from_the_lcd_display[7] J4 5 53 27 2 1 0 no no no no no no no no no Off LVTTL 24mA Off User 10 pF
bidir_port_to_and_from_the_reconfig_request_pio U2 6 53 11 3 1 0 no no no no no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[0] H12 4 33 31 3 0 11 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[10] A9 4 44 31 1 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[11] C9 4 44 31 4 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[12] E10 4 41 31 2 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[13] A10 4 41 31 3 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[14] C10 4 41 31 0 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[15] B10 4 36 31 4 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[16] A11 4 36 31 5 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[17] C11 4 36 31 2 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[18] D11 4 36 31 0 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[19] B11 4 36 31 1 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[1] F12 4 33 31 0 0 11 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[20] D10 4 41 31 1 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[21] G10 4 41 31 4 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[22] F10 4 41 31 5 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[23] H11 4 33 31 4 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[24] G11 4 33 31 5 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[25] F8 4 31 31 0 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[26] J9 4 31 31 1 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[27] J13 4 29 31 2 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[28] L13 4 29 31 0 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[29] M11 4 50 31 1 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[2] J12 4 33 31 1 0 11 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[30] L11 4 50 31 0 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[31] G7 4 52 31 4 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[3] M12 4 31 31 3 0 11 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[4] H17 3 19 31 4 0 11 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[5] K18 3 19 31 5 0 11 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[6] H18 3 19 31 2 0 11 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[7] G18 3 17 31 5 0 11 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[8] B8 4 44 31 3 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
ext_ram_bus_data[9] A8 4 44 31 0 0 3 no yes yes yes no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[0] AH4 7 52 0 5 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[10] AH6 7 48 0 2 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[11] AD6 7 48 0 0 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[12] AF7 7 48 0 1 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[13] AH7 7 46 0 4 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[14] AG7 7 46 0 2 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[15] AF6 7 46 0 0 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[16] AG8 7 46 0 5 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[17] AF8 7 46 0 3 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[18] AD8 7 46 0 1 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[19] AH9 7 44 0 5 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[1] AE5 7 52 0 2 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[20] AH8 7 44 0 2 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[21] AE9 7 44 0 3 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[22] AF9 7 44 0 0 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[23] AG9 7 44 0 1 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[24] AD10 7 41 0 2 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[25] AF10 7 41 0 3 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[26] AH10 7 41 0 0 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[27] AE10 7 36 0 4 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[28] AF11 7 36 0 5 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[29] AE11 7 36 0 3 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[2] AG3 7 52 0 3 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[30] AH11 7 36 0 0 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[31] AG11 7 36 0 1 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[3] AG5 7 52 0 1 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[4] AG4 7 50 0 4 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[5] AF4 7 50 0 5 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[6] AH5 7 50 0 2 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[7] AF5 7 50 0 3 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[8] AE6 7 48 0 4 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF
zs_dq_to_and_from_the_sdram[9] AG6 7 48 0 5 0 2 no yes yes no no no no no no Off LVTTL 24mA Off User 10 pF


I/O Bank Usage

Top
I/O Bank Usage VCCIO Voltage VREF Voltage
1 11 / 48 ( 23 % ) 3.3V --
2 8 / 48 ( 17 % ) 3.3V --
3 31 / 52 ( 60 % ) 3.3V --
4 51 / 55 ( 93 % ) 3.3V --
5 11 / 48 ( 23 % ) 3.3V --
6 5 / 48 ( 10 % ) 3.3V --
7 50 / 55 ( 91 % ) 3.3V --
8 6 / 52 ( 12 % ) 3.3V --
9 1 / 6 ( 17 % ) 3.3V --
10 0 / 4 ( 0 % ) 3.3V --
11 0 / 6 ( 0 % ) 3.3V --
12 0 / 4 ( 0 % ) 3.3V --


All Package Pins

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Location Pad Number I/O Bank Pin Name/Usage Dir. I/O Standard Voltage I/O Type Termination User Assignment Bus Hold Weak Pull Up
A2   4 VCCIO4 power   3.3V -- --   -- --
A3 332 4 ext_ram_bus_address[1] output LVTTL   Column I/O Off Y no Off
A4 331 4 ext_ram_bus_address[0] output LVTTL   Column I/O Off Y no Off
A5 338 4 ext_ram_bus_address[6] output LVTTL   Column I/O Off Y no Off
A6 344 4 ext_ram_bus_address[10] output LVTTL   Column I/O Off Y no Off
A7 348 4 ext_ram_bus_address[13] output LVTTL   Column I/O Off Y no Off
A8 359 4 ext_ram_bus_data[9] bidir LVTTL   Column I/O Off Y no Off
A9 360 4 ext_ram_bus_data[10] bidir LVTTL   Column I/O Off Y no Off
A10 364 4 ext_ram_bus_data[13] bidir LVTTL   Column I/O Off Y no Off
A11 368 4 ext_ram_bus_data[16] bidir LVTTL   Column I/O Off Y no Off
A12   4 VCCIO4 power   3.3V -- --   -- --
A13     NC       -- --   -- --
A14     GND gnd     -- --   -- --
A15     GND gnd     -- --   -- --
A16     NC       -- --   -- --
A17   3 VCCIO3 power   3.3V -- --   -- --
A18 416 3 out_port_from_the_seven_seg_pio[14] output LVTTL   Column I/O Off Y no Off
A19 421 3 out_port_from_the_seven_seg_pio[11] output LVTTL   Column I/O Off Y no Off
A20 430 3 out_port_from_the_seven_seg_pio[4] output LVTTL   Column I/O Off Y no Off
A21 433 3 out_port_from_the_seven_seg_pio[2] output LVTTL   Column I/O Off Y no Off
A22 438 3 RESERVED_INPUT       Column I/O --   no Off
A23 443 3 RESERVED_INPUT       Column I/O --   no Off
A24 450 3 RESERVED_INPUT       Column I/O --   no Off
A25 452 3 RESERVED_INPUT       Column I/O --   no Off
A26 457 3 RESERVED_INPUT       Column I/O --   no Off
A27   3 VCCIO3 power   3.3V -- --   -- --
AA1 241 6 RESERVED_INPUT       Row I/O --   no Off
AA2 240 6 RESERVED_INPUT       Row I/O --   no Off
AA3 236 6 RESERVED_INPUT       Row I/O --   no Off
AA4 237 6 RESERVED_INPUT       Row I/O --   no Off
AA5     NC       -- --   -- --
AA6     NC       -- --   -- --
AA7     NC       -- --   -- --
AA8     NC       -- --   -- --
AA9     NC       -- --   -- --
AA10     NC       -- --   -- --
AA11 183 7 zs_addr_from_the_sdram[4] output LVTTL   Column I/O Off Y no Off
AA12 178 7 ^VCCSEL       -- --   -- --
AA13     VCCG_PLL6 power   1.5V -- --   -- --
AA14 163 11 RESERVED_INPUT       Column I/O --   no Off
AA15 162 11 RESERVED_INPUT       Column I/O --   no Off
AA16     GND gnd     -- --   -- --
AA17 151 8 GND+       Column I/O --   -- --
AA18 148 8 RESERVED_INPUT       Column I/O --   no Off
AA19 146 8 RESERVED_INPUT       Column I/O --   no Off
AA20 140 8 RESERVED_INPUT       Column I/O --   no Off
AA21     NC       -- --   -- --
AA22     NC       -- --   -- --
AA23     NC       -- --   -- --
AA24     NC       -- --   -- --
AA25 92 1 RESERVED_INPUT       Row I/O --   no Off
AA26 93 1 RESERVED_INPUT       Row I/O --   no Off
AA27 89 1 RESERVED_INPUT       Row I/O --   no Off
AA28 88 1 RESERVED_INPUT       Row I/O --   no Off
AB1 233 6 in_port_to_the_button_pio[3] input LVTTL   Row I/O Off Y no Off
AB2 232 6 in_port_to_the_button_pio[2] input LVTTL   Row I/O Off Y no Off
AB3     NC       -- --   -- --
AB4     NC       -- --   -- --
AB5     NC       -- --   -- --
AB6     NC       -- --   -- --
AB7 229 7 zs_addr_from_the_sdram[11] output LVTTL   Column I/O Off Y no Off
AB8     NC       -- --   -- --
AB9     NC       -- --   -- --
AB10 198 7 zs_addr_from_the_sdram[8] output LVTTL   Column I/O Off Y no Off
AB11 185 7 zs_addr_from_the_sdram[6] output LVTTL   Column I/O Off Y no Off
AB12     NC       -- --   -- --
AB13 172 7 ^nCE       -- --   -- --
AB14     GNDG_PLL6 gnd     -- --   -- --
AB15 157 8 ^MSEL2       -- --   -- --
AB16   12 VCC_PLL6_OUTB power   3.3V -- --   -- --
AB17 152 8 RESERVED_INPUT       Column I/O --   no Off
AB18 126 8 RESERVED_INPUT       Column I/O --   no Off
AB19 134 8 RESERVED_INPUT       Column I/O --   no Off
AB20     NC       -- --   -- --
AB21     NC       -- --   -- --
AB22     NC       -- --   -- --
AB23     NC       -- --   -- --
AB24     NC       -- --   -- --
AB25     NC       -- --   -- --
AB26     NC       -- --   -- --
AB27 97 1 RESERVED_INPUT       Row I/O --   no Off
AB28 96 1 RESERVED_INPUT       Row I/O --   no Off
AC1     NC       -- --   -- --
AC2     NC       -- --   -- --
AC3     NC       -- --   -- --
AC4     NC       -- --   -- --
AC5     NC       -- --   -- --
AC6     NC       -- --   -- --
AC7     NC       -- --   -- --
AC8 197 7 zs_addr_from_the_sdram[7] output LVTTL   Column I/O Off Y no Off
AC9 190 7 PLD_CLEAR_N input LVTTL   Column I/O Off Y no Off
AC10 184 7 zs_addr_from_the_sdram[5] output LVTTL   Column I/O Off Y no Off
AC11 181 7 zs_addr_from_the_sdram[2] output LVTTL   Column I/O Off Y no Off
AC12 179 7 ^PORSEL       -- --   -- --
AC13 173 7 ^nCEO       -- --   -- --
AC14   11 VCC_PLL6_OUTA power   3.3V -- --   -- --
AC15     GND gnd     -- --   -- --
AC16 155 8 ^MSEL0       -- --   -- --
AC17 153 8 GND+       Column I/O --   -- --
AC18 154 8 PLL_ENA       -- --   -- --
AC19 136 8 RESERVED_INPUT       Column I/O --   no Off
AC20     NC       -- --   -- --
AC21 135 8 RESERVED_INPUT       Column I/O --   no Off
AC22     NC       -- --   -- --
AC23     NC       -- --   -- --
AC24     NC       -- --   -- --
AC25     NC       -- --   -- --
AC26     NC       -- --   -- --
AC27     NC       -- --   -- --
AC28     NC       -- --   -- --
AD1     NC       -- --   -- --
AD2     NC       -- --   -- --
AD3     NC       -- --   -- --
AD4     NC       -- --   -- --
AD5     NC       -- --   -- --
AD6 212 7 zs_dq_to_and_from_the_sdram[11] bidir LVTTL   Column I/O Off Y no Off
AD7     NC       -- --   -- --
AD8 205 7 zs_dq_to_and_from_the_sdram[18] bidir LVTTL   Column I/O Off Y no Off
AD9 217   GND gnd     -- --   no Off
AD10 196 7 zs_dq_to_and_from_the_sdram[24] bidir LVTTL   Column I/O Off Y no Off
AD11 186   GND gnd     -- --   no Off
AD12     NC       -- --   -- --
AD13     NC       -- --   -- --
AD14 170 7 GND+       Column I/O --   -- --
AD15 167 11 RESERVED_INPUT       Column I/O --   no Off
AD16     NC       -- --   -- --
AD17     NC       -- --   -- --
AD18 139 8 zs_cas_n_from_the_sdram output LVTTL   Column I/O Off Y no Off
AD19 131 8 RESERVED_INPUT       Column I/O --   no Off
AD20 149   GND gnd     -- --   no Off
AD21 120 8 RESERVED_INPUT       Column I/O --   no Off
AD22 112   GND gnd     -- --   no Off
AD23 109 8 RESERVED_INPUT       Column I/O --   no Off
AD24     NC       -- --   -- --
AD25     NC       -- --   -- --
AD26     NC       -- --   -- --
AD27     NC       -- --   -- --
AD28     NC       -- --   -- --
AE1     NC       -- --   -- --
AE2     NC       -- --   -- --
AE3 242   GND gnd     -- --   no Off
AE4 175 7 zs_addr_from_the_sdram[0] output LVTTL   Column I/O Off Y no Off
AE5 227 7 zs_dq_to_and_from_the_sdram[1] bidir LVTTL   Column I/O Off Y no Off
AE6 216 7 zs_dq_to_and_from_the_sdram[8] bidir LVTTL   Column I/O Off Y no Off
AE7 213 7 zs_dqm_from_the_sdram[2] output LVTTL   Column I/O Off Y no Off
AE8 204 7 RESERVED_INPUT       Column I/O --   no Off
AE9 201 7 zs_dq_to_and_from_the_sdram[21] bidir LVTTL   Column I/O Off Y no Off
AE10 192 7 zs_dq_to_and_from_the_sdram[27] bidir LVTTL   Column I/O Off Y no Off
AE11 189 7 zs_dq_to_and_from_the_sdram[29] bidir LVTTL   Column I/O Off Y no Off
AE12     NC       -- --   -- --
AE13     NC       -- --   -- --
AE14 171 7 zs_dqm_from_the_sdram[0] output LVTTL   Column I/O Off Y no Off
AE15 166 11 RESERVED_INPUT       Column I/O --   no Off
AE16     NC       -- --   -- --
AE17     NC       -- --   -- --
AE18 141 8 zs_cke_from_the_sdram output LVTTL   Column I/O Off Y no Off
AE19 130 8 RESERVED_INPUT       Column I/O --   no Off
AE20 124 8 RESERVED_INPUT       Column I/O --   no Off
AE21 121 8 RESERVED_INPUT       Column I/O --   no Off
AE22 114 8 RESERVED_INPUT       Column I/O --   no Off
AE23 115 8 RESERVED_INPUT       Column I/O --   no Off
AE24 108 8 RESERVED_INPUT       Column I/O --   no Off
AE25     NC       -- --   -- --
AE26     NC       -- --   -- --
AE27     NC       -- --   -- --
AE28     NC       -- --   -- --
AF1     NC       -- --   -- --
AF2     NC       -- --   -- --
AF3     GND gnd     -- --   -- --
AF4 222 7 zs_dq_to_and_from_the_sdram[5] bidir LVTTL   Column I/O Off Y no Off
AF5 220 7 zs_dq_to_and_from_the_sdram[7] bidir LVTTL   Column I/O Off Y no Off
AF6 206 7 zs_dq_to_and_from_the_sdram[15] bidir LVTTL   Column I/O Off Y no Off
AF7 211 7 zs_dq_to_and_from_the_sdram[12] bidir LVTTL   Column I/O Off Y no Off
AF8 207 7 zs_dq_to_and_from_the_sdram[17] bidir LVTTL   Column I/O Off Y no Off
AF9 200 7 zs_dq_to_and_from_the_sdram[22] bidir LVTTL   Column I/O Off Y no Off
AF10 195 7 zs_dq_to_and_from_the_sdram[25] bidir LVTTL   Column I/O Off Y no Off
AF11 191 7 zs_dq_to_and_from_the_sdram[28] bidir LVTTL   Column I/O Off Y no Off
AF12     NC       -- --   -- --
AF13     NC       -- --   -- --
AF14     GNDA_PLL6 gnd     -- --   -- --
AF15 161 12 RESERVED_INPUT       Column I/O --   no Off
AF16     NC       -- --   -- --
AF17     NC       -- --   -- --
AF18 138 8 RESERVED_INPUT       Column I/O --   no Off
AF19 132 8 zs_ba_from_the_sdram[1] output LVTTL   Column I/O Off Y no Off
AF20 119 8 RESERVED_INPUT       Column I/O --   no Off
AF21 123 8 RESERVED_INPUT       Column I/O --   no Off
AF22 116 8 RESERVED_INPUT       Column I/O --   no Off
AF23 111 8 RESERVED_INPUT       Column I/O --   no Off
AF24 105 8 RESERVED_INPUT       Column I/O --   no Off
AF25 104 8 RESERVED_INPUT       Column I/O --   no Off
AF26     GND gnd     -- --   -- --
AF27     NC       -- --   -- --
AF28     NC       -- --   -- --
AG1   6 VCCIO6 power   3.3V -- --   -- --
AG2     GND gnd     -- --   -- --
AG3 226 7 zs_dq_to_and_from_the_sdram[2] bidir LVTTL   Column I/O Off Y no Off
AG4 223 7 zs_dq_to_and_from_the_sdram[4] bidir LVTTL   Column I/O Off Y no Off
AG5 224 7 zs_dq_to_and_from_the_sdram[3] bidir LVTTL   Column I/O Off Y no Off
AG6 215 7 zs_dq_to_and_from_the_sdram[9] bidir LVTTL   Column I/O Off Y no Off
AG7 208 7 zs_dq_to_and_from_the_sdram[14] bidir LVTTL   Column I/O Off Y no Off
AG8 209 7 zs_dq_to_and_from_the_sdram[16] bidir LVTTL   Column I/O Off Y no Off
AG9 199 7 zs_dq_to_and_from_the_sdram[23] bidir LVTTL   Column I/O Off Y no Off
AG10 193 7 zs_dqm_from_the_sdram[3] output LVTTL   Column I/O Off Y no Off
AG11 187 7 zs_dq_to_and_from_the_sdram[31] bidir LVTTL   Column I/O Off Y no Off
AG12     NC       -- --   -- --
AG13     NC       -- --   -- --
AG14     VCCA_PLL6 power   1.5V -- --   -- --
AG15 160 12 RESERVED_INPUT       Column I/O --   no Off
AG16     NC       -- --   -- --
AG17     NC       -- --   -- --
AG18 142 8 zs_cs_n_from_the_sdram output LVTTL   Column I/O Off Y no Off
AG19 133 8 zs_ba_from_the_sdram[0] output LVTTL   Column I/O Off Y no Off
AG20 125 8 RESERVED_INPUT       Column I/O --   no Off
AG21 122 8 RESERVED_INPUT       Column I/O --   no Off
AG22 118 8 RESERVED_INPUT       Column I/O --   no Off
AG23 107 8 RESERVED_INPUT       Column I/O --   no Off
AG24 106 8 RESERVED_INPUT       Column I/O --   no Off
AG25 102 8 RESERVED_INPUT       Column I/O --   no Off
AG26 100 8 RESERVED_INPUT       Column I/O --   no Off
AG27     GND gnd     -- --   -- --
AG28   1 VCCIO1 power   3.3V -- --   -- --
AH2   7 VCCIO7 power   3.3V -- --   -- --
AH3 225 7 zs_ras_n_from_the_sdram output LVTTL   Column I/O Off Y no Off
AH4 228 7 zs_dq_to_and_from_the_sdram[0] bidir LVTTL   Column I/O Off Y no Off
AH5 221 7 zs_dq_to_and_from_the_sdram[6] bidir LVTTL   Column I/O Off Y no Off
AH6 214 7 zs_dq_to_and_from_the_sdram[10] bidir LVTTL   Column I/O Off Y no Off
AH7 210 7 zs_dq_to_and_from_the_sdram[13] bidir LVTTL   Column I/O Off Y no Off
AH8 202 7 zs_dq_to_and_from_the_sdram[20] bidir LVTTL   Column I/O Off Y no Off
AH9 203 7 zs_dq_to_and_from_the_sdram[19] bidir LVTTL   Column I/O Off Y no Off
AH10 194 7 zs_dq_to_and_from_the_sdram[26] bidir LVTTL   Column I/O Off Y no Off
AH11 188 7 zs_dq_to_and_from_the_sdram[30] bidir LVTTL   Column I/O Off Y no Off
AH12   7 VCCIO7 power   3.3V -- --   -- --
AH13     NC       -- --   -- --
AH14     GND gnd     -- --   -- --
AH15     GND gnd     -- --   -- --
AH16     NC       -- --   -- --
AH17   8 VCCIO8 power   3.3V -- --   -- --
AH18     NC       -- --   -- --
AH19 137 8 zs_we_n_from_the_sdram output LVTTL   Column I/O Off Y no Off
AH20 129 8 RESERVED_INPUT       Column I/O --   no Off
AH21 127 8 RESERVED_INPUT       Column I/O --   no Off
AH22 117 8 RESERVED_INPUT       Column I/O --   no Off
AH23 113 8 RESERVED_INPUT       Column I/O --   no Off
AH24 110 8 RESERVED_INPUT       Column I/O --   no Off
AH25 103 8 RESERVED_INPUT       Column I/O --   no Off
AH26 101 8 RESERVED_INPUT       Column I/O --   no Off
AH27   8 VCCIO8 power   3.3V -- --   -- --
B1   5 VCCIO5 power   3.3V -- --   -- --
B2     GND gnd     -- --   -- --
B3 333 4 ext_ram_bus_address[2] output LVTTL   Column I/O Off Y no Off
B4 336 4 ext_ram_bus_address[4] output LVTTL   Column I/O Off Y no Off
B5 335 4 ext_ram_bus_address[3] output LVTTL   Column I/O Off Y no Off
B6 346 4 ext_ram_bus_address[17] output LVTTL   Column I/O Off Y no Off
B7 345 4 ext_ram_bus_address[11] output LVTTL   Column I/O Off Y no Off
B8 358 4 ext_ram_bus_data[8] bidir LVTTL   Column I/O Off Y no Off
B9 357 4 ext_ram_bus_address[22] output LVTTL   Column I/O Off Y no Off
B10 367 4 ext_ram_bus_data[15] bidir LVTTL   Column I/O Off Y no Off
B11 372 4 ext_ram_bus_data[19] bidir LVTTL   Column I/O Off Y no Off
B12     NC       -- --   -- --
B13     NC       -- --   -- --
B14     TEMPDIODEp       -- --   -- --
B15 399 10 RESERVED_INPUT       Column I/O --   no Off
B16     NC       -- --   -- --
B17     NC       -- --   -- --
B18 420 3 out_port_from_the_seven_seg_pio[6] output LVTTL   Column I/O Off Y no Off
B19 425 3 out_port_from_the_seven_seg_pio[10] output LVTTL   Column I/O Off Y no Off
B20 429 3 out_port_from_the_seven_seg_pio[5] output LVTTL   Column I/O Off Y no Off
B21 434 3 out_port_from_the_seven_seg_pio[1] output LVTTL   Column I/O Off Y no Off
B22 436 3 RESERVED_INPUT       Column I/O --   no Off
B23 446 3 RESERVED_INPUT       Column I/O --   no Off
B24 455 3 select_n_to_the_ext_ram output LVTTL   Column I/O Off Y no Off
B25 456 3 RESERVED_INPUT       Column I/O --   no Off
B26 458 3 read_n_to_the_ext_ram output LVTTL   Column I/O Off Y no Off
B27     GND gnd     -- --   -- --
B28   2 VCCIO2 power   3.3V -- --   -- --
C1     NC       -- --   -- --
C2     NC       -- --   -- --
C3     GND gnd     -- --   -- --
C4 337 4 ext_ram_bus_address[5] output LVTTL   Column I/O Off Y no Off
C5 339 4 ext_ram_bus_address[7] output LVTTL   Column I/O Off Y no Off
C6 351 4 ext_ram_bus_address[15] output LVTTL   Column I/O Off Y no Off
C7 353 4 ext_ram_bus_address[16] output LVTTL   Column I/O Off Y no Off
C8 352 4 ext_ram_bus_address[19] output LVTTL   Column I/O Off Y no Off
C9 355 4 ext_ram_bus_data[11] bidir LVTTL   Column I/O Off Y no Off
C10 365 4 ext_ram_bus_data[14] bidir LVTTL   Column I/O Off Y no Off
C11 369 4 ext_ram_bus_data[17] bidir LVTTL   Column I/O Off Y no Off
C12     NC       -- --   -- --
C13     NC       -- --   -- --
C14     TEMPDIODEn       -- --   -- --
C15 398 10 RESERVED_INPUT       Column I/O --   no Off
C16     NC       -- --   -- --
C17     NC       -- --   -- --
C18 417 3 out_port_from_the_seven_seg_pio[13] output LVTTL   Column I/O Off Y no Off
C19 426 3 out_port_from_the_seven_seg_pio[9] output LVTTL   Column I/O Off Y no Off
C20 431 3 out_port_from_the_seven_seg_pio[3] output LVTTL   Column I/O Off Y no Off
C21 435 3 out_port_from_the_seven_seg_pio[0] output LVTTL   Column I/O Off Y no Off
C22 440 3 RESERVED_INPUT       Column I/O --   no Off
C23 444 3 RESERVED_INPUT       Column I/O --   no Off
C24 453 3 write_n_to_the_ext_ram output LVTTL   Column I/O Off Y no Off
C25 451 3 RESERVED_INPUT       Column I/O --   no Off
C26     GND gnd     -- --   -- --
C27     NC       -- --   -- --
C28     NC       -- --   -- --
D1     NC       -- --   -- --
D2     NC       -- --   -- --
D3     NC       -- --   -- --
D4     NC       -- --   -- --
D5 334 4 ext_ram_bus_address[8] output LVTTL   Column I/O Off Y no Off
D6 347 4 ext_ram_bus_address[12] output LVTTL   Column I/O Off Y no Off
D7 349 4 ext_ram_bus_address[14] output LVTTL   Column I/O Off Y no Off
D8 350 4 ext_ram_bus_address[18] output LVTTL   Column I/O Off Y no Off
D9 356 4 ext_ram_bus_address[21] output LVTTL   Column I/O Off Y no Off
D10 366 4 ext_ram_bus_data[20] bidir LVTTL   Column I/O Off Y no Off
D11 371 4 ext_ram_bus_data[18] bidir LVTTL   Column I/O Off Y no Off
D12     NC       -- --   -- --
D13     NC       -- --   -- --
D14     VCCG_PLL5 power   1.5V -- --   -- --
D15 393 9 RESERVED_INPUT       Column I/O --   no Off
D16     NC       -- --   -- --
D17     NC       -- --   -- --
D18 419 3 out_port_from_the_seven_seg_pio[12] output LVTTL   Column I/O Off Y no Off
D19 428 3 out_port_from_the_seven_seg_pio[15] output LVTTL   Column I/O Off Y no Off
D20 432 3 RESERVED_INPUT       Column I/O --   no Off
D21 437 3 out_port_from_the_seven_seg_pio[7] output LVTTL   Column I/O Off Y no Off
D22 442 3 RESERVED_INPUT       Column I/O --   no Off
D23 441 3 RESERVED_INPUT       Column I/O --   no Off
D24 454 3 RESERVED_INPUT       Column I/O --   no Off
D25     NC       -- --   -- --
D26     NC       -- --   -- --
D27     NC       -- --   -- --
D28     NC       -- --   -- --
E1     NC       -- --   -- --
E2     NC       -- --   -- --
E3     NC       -- --   -- --
E4     NC       -- --   -- --
E5     NC       -- --   -- --
E6 343 4 ext_ram_bus_address[9] output LVTTL   Column I/O Off Y no Off
E7 342   GND gnd     -- --   no Off
E8 354 4 ext_ram_bus_address[20] output LVTTL   Column I/O Off Y no Off
E9 373   GND gnd     -- --   no Off
E10 363 4 ext_ram_bus_data[12] bidir LVTTL   Column I/O Off Y no Off
E11     NC       -- --   -- --
E12     NC       -- --   -- --
E13     NC       -- --   -- --
E14     GNDG_PLL5 gnd     -- --   -- --
E15 392 9 SDRAM_CLKOUT output LVTTL   Column I/O Off Y no Off
E16     NC       -- --   -- --
E17     NC       -- --   -- --
E18 410   GND gnd     -- --   no Off
E19 427 3 out_port_from_the_seven_seg_pio[8] output LVTTL   Column I/O Off Y no Off
E20 447   GND gnd     -- --   no Off
E21 439 3 RESERVED_INPUT       Column I/O --   no Off
E22     NC       -- --   -- --
E23 445 3 RESERVED_INPUT       Column I/O --   no Off
E24 12   GND gnd     -- --   no Off
E25     NC       -- --   -- --
E26     NC       -- --   -- --
E27     NC       -- --   -- --
E28     NC       -- --   -- --
F1     NC       -- --   -- --
F2     NC       -- --   -- --
F3     NC       -- --   -- --
F4     NC       -- --   -- --
F5     NC       -- --   -- --
F6     NC       -- --   -- --
F7     NC       -- --   -- --
F8 384 4 ext_ram_bus_data[25] bidir LVTTL   Column I/O Off Y no Off
F9     NC       -- --   -- --
F10 362 4 ext_ram_bus_data[22] bidir LVTTL   Column I/O Off Y no Off
F11     NC       -- --   -- --
F12 378 4 ext_ram_bus_data[1] bidir LVTTL   Column I/O Off Y no Off
F13 380 4 #altera_reserved_tms input LVTTL   -- Off N no Off
F14     VCCA_PLL5 power   1.5V -- --   -- --
F15   9 VCC_PLL5_OUTA power   3.3V -- --   -- --
F16 404 3 ^DCLK       -- --   -- --
F17 459 3 be_n_to_the_ext_ram[1] output LVTTL   Column I/O Off Y no Off
F18     NC       -- --   -- --
F19 423 3 read_n_to_the_ext_flash output LVTTL   Column I/O Off Y no Off
F20     NC       -- --   -- --
F21     NC       -- --   -- --
F22     NC       -- --   -- --
F23     NC       -- --   -- --
F24     NC       -- --   -- --
F25     NC       -- --   -- --
F26     NC       -- --   -- --
F27     NC       -- --   -- --
F28     NC       -- --   -- --
G1 328 5 RESERVED_INPUT       Row I/O --   no Off
G2 329 5 RESERVED_INPUT       Row I/O --   no Off
G3     NC       -- --   -- --
G4     NC       -- --   -- --
G5     NC       -- --   -- --
G6     NC       -- --   -- --
G7 330 4 ext_ram_bus_data[31] bidir LVTTL   Column I/O Off Y no Off
G8     NC       -- --   -- --
G9     NC       -- --   -- --
G10 361 4 ext_ram_bus_data[21] bidir LVTTL   Column I/O Off Y no Off
G11 375 4 ext_ram_bus_data[24] bidir LVTTL   Column I/O Off Y no Off
G12     NC       -- --   -- --
G13 386 4 #altera_reserved_tdi input LVTTL   -- Off N no Off
G14     GNDA_PLL5 gnd     -- --   -- --
G15     GND gnd     -- --   -- --
G16   10 VCC_PLL5_OUTB power   3.3V -- --   -- --
G17 405 3 ^CONF_DONE       -- --   -- --
G18 418 3 ext_ram_bus_data[7] bidir LVTTL   Column I/O Off Y no Off
G19 424 3 write_n_to_the_ext_flash output LVTTL   Column I/O Off Y no Off
G20     GND gnd     -- --   -- --
G21     NC       -- --   -- --
G22     NC       -- --   -- --
G23     NC       -- --   -- --
G24     NC       -- --   -- --
G25     NC       -- --   -- --
G26     NC       -- --   -- --
G27 0 2 RESERVED_INPUT       Row I/O --   no Off
G28 1 2 RESERVED_INPUT       Row I/O --   no Off
H1 320 5 LCD_data_to_and_from_the_lcd_display[4] bidir LVTTL   Row I/O Off Y no Off
H2 321 5 LCD_data_to_and_from_the_lcd_display[3] bidir LVTTL   Row I/O Off Y no Off
H3 324 5 LCD_data_to_and_from_the_lcd_display[0] bidir LVTTL   Row I/O Off Y no Off
H4 325 5 RESERVED_INPUT       Row I/O --   no Off
H5     NC       -- --   -- --
H6     NC       -- --   -- --
H7     NC       -- --   -- --
H8     NC       -- --   -- --
H9     NC       -- --   -- --
H10     NC       -- --   -- --
H11 374 4 ext_ram_bus_data[23] bidir LVTTL   Column I/O Off Y no Off
H12 377 4 ext_ram_bus_data[0] bidir LVTTL   Column I/O Off Y no Off
H13 387 4 #altera_reserved_tdo output LVTTL   -- Off N no Off
H14 396 9 RESERVED_INPUT       Column I/O --   no Off
H15 397 9 RESERVED_INPUT       Column I/O --   no Off
H16     GND gnd     -- --   -- --
H17 411 3 ext_ram_bus_data[4] bidir LVTTL   Column I/O Off Y no Off
H18 413 3 ext_ram_bus_data[6] bidir LVTTL   Column I/O Off Y no Off
H19     NC       -- --   -- --
H20     NC       -- --   -- --
H21     NC       -- --   -- --
H22     NC       -- --   -- --
H23     NC       -- --   -- --
H24     NC       -- --   -- --
H25 5 2 RESERVED_INPUT       Row I/O --   no Off
H26 4 2 RESERVED_INPUT       Row I/O --   no Off
H27 8 2 out_port_from_the_led_pio[0] output LVTTL   Row I/O Off Y no Off
H28 9 2 out_port_from_the_led_pio[1] output LVTTL   Row I/O Off Y no Off
J1 311 5 RESERVED_INPUT       Row I/O --   no Off
J2 312 5 RESERVED_INPUT       Row I/O --   no Off
J3 315 5 RESERVED_INPUT       Row I/O --   no Off
J4 316 5 LCD_data_to_and_from_the_lcd_display[7] bidir LVTTL   Row I/O Off Y no Off
J5     NC       -- --   -- --
J6     NC       -- --   -- --
J7     NC       -- --   -- --
J8     NC       -- --   -- --
J9 385 4 ext_ram_bus_data[26] bidir LVTTL   Column I/O Off Y no Off
J10     NC       -- --   -- --
J11 370 4 RESERVED_INPUT       Column I/O --   no Off
J12 379 4 ext_ram_bus_data[2] bidir LVTTL   Column I/O Off Y no Off
J13 388 4 ext_ram_bus_data[27] bidir LVTTL   Column I/O Off Y no Off
J14   4 VCCIO4 power   3.3V -- --   -- --
J15   3 VCCIO3 power   3.3V -- --   -- --
J16 401 10 RESERVED_INPUT       Column I/O --   no Off
J17 407 3 RESERVED_INPUT       Column I/O --   no Off
J18 414 3 be_n_to_the_ext_ram[2] output LVTTL   Column I/O Off Y no Off
J19 422 3 RESERVED_INPUT       Column I/O --   no Off
J20     NC       -- --   -- --
J21     NC       -- --   -- --
J22     NC       -- --   -- --
J23     NC       -- --   -- --
J24     NC       -- --   -- --
J25 13 2 out_port_from_the_led_pio[4] output LVTTL   Row I/O Off Y no Off
J26 14 2 out_port_from_the_led_pio[5] output LVTTL   Row I/O Off Y no Off
J27 17 2 RESERVED_INPUT       Row I/O --   no Off
J28 18 2 RESERVED_INPUT       Row I/O --   no Off
K1 303 5 RESERVED_INPUT       Row I/O --   no Off
K2 304 5 RESERVED_INPUT       Row I/O --   no Off
K3 308 5 LCD_E_from_the_lcd_display output LVTTL   Row I/O Off Y no Off
K4 307 5 RESERVED_INPUT       Row I/O --   no Off
K5     NC       -- --   -- --
K6     NC       -- --   -- --
K7 326 5 RESERVED_INPUT       Row I/O --   no Off
K8 327 5 RESERVED_INPUT       Row I/O --   no Off
K9 317   GND gnd     -- --   no Off
K10     NC       -- --   -- --
K11 376 4 RESERVED_INPUT       Column I/O --   no Off
K12 382 4 #altera_reserved_tck input LVTTL   -- Off N no Off
K13 389 4 GND+       Column I/O --   -- --
K14 394 9 RESERVED_INPUT       Column I/O --   no Off
K15 395 9 RESERVED_INPUT       Column I/O --   no Off
K16 400 10 RESERVED_INPUT       Column I/O --   no Off
K17 406 3 PLD_CLOCKINPUT input LVTTL   Column I/O Off Y no Off
K18 412 3 ext_ram_bus_data[5] bidir LVTTL   Column I/O Off Y no Off
K19 415 3 select_n_to_the_ext_flash output LVTTL   Column I/O Off Y no Off
K20 37   GND gnd     -- --   no Off
K21 2 2 RESERVED_INPUT       Row I/O --   no Off
K22 3 2 RESERVED_INPUT       Row I/O --   no Off
K23     NC       -- --   -- --
K24     NC       -- --   -- --
K25 22 2 RESERVED_INPUT       Row I/O --   no Off
K26 21 2 RESERVED_INPUT       Row I/O --   no Off
K27 25 2 RESERVED_INPUT       Row I/O --   no Off
K28 26 2 RESERVED_INPUT       Row I/O --   no Off
L1 295 5 RESERVED_INPUT       Row I/O --   no Off
L2 296 5 RESERVED_INPUT       Row I/O --   no Off
L3 299 5 RESERVED_INPUT       Row I/O --   no Off
L4 300 5 RESERVED_INPUT       Row I/O --   no Off
L5 318 5 LCD_data_to_and_from_the_lcd_display[6] bidir LVTTL   Row I/O Off Y no Off
L6 319 5 LCD_data_to_and_from_the_lcd_display[5] bidir LVTTL   Row I/O Off Y no Off
L7 323 5 LCD_data_to_and_from_the_lcd_display[1] bidir LVTTL   Row I/O Off Y no Off
L8 322 5 LCD_data_to_and_from_the_lcd_display[2] bidir LVTTL   Row I/O Off Y no Off
L9 314 5 RESERVED_INPUT       Row I/O --   no Off
L10 313 5 RESERVED_INPUT       Row I/O --   no Off
L11 340 4 ext_ram_bus_data[30] bidir LVTTL   Column I/O Off Y no Off
L12 381 4 #altera_reserved_ntrst input LVTTL   -- Off N no Off
L13 390 4 ext_ram_bus_data[28] bidir LVTTL   Column I/O Off Y no Off
L14     GND gnd     -- --   -- --
L15     GND gnd     -- --   -- --
L16 403 3 ^nCONFIG       -- --   -- --
L17 409 3 be_n_to_the_ext_ram[3] output LVTTL   Column I/O Off Y no Off
L18 448 3 RESERVED_INPUT       Column I/O --   no Off
L19 16 2 out_port_from_the_led_pio[7] output LVTTL   Row I/O Off Y no Off
L20 15 2 out_port_from_the_led_pio[6] output LVTTL   Row I/O Off Y no Off
L21 7 2 RESERVED_INPUT       Row I/O --   no Off
L22 6 2 RESERVED_INPUT       Row I/O --   no Off
L23 10 2 out_port_from_the_led_pio[2] output LVTTL   Row I/O Off Y no Off
L24 11 2 out_port_from_the_led_pio[3] output LVTTL   Row I/O Off Y no Off
L25 29 2 RESERVED_INPUT       Row I/O --   no Off
L26 30 2 RESERVED_INPUT       Row I/O --   no Off
L27 33 2 RESERVED_INPUT       Row I/O --   no Off
L28 34 2 RESERVED_INPUT       Row I/O --   no Off
M1   5 VCCIO5 power   3.3V -- --   -- --
M2 286 5 RESERVED_INPUT       Row I/O --   no Off
M3 290 5 RESERVED_INPUT       Row I/O --   no Off
M4 291 5 RESERVED_INPUT       Row I/O --   no Off
M5 306 5 RESERVED_INPUT       Row I/O --   no Off
M6 305 5 RESERVED_INPUT       Row I/O --   no Off
M7 310 5 LCD_RS_from_the_lcd_display output LVTTL   Row I/O Off Y no Off
M8 309 5 LCD_RW_from_the_lcd_display output LVTTL   Row I/O Off Y no Off
M9 302 5 RESERVED_INPUT       Row I/O --   no Off
M10 301 5 RESERVED_INPUT       Row I/O --   no Off
M11 341 4 ext_ram_bus_data[29] bidir LVTTL   Column I/O Off Y no Off
M12 383 4 ext_ram_bus_data[3] bidir LVTTL   Column I/O Off Y no Off
M13 391 4 GND+       Column I/O --   -- --
M14     VCCINT power   1.5V -- --   -- --
M15     GND gnd     -- --   -- --
M16 402 3 ^nSTATUS       -- --   -- --
M17 408 3 GND+       Column I/O --   -- --
M18 449 3 be_n_to_the_ext_ram[0] output LVTTL   Column I/O Off Y no Off
M19 28 2 RESERVED_INPUT       Row I/O --   no Off
M20 27 2 RESERVED_INPUT       Row I/O --   no Off
M21 20 2 RESERVED_INPUT       Row I/O --   no Off
M22 19 2 RESERVED_INPUT       Row I/O --   no Off
M23 24 2 RESERVED_INPUT       Row I/O --   no Off
M24 23 2 RESERVED_INPUT       Row I/O --   no Off
M25 38 2 RESERVED_INPUT       Row I/O --   no Off
M26 39 2 RESERVED_INPUT       Row I/O --   no Off
M27 42 2 RESERVED_INPUT       Row I/O --   no Off
M28   2 VCCIO2 power   3.3V -- --   -- --
N1 287 5 RESERVED_INPUT       Row I/O --   no Off
N2 283 5 GND+       Row I/O --   -- --
N3 298 5 RESERVED_INPUT       Row I/O --   no Off
N4 297 5 RESERVED_INPUT       Row I/O --   no Off
N5 288 5 RESERVED_INPUT       Row I/O --   no Off
N6 289 5 RESERVED_INPUT       Row I/O --   no Off
N7 293 5 RESERVED_INPUT       Row I/O --   no Off
N8 294 5 RESERVED_INPUT       Row I/O --   no Off
N9 285 5 RESERVED_INPUT       Row I/O --   no Off
N10 284 5 RESERVED_INPUT       Row I/O --   no Off
N11     VCCINT power   1.5V -- --   -- --
N12     GND gnd     -- --   -- --
N13     VCCINT power   1.5V -- --   -- --
N14     GND gnd     -- --   -- --
N15     VCCINT power   1.5V -- --   -- --
N16     GND gnd     -- --   -- --
N17     VCCINT power   1.5V -- --   -- --
N18     GND gnd     -- --   -- --
N19 45 2 RESERVED_INPUT       Row I/O --   no Off
N20 44 2 RESERVED_INPUT       Row I/O --   no Off
N21 41 2 RESERVED_INPUT       Row I/O --   no Off
N22 40 2 RESERVED_INPUT       Row I/O --   no Off
N23 36 2 RESERVED_INPUT       Row I/O --   no Off
N24 35 2 RESERVED_INPUT       Row I/O --   no Off
N25 32 2 RESERVED_INPUT       Row I/O --   no Off
N26 31 2 RESERVED_INPUT       Row I/O --   no Off
N27 46 2 GND+       Row I/O --   -- --
N28 43 2 RESERVED_INPUT       Row I/O --   no Off
P1     GND gnd     -- --   -- --
P2 282 5 GND+       Row I/O --   -- --
P3 281 5 RESERVED_INPUT       Row I/O --   no Off
P4 280 5 GND+       Row I/O --   -- --
P5     GNDA_PLL4 gnd     -- --   -- --
P6     VCCA_PLL4 power   1.5V -- --   -- --
P7     GNDG_PLL4 gnd     -- --   -- --
P8     VCCG_PLL4 power   1.5V -- --   -- --
P9   5 VCCIO5 power   3.3V -- --   -- --
P10 292   GND gnd     -- --   no Off
P11     GND gnd     -- --   -- --
P12     VCCINT power   1.5V -- --   -- --
P13     GND gnd     -- --   -- --
P14     VCCINT power   1.5V -- --   -- --
P15     GND gnd     -- --   -- --
P16     VCCINT power   1.5V -- --   -- --
P17     GND gnd     -- --   -- --
P18     GND gnd     -- --   -- --
P19     NC       -- --   -- --
P20   2 VCCIO2 power   3.3V -- --   -- --
P21     VCCG_PLL1 power   1.5V -- --   -- --
P22     GNDG_PLL1 gnd     -- --   -- --
P23     VCCA_PLL1 power   1.5V -- --   -- --
P24     GNDA_PLL1 gnd     -- --   -- --
P25 49 2 GND+       Row I/O --   -- --
P26 48 2 RESERVED_INPUT       Row I/O --   no Off
P27 47 2 GND+       Row I/O --   -- --
P28     GND gnd     -- --   -- --
R1     GND gnd     -- --   -- --
R2 279 6 GND+       Row I/O --   -- --
R3 276 6 RESERVED_INPUT       Row I/O --   no Off
R4 277 6 GND+       Row I/O --   -- --
R5     GNDA_PLL3 gnd     -- --   -- --
R6     VCCA_PLL3 power   1.5V -- --   -- --
R7     GNDG_PLL3 gnd     -- --   -- --
R8     VCCG_PLL3 power   1.5V -- --   -- --
R9   6 VCCIO6 power   3.3V -- --   -- --
R10     NC       -- --   -- --
R11     GND gnd     -- --   -- --
R12     GND gnd     -- --   -- --
R13     VCCINT power   1.5V -- --   -- --
R14     GND gnd     -- --   -- --
R15     VCCINT power   1.5V -- --   -- --
R16     GND gnd     -- --   -- --
R17     VCCINT power   1.5V -- --   -- --
R18     GND gnd     -- --   -- --
R19 62   GND gnd     -- --   no Off
R20   1 VCCIO1 power   3.3V -- --   -- --
R21     VCCG_PLL2 power   1.5V -- --   -- --
R22     GNDG_PLL2 gnd     -- --   -- --
R23     VCCA_PLL2 power   1.5V -- --   -- --
R24     GNDA_PLL2 gnd     -- --   -- --
R25 52 1 GND+       Row I/O --   -- --
R26 53 1 RESERVED_INPUT       Row I/O --   no Off
R27 50 1 GND+       Row I/O --   -- --
R28     GND gnd     -- --   -- --
T1 275 6 RESERVED_INPUT       Row I/O --   no Off
T2 278 6 GND+       Row I/O --   -- --
T3 273 6 RESERVED_INPUT       Row I/O --   no Off
T4 272 6 RESERVED_INPUT       Row I/O --   no Off
T5 260 6 RESERVED_INPUT       Row I/O --   no Off
T6 259 6 RESERVED_INPUT       Row I/O --   no Off
T7 268 6 RESERVED_INPUT       Row I/O --   no Off
T8 269 6 RESERVED_INPUT       Row I/O --   no Off
T9 264 6 RESERVED_INPUT       Row I/O --   no Off
T10 263 6 RESERVED_INPUT       Row I/O --   no Off
T11     GND gnd     -- --   -- --
T12     VCCINT power   1.5V -- --   -- --
T13     GND gnd     -- --   -- --
T14     VCCINT power   1.5V -- --   -- --
T15     GND gnd     -- --   -- --
T16     VCCINT power   1.5V -- --   -- --
T17     GND gnd     -- --   -- --
T18     VCCINT power   1.5V -- --   -- --
T19 60 1 byteenablen_to_the_lan91c111[3] output LVTTL   Row I/O Off Y no Off
T20 61 1 RESERVED_INPUT       Row I/O --   no Off
T21 56 1 RESERVED_INPUT       Row I/O --   no Off
T22 57 1 byteenablen_to_the_lan91c111[0] output LVTTL   Row I/O Off Y no Off
T23 65 1 ior_n_to_the_lan91c111 output LVTTL   Row I/O Off Y no Off
T24 66 1 iow_n_to_the_lan91c111 output LVTTL   Row I/O Off Y no Off
T25 70 1 RESERVED_INPUT       Row I/O --   no Off
T26 69 1 RESERVED_INPUT       Row I/O --   no Off
T27 51 1 GND+       Row I/O --   -- --
T28 54 1 RESERVED_INPUT       Row I/O --   no Off
U1   6 VCCIO6 power   3.3V -- --   -- --
U2 274 6 bidir_port_to_and_from_the_reconfig_request_pio bidir LVTTL   Row I/O Off Y no Off
U3 271 6 RESERVED_INPUT       Row I/O --   no Off
U4 270 6 RESERVED_INPUT       Row I/O --   no Off
U5 252 6 RESERVED_INPUT       Row I/O --   no Off
U6 251 6 RESERVED_INPUT       Row I/O --   no Off
U7 247 6 RESERVED_INPUT       Row I/O --   no Off
U8 248 6 RESERVED_INPUT       Row I/O --   no Off
U9 255 6 RESERVED_INPUT       Row I/O --   no Off
U10 256 6 RESERVED_INPUT       Row I/O --   no Off
U11     VCCINT power   1.5V -- --   -- --
U12     GND gnd     -- --   -- --
U13     VCCINT power   1.5V -- --   -- --
U14     GND gnd     -- --   -- --
U15     VCCINT power   1.5V -- --   -- --
U16     GND gnd     -- --   -- --
U17     VCCINT power   1.5V -- --   -- --
U18     GND gnd     -- --   -- --
U19 73 1 RESERVED_INPUT       Row I/O --   no Off
U20 74 1 RESERVED_INPUT       Row I/O --   no Off
U21 81 1 txd_from_the_uart1 output LVTTL   Row I/O Off Y no Off
U22 82 1 RESERVED_INPUT       Row I/O --   no Off
U23 78 1 RESERVED_INPUT       Row I/O --   no Off
U24 77 1 RESERVED_INPUT       Row I/O --   no Off
U25 59 1 byteenablen_to_the_lan91c111[2] output LVTTL   Row I/O Off Y no Off
U26 58 1 byteenablen_to_the_lan91c111[1] output LVTTL   Row I/O Off Y no Off
U27 55 1 RESERVED_INPUT       Row I/O --   no Off
U28   1 VCCIO1 power   3.3V -- --   -- --
V1 265 6 RESERVED_INPUT       Row I/O --   no Off
V2 266 6 RESERVED_INPUT       Row I/O --   no Off
V3 262 6 RESERVED_INPUT       Row I/O --   no Off
V4 261 6 RESERVED_INPUT       Row I/O --   no Off
V5 239 6 RESERVED_INPUT       Row I/O --   no Off
V6 238 6 RESERVED_INPUT       Row I/O --   no Off
V7 235 6 RESERVED_INPUT       Row I/O --   no Off
V8 234 6 RESERVED_INPUT       Row I/O --   no Off
V9 243 6 RESERVED_INPUT       Row I/O --   no Off
V10 244 6 RESERVED_INPUT       Row I/O --   no Off
V11 218 7 zs_addr_from_the_sdram[9] output LVTTL   Column I/O Off Y no Off
V12     VCCINT power   1.5V -- --   -- --
V13     GND gnd     -- --   -- --
V14     GND gnd     -- --   -- --
V15     GND gnd     -- --   -- --
V16     VCCINT power   1.5V -- --   -- --
V17     GND gnd     -- --   -- --
V18 128 8 RESERVED_INPUT       Column I/O --   no Off
V19 85 1 RESERVED_INPUT       Row I/O --   no Off
V20 86 1 RESERVED_INPUT       Row I/O --   no Off
V21 95 1 RESERVED_INPUT       Row I/O --   no Off
V22 94 1 RESERVED_INPUT       Row I/O --   no Off
V23 91 1 RESERVED_INPUT       Row I/O --   no Off
V24 90 1 RESERVED_INPUT       Row I/O --   no Off
V25 68 1 ENET_ADS_N output LVTTL   Row I/O Off Y no Off
V26 67 1 RESERVED_INPUT       Row I/O --   no Off
V27 63 1 irq_from_the_lan91c111 input LVTTL   Row I/O Off Y no Off
V28 64 1 ENET_AEN output LVTTL   Row I/O Off Y no Off
W1 258 6 RESERVED_INPUT       Row I/O --   no Off
W2 257 6 RESERVED_INPUT       Row I/O --   no Off
W3 254 6 RESERVED_INPUT       Row I/O --   no Off
W4 253 6 RESERVED_INPUT       Row I/O --   no Off
W5 230 6 in_port_to_the_button_pio[0] input LVTTL   Row I/O Off Y no Off
W6 231 6 in_port_to_the_button_pio[1] input LVTTL   Row I/O Off Y no Off
W7     NC       -- --   -- --
W8     NC       -- --   -- --
W9 267   GND gnd     -- --   no Off
W10 182 7 zs_addr_from_the_sdram[3] output LVTTL   Column I/O Off Y no Off
W11 180 7 RESERVED_INPUT       Column I/O --   no Off
W12 176 7 zs_addr_from_the_sdram[1] output LVTTL   Column I/O Off Y no Off
W13 168 7 GND+       Column I/O --   -- --
W14 165 11 RESERVED_INPUT       Column I/O --   no Off
W15 164 11 RESERVED_INPUT       Column I/O --   no Off
W16 159 12 RESERVED_INPUT       Column I/O --   no Off
W17 156 8 ^MSEL1       -- --   -- --
W18 145 8 RESERVED_INPUT       Column I/O --   no Off
W19 144 8 RESERVED_INPUT       Column I/O --   no Off
W20 87   GND gnd     -- --   no Off
W21     NC       -- --   -- --
W22     NC       -- --   -- --
W23 98 1 RESERVED_INPUT       Row I/O --   no Off
W24 99 1 RESERVED_INPUT       Row I/O --   no Off
W25 76 1 RESERVED_INPUT       Row I/O --   no Off
W26 75 1 RESERVED_INPUT       Row I/O --   no Off
W27 72 1 RESERVED_INPUT       Row I/O --   no Off
W28 71 1 RESERVED_INPUT       Row I/O --   no Off
Y1 250 6 RESERVED_INPUT       Row I/O --   no Off
Y2 249 6 RESERVED_INPUT       Row I/O --   no Off
Y3 246 6 RESERVED_INPUT       Row I/O --   no Off
Y4 245 6 RESERVED_INPUT       Row I/O --   no Off
Y5     NC       -- --   -- --
Y6     NC       -- --   -- --
Y7     NC       -- --   -- --
Y8     NC       -- --   -- --
Y9 174 7 RESERVED_INPUT       Column I/O --   no Off
Y10     NC       -- --   -- --
Y11 219 7 zs_addr_from_the_sdram[10] output LVTTL   Column I/O Off Y no Off
Y12 177 7 ^nIO_PULLUP       -- --   -- --
Y13 169 7 zs_dqm_from_the_sdram[1] output LVTTL   Column I/O Off Y no Off
Y14   7 VCCIO7 power   3.3V -- --   -- --
Y15   8 VCCIO8 power   3.3V -- --   -- --
Y16 158 12 RESERVED_INPUT       Column I/O --   no Off
Y17 150 8 RESERVED_INPUT       Column I/O --   no Off
Y18 147 8 RESERVED_INPUT       Column I/O --   no Off
Y19 143 8 RESERVED_INPUT       Column I/O --   no Off
Y20     NC       -- --   -- --
Y21     NC       -- --   -- --
Y22     NC       -- --   -- --
Y23     NC       -- --   -- --
Y24     NC       -- --   -- --
Y25 84 1 RESERVED_INPUT       Row I/O --   no Off
Y26 83 1 RESERVED_INPUT       Row I/O --   no Off
Y27 80 1 RESERVED_INPUT       Row I/O --   no Off
Y28 79 1 rxd_to_the_uart1 input LVTTL   Row I/O Off Y no Off


PLL Summary

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Name std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|pll
PLL type Enhanced
Scan chain None
PLL mode Normal
Feedback source --
Compensate clock clock0
Switchover on loss of clock --
Switchover counter --
Primary clock inclk0
Input frequency 0 50.0 MHz
Input frequency 1 --
Nominal PFD frequency 50.0 MHz
Nominal VCO frequency 500.0 MHz
Freq min lock 29.99 MHz
Freq max lock 80.0 MHz
Clock Offset 0 ps
M VCO Tap 6
M Initial 2
M value 10
N value 1
M counter delay 0 ps
N counter delay 0 ps
M2 value --
N2 value --
SS counter --
Downspread --
Spread frequency --
Charge pump current 50 uA
Loop filter resistance 1.021000 KOhm
Loop filter capacitance 10 pF
Freq zero 0.240 MHz
Bandwidth 1 MHz
Freq pole 15.844 MHz
enable0 counter --
enable1 counter --
Real time reconfigurable Off
Scan chain MIF file --
Preserve counter order Off
PLL location PLL_5
Inclk0 signal PLD_CLOCKINPUT
Inclk1 signal --
Inclk0 signal type Dedicated Pin
Inclk1 signal type --


PLL Usage

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Name Output Clock Mult Div Output Frequency Phase Shift Delay Duty Cycle Counter Counter Delay Counter Value High / Low Initial VCO Tap
std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0 clock0 1 1 50.0 MHz 0 (0 ps) 0 ps 50/50 G3 0 ps 10 5/5 Even 2 6
std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_extclk0 extclock0 1 1 50.0 MHz -63 (-3499 ps) 0 ps 50/50 E0 0 ps 10 5/5 Even 1 0


Output Pin Default Load For Reported TCO

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I/O Standard Load Termination Resistance
LVTTL 10 pF Not Available
LVCMOS 10 pF Not Available
2.5 V 10 pF Not Available
1.8 V 10 pF Not Available
1.5 V 10 pF Not Available
GTL 30 pF 25 Ohm (Parallel)
GTL+ 30 pF 25 Ohm (Parallel)
3.3-V PCI 10 pF 25 Ohm (Parallel)
3.3-V PCI-X 8 pF 25 Ohm (Parallel)
Compact PCI 10 pF 25 Ohm (Parallel)
AGP 1X 10 pF Not Available
AGP 2X 10 pF Not Available
CTT 30 pF 50 Ohm (Parallel)
SSTL-3 Class I 30 pF 50 Ohm (Parallel), 25 Ohm (Serial)
SSTL-3 Class II 30 pF 25 Ohm (Parallel), 25 Ohm (Serial)
SSTL-2 Class I 30 pF 50 Ohm (Parallel), 25 Ohm (Serial)
SSTL-2 Class II 30 pF 25 Ohm (Parallel), 25 Ohm (Serial)
SSTL-18 Class I 30 pF 50 Ohm (Parallel), 25 Ohm (Serial)
SSTL-18 Class II 30 pF 25 Ohm (Parallel), 25 Ohm (Serial)
1.5-V HSTL Class I 20 pF 50 Ohm (Parallel)
1.5-V HSTL Class II 20 pF 25 Ohm (Parallel)
1.8-V HSTL Class I 20 pF 50 Ohm (Parallel)
1.8-V HSTL Class II 20 pF 25 Ohm (Parallel)
LVDS 4 pF 100 Ohm (Differential)
Differential LVPECL 4 pF 100 Ohm (Differential)
3.3-V PCML 4 pF 50 Ohm (Parallel)
HyperTransport 4 pF 100 Ohm (Differential)
Differential 1.5-V HSTL Class I 20 pF (See 1.5-V HSTL Class I)
Differential 1.8-V HSTL Class I 20 pF (See 1.8-V HSTL Class I)
Differential 1.8-V HSTL Class II 20 pF (See 1.8-V HSTL Class II)
Differential SSTL-2 30 pF (See SSTL-2)
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.


Fitter Resource Utilization by Entity

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Compilation Hierarchy Node Logic Cells LC Registers Memory Bits M512s M4Ks M-RAMs DSP Elements DSP 9x9 DSP 18x18 DSP 36x36 Pins Virtual Pins LUT-Only LCs Register-Only LCs LUT/Register LCs Carry Chain LCs Packed LCs Full Hierarchy Name
|standard 4013 (2) 2042 571136 2 13 1 8 0 0 1 179 0 1971 (2) 286 (0) 1756 (0) 305 (0) 344 (0) |standard
   |sld_hub:sld_hub_inst| 106 (26) 68 0 0 0 0 0 0 0 0 0 0 38 (19) 9 (0) 59 (7) 5 (0) 2 (2) |standard|sld_hub:sld_hub_inst
      |lpm_decode:instruction_decoder| 5 (0) 5 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 5 (0) 0 (0) 0 (0) |standard|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder
         |decode_lhi:auto_generated| 5 (5) 5 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 5 (5) 0 (0) 0 (0) |standard|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_lhi:auto_generated
      |lpm_shiftreg:jtag_ir_register| 10 (10) 10 0 0 0 0 0 0 0 0 0 0 0 (0) 7 (7) 3 (3) 0 (0) 0 (0) |standard|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register
      |sld_dffex:BROADCAST| 1 (1) 1 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 1 (1) 0 (0) 0 (0) |standard|sld_hub:sld_hub_inst|sld_dffex:BROADCAST
      |sld_dffex:IRF_ENA_0| 1 (1) 1 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 1 (1) 0 (0) 0 (0) |standard|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0
      |sld_dffex:IRF_ENA| 2 (2) 2 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 2 (2) 0 (0) 0 (0) |standard|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA
      |sld_dffex:IRSR| 9 (9) 7 0 0 0 0 0 0 0 0 0 0 2 (2) 0 (0) 7 (7) 0 (0) 0 (0) |standard|sld_hub:sld_hub_inst|sld_dffex:IRSR
      |sld_dffex:RESET| 1 (1) 1 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 1 (1) 0 (0) 0 (0) |standard|sld_hub:sld_hub_inst|sld_dffex:RESET
      |sld_dffex:\GEN_IRF:1:IRF| 2 (2) 2 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 2 (2) 0 (0) 0 (0) |standard|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF
      |sld_dffex:\GEN_IRF:2:IRF| 2 (2) 1 0 0 0 0 0 0 0 0 0 0 1 (1) 0 (0) 1 (1) 0 (0) 0 (0) |standard|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF
      |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF| 2 (2) 2 0 0 0 0 0 0 0 0 0 0 0 (0) 2 (2) 0 (0) 0 (0) 0 (0) |standard|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF
      |sld_dffex:\GEN_SHADOW_IRF:2:S_IRF| 1 (1) 1 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 1 (1) 0 (0) 0 (0) |standard|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF
      |sld_jtag_state_machine:jtag_state_machine| 20 (20) 19 0 0 0 0 0 0 0 0 0 0 1 (1) 0 (0) 19 (19) 0 (0) 0 (0) |standard|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine
      |sld_rom_sr:HUB_INFO_REG| 24 (24) 9 0 0 0 0 0 0 0 0 0 0 15 (15) 0 (0) 9 (9) 5 (5) 0 (0) |standard|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
   |std_1s10:inst| 3905 (1) 1974 571136 2 13 1 8 0 0 1 0 0 1931 (1) 277 (0) 1697 (0) 300 (0) 342 (0) |standard|std_1s10:inst
      |button_pio:the_button_pio| 23 (23) 20 0 0 0 0 0 0 0 0 0 0 3 (3) 8 (8) 12 (12) 0 (0) 4 (4) |standard|std_1s10:inst|button_pio:the_button_pio
      |button_pio_s1_arbitrator:the_button_pio_s1| 1 (1) 0 0 0 0 0 0 0 0 0 0 0 1 (1) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|button_pio_s1_arbitrator:the_button_pio_s1
      |clock_0:the_clock_0| 101 (71) 92 0 0 0 0 0 0 0 0 0 0 9 (1) 42 (37) 50 (33) 0 (0) 6 (0) |standard|std_1s10:inst|clock_0:the_clock_0
         |clock_0_edge_to_pulse:read_done_edge_to_pulse| 1 (1) 1 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 1 (1) 0 (0) 0 (0) |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse
         |clock_0_edge_to_pulse:read_request_edge_to_pulse| 1 (1) 1 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 1 (1) 0 (0) 0 (0) |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_request_edge_to_pulse
         |clock_0_edge_to_pulse:write_done_edge_to_pulse| 1 (1) 1 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 1 (1) 0 (0) 0 (0) |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_done_edge_to_pulse
         |clock_0_edge_to_pulse:write_request_edge_to_pulse| 1 (1) 1 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 1 (1) 0 (0) 0 (0) |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:write_request_edge_to_pulse
         |clock_0_master_FSM:master_FSM| 8 (8) 5 0 0 0 0 0 0 0 0 0 0 3 (3) 0 (0) 5 (5) 0 (0) 3 (3) |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_master_FSM:master_FSM
         |clock_0_master_read_done_sync_module:clock_0_master_read_done_sync| 2 (2) 2 0 0 0 0 0 0 0 0 0 0 0 (0) 1 (1) 1 (1) 0 (0) 0 (0) |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync
         |clock_0_master_write_done_sync_module:clock_0_master_write_done_sync| 2 (2) 2 0 0 0 0 0 0 0 0 0 0 0 (0) 1 (1) 1 (1) 0 (0) 0 (0) |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync
         |clock_0_slave_FSM:slave_FSM| 10 (10) 5 0 0 0 0 0 0 0 0 0 0 5 (5) 0 (0) 5 (5) 0 (0) 3 (3) |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM
         |clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync| 2 (2) 2 0 0 0 0 0 0 0 0 0 0 0 (0) 1 (1) 1 (1) 0 (0) 0 (0) |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync
         |clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync| 2 (2) 2 0 0 0 0 0 0 0 0 0 0 0 (0) 2 (2) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync
      |clock_0_in_arbitrator:the_clock_0_in| 3 (3) 0 0 0 0 0 0 0 0 0 0 0 3 (3) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|clock_0_in_arbitrator:the_clock_0_in
      |cpu:the_cpu| 1633 (1220) 882 45824 0 13 0 8 0 0 1 0 0 751 (518) 92 (54) 790 (648) 125 (50) 72 (64) |standard|std_1s10:inst|cpu:the_cpu
         |cpu_ic_data_module:cpu_ic_data| 0 (0) 0 32768 0 8 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data
            |altsyncram:the_altsyncram| 0 (0) 0 32768 0 8 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram
               |altsyncram_nnb1:auto_generated| 0 (0) 0 32768 0 8 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated
         |cpu_ic_tag_module:cpu_ic_tag| 0 (0) 0 2816 0 1 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag
            |altsyncram:the_altsyncram| 0 (0) 0 2816 0 1 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram
               |altsyncram_t9e1:auto_generated| 0 (0) 0 2816 0 1 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated
         |cpu_mult_cell:the_cpu_mult_cell| 2 (0) 0 0 0 0 0 8 0 0 1 0 0 2 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell
            |altmult_add:the_altmult_add| 2 (0) 0 0 0 0 0 8 0 0 1 0 0 2 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add
               |mult_add_1f72:auto_generated| 2 (2) 0 0 0 0 0 8 0 0 1 0 0 2 (2) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated
         |cpu_nios2_oci:the_cpu_nios2_oci| 345 (35) 180 8192 0 2 0 0 0 0 0 0 0 165 (35) 38 (0) 142 (0) 9 (0) 8 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci
            |cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper| 183 (0) 90 0 0 0 0 0 0 0 0 0 0 93 (0) 38 (0) 52 (0) 0 (0) 4 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper
               |cpu_jtag_debug_module:the_cpu_jtag_debug_module1| 183 (183) 90 0 0 0 0 0 0 0 0 0 0 93 (93) 38 (38) 52 (52) 0 (0) 4 (4) |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1
            |cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg| 12 (12) 7 0 0 0 0 0 0 0 0 0 0 5 (5) 0 (0) 7 (7) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg
            |cpu_nios2_oci_break:the_cpu_nios2_oci_break| 32 (32) 32 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 32 (32) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_break:the_cpu_nios2_oci_break
            |cpu_nios2_oci_debug:the_cpu_nios2_oci_debug| 10 (10) 7 0 0 0 0 0 0 0 0 0 0 3 (3) 0 (0) 7 (7) 0 (0) 2 (2) |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug
            |cpu_nios2_ocimem:the_cpu_nios2_ocimem| 73 (73) 44 8192 0 2 0 0 0 0 0 0 0 29 (29) 0 (0) 44 (44) 9 (9) 2 (2) |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem
               |cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component| 0 (0) 0 8192 0 2 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component
                  |altsyncram:the_altsyncram| 0 (0) 0 8192 0 2 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
                     |altsyncram_8q62:auto_generated| 0 (0) 0 8192 0 2 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated
         |cpu_register_bank_a_module:cpu_register_bank_a| 0 (0) 0 1024 0 1 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a
            |altsyncram:the_altsyncram| 0 (0) 0 1024 0 1 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram
               |altsyncram_00e1:auto_generated| 0 (0) 0 1024 0 1 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated
         |cpu_register_bank_b_module:cpu_register_bank_b| 0 (0) 0 1024 0 1 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b
            |altsyncram:the_altsyncram| 0 (0) 0 1024 0 1 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram
               |altsyncram_10e1:auto_generated| 0 (0) 0 1024 0 1 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated
         |cpu_test_bench:the_cpu_test_bench| 33 (33) 0 0 0 0 0 0 0 0 0 0 0 33 (33) 0 (0) 0 (0) 33 (33) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench
         |lpm_add_sub:Add8| 33 (0) 0 0 0 0 0 0 0 0 0 0 0 33 (0) 0 (0) 0 (0) 33 (0) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8
            |alt_stratix_add_sub:stratix_adder| 33 (33) 0 0 0 0 0 0 0 0 0 0 0 33 (33) 0 (0) 0 (0) 33 (33) 0 (0) |standard|std_1s10:inst|cpu:the_cpu|lpm_add_sub:Add8|alt_stratix_add_sub:stratix_adder
      |cpu_data_master_arbitrator:the_cpu_data_master| 299 (299) 60 0 0 0 0 0 0 0 0 0 0 239 (239) 0 (0) 60 (60) 0 (0) 43 (43) |standard|std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master
      |cpu_instruction_master_arbitrator:the_cpu_instruction_master| 130 (130) 31 0 0 0 0 0 0 0 0 0 0 99 (99) 0 (0) 31 (31) 0 (0) 27 (27) |standard|std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master
      |cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module| 26 (26) 4 0 0 0 0 0 0 0 0 0 0 22 (22) 0 (0) 4 (4) 0 (0) 9 (9) |standard|std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module
      |ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave| 208 (208) 45 0 0 0 0 0 0 0 0 0 0 163 (163) 2 (2) 43 (43) 12 (12) 21 (21) |standard|std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave
      |high_res_timer:the_high_res_timer| 141 (141) 120 0 0 0 0 0 0 0 0 0 0 21 (21) 18 (18) 102 (102) 32 (32) 32 (32) |standard|std_1s10:inst|high_res_timer:the_high_res_timer
      |high_res_timer_s1_arbitrator:the_high_res_timer_s1| 2 (2) 0 0 0 0 0 0 0 0 0 0 0 2 (2) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|high_res_timer_s1_arbitrator:the_high_res_timer_s1
      |jtag_uart:the_jtag_uart| 166 (47) 106 1024 2 0 0 0 0 0 0 0 0 60 (34) 13 (0) 93 (13) 51 (15) 12 (2) |standard|std_1s10:inst|jtag_uart:the_jtag_uart
         |alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic| 68 (68) 53 0 0 0 0 0 0 0 0 0 0 15 (15) 13 (13) 40 (40) 0 (0) 10 (10) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic
         |jtag_uart_scfifo_r:the_jtag_uart_scfifo_r| 26 (0) 20 512 1 0 0 0 0 0 0 0 0 6 (0) 0 (0) 20 (0) 18 (0) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r
            |scfifo:rfifo| 26 (0) 20 512 1 0 0 0 0 0 0 0 0 6 (0) 0 (0) 20 (0) 18 (0) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo
               |scfifo_gg21:auto_generated| 26 (0) 20 512 1 0 0 0 0 0 0 0 0 6 (0) 0 (0) 20 (0) 18 (0) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated
                  |a_dpfifo_jm21:dpfifo| 26 (0) 20 512 1 0 0 0 0 0 0 0 0 6 (0) 0 (0) 20 (0) 18 (0) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo
                     |a_fefifo_7cf:fifo_state| 14 (8) 8 0 0 0 0 0 0 0 0 0 0 6 (6) 0 (0) 8 (2) 6 (0) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state
                        |cntr_bd7:count_usedw| 6 (6) 6 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 6 (6) 6 (6) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw
                     |cntr_te8:rd_ptr_count| 6 (6) 6 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 6 (6) 6 (6) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count
                     |cntr_te8:wr_ptr| 6 (6) 6 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 6 (6) 6 (6) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr
                     |dpram_ga21:FIFOram| 0 (0) 0 512 1 0 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram
                        |altsyncram_kml1:altsyncram1| 0 (0) 0 512 1 0 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1
         |jtag_uart_scfifo_w:the_jtag_uart_scfifo_w| 25 (0) 20 512 1 0 0 0 0 0 0 0 0 5 (0) 0 (0) 20 (0) 18 (0) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w
            |scfifo:wfifo| 25 (0) 20 512 1 0 0 0 0 0 0 0 0 5 (0) 0 (0) 20 (0) 18 (0) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo
               |scfifo_gg21:auto_generated| 25 (0) 20 512 1 0 0 0 0 0 0 0 0 5 (0) 0 (0) 20 (0) 18 (0) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated
                  |a_dpfifo_jm21:dpfifo| 25 (0) 20 512 1 0 0 0 0 0 0 0 0 5 (0) 0 (0) 20 (0) 18 (0) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo
                     |a_fefifo_7cf:fifo_state| 13 (7) 8 0 0 0 0 0 0 0 0 0 0 5 (5) 0 (0) 8 (2) 6 (0) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state
                        |cntr_bd7:count_usedw| 6 (6) 6 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 6 (6) 6 (6) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|cntr_bd7:count_usedw
                     |cntr_te8:rd_ptr_count| 6 (6) 6 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 6 (6) 6 (6) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:rd_ptr_count
                     |cntr_te8:wr_ptr| 6 (6) 6 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 6 (6) 6 (6) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|cntr_te8:wr_ptr
                     |dpram_ga21:FIFOram| 0 (0) 0 512 1 0 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram
                        |altsyncram_kml1:altsyncram1| 0 (0) 0 512 1 0 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1
      |jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave| 2 (2) 0 0 0 0 0 0 0 0 0 0 0 2 (2) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave
      |lcd_display:the_lcd_display| 5 (5) 0 0 0 0 0 0 0 0 0 0 0 5 (5) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|lcd_display:the_lcd_display
      |lcd_display_control_slave_arbitrator:the_lcd_display_control_slave| 24 (24) 7 0 0 0 0 0 0 0 0 0 0 17 (17) 0 (0) 7 (7) 6 (6) 0 (0) |standard|std_1s10:inst|lcd_display_control_slave_arbitrator:the_lcd_display_control_slave
      |led_pio:the_led_pio| 12 (12) 8 0 0 0 0 0 0 0 0 0 0 4 (4) 8 (8) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|led_pio:the_led_pio
      |onchip_ram_64_kbytes:the_onchip_ram_64_kbytes| 1 (1) 0 524288 0 0 1 0 0 0 0 0 0 1 (1) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes
         |altsyncram:the_altsyncram| 0 (0) 0 524288 0 0 1 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram
            |altsyncram_7b71:auto_generated| 0 (0) 0 524288 0 0 1 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated
      |onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1| 32 (32) 3 0 0 0 0 0 0 0 0 0 0 29 (29) 0 (0) 3 (3) 0 (0) 3 (3) |standard|std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1
      |pll:the_pll| 25 (25) 24 0 0 0 0 0 0 0 0 0 0 1 (1) 15 (15) 9 (9) 5 (5) 1 (1) |standard|std_1s10:inst|pll:the_pll
         |altpllpll:the_pll| 0 (0) 0 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|pll:the_pll|altpllpll:the_pll
            |altpll:altpll_component| 0 (0) 0 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component
      |pll_s1_arbitrator:the_pll_s1| 1 (1) 1 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 1 (1) 0 (0) 0 (0) |standard|std_1s10:inst|pll_s1_arbitrator:the_pll_s1
      |reconfig_request_pio:the_reconfig_request_pio| 4 (4) 3 0 0 0 0 0 0 0 0 0 0 1 (1) 0 (0) 3 (3) 0 (0) 0 (0) |standard|std_1s10:inst|reconfig_request_pio:the_reconfig_request_pio
      |reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1| 4 (4) 0 0 0 0 0 0 0 0 0 0 0 4 (4) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1
      |sdram:the_sdram| 655 (526) 290 0 0 0 0 0 0 0 0 0 0 365 (358) 36 (4) 254 (164) 13 (13) 59 (15) |standard|std_1s10:inst|sdram:the_sdram
         |sdram_input_efifo_module:the_sdram_input_efifo_module| 129 (129) 122 0 0 0 0 0 0 0 0 0 0 7 (7) 32 (32) 90 (90) 0 (0) 44 (44) |standard|std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module
      |sdram_s1_arbitrator:the_sdram_s1| 95 (47) 45 0 0 0 0 0 0 0 0 0 0 50 (33) 0 (0) 45 (14) 6 (6) 2 (2) |standard|std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1
         |rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1| 17 (17) 12 0 0 0 0 0 0 0 0 0 0 5 (5) 0 (0) 12 (12) 0 (0) 0 (0) |standard|std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1
         |rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1| 31 (31) 19 0 0 0 0 0 0 0 0 0 0 12 (12) 0 (0) 19 (19) 0 (0) 0 (0) |standard|std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1
      |seven_seg_pio:the_seven_seg_pio| 17 (17) 16 0 0 0 0 0 0 0 0 0 0 1 (1) 16 (16) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|seven_seg_pio:the_seven_seg_pio
      |std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch| 2 (2) 2 0 0 0 0 0 0 0 0 0 0 0 (0) 1 (1) 1 (1) 0 (0) 0 (0) |standard|std_1s10:inst|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch
      |std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch| 2 (2) 2 0 0 0 0 0 0 0 0 0 0 0 (0) 0 (0) 2 (2) 0 (0) 0 (0) |standard|std_1s10:inst|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch
      |sys_clk_timer:the_sys_clk_timer| 145 (145) 120 0 0 0 0 0 0 0 0 0 0 25 (25) 17 (17) 103 (103) 32 (32) 29 (29) |standard|std_1s10:inst|sys_clk_timer:the_sys_clk_timer
      |sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1| 3 (3) 0 0 0 0 0 0 0 0 0 0 0 3 (3) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|sys_clk_timer_s1_arbitrator:the_sys_clk_timer_s1
      |sysid_control_slave_arbitrator:the_sysid_control_slave| 4 (4) 0 0 0 0 0 0 0 0 0 0 0 4 (4) 0 (0) 0 (0) 0 (0) 0 (0) |standard|std_1s10:inst|sysid_control_slave_arbitrator:the_sysid_control_slave
      |uart1:the_uart1| 134 (0) 92 0 0 0 0 0 0 0 0 0 0 42 (0) 9 (0) 83 (0) 18 (0) 22 (0) |standard|std_1s10:inst|uart1:the_uart1
         |uart1_regs:the_uart1_regs| 42 (42) 29 0 0 0 0 0 0 0 0 0 0 13 (13) 7 (7) 22 (22) 0 (0) 19 (19) |standard|std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs
         |uart1_rx:the_uart1_rx| 58 (58) 37 0 0 0 0 0 0 0 0 0 0 21 (21) 2 (2) 35 (35) 9 (9) 2 (2) |standard|std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx
         |uart1_tx:the_uart1_tx| 34 (34) 26 0 0 0 0 0 0 0 0 0 0 8 (8) 0 (0) 26 (26) 9 (9) 1 (1) |standard|std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx
      |uart1_s1_arbitrator:the_uart1_s1| 4 (4) 1 0 0 0 0 0 0 0 0 0 0 3 (3) 0 (0) 1 (1) 0 (0) 0 (0) |standard|std_1s10:inst|uart1_s1_arbitrator:the_uart1_s1
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Delay Chain Summary

Top
Name Pin Type Pad to Core 0 Pad to Core 1 Pad to Input Register Core to Output Register Clock Enable to Output Enable Register Clock Enable to Output Register Clock Enable to Input Register TCO TCOE Falling Edge Output Enable
PLD_CLOCKINPUT Input -- -- -- -- -- -- -- -- -- --
PLD_CLEAR_N Input ON ON -- -- -- -- -- -- -- --
in_port_to_the_button_pio[2] Input ON ON -- -- -- -- -- -- -- --
in_port_to_the_button_pio[3] Input ON ON -- -- -- -- -- -- -- --
irq_from_the_lan91c111 Input ON ON -- -- -- -- -- -- -- --
in_port_to_the_button_pio[1] Input ON ON -- -- -- -- -- -- -- --
in_port_to_the_button_pio[0] Input ON ON -- -- -- -- -- -- -- --
rxd_to_the_uart1 Input ON ON -- -- -- -- -- -- -- --
ENET_ADS_N Output -- -- -- -- -- -- -- -- OFF OFF
ENET_AEN Output -- -- -- -- -- -- -- -- OFF OFF
ior_n_to_the_lan91c111 Output -- -- -- OFF -- OFF -- OFF OFF OFF
write_n_to_the_ext_flash Output -- -- -- ON -- OFF -- OFF OFF OFF
iow_n_to_the_lan91c111 Output -- -- -- OFF -- OFF -- OFF OFF OFF
read_n_to_the_ext_flash Output -- -- -- ON -- OFF -- OFF OFF OFF
read_n_to_the_ext_ram Output -- -- -- OFF -- OFF -- OFF OFF OFF
select_n_to_the_ext_ram Output -- -- -- OFF -- OFF -- OFF OFF OFF
write_n_to_the_ext_ram Output -- -- -- -- -- -- -- -- OFF OFF
zs_cas_n_from_the_sdram Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_cke_from_the_sdram Output -- -- -- -- -- -- -- -- OFF OFF
zs_cs_n_from_the_sdram Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_ras_n_from_the_sdram Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_we_n_from_the_sdram Output -- -- -- ON -- OFF -- OFF OFF OFF
LCD_RW_from_the_lcd_display Output -- -- -- -- -- -- -- -- OFF OFF
LCD_RS_from_the_lcd_display Output -- -- -- -- -- -- -- -- OFF OFF
LCD_E_from_the_lcd_display Output -- -- -- -- -- -- -- -- OFF OFF
txd_from_the_uart1 Output -- -- -- -- -- -- -- -- OFF OFF
select_n_to_the_ext_flash Output -- -- -- ON -- OFF -- OFF OFF OFF
SDRAM_CLKOUT Output -- -- -- -- -- -- -- -- OFF OFF
be_n_to_the_ext_ram[3] Output -- -- -- ON -- OFF -- OFF OFF OFF
be_n_to_the_ext_ram[2] Output -- -- -- ON -- OFF -- OFF OFF OFF
be_n_to_the_ext_ram[1] Output -- -- -- ON -- OFF -- OFF OFF OFF
be_n_to_the_ext_ram[0] Output -- -- -- ON -- OFF -- OFF OFF OFF
byteenablen_to_the_lan91c111[3] Output -- -- -- ON -- OFF -- OFF OFF OFF
byteenablen_to_the_lan91c111[2] Output -- -- -- ON -- OFF -- OFF OFF OFF
byteenablen_to_the_lan91c111[1] Output -- -- -- ON -- OFF -- OFF OFF OFF
byteenablen_to_the_lan91c111[0] Output -- -- -- ON -- OFF -- OFF OFF OFF
ext_ram_bus_address[22] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[21] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[20] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[19] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[18] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[17] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[16] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[15] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[14] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[13] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[12] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[11] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[10] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[9] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[8] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[7] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[6] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[5] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[4] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[3] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[2] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[1] Output -- -- -- OFF -- OFF -- OFF OFF OFF
ext_ram_bus_address[0] Output -- -- -- OFF -- OFF -- OFF OFF OFF
out_port_from_the_led_pio[7] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_led_pio[6] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_led_pio[5] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_led_pio[4] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_led_pio[3] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_led_pio[2] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_led_pio[1] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_led_pio[0] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[15] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[14] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[13] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[12] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[11] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[10] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[9] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[8] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[7] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[6] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[5] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[4] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[3] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[2] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[1] Output -- -- -- -- -- -- -- -- OFF OFF
out_port_from_the_seven_seg_pio[0] Output -- -- -- -- -- -- -- -- OFF OFF
zs_addr_from_the_sdram[11] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_addr_from_the_sdram[10] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_addr_from_the_sdram[9] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_addr_from_the_sdram[8] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_addr_from_the_sdram[7] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_addr_from_the_sdram[6] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_addr_from_the_sdram[5] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_addr_from_the_sdram[4] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_addr_from_the_sdram[3] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_addr_from_the_sdram[2] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_addr_from_the_sdram[1] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_addr_from_the_sdram[0] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_ba_from_the_sdram[1] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_ba_from_the_sdram[0] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_dqm_from_the_sdram[3] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_dqm_from_the_sdram[2] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_dqm_from_the_sdram[1] Output -- -- -- ON -- OFF -- OFF OFF OFF
zs_dqm_from_the_sdram[0] Output -- -- -- ON -- OFF -- OFF OFF OFF
bidir_port_to_and_from_the_reconfig_request_pio Bidir ON ON -- -- -- -- -- -- OFF OFF
ext_ram_bus_data[31] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[30] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[29] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[28] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[27] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[26] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[25] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[24] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[23] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[22] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[21] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[20] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[19] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[18] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[17] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[16] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[15] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[14] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[13] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[12] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[11] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[10] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[9] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[8] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[7] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[6] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[5] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[4] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[3] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[2] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[1] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
ext_ram_bus_data[0] Bidir OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
LCD_data_to_and_from_the_lcd_display[7] Bidir ON ON -- -- -- -- -- -- OFF OFF
LCD_data_to_and_from_the_lcd_display[6] Bidir ON ON -- -- -- -- -- -- OFF OFF
LCD_data_to_and_from_the_lcd_display[5] Bidir ON ON -- -- -- -- -- -- OFF OFF
LCD_data_to_and_from_the_lcd_display[4] Bidir ON ON -- -- -- -- -- -- OFF OFF
LCD_data_to_and_from_the_lcd_display[3] Bidir ON ON -- -- -- -- -- -- OFF OFF
LCD_data_to_and_from_the_lcd_display[2] Bidir ON ON -- -- -- -- -- -- OFF OFF
LCD_data_to_and_from_the_lcd_display[1] Bidir ON ON -- -- -- -- -- -- OFF OFF
LCD_data_to_and_from_the_lcd_display[0] Bidir ON ON -- -- -- -- -- -- OFF OFF
zs_dq_to_and_from_the_sdram[31] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[30] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[29] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[28] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[27] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[26] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[25] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[24] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[23] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[22] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[21] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[20] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[19] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[18] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[17] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[16] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[15] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[14] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[13] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[12] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[11] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[10] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[9] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[8] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[7] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[6] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[5] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[4] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[3] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[2] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[1] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF
zs_dq_to_and_from_the_sdram[0] Bidir OFF OFF OFF OFF -- OFF OFF OFF OFF OFF


Pad To Core Delay Chain Fanout

Top
Source Pin / Fanout Pad To Core Index Setting
PLD_CLOCKINPUT    
PLD_CLEAR_N    
     - std_1s10:inst|reset_n_sources~17 0 ON
in_port_to_the_button_pio[2]    
     - std_1s10:inst|button_pio:the_button_pio|readdata[2] 1 ON
     - std_1s10:inst|button_pio:the_button_pio|d1_data_in[2] 1 ON
in_port_to_the_button_pio[3]    
     - std_1s10:inst|button_pio:the_button_pio|readdata[3] 0 ON
     - std_1s10:inst|button_pio:the_button_pio|d1_data_in[3] 0 ON
irq_from_the_lan91c111    
     - std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_irq_from_the_lan91c111 0 ON
in_port_to_the_button_pio[1]    
     - std_1s10:inst|button_pio:the_button_pio|readdata[1] 0 ON
     - std_1s10:inst|button_pio:the_button_pio|d1_data_in[1] 0 ON
in_port_to_the_button_pio[0]    
     - std_1s10:inst|button_pio:the_button_pio|readdata[0] 1 ON
     - std_1s10:inst|button_pio:the_button_pio|d1_data_in[0] 1 ON
rxd_to_the_uart1    
     - std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|d1_source_rxd 1 ON
bidir_port_to_and_from_the_reconfig_request_pio    
     - std_1s10:inst|reconfig_request_pio:the_reconfig_request_pio|readdata 1 ON
ext_ram_bus_data[31]    
ext_ram_bus_data[30]    
ext_ram_bus_data[29]    
ext_ram_bus_data[28]    
ext_ram_bus_data[27]    
ext_ram_bus_data[26]    
ext_ram_bus_data[25]    
ext_ram_bus_data[24]    
ext_ram_bus_data[23]    
ext_ram_bus_data[22]    
ext_ram_bus_data[21]    
ext_ram_bus_data[20]    
ext_ram_bus_data[19]    
ext_ram_bus_data[18]    
ext_ram_bus_data[17]    
ext_ram_bus_data[16]    
ext_ram_bus_data[15]    
ext_ram_bus_data[14]    
ext_ram_bus_data[13]    
ext_ram_bus_data[12]    
ext_ram_bus_data[11]    
ext_ram_bus_data[10]    
ext_ram_bus_data[9]    
ext_ram_bus_data[8]    
ext_ram_bus_data[7]    
ext_ram_bus_data[6]    
ext_ram_bus_data[5]    
ext_ram_bus_data[4]    
ext_ram_bus_data[3]    
ext_ram_bus_data[2]    
ext_ram_bus_data[1]    
ext_ram_bus_data[0]    
LCD_data_to_and_from_the_lcd_display[7]    
     - std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[7]~4865 1 ON
LCD_data_to_and_from_the_lcd_display[6]    
     - std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[6]~4995 0 ON
LCD_data_to_and_from_the_lcd_display[5]    
     - std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[5]~4988 1 ON
LCD_data_to_and_from_the_lcd_display[4]    
     - std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[4]~4877 0 ON
LCD_data_to_and_from_the_lcd_display[3]    
     - std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[3]~4845 0 ON
LCD_data_to_and_from_the_lcd_display[2]    
     - std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[2]~4830 0 ON
LCD_data_to_and_from_the_lcd_display[1]    
     - std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[1]~5010 0 ON
LCD_data_to_and_from_the_lcd_display[0]    
     - std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|cpu_data_master_readdata[0]~5002 0 ON
zs_dq_to_and_from_the_sdram[31]    
zs_dq_to_and_from_the_sdram[30]    
zs_dq_to_and_from_the_sdram[29]    
zs_dq_to_and_from_the_sdram[28]    
zs_dq_to_and_from_the_sdram[27]    
zs_dq_to_and_from_the_sdram[26]    
zs_dq_to_and_from_the_sdram[25]    
zs_dq_to_and_from_the_sdram[24]    
zs_dq_to_and_from_the_sdram[23]    
zs_dq_to_and_from_the_sdram[22]    
zs_dq_to_and_from_the_sdram[21]    
zs_dq_to_and_from_the_sdram[20]    
zs_dq_to_and_from_the_sdram[19]    
zs_dq_to_and_from_the_sdram[18]    
zs_dq_to_and_from_the_sdram[17]    
zs_dq_to_and_from_the_sdram[16]    
zs_dq_to_and_from_the_sdram[15]    
zs_dq_to_and_from_the_sdram[14]    
zs_dq_to_and_from_the_sdram[13]    
zs_dq_to_and_from_the_sdram[12]    
zs_dq_to_and_from_the_sdram[11]    
zs_dq_to_and_from_the_sdram[10]    
zs_dq_to_and_from_the_sdram[9]    
zs_dq_to_and_from_the_sdram[8]    
zs_dq_to_and_from_the_sdram[7]    
zs_dq_to_and_from_the_sdram[6]    
zs_dq_to_and_from_the_sdram[5]    
zs_dq_to_and_from_the_sdram[4]    
zs_dq_to_and_from_the_sdram[3]    
zs_dq_to_and_from_the_sdram[2]    
zs_dq_to_and_from_the_sdram[1]    
zs_dq_to_and_from_the_sdram[0]    


Control Signals

Top
Name Location Fan-Out Usage Global Global Resource Used Global Line Name
PLD_CLOCKINPUT PIN_K17 74 Clock yes Global clock GCLK14
altera_internal_jtag~TCKUTAP ELA_X0_Y15_N0 153 Clock yes Global clock GCLK0
altera_internal_jtag~TMSUTAP ELA_X0_Y15_N0 22 Sync. clear no -- --
altera_internal_jtag~UPDATEUSER ELA_X0_Y15_N0 41 Async. clear, Async. load, Clock yes Global clock GCLK3
sld_hub:sld_hub_inst|CLR_SIGNAL LC_X28_Y4_N2 182 Async. clear, Async. load yes Global clock GCLK5
sld_hub:sld_hub_inst|GEN_SHADOW_IRF~1 LC_X29_Y27_N5 2 Clock enable no -- --
sld_hub:sld_hub_inst|IRF_ENABLE[1]~126 LC_X30_Y26_N4 2 Clock enable no -- --
sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 LC_X28_Y28_N9 3 Clock enable no -- --
sld_hub:sld_hub_inst|IRSR_ENA LC_X28_Y26_N3 2 Clock enable no -- --
sld_hub:sld_hub_inst|comb~97 LC_X28_Y26_N4 5 Clock enable no -- --
sld_hub:sld_hub_inst|jtag_debug_mode_usr1 LC_X28_Y23_N9 14 Async. clear no -- --
sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]~7773 LC_X28_Y28_N2 5 Clock enable no -- --
sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] LC_X28_Y5_N4 15 Async. clear yes Global clock GCLK6
sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11] LC_X28_Y4_N7 12 Clock enable no -- --
sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12] LC_X28_Y5_N5 5 Clock enable no -- --
sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] LC_X28_Y26_N0 42 Sync. clear, Sync. load no -- --
sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8] LC_X28_Y6_N4 10 Async. clear no -- --
sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|clear_signal LC_X28_Y27_N4 9 Sync. clear no -- --
sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1250 LC_X28_Y26_N7 4 Clock enable no -- --
sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]~1253 LC_X28_Y26_N5 5 Clock enable no -- --
std_1s10:inst|button_pio:the_button_pio|process1~12 LC_X50_Y12_N4 4 Clock enable no -- --
std_1s10:inst|clock_0:the_clock_0|process0~9 LC_X47_Y18_N1 16 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|D_ic_fill_starting LC_X35_Y21_N4 30 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|D_src1_hazard_M LC_X19_Y19_N6 32 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|D_src2_hazard_M~43 LC_X18_Y18_N7 32 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|E_ctrl_alu_subtract LC_X18_Y9_N5 33 Invert A no -- --
std_1s10:inst|cpu:the_cpu|E_ctrl_break LC_X18_Y18_N2 8 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|E_ctrl_dst_data_sel_cmp LC_X22_Y6_N3 33 Sync. clear no -- --
std_1s10:inst|cpu:the_cpu|E_ctrl_exception LC_X19_Y7_N5 7 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|E_ctrl_rdctl_inst LC_X22_Y20_N8 32 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|E_hbreak_req LC_X27_Y22_N3 25 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|E_iw[4] LC_X25_Y22_N2 22 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|Equal143~6 LC_X23_Y20_N6 8 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|Equal145~6 LC_X23_Y20_N4 8 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|M_alu_result[2] LC_X28_Y21_N6 81 Output enable no -- --
std_1s10:inst|cpu:the_cpu|M_ctrl_rot LC_X17_Y11_N4 32 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|M_ienable_reg[2]~3 LC_X29_Y20_N7 6 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|M_ld_align_sh8 LC_X23_Y20_N5 8 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|M_pipe_flush LC_X27_Y21_N6 32 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|M_status_reg_pie~157 LC_X28_Y22_N4 2 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|M_wr_dst_reg LC_X19_Y17_N1 5 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|W_stall LC_X22_Y21_N6 511 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19890 LC_X32_Y28_N0 16 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19897 LC_X32_Y25_N1 20 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|DRsize[0]~19922 LC_X32_Y28_N7 2 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0] LC_X32_Y25_N6 56 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0]~0 LC_X32_Y25_N5 2 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process2~234 LC_X31_Y27_N6 25 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process3~12 LC_X32_Y24_N5 73 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_updateir LC_X32_Y29_N4 7 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_break_c~45 LC_X33_Y28_N4 32 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_a~42 LC_X34_Y25_N9 8 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_a~43 LC_X34_Y25_N2 15 Clock enable, Sync. load no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_ocimem_b~22 LC_X33_Y28_N7 14 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_no_action_ocimem_a~16 LC_X34_Y25_N6 9 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|take_action_oci_intr_mask_reg~8 LC_X40_Y21_N8 6 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonWr LC_X36_Y21_N4 3 Write enable no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7315 LC_X40_Y4_N8 2 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7318 LC_X36_Y24_N1 32 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|internal_MonDReg[1]~7319 LC_X36_Y24_N2 31 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|module_input6~23 LC_X35_Y15_N5 2 Write enable no -- --
std_1s10:inst|cpu:the_cpu|i_readdatavalid_d1 LC_X41_Y13_N6 11 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|ic_fill_dp_offset_en~1 LC_X36_Y20_N8 4 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|ic_fill_initial_offset[0]~801 LC_X40_Y13_N4 3 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|ic_fill_prevent_refill_nxt~0 LC_X35_Y21_N0 9 Sync. load no -- --
std_1s10:inst|cpu:the_cpu|ic_fill_valid_bits_en LC_X35_Y21_N6 8 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|ic_tag_wren LC_X36_Y18_N6 1 Clock enable no -- --
std_1s10:inst|cpu:the_cpu|reset_d1 LC_X35_Y15_N4 9 Sync. clear no -- --
std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|process3~0 LC_X41_Y16_N9 8 Clock enable no -- --
std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|process4~0 LC_X41_Y16_N1 8 Clock enable no -- --
std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|process5~0 LC_X41_Y16_N0 8 Clock enable no -- --
std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|p1_cpu_instruction_master_latency_counter~0 LC_X40_Y13_N8 5 Sync. load no -- --
std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process2~0 LC_X46_Y12_N0 8 Clock enable no -- --
std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process3~0 LC_X45_Y15_N2 8 Clock enable no -- --
std_1s10:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master|process4~0 LC_X45_Y17_N2 8 Clock enable no -- --
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|WideOr6 LC_X35_Y12_N2 7 Clock enable no -- --
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] LC_X44_Y13_N7 37 Clock enable no -- --
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~COMB_OUT LC_X40_Y16_N2 32 Output enable no -- --
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_counter_enable~18 LC_X39_Y16_N8 2 Clock enable no -- --
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_arb_winner~0 LC_X39_Y17_N0 11 Clock enable no -- --
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_avalon_slave_end_xfer~80 LC_X39_Y16_N7 8 Sync. load no -- --
std_1s10:inst|high_res_timer:the_high_res_timer|control_wr_strobe LC_X46_Y9_N5 5 Clock enable no -- --
std_1s10:inst|high_res_timer:the_high_res_timer|period_h_wr_strobe LC_X46_Y9_N7 16 Clock enable no -- --
std_1s10:inst|high_res_timer:the_high_res_timer|period_l_wr_strobe LC_X46_Y9_N0 16 Clock enable no -- --
std_1s10:inst|high_res_timer:the_high_res_timer|process0~0 LC_X48_Y7_N1 32 Clock enable no -- --
std_1s10:inst|high_res_timer:the_high_res_timer|process0~1 LC_X48_Y7_N7 32 Sync. load no -- --
std_1s10:inst|high_res_timer:the_high_res_timer|snap_strobe~16 LC_X46_Y9_N1 32 Clock enable no -- --
std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena~0 LC_X34_Y23_N8 8 Clock enable no -- --
std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|td_shift[9]~3497 LC_X34_Y24_N2 21 Clock enable no -- --
std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[0]~7 LC_X34_Y23_N5 4 Clock enable no -- --
std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[1]~6 LC_X33_Y23_N4 8 Clock enable no -- --
std_1s10:inst|jtag_uart:the_jtag_uart|fifo_wr LC_X50_Y14_N3 15 Clock enable no -- --
std_1s10:inst|jtag_uart:the_jtag_uart|ien_AE~15 LC_X50_Y8_N4 3 Clock enable no -- --
std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|_~28 LC_X51_Y15_N3 6 Clock enable no -- --
std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|a_fefifo_7cf:fifo_state|_~28 LC_X52_Y17_N7 6 Clock enable no -- --
std_1s10:inst|jtag_uart:the_jtag_uart|rd_wfifo LC_X48_Y17_N5 10 Clock enable no -- --
std_1s10:inst|jtag_uart:the_jtag_uart|rvalid~18 LC_X51_Y15_N7 7 Clock enable no -- --
std_1s10:inst|jtag_uart:the_jtag_uart|wr_rfifo LC_X51_Y15_N9 13 Clock enable no -- --
std_1s10:inst|led_pio:the_led_pio|process0~1 LC_X40_Y12_N6 8 Clock enable no -- --
std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|wren~1 LC_X34_Y11_N9 1 Write enable no -- --
std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0 PLL_5 1923 Clock yes Global clock GCLK15
std_1s10:inst|pll:the_pll|control_reg_en~18 LC_X50_Y20_N1 16 Clock enable no -- --
std_1s10:inst|pll:the_pll|count_done LC_X17_Y29_N3 8 Clock enable no -- --
std_1s10:inst|pll:the_pll|not_areset LC_X28_Y1_N2 7 Async. clear yes Global clock GCLK7
std_1s10:inst|reconfig_request_pio:the_reconfig_request_pio|data_dir LC_X41_Y15_N7 3 Output enable no -- --
std_1s10:inst|reset_n_sources~17 LC_X36_Y21_N9 4 Async. clear yes Global clock GCLK10
std_1s10:inst|sdram:the_sdram|Mux10~94 LC_X40_Y2_N5 3 Clock enable no -- --
std_1s10:inst|sdram:the_sdram|Mux39~1228 LC_X32_Y3_N8 5 Clock enable no -- --
std_1s10:inst|sdram:the_sdram|i_cmd[0]~636 LC_X40_Y2_N3 4 Clock enable no -- --
std_1s10:inst|sdram:the_sdram|m_state[6] LC_X36_Y2_N5 46 Clock enable no -- --
std_1s10:inst|sdram:the_sdram|oe LC_X36_Y1_N7 32 Output enable no -- --
std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56]~56 LC_X36_Y4_N9 59 Clock enable no -- --
std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[56]~56 LC_X36_Y4_N6 59 Clock enable no -- --
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_data_master_to_sdram_s1_module:rdv_fifo_for_cpu_data_master_to_sdram_s1|process1~3 LC_X45_Y9_N3 7 Clock enable no -- --
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process0~1 LC_X44_Y9_N6 2 Clock enable no -- --
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process10~1 LC_X44_Y10_N3 2 Clock enable no -- --
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process12~3 LC_X45_Y9_N2 2 Clock enable no -- --
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process15~0 LC_X40_Y10_N5 10 Clock enable no -- --
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process2~1 LC_X45_Y9_N7 2 Clock enable no -- --
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process4~1 LC_X44_Y9_N2 2 Clock enable no -- --
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process6~1 LC_X44_Y10_N4 2 Clock enable no -- --
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|rdv_fifo_for_cpu_instruction_master_to_sdram_s1_module:rdv_fifo_for_cpu_instruction_master_to_sdram_s1|process8~1 LC_X44_Y10_N2 2 Clock enable no -- --
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_counter_enable~43 LC_X39_Y10_N9 6 Clock enable no -- --
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|sdram_s1_arb_winner~0 LC_X41_Y11_N1 2 Clock enable no -- --
std_1s10:inst|seven_seg_pio:the_seven_seg_pio|process0~1 LC_X40_Y12_N2 16 Clock enable no -- --
std_1s10:inst|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch|data_out LC_X27_Y1_N2 63 Async. clear yes Global clock GCLK4
std_1s10:inst|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch|data_out LC_X2_Y12_N6 1642 Async. clear, Async. load yes Global clock GCLK2
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|control_wr_strobe LC_X48_Y9_N2 5 Clock enable no -- --
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_h_wr_strobe LC_X48_Y9_N5 16 Clock enable no -- --
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|period_l_wr_strobe LC_X48_Y9_N9 16 Clock enable no -- --
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|process0~0 LC_X50_Y5_N0 32 Clock enable no -- --
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|process0~1 LC_X50_Y6_N8 32 Sync. load no -- --
std_1s10:inst|sys_clk_timer:the_sys_clk_timer|snap_strobe~22 LC_X46_Y9_N8 32 Clock enable no -- --
std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|control_wr_strobe~20 LC_X48_Y9_N4 10 Clock enable no -- --
std_1s10:inst|uart1:the_uart1|uart1_regs:the_uart1_regs|tx_wr_strobe~10 LC_X48_Y9_N6 8 Clock enable no -- --
std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|got_new_char LC_X48_Y10_N0 11 Clock enable no -- --
std_1s10:inst|uart1:the_uart1|uart1_rx:the_uart1_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3]~7381 LC_X41_Y29_N8 9 Clock enable no -- --
std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|process4~0 LC_X52_Y7_N7 9 Sync. load no -- --
std_1s10:inst|uart1:the_uart1|uart1_tx:the_uart1_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3]~2816 LC_X51_Y7_N1 10 Clock enable no -- --


Global & Other Fast Signals

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Name Location Fan-Out Global Resource Used Global Line Name
PLD_CLOCKINPUT PIN_K17 74 Global clock GCLK14
altera_internal_jtag~TCKUTAP ELA_X0_Y15_N0 153 Global clock GCLK0
altera_internal_jtag~UPDATEUSER ELA_X0_Y15_N0 41 Global clock GCLK3
sld_hub:sld_hub_inst|CLR_SIGNAL LC_X28_Y4_N2 182 Global clock GCLK5
sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] LC_X28_Y5_N4 15 Global clock GCLK6
std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0 PLL_5 1923 Global clock GCLK15
std_1s10:inst|pll:the_pll|not_areset LC_X28_Y1_N2 7 Global clock GCLK7
std_1s10:inst|reset_n_sources~17 LC_X36_Y21_N9 4 Global clock GCLK10
std_1s10:inst|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch|data_out LC_X27_Y1_N2 63 Global clock GCLK4
std_1s10:inst|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch|data_out LC_X2_Y12_N6 1642 Global clock GCLK2


Non-Global High Fan-Out Signals

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Name Fan-Out
std_1s10:inst|cpu:the_cpu|W_stall 511
std_1s10:inst|cpu:the_cpu|M_ctrl_mul_shift_rot 95
std_1s10:inst|sdram:the_sdram|m_state[1] 91
std_1s10:inst|cpu:the_cpu|M_alu_result[2] 81
std_1s10:inst|cpu:the_cpu|M_alu_result[4] 80
std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|rd_address 75
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|process3~12 73
std_1s10:inst|clock_0_in_arbitrator:the_clock_0_in|cpu_data_master_requests_clock_0_in 68
std_1s10:inst|cpu:the_cpu|M_alu_result[3] 68
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|take_action_break_c~45 64
std_1s10:inst|sdram:the_sdram|m_state[4] 64
std_1s10:inst|sdram:the_sdram|m_state[3] 61
std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_1[56]~56 59
std_1s10:inst|sdram:the_sdram|sdram_input_efifo_module:the_sdram_input_efifo_module|entry_0[56]~56 59
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[18]~1195 58
std_1s10:inst|sdram:the_sdram|m_state[0] 58
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_requests_sdram_s1~431 56
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0] 56
std_1s10:inst|cpu:the_cpu|D_iw[21] 55
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_lan91c111_s1~119 51
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[1] 49
std_1s10:inst|sdram:the_sdram|f_select 48
std_1s10:inst|cpu:the_cpu|internal_d_write 48
std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_granted_cpu_jtag_debug_module~54 47
std_1s10:inst|sdram:the_sdram|m_state[6] 46
std_1s10:inst|reconfig_request_pio_s1_arbitrator:the_reconfig_request_pio_s1|cpu_data_master_requests_reconfig_request_pio_s1~44 45
sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] 42
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_ext_flash_s1~55 41
std_1s10:inst|sdram_s1_arbitrator:the_sdram_s1|cpu_data_master_granted_sdram_s1~30 40
std_1s10:inst|cpu:the_cpu|hbreak_enabled 40
std_1s10:inst|cpu:the_cpu|ic_fill_line[5] 39
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_ext_flash_s1 39
std_1s10:inst|sdram:the_sdram|Mux118~1215 38
std_1s10:inst|jtag_uart_avalon_jtag_slave_arbitrator:the_jtag_uart_avalon_jtag_slave|cpu_data_master_requests_jtag_uart_avalon_jtag_slave~443 38
std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_data_master_requests_onchip_ram_64_kbytes_s1 38
std_1s10:inst|cpu:the_cpu|M_alu_result[7] 38
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_read_data_valid_ext_flash_s1_shift_register[1] 37
std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_instruction_master_qualified_request_cpu_jtag_debug_module~254 37
std_1s10:inst|sdram:the_sdram|m_state[8] 37
std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_requests_lan91c111_s1 37
~GND 35
std_1s10:inst|cpu:the_cpu|D_iw[2] 35
std_1s10:inst|sdram:the_sdram|m_state[7] 35
std_1s10:inst|sdram:the_sdram|m_state[2] 35
std_1s10:inst|cpu:the_cpu|internal_d_read 35
std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module 34
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|MonAReg[10] 34
std_1s10:inst|cpu:the_cpu|latched_oci_tb_hbreak_req 34
std_1s10:inst|cpu:the_cpu|M_alu_result[10] 34
std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_read_data_valid_onchip_ram_64_kbytes_s1_shift_register 33


Fitter RAM Summary

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Name Type Mode Port A Depth Port A Width Port B Depth Port B Width Port A Input Registers Port A Output Registers Port B Input Registers Port B Output Registers Size Implementation Port A Depth Implementation Port A Width Implementation Port B Depth Implementation Port B Width Implementation Bits M512s M4Ks M-RAMs MIF Location
std_1s10:inst|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_nnb1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port 1024 32 1024 32 yes no yes no 32768 1024 32 1024 32 32768 0 8 0 None M4K_X37_Y16, M4K_X37_Y20, M4K_X37_Y18, M4K_X15_Y20, M4K_X37_Y17, M4K_X37_Y19, M4K_X15_Y16, M4K_X15_Y19
std_1s10:inst|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_t9e1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port 128 22 128 22 yes no yes no 2816 128 22 128 22 2816 0 1 0 cpu_ic_tag_ram.mif M4K_X37_Y15
std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_8q62:auto_generated|ALTSYNCRAM AUTO True Dual Port 256 32 256 32 yes no yes no 8192 256 32 256 32 8192 0 2 0 cpu_ociram_default_contents.mif M4K_X37_Y24, M4K_X37_Y23
std_1s10:inst|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_00e1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port 32 32 32 32 yes no yes no 1024 32 32 32 32 1024 0 1 0 cpu_rf_ram_a.mif M4K_X15_Y17
std_1s10:inst|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_10e1:auto_generated|ALTSYNCRAM AUTO Simple Dual Port 32 32 32 32 yes no yes no 1024 32 32 32 32 1024 0 1 0 cpu_rf_ram_b.mif M4K_X15_Y18
std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_r:the_jtag_uart_scfifo_r|scfifo:rfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port 64 8 64 8 yes no yes no 512 64 8 64 8 512 1 0 0 None M512_X49_Y18
std_1s10:inst|jtag_uart:the_jtag_uart|jtag_uart_scfifo_w:the_jtag_uart_scfifo_w|scfifo:wfifo|scfifo_gg21:auto_generated|a_dpfifo_jm21:dpfifo|dpram_ga21:FIFOram|altsyncram_kml1:altsyncram1|ALTSYNCRAM AUTO Simple Dual Port 64 8 64 8 yes no yes no 512 64 8 64 8 512 1 0 0 None M512_X49_Y24
std_1s10:inst|onchip_ram_64_kbytes:the_onchip_ram_64_kbytes|altsyncram:the_altsyncram|altsyncram_7b71:auto_generated|ALTSYNCRAM M-RAM Single Port 16384 32 -- -- yes no -- -- 524288 16384 32 -- -- 524288 0 0 1 None MRAM_X20_Y7
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.


Fitter DSP Block Usage Summary

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Statistic Number Used Available per Block Maximum Available
Simple Multipliers (9-bit) 0 8 48
Simple Multipliers (18-bit) 0 4 24
Simple Multipliers (36-bit) 1 1 6
Multiply Accumulators (18-bit) 0 2 12
Two-Multipliers Adders (9-bit) 0 4 24
Two-Multipliers Adders (18-bit) 0 2 12
Four-Multipliers Adders (9-bit) 0 2 12
Four-Multipliers Adders (18-bit) 0 1 6
DSP Blocks 1 -- 6
DSP Block 9-bit Elements 8 8 48
Signed Multipliers 1 -- --
Unsigned Multipliers 0 -- --
Mixed Sign Multipliers 0 -- --
Variable Sign Multipliers 0 -- --
Dedicated Shift Register Chains 0 -- --


DSP Block Details

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Name Mode Location Sign Representation Has Input Shift Register Chain
std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_out5 Simple Multiplier (36-bit) DSPOUT_X11_Y9_N0   No
   std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult1   DSPMULT_X10_Y15_N0 Unsigned  
   std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult2   DSPMULT_X10_Y13_N0 Signed  
   std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult3   DSPMULT_X10_Y11_N0 Mixed  
   std_1s10:inst|cpu:the_cpu|cpu_mult_cell:the_cpu_mult_cell|altmult_add:the_altmult_add|mult_add_1f72:auto_generated|mac_mult4   DSPMULT_X10_Y9_N0 Mixed  


Interconnect Usage Summary

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Interconnect Resource Type Usage
C16 interconnects 388 / 2,286 ( 17 % )
C4 interconnects 4,115 / 31,320 ( 13 % )
C8 interconnects 1,162 / 7,272 ( 16 % )
DIFFIOCLKs 0 / 16 ( 0 % )
DQS bus muxes 0 / 56 ( 0 % )
DQS-32 I/O buses 0 / 4 ( 0 % )
DQS-8 I/O buses 0 / 16 ( 0 % )
Direct links 483 / 44,740 ( 1 % )
Fast regional clocks 0 / 8 ( 0 % )
Global clocks 10 / 16 ( 63 % )
I/O buses 47 / 208 ( 23 % )
LUT chains 194 / 9,513 ( 2 % )
Local routing interconnects 1,905 / 10,570 ( 18 % )
R24 interconnects 432 / 2,280 ( 19 % )
R4 interconnects 5,046 / 62,520 ( 8 % )
R8 interconnects 1,381 / 10,410 ( 13 % )
Regional clocks 0 / 16 ( 0 % )


LAB Logic Elements

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Number of Logic Elements  (Average = 8.61) Number of LABs  (Total = 466)
1 33
2 16
3 5
4 3
5 5
6 15
7 7
8 21
9 21
10 340


LAB-wide Signals

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LAB-wide Signals  (Average = 2.49) Number of LABs  (Total = 466)
1 Async. clear 362
1 Async. load 4
1 Clock 390
1 Clock enable 214
1 Invert A 3
1 Sync. clear 10
1 Sync. load 83
2 Async. clears 24
2 Clock enables 40
2 Clocks 30


LAB Signals Sourced

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Number of Signals Sourced  (Average = 9.36) Number of LABs  (Total = 466)
0 2
1 33
2 15
3 5
4 6
5 4
6 14
7 9
8 18
9 21
10 187
11 58
12 38
13 29
14 9
15 9
16 2
17 4
18 2
19 0
20 1


LAB Signals Sourced Out

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Number of Signals Sourced Out  (Average = 6.24) Number of LABs  (Total = 466)
0 2
1 43
2 22
3 39
4 35
5 43
6 64
7 57
8 57
9 31
10 45
11 4
12 7
13 6
14 0
15 6
16 2
17 1
18 1
19 0
20 1


LAB Distinct Inputs

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Number of Distinct Inputs  (Average = 15.93) Number of LABs  (Total = 466)
0 0
1 2
2 8
3 21
4 7
5 20
6 6
7 7
8 7
9 7
10 15
11 13
12 15
13 13
14 22
15 31
16 27
17 26
18 37
19 23
20 14
21 24
22 27
23 22
24 68
25 1
26 3


Fitter Device Options

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Option Setting
Enable user-supplied start-up clock (CLKUSR) Off
Enable device-wide reset (DEV_CLRn) Off
Enable device-wide output enable (DEV_OE) Off
Enable INIT_DONE output Off
Configuration scheme Fast Passive Parallel
Error detection CRC Off
Reserve all unused pins As input tri-stated
Base pin-out file on sameframe device Off


Fitter Messages

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Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 176 04/19/2006 SJ Full Version
    Info: Processing started: Fri Apr 21 02:59:23 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off standard -c standard
Info: Selected device EP1S10F780C6 for design "standard"
Info: Implemented Enhanced for PLL "std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|pll"
Info: Implementing parameter values for PLL "std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|pll"
    Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0 port
    Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of -63 degrees (-3499 ps) for std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_extclk0 port
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1S10F780I6 is compatible
    Info: Device EP1S10F780C6ES is compatible
    Info: Device EP1S20F780C6 is compatible
    Info: Device EP1S20F780I6 is compatible
    Info: Device EP1S25F780C6 is compatible
    Info: Device EP1S25F780I6 is compatible
    Info: Device EP1S30F780C6 is compatible
    Info: Device EP1S30F780I6 is compatible
    Info: Device EP1S30F780C6_HARDCOPY_FPGA_PROTOTYPE is compatible
    Info: Device EP1S40F780C6 is compatible
    Info: Device EP1S40F780I6 is compatible
    Info: Device EP1S40F780C6_HARDCOPY_FPGA_PROTOTYPE is compatible
Info: DATA[0] dual-purpose pin not reserved
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: Promoted PLL clock signals
    Info: Promoted signal "std_1s10:inst|pll:the_pll|altpllpll:the_pll|altpll:altpll_component|_clk0" to use global clock
Info: Completed PLL Placement Operation
Info: Automatically promoted signal "PLD_CLOCKINPUT" to use Global clock in PIN K17
Info: Automatically promoted signal "altera_internal_jtag~TCKUTAP" to use Global clock
Info: Automatically promoted signal "altera_internal_jtag~UPDATEUSER" to use Global clock
Info: Automatically promoted some destinations of signal "std_1s10:inst|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch|data_out" to use Global clock
    Info: Destination "std_1s10:inst|sdram:the_sdram|active_addr[9]" may be non-global or may not use global clock
    Info: Destination "std_1s10:inst|sdram:the_sdram|active_addr[14]" may be non-global or may not use global clock
    Info: Destination "std_1s10:inst|sdram:the_sdram|active_addr[13]" may be non-global or may not use global clock
    Info: Destination "std_1s10:inst|sdram:the_sdram|active_addr[11]" may be non-global or may not use global clock
    Info: Destination "std_1s10:inst|sdram:the_sdram|active_addr[16]" may be non-global or may not use global clock
    Info: Destination "std_1s10:inst|sdram:the_sdram|active_addr[15]" may be non-global or may not use global clock
    Info: Destination "std_1s10:inst|sdram:the_sdram|active_addr[17]" may be non-global or may not use global clock
    Info: Destination "std_1s10:inst|sdram:the_sdram|active_addr[10]" may be non-global or may not use global clock
    Info: Destination "std_1s10:inst|sdram:the_sdram|active_addr[20]" may be non-global or may not use global clock
    Info: Destination "std_1s10:inst|sdram:the_sdram|active_addr[18]" may be non-global or may not use global clock
    Info: Limited to 10 non-global destinations
Info: Automatically promoted some destinations of signal "sld_hub:sld_hub_inst|CLR_SIGNAL" to use Global clock
    Info: Destination "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[0]~0" may be non-global or may not use global clock
    Info: Destination "std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|internal_resetlatch~185" may be non-global or may not use global clock
Info: Automatically promoted signal "std_1s10:inst|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch|data_out" to use Global clock
Info: Automatically promoted some destinations of signal "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]" to use Global clock
    Info: Destination "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1]" may be non-global or may not use global clock
    Info: Destination "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]" may be non-global or may not use global clock
Info: Automatically promoted signal "std_1s10:inst|pll:the_pll|not_areset" to use Global clock
Info: Automatically promoted signal "std_1s10:inst|reset_n_sources~17" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Ignoring invalid fast I/O register assignments
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished register packing: elapsed time is 00:00:06
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "CTS[1]" is assigned to location or region, but does not exist in design
    Warning: Node "CTS[2]" is assigned to location or region, but does not exist in design
    Warning: Node "DCD[1]" is assigned to location or region, but does not exist in design
    Warning: Node "DCD[2]" is assigned to location or region, but does not exist in design
    Warning: Node "DSR[1]" is assigned to location or region, but does not exist in design
    Warning: Node "DSR[2]" is assigned to location or region, but does not exist in design
    Warning: Node "DTR[1]" is assigned to location or region, but does not exist in design
    Warning: Node "DTR[2]" is assigned to location or region, but does not exist in design
    Warning: Node "ENET_CYCLE_N" is assigned to location or region, but does not exist in design
    Warning: Node "ENET_DATACS_N" is assigned to location or region, but does not exist in design
    Warning: Node "ENET_LCLK" is assigned to location or region, but does not exist in design
    Warning: Node "ENET_LDEV_N" is assigned to location or region, but does not exist in design
    Warning: Node "ENET_RDYRTN_N" is assigned to location or region, but does not exist in design
    Warning: Node "ENET_SRDY_N" is assigned to location or region, but does not exist in design
    Warning: Node "ENET_VLBUS_N" is assigned to location or region, but does not exist in design
    Warning: Node "ENET_W_R_N" is assigned to location or region, but does not exist in design
    Warning: Node "FLASH_RY_BY_N" is assigned to location or region, but does not exist in design
    Warning: Node "INIT_DONE" is assigned to location or region, but does not exist in design
    Warning: Node "PLD_CLKFB" is assigned to location or region, but does not exist in design
    Warning: Node "PLD_CLOCKINPUT[2]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO1_CLKOUT" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO1_IO[16]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO1_IO[19]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO1_IO[22]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO1_IO[23]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO1_IO[28]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO1_IO[40]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_CARDSEL_N" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_CLKOUT" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[0]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[10]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[11]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[12]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[13]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[14]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[15]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[16]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[17]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[18]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[19]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[1]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[20]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[21]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[22]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[23]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[24]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[25]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[26]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[27]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[28]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[29]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[2]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[30]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[31]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[32]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[33]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[34]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[35]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[36]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[37]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[38]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[39]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[3]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[40]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[4]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[5]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[6]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[7]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[8]" is assigned to location or region, but does not exist in design
    Warning: Node "PROTO2_IO[9]" is assigned to location or region, but does not exist in design
    Warning: Node "RI[1]" is assigned to location or region, but does not exist in design
    Warning: Node "RI[2]" is assigned to location or region, but does not exist in design
    Warning: Node "RTS[1]" is assigned to location or region, but does not exist in design
    Warning: Node "RTS[2]" is assigned to location or region, but does not exist in design
    Warning: Node "TR_DEBUGACK" is assigned to location or region, but does not exist in design
    Warning: Node "TR_DEBUGREQ" is assigned to location or region, but does not exist in design
    Warning: Node "ardy_from_the_lan91c111" is assigned to location or region, but does not exist in design
    Warning: Node "cf_addr[0]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_addr[10]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_addr[1]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_addr[2]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_addr[3]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_addr[4]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_addr[5]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_addr[6]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_addr[7]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_addr[8]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_addr[9]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_atasel" is assigned to location or region, but does not exist in design
    Warning: Node "cf_cs_n[0]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_cs_n[1]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[0]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[10]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[11]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[12]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[13]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[14]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[15]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[1]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[2]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[3]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[4]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[5]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[6]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[7]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[8]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_data[9]" is assigned to location or region, but does not exist in design
    Warning: Node "cf_detect" is assigned to location or region, but does not exist in design
    Warning: Node "cf_intrq" is assigned to location or region, but does not exist in design
    Warning: Node "cf_iord_n" is assigned to location or region, but does not exist in design
    Warning: Node "cf_iordy" is assigned to location or region, but does not exist in design
    Warning: Node "cf_iowr_n" is assigned to location or region, but does not exist in design
    Warning: Node "cf_power" is assigned to location or region, but does not exist in design
    Warning: Node "cf_rfu" is assigned to location or region, but does not exist in design
    Warning: Node "cf_we_n" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_clk_from_the_cpu" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[0]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[10]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[11]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[12]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[13]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[14]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[15]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[16]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[17]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[1]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[2]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[3]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[4]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[5]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[6]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[7]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[8]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_offchip_trace_data_from_the_cpu[9]" is assigned to location or region, but does not exist in design
    Warning: Node "jtag_debug_trigout_from_the_cpu" is assigned to location or region, but does not exist in design
    Warning: Node "out_port_from_the_reconfig_request_pio" is assigned to location or region, but does not exist in design
    Warning: Node "rxd_to_the_uart2" is assigned to location or region, but does not exist in design
    Warning: Node "txd_from_the_uart2" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:03
Info: Fitter placement operations beginning
Info: Starting physical synthesis optimizations
Info: Starting physical synthesis algorithm logic and register replication
Info: Physical synthesis algorithm logic and register replication complete: estimated performance improvement of up to 0 percent
Info: Starting physical synthesis algorithm register unpacking
Info: Physical synthesis algorithm register unpacking complete: estimated performance improvement of up to 0 percent
Info: Physical synthesis optimizations complete: elapsed time is 00:01:01
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:01:24
Info: Estimated most critical path is register to register delay of 15.200 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X40_Y11; Fanout = 19; REG Node = 'std_1s10:inst|cpu:the_cpu|internal_i_read'
    Info: 2: + IC(1.160 ns) + CELL(0.459 ns) = 1.619 ns; Loc. = LAB_X36_Y14; Fanout = 5; COMB Node = 'std_1s10:inst|onchip_ram_64_kbytes_s1_arbitrator:the_onchip_ram_64_kbytes_s1|cpu_instruction_master_requests_onchip_ram_64_kbytes_s1~48'
    Info: 3: + IC(0.301 ns) + CELL(0.213 ns) = 2.133 ns; Loc. = LAB_X36_Y14; Fanout = 1; COMB Node = 'std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~3'
    Info: 4: + IC(1.027 ns) + CELL(0.459 ns) = 3.619 ns; Loc. = LAB_X40_Y15; Fanout = 4; COMB Node = 'std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_instruction_master_continuerequest~54'
    Info: 5: + IC(1.262 ns) + CELL(0.332 ns) = 5.213 ns; Loc. = LAB_X34_Y13; Fanout = 16; COMB Node = 'std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_qualified_request_ext_flash_s1~146'
    Info: 6: + IC(1.526 ns) + CELL(0.341 ns) = 7.080 ns; Loc. = LAB_X40_Y15; Fanout = 2; COMB Node = 'std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~361COUT1_424'
    Info: 7: + IC(0.000 ns) + CELL(0.062 ns) = 7.142 ns; Loc. = LAB_X40_Y15; Fanout = 2; COMB Node = 'std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~369COUT1_426'
    Info: 8: + IC(0.000 ns) + CELL(0.449 ns) = 7.591 ns; Loc. = LAB_X40_Y15; Fanout = 9; COMB Node = 'std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|Add2~372'
    Info: 9: + IC(0.886 ns) + CELL(0.332 ns) = 8.809 ns; Loc. = LAB_X40_Y14; Fanout = 12; COMB Node = 'std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|cpu_data_master_granted_ext_ram_s1~76'
    Info: 10: + IC(1.030 ns) + CELL(0.213 ns) = 10.052 ns; Loc. = LAB_X40_Y17; Fanout = 14; COMB Node = 'std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|p1_ext_ram_bus_address[15]~3324'
    Info: 11: + IC(1.435 ns) + CELL(0.213 ns) = 11.700 ns; Loc. = LAB_X35_Y9; Fanout = 1; COMB Node = 'std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[13]~COMB_OUT'
    Info: 12: + IC(3.246 ns) + CELL(0.254 ns) = 15.200 ns; Loc. = IOC_X48_Y31_N1; Fanout = 1; REG Node = 'std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|ext_ram_bus_address[13]'
    Info: Total cell delay = 3.327 ns ( 21.89 % )
    Info: Total interconnect delay = 11.873 ns ( 78.11 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 12% of the available device resources. Peak interconnect usage is 28%
    Info: The peak interconnect region extends from location x32_y10 to location x42_y20
Info: Fitter routing operations ending: elapsed time is 00:00:44
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Node altera_internal_jtag uses non-global routing resources to route signals to global destination nodes
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|st_shiftdr -- routed using non-global resources
Info: Node std_1s10:inst|std_1s10_reset_sys_clk_domain_synch_module:std_1s10_reset_sys_clk_domain_synch|data_out uses non-global routing resources to route signals to global destination nodes
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate2 -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate1 -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write2 -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_ena~reg0 -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|t_dav -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rvalid -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|t_pause~reg0 -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|r_ena1 -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|read_write1 -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rvalid0 -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[5] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[7] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[6] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[0] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[3] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[1] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[2] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|rdata[4] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_saved_chosen_master_vector[0] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[0] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_arb_addend[1] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|d1_reasons_to_wait -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[3] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|cpu:the_cpu|d_readdata_d1[1] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|cpu:the_cpu|i_readdata_d1[1] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync|data_in_d1 -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_readdata[2] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_readdata[5] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[5] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[2] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|read_0 -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_readdata[10] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[11] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|jtag_uart:the_jtag_uart|ac -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|cpu_data_master_arbitrator:the_cpu_data_master|registered_cpu_data_master_readdata[10] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_readdata[11] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_out -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state[1] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_read_request -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse|data_in_d1 -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|internal_slave_write_request -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[15] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_readdata[3] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_readdata[12] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[7] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[14] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[4] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_writedata_d1[2] -- routed using non-global resources
Info: Node std_1s10:inst|std_1s10_reset_clk_domain_synch_module:std_1s10_reset_clk_domain_synch|data_out uses non-global routing resources to route signals to global destination nodes
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[4] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[2] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[13] -- routed using non-global resources
    Info: Port clear -- assigned as a global for destination node std_1s10:inst|clock_0:the_clock_0|slave_readdata_p1[7] -- routed using non-global resources
Warning: Following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin ENET_ADS_N has GND driving its datain port
    Info: Pin ENET_AEN has GND driving its datain port
    Info: Pin zs_cke_from_the_sdram has GND driving its datain port
Info: Following groups of pins have the same output enable
    Info: Following pins have the same output enable: std_1s10:inst|ext_ram_bus_avalon_slave_arbitrator:the_ext_ram_bus_avalon_slave|d1_in_a_write_cycle~COMB_OUT
        Info: Type bidirectional pin ext_ram_bus_data[30] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[7] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[16] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[25] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[9] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[18] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[2] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[27] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[11] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[20] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[4] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[29] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[13] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[22] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[6] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[31] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[15] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[24] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[8] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[17] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[1] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[26] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[10] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[19] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[3] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[28] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[12] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[21] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[5] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[14] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[23] uses the LVTTL I/O standard
        Info: Type bidirectional pin ext_ram_bus_data[0] uses the LVTTL I/O standard
    Info: Following pins have the same output enable: std_1s10:inst|cpu:the_cpu|M_alu_result[2] (inverted)
        Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[6] uses the LVTTL I/O standard
        Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[1] uses the LVTTL I/O standard
        Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[3] uses the LVTTL I/O standard
        Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[5] uses the LVTTL I/O standard
        Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[7] uses the LVTTL I/O standard
        Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[0] uses the LVTTL I/O standard
        Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[2] uses the LVTTL I/O standard
        Info: Type bidirectional pin LCD_data_to_and_from_the_lcd_display[4] uses the LVTTL I/O standard
    Info: Following pins have the same output enable: std_1s10:inst|sdram:the_sdram|oe
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[6] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[15] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[24] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[17] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[1] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[26] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[10] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[19] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[3] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[28] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[12] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[21] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[5] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[30] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[14] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[23] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[7] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[16] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[0] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[25] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[9] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[18] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[2] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[27] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[11] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[20] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[4] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[29] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[13] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[22] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[31] uses the LVTTL I/O standard
        Info: Type bidirectional pin zs_dq_to_and_from_the_sdram[8] uses the LVTTL I/O standard
    Info: Following pins have the same output enable: std_1s10:inst|reconfig_request_pio:the_reconfig_request_pio|data_dir
        Info: Type bidirectional pin bidir_port_to_and_from_the_reconfig_request_pio uses the LVTTL I/O standard
Info: Quartus II Fitter was successful. 0 errors, 140 warnings
    Info: Processing ended: Fri Apr 21 03:03:24 2006
    Info: Elapsed time: 00:04:01
Info: Generated suppressed messages file /data/job/20060421/1014742/examples/vhdl/niosII_stratix_1s10/standard/standard.fit.smsg


Fitter Suppressed Messages

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Fitter Suppressed Messages

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